/** @file
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Kaby Lake RVP 3 SMM Silicon ACPI Enable library
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Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <PiDxe.h>
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#include <Library/BaseLib.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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#include <Library/DebugLib.h>
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#include <PchAccess.h>
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#include <Library/MmPciLib.h>
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#include <Library/PchCycleDecodingLib.h>
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/**
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Clear Port 80h
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SMI handler to enable ACPI mode
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Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI
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Disables the SW SMI Timer.
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ACPI events are disabled and ACPI event status is cleared.
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SCI mode is then enabled.
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Clear SLP SMI status
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Enable SLP SMI
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Disable SW SMI Timer
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Clear all ACPI event status and disable all ACPI events
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Disable PM sources except power button
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Clear status bits
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Disable GPE0 sources
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Clear status bits
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Disable GPE1 sources
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Clear status bits
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Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
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Enable SCI
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**/
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EFI_STATUS
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EFIAPI
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SiliconEnableAcpi (
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IN BOOLEAN EnableSci
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)
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{
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UINT32 OutputValue;
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UINT32 SmiEn;
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UINT32 SmiSts;
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UINT32 ULKMC;
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UINTN LpcBaseAddress;
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UINT16 AcpiBaseAddr;
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UINT32 Pm1Cnt;
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LpcBaseAddress = MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_LPC,
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PCI_FUNCTION_NUMBER_PCH_LPC
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);
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//
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// Get the ACPI Base Address
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//
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PchAcpiBaseGet (&AcpiBaseAddr);
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//
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// BIOS must also ensure that CF9GR is cleared and locked before handing control to the
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// OS in order to prevent the host from issuing global resets and resetting ME
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//
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// EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global Reset
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// MmioWrite32 (
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// PmcBaseAddress + R_PCH_PMC_ETR3),
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// PmInit);
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//
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// Clear Port 80h
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//
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IoWrite8 (0x80, 0);
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//
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// Disable SW SMI Timer and clean the status
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//
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SmiEn = IoRead32 (AcpiBaseAddr + R_PCH_SMI_EN);
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SmiEn &= ~(B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB);
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IoWrite32 (AcpiBaseAddr + R_PCH_SMI_EN, SmiEn);
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SmiSts = IoRead32 (AcpiBaseAddr + R_PCH_SMI_STS);
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SmiSts |= B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB;
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IoWrite32 (AcpiBaseAddr + R_PCH_SMI_STS, SmiSts);
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//
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// Disable port 60/64 SMI trap if they are enabled
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//
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ULKMC = MmioRead32 (LpcBaseAddress + R_PCH_LPC_ULKMC) & ~(B_PCH_LPC_ULKMC_60REN | B_PCH_LPC_ULKMC_60WEN | B_PCH_LPC_ULKMC_64REN | B_PCH_LPC_ULKMC_64WEN | B_PCH_LPC_ULKMC_A20PASSEN);
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MmioWrite32 (LpcBaseAddress + R_PCH_LPC_ULKMC, ULKMC);
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//
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// Disable PM sources except power button
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//
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IoWrite16 (AcpiBaseAddr + R_PCH_ACPI_PM1_EN, B_PCH_ACPI_PM1_EN_PWRBTN);
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//
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// Clear PM status except Power Button status for RapidStart Resume
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//
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IoWrite16 (AcpiBaseAddr + R_PCH_ACPI_PM1_STS, 0xFEFF);
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//
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// Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
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//
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IoWrite8 (R_PCH_RTC_INDEX_ALT, R_PCH_RTC_REGD);
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IoWrite8 (R_PCH_RTC_TARGET_ALT, 0x0);
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//
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// Write ALT_GPI_SMI_EN to disable GPI1 (SMC_EXTSMI#)
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//
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OutputValue = IoRead32 (AcpiBaseAddr + 0x38);
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OutputValue = OutputValue & ~(1 << (UINTN) PcdGet8 (PcdSmcExtSmiBitPosition));
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IoWrite32 (AcpiBaseAddr + 0x38, OutputValue);
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//
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// Enable SCI
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//
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if (EnableSci) {
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Pm1Cnt = IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT);
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Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SCI_EN;
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IoWrite32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
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}
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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SiliconDisableAcpi (
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IN BOOLEAN DisableSci
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)
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{
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UINT16 AcpiBaseAddr;
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UINT32 Pm1Cnt;
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//
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// Get the ACPI Base Address
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//
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PchAcpiBaseGet (&AcpiBaseAddr);
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//
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// Disable SCI
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//
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if (DisableSci) {
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Pm1Cnt = IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT);
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Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SCI_EN;
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IoWrite32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
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}
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return EFI_SUCCESS;
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}
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