/** @file
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This file is SampleCode of the library for Intel PCH PEI Policy initialization.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PeiPchPolicyUpdate.h"
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#include <Library/BaseMemoryLib.h>
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#include <Library/PchInfoLib.h>
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#include <Library/PchPcrLib.h>
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#include <Library/PchHsioLib.h>
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#include <Library/PchPcieRpLib.h>
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#include <PchHsioPtssTables.h>
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VOID
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InstallPlatformHsioPtssTable (
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IN OUT FSPM_UPD *FspmUpd
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)
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{
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HSIO_PTSS_TABLES *UnknowPtssTables;
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HSIO_PTSS_TABLES *SpecificPtssTables;
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HSIO_PTSS_TABLES *PtssTables;
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UINT8 PtssTableIndex;
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UINT32 UnknowTableSize;
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UINT32 SpecificTableSize;
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UINT32 TableSize;
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UINT32 Entry;
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UINT8 LaneNum;
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UINT8 Index;
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UINT8 MaxSataPorts;
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UINT8 MaxPciePorts;
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UINT8 PcieTopologyReal[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PciePort;
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UINTN RpBase;
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UINTN RpDevice;
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UINTN RpFunction;
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UINT32 StrapFuseCfg;
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UINT8 PcieControllerCfg;
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EFI_STATUS Status;
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UnknowPtssTables = NULL;
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UnknowTableSize = 0;
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SpecificPtssTables = NULL;
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SpecificTableSize = 0;
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if (GetPchGeneration () == SklPch) {
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switch (PchStepping ()) {
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case PchLpB0:
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case PchLpB1:
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UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable1);
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UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable1Size);
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SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable1);
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SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable1Size);
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break;
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case PchLpC0:
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case PchLpC1:
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UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable2);
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UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable2Size);
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SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable2);
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SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable2Size);
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break;
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case PchHB0:
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case PchHC0:
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UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable1);
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UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable1Size);
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SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable1);
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SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable1Size);
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break;
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case PchHD0:
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case PchHD1:
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UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2);
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UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size);
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SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2);
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SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size);
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break;
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default:
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UnknowPtssTables = NULL;
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UnknowTableSize = 0;
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SpecificPtssTables = NULL;
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SpecificTableSize = 0;
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DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n"));
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}
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} else {
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switch (PchStepping ()) {
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case KblPchHA0:
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UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2);
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UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size);
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SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2);
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SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size);
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break;
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default:
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UnknowPtssTables = NULL;
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UnknowTableSize = 0;
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SpecificPtssTables = NULL;
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SpecificTableSize = 0;
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DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n"));
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}
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}
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PtssTableIndex = 0;
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MaxSataPorts = GetPchMaxSataPortNum ();
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MaxPciePorts = GetPchMaxPciePortNum ();
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ZeroMem (PcieTopologyReal, sizeof (PcieTopologyReal));
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//Populate PCIe topology based on lane configuration
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for (PciePort = 0; PciePort < MaxPciePorts; PciePort += 4) {
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Status = GetPchPcieRpDevFun (PciePort, &RpDevice, &RpFunction);
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ASSERT_EFI_ERROR (Status);
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RpBase = MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (UINT32) RpFunction);
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StrapFuseCfg = MmioRead32 (RpBase + R_PCH_PCIE_STRPFUSECFG);
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PcieControllerCfg = (UINT8) ((StrapFuseCfg & B_PCH_PCIE_STRPFUSECFG_RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC);
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DEBUG ((DEBUG_INFO, "PCIE Port %d StrapFuseCfg Value = %d\n", PciePort, PcieControllerCfg));
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}
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for (Index = 0; Index < MaxPciePorts; Index++) {
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DEBUG ((DEBUG_INFO, "PCIE PTSS Assigned RP %d Topology = %d\n", Index, PcieTopologyReal[Index]));
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}
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//Case 1: BoardId is known, Topology is known/unknown
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//Case 1a: SATA
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PtssTables = SpecificPtssTables;
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TableSize = SpecificTableSize;
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for (Index = 0; Index < MaxSataPorts; Index++) {
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if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
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for (Entry = 0; Entry < TableSize; Entry++) {
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if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
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(PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA)
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)
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{
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PtssTableIndex++;
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if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) &&
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(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) {
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FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] = TRUE;
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FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;
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} else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8)) {
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if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) {
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FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] = TRUE;
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FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0);
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}
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if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) {
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FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] = TRUE;
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FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0);
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}
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} else {
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ASSERT (FALSE);
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}
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}
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}
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}
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}
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//Case 1b: PCIe
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for (Index = 0; Index < MaxPciePorts; Index++) {
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if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
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for (Entry = 0; Entry < TableSize; Entry++) {
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if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
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(PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) &&
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(PcieTopologyReal[Index] == PtssTables[Entry].Topology)) {
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PtssTableIndex++;
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if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) &&
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(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) {
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FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] = TRUE;
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FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0);
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} else {
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ASSERT (FALSE);
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}
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}
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}
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}
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}
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//Case 2: BoardId is unknown, Topology is known/unknown
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if (PtssTableIndex == 0) {
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DEBUG ((DEBUG_INFO, "PTSS Settings for unknown board will be applied\n"));
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PtssTables = UnknowPtssTables;
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TableSize = UnknowTableSize;
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for (Index = 0; Index < MaxSataPorts; Index++) {
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if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
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for (Entry = 0; Entry < TableSize; Entry++) {
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if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
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(PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA)
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)
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{
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if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) &&
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(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) {
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FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] = TRUE;
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FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;
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} else if (PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8) {
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if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) {
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FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] = TRUE;
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FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0);
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}
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if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) {
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FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] = TRUE;
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FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0);
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}
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} else {
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ASSERT (FALSE);
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}
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}
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}
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}
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}
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for (Index = 0; Index < MaxPciePorts; Index++) {
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if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
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for (Entry = 0; Entry < TableSize; Entry++) {
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if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
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(PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) &&
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(PcieTopologyReal[Index] == PtssTables[Entry].Topology)) {
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if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) &&
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(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) {
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FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] = TRUE;
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FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0);
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} else {
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ASSERT (FALSE);
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}
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}
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}
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}
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}
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}
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}
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/**
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Performs FSP PCH PEI Policy pre mem initialization.
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@param[in][out] FspmUpd Pointer to FSP UPD Data.
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@retval EFI_SUCCESS FSP UPD Data is updated.
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@retval EFI_NOT_FOUND Fail to locate required PPI.
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@retval Other FSP UPD Data update process fail.
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**/
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EFI_STATUS
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EFIAPI
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PeiFspPchPolicyUpdatePreMem (
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IN OUT FSPM_UPD *FspmUpd
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)
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{
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InstallPlatformHsioPtssTable (FspmUpd);
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return EFI_SUCCESS;
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}
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