/** @file
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ACPI DSDT table
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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DefinitionBlock (
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"DSDT.aml",
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"DSDT",
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0x02, // DSDT revision.
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// A Revision field value greater than or equal to 2 signifies that integers
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// declared within the Definition Block are to be evaluated as 64-bit values
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"INTEL", // OEM ID (6 byte string)
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"SKL ",// OEM table ID (8 byte string)
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0x0 // OEM version of DSDT table (4 byte Integer)
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)
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// BEGIN OF ASL SCOPE
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{
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External(LHIH)
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External(LLOW)
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External(IGDS)
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External(LIDS)
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External(BRTL)
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External(ALSE)
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External(GSMI)
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External(\_SB.PCI0.GFX0.ALSI)
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External(\_SB.PCI0.GFX0.CDCK)
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External(\_SB.PCI0.GFX0.CBLV)
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External(\_SB.PCI0.GFX0.GSSE)
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External(\_SB.PCI0.PEG0, DeviceObj)
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External(\_SB.PCI0.PEG0.PEGP, DeviceObj)
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External(\_SB.PCI0.PEG1, DeviceObj)
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External(\_SB.PCI0.PEG2, DeviceObj)
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External(\_SB.PCI0.GFX0.DD1F, DeviceObj)
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External(\_SB.PCI0.GFX0.GDCK, MethodObj)
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External(\_SB.PCI0.GFX0.GHDS, MethodObj)
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External(\_SB.PCI0.GFX0.AINT, MethodObj)
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External(\_SB.PCI0.GFX0.GLID, MethodObj)
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External(\_SB.PCI0.GFX0.GSCI, MethodObj)
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External(\_PR.PR00._PSS, MethodObj)
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External(\_PR.PR00.LPSS, PkgObj)
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External(\_PR.PR00.TPSS, PkgObj)
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External(\_PR.PR00._PPC, MethodObj)
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External(\_PR.CPPC, IntObj)
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External(\_TZ.TZ00, DeviceObj)
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External(\_TZ.TZ01, DeviceObj)
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External(\_TZ.ETMD, IntObj)
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External(\_TZ.FN00._OFF, MethodObj)
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// Miscellaneous services enabled in Project
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Include ("AMLUPD.asl")
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Include ("Acpi/GlobalNvs.asl")
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Include ("PciTree.asl")
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if(LEqual(ECR1,1)){
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Scope(\_SB.PCI0) {
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//
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// PCI-specific method's GUID
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//
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Name(PCIG, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))
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//
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// PCI's _DSM - an attempt at modular _DSM implementation
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// When writing your own _DSM function that needs to include PCI-specific methods, do this:
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//
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// Method(_YOUR_DSM,4){
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// if(Lequal(Arg0,PCIG)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }
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// ...continue your _DSM by checking different GUIDs...
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// else { return(0) }
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// }
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//
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Method(PCID, 4, Serialized) {
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If(LEqual(Arg0, PCIG)) { // PCIE capabilities UUID
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If(LGreaterEqual(Arg1,3)) { // revision at least 3
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If(LEqual(Arg2,0)) { Return (Buffer(2){0x01,0x03}) } // function 0: list of supported functions
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If(LEqual(Arg2,8)) { Return (1) } // function 8: Avoiding Power-On Reset Delay Duplication on Sx Resume
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If(LEqual(Arg2,9)) { Return (Package(5){50000,Ones,Ones,50000,Ones}) } // function 9: Specifying Device Readiness Durations
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}
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}
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return (Buffer(1){0})
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}
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}//scope
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}//if
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Scope(\_SB.PCI0) {
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//PciCheck, Arg0=UUID, returns true if support for 'PCI delays optimization ECR' is enabled and the UUID is correct
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Method(PCIC,1,Serialized) {
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If(LEqual(ECR1,1)) {
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If(LEqual(Arg0, PCIG)) {
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return (1)
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}
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}
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return (0)
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}
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}
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Include ("Pch.asl") // Not in this package. Refer to the PCH Reference Code accordingly
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Include ("LpcB.asl")
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Include ("Platform.asl")
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Include ("CPU.asl")
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Include ("PCI_DRC.ASL")
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Include ("Video.asl")
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Include ("PlatformGnvs.asl")
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Include ("Gpe.asl")
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Name(\_S0, Package(4){0x0,0x0,0,0}) // mandatory System state
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if(SS1) { Name(\_S1, Package(4){0x1,0x0,0,0})}
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if(SS3) { Name(\_S3, Package(4){0x5,0x0,0,0})}
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if(SS4) { Name(\_S4, Package(4){0x6,0x0,0,0})}
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Name(\_S5, Package(4){0x7,0x0,0,0}) // mandatory System state
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Method(PTS, 1) { // METHOD CALLED FROM _PTS PRIOR TO ENTER ANY SLEEP STATE
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If(Arg0) // entering any sleep state
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{
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}
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}
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Method(WAK, 1) { // METHOD CALLED FROM _WAK RIGHT AFTER WAKE UP
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}
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}// End of ASL File
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