/** @file
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Source code for the board SA configuration Pcd init functions in Pre-Memory init phase.
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Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "BoardSaConfigPreMem.h"
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#include "SaPolicyCommon.h"
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#include "CometlakeURvpInit.h"
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#include <PlatformBoardConfig.h>
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#include <Library/CpuPlatformLib.h>
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//
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// LPDDR3 178b 8Gb die, DDP, x32
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// Micron MT52L512M32D2PF-093
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// 2133, 16-20-20-45
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// 2 ranks per channel, 2 SDRAMs per rank, 4x8Gb = 4GB total per channel
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//
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GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr3Ddp8Gb178b2133Spd[] = {
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0x24, // 512 SPD bytes used, 512 total
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0x01, // SPD Revision 0.1
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0x0F, // DRAM Type: LPDDR3 SDRAM
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0x0E, // Module Type: Non-DIMM Solution
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0x15, // 8 Banks, 8 Gb SDRAM density
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0x19, // 15 Rows, 10 Columns
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0x90, // SDRAM Package Type: DDP, 1 Channel per package
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0x00, // SDRAM Optional Features: none, tMAW = 8192 * tREFI
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0x00, // SDRAM Thermal / Refresh options: none
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0x00, // Other SDRAM Optional Features: none
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0x00, // Reserved
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0x0B, // Module Nominal Voltage, VDD = 1.2v
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0x0B, // SDRAM width: 32 bits, 2 Ranks
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0x03, // SDRAM bus width: 1 Channel, 64 bits channel width
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0x00, // Module Thermal Sensor: none
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0x00, // Extended Module Type: Reserved
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0x00, // Signal Loading: Unspecified
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0x00, // MTB = 0.125ns, FTB = 1 ps
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0x08, // tCKmin = 0.938 ns (LPDDR3-2133)
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0xFF, // tCKmax = 32.002 ns
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0xD4, // CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (First Byte)
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0x01, // CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (Second Byte)
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0x00, // CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (Third Byte)
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0x00, // CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (Fourth Byte)
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0x78, // Minimum CAS Latency (tAAmin) = 15.008 ns
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0x00, // Read and Write Latency Set options: none
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0x90, // Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
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0xA8, // Row precharge time for all banks (tRPab) = 21 ns
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0x90, // Minimum row precharge time (tRPmin) = 18 ns
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0x90, // tRFCab = 210 ns (8 Gb)
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0x06, // tRFCab MSB
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0xD0, // tRFCpb = 90 ns (8 Gb)
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0x02, // tRFCpb MSB
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0, 0, 0, 0, 0, 0, 0, // 33-39
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 40-49
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 50-59
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 60-69
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 70-79
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 80-89
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 90-99
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 100-109
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 110-119
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0x00, // FTB for Row precharge time per bank (tRPpb) = 18 ns
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0x00, // FTB for Row precharge time for all banks (tRPab) = 21 ns
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0x00, // FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
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0x08, // FTB for tAAmin = 15.008 ns (LPDDR3-2133)
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0x7F, // FTB for tCKmax = 32.002 ns
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0xC2, // FTB for tCKmin = 0.938 ns (LPDDR3-2133)
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0, 0, 0, 0, // 126-129
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 130-139
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 140-149
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 150-159
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 160-169
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 170-179
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 180-189
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 190-199
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 200-209
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 210-219
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 220-229
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 230-239
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 240-249
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 250-259
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 260-269
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 270-279
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 280-289
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 290-299
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 300-309
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 310-319
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0, 0, 0, 0, 0, // 320-324
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0x55, 0, 0, 0, // 325-328: Module ID: Module Serial Number
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0x20, 0x20, 0x20, 0x20, 0x20, // 329-333: Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
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0x20, 0x20, 0x20, 0x20, 0x20, // 334-338: Module Part Number
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0x20, 0x20, 0x20, 0x20, 0x20, // 339-343: Module Part Number
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0x20, 0x20, 0x20, 0x20, 0x20, // 344-348: Module Part Number
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0x00, // 349 Module Revision Code
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0x00, // 350 DRAM Manufacturer ID Code, Least Significant Byte
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0x00, // 351 DRAM Manufacturer ID Code, Most Significant Byte
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0x00, // 352 DRAM Stepping
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0, 0, 0, 0, 0, 0, 0, // 353 - 359
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 360 - 369
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 370 - 379
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 380 - 389
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 390 - 399
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 400 - 409
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 410 - 419
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 420 - 429
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 430 - 439
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 440 - 449
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 450 - 459
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 460 - 469
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 470 - 479
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 480 - 489
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 490 - 499
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 500 - 509
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0, 0 // 510 - 511
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};
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//
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// Display DDI settings for WHL ERB
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//
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GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mWhlErbRowDisplayDdiConfig[9] = {
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DdiPortAEdp, // DDI Port A Config : DdiPortADisabled = Disabled, DdiPortAEdp = eDP, DdiPortAMipiDsi = MIPI DSI
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DdiHpdEnable, // DDI Port B HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
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DdiHpdEnable, // DDI Port C HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
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DdiHpdDisable, // DDI Port D HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
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DdiHpdDisable, // DDI Port F HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
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DdiDdcEnable, // DDI Port B DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
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DdiDdcEnable, // DDI Port C DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
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DdiDdcEnable, // DDI Port D DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
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DdiDisable // DDI Port F DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
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};
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/**
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MRC configuration init function for PEI pre-memory phase.
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@param[in] BoardId An unsigned integer represent the board id.
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@retval EFI_SUCCESS The function completed successfully.
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**/
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EFI_STATUS
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SaMiscConfigInit (
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IN UINT16 BoardId
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)
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{
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//
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// UserBd
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//
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switch (BoardId) {
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case BoardIdCometLakeULpddr3Rvp:
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//
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// Assign UserBd to 5 which is assigned to MrcInputs->BoardType btUser4 for ULT platforms.
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// This is required to skip Memory voltage programming based on GPIO's in MRC
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//
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PcdSet8S (PcdSaMiscUserBd, 5); // MrcBoardType btUser4 for ULT platform
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break;
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default:
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// MiscPeiPreMemConfig.UserBd = 0 by default.
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break;
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}
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PcdSet16S (PcdSaDdrFreqLimit, 0);
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return EFI_SUCCESS;
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}
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/**
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Board Memory Init related configuration init function for PEI pre-memory phase.
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@param[in] BoardId An unsigned integrer represent the board id.
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@retval EFI_SUCCESS The function completed successfully.
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**/
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EFI_STATUS
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MrcConfigInit (
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IN UINT16 BoardId
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)
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{
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CPU_FAMILY CpuFamilyId;
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CpuFamilyId = GetCpuFamily();
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if (CpuFamilyId == EnumCpuCflDtHalo) {
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PcdSetBoolS (PcdDualDimmPerChannelBoardType, TRUE);
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} else {
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PcdSetBoolS (PcdDualDimmPerChannelBoardType, FALSE);
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}
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//
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// Example policy for DIMM slots implementation boards:
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// 1. Assign Smbus address of DIMMs and SpdData will be updated later
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// by reading from DIMM SPD.
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// 2. No need to apply hardcoded SpdData buffers here for such board.
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//
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// Comet Lake U LP3 has removable DIMM slots.
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// So assign all Smbus address of DIMMs and leave PcdMrcSpdData set to 0.
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// Example:
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// PcdMrcSpdData = 0
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// PcdMrcSpdDataSize = 0
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// PcdMrcSpdAddressTable0 = 0xA0
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// PcdMrcSpdAddressTable1 = 0xA2
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// PcdMrcSpdAddressTable2 = 0xA4
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// PcdMrcSpdAddressTable3 = 0xA6
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//
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// If a board has soldered down memory. It should use the following settings.
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// Example:
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// PcdMrcSpdAddressTable0 = 0
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// PcdMrcSpdAddressTable1 = 0
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// PcdMrcSpdAddressTable2 = 0
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// PcdMrcSpdAddressTable3 = 0
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// PcdMrcSpdData = static data buffer
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// PcdMrcSpdDataSize = sizeof (static data buffer)
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//
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//
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// SPD Address Table
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//
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PcdSet32S (PcdMrcSpdData, (UINTN)mLpddr3Ddp8Gb178b2133Spd);
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PcdSet16S (PcdMrcSpdDataSize, sizeof(mLpddr3Ddp8Gb178b2133Spd));
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PcdSet8S (PcdMrcSpdAddressTable0, 0);
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PcdSet8S (PcdMrcSpdAddressTable1, 0);
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PcdSet8S (PcdMrcSpdAddressTable2, 0);
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PcdSet8S (PcdMrcSpdAddressTable3, 0);
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//
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// DRAM SPD Data & related configuration
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//
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// Setting the PCD's to default value (CML LP3). It will be overriden to board specific settings below.
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PcdSet32S(PcdMrcDqByteMap, (UINTN) DqByteMapCmlULpddr3Rvp);
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PcdSet16S (PcdMrcDqByteMapSize, sizeof (DqByteMapCmlULpddr3Rvp));
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PcdSet32S(PcdMrcDqsMapCpu2Dram, (UINTN) DqsMapCpu2DramCmlULpddr3Rvp);
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PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (DqsMapCpu2DramCmlULpddr3Rvp));
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switch (BoardId) {
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case BoardIdCometLakeULpddr3Rvp:
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PcdSet32S(PcdMrcRcompResistor, (UINTN)RcompResistorCmlULpKc);
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PcdSet32S(PcdMrcRcompTarget, (UINTN)RcompTargetCmlULpKc);
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PcdSetBoolS(PcdMrcDqPinsInterleavedControl, TRUE);
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PcdSetBoolS(PcdMrcDqPinsInterleaved, FALSE);
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break;
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default:
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break;
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}
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//
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// CA Vref routing: board-dependent
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// 0 - VREF_CA goes to both CH_A and CH_B (LPDDR3/DDR3L)
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// 1 - VREF_CA to CH_A, VREF_DQ_A to CH_B (should not be used)
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// 2 - VREF_CA to CH_A, VREF_DQ_B to CH_B (DDR4)
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//
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switch (BoardId) {
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case BoardIdCometLakeULpddr3Rvp:
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PcdSet8S (PcdMrcCaVrefConfig, 0); // All DDR3L/LPDDR3/LPDDR4 boards
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break;
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default:
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PcdSet8S (PcdMrcCaVrefConfig, 2); // DDR4 boards
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break;
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}
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return EFI_SUCCESS;
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}
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/**
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Board SA related GPIO configuration init function for PEI pre-memory phase.
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@param[in] BoardId An unsigned integer represent the board id.
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@retval EFI_SUCCESS The function completed successfully.
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**/
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EFI_STATUS
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SaGpioConfigInit (
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IN UINT16 BoardId
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)
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{
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//
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// Update board's GPIO for PEG slot reset
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//
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PcdSetBoolS (PcdPegGpioResetControl, TRUE);
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PcdSetBoolS (PcdPegGpioResetSupoort, FALSE);
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PcdSet32S (PcdPeg0ResetGpioPad, 0);
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PcdSetBoolS (PcdPeg0ResetGpioActive, FALSE);
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PcdSet32S (PcdPeg3ResetGpioPad, 0);
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PcdSetBoolS (PcdPeg3ResetGpioActive, FALSE);
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//
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// PCIE RTD3 GPIO
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//
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switch (BoardId) {
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case BoardIdCometLakeULpddr3Rvp:
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PcdSet8S(PcdRootPortIndex, 4);
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PcdSet8S (PcdPcie0GpioSupport, PchGpio);
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PcdSet32S (PcdPcie0WakeGpioNo, 0);
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PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
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PcdSet32S (PcdPcie0HoldRstGpioNo, GPIO_CNL_LP_GPP_C15);
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PcdSetBoolS (PcdPcie0HoldRstActive, FALSE);
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PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
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PcdSet32S (PcdPcie0PwrEnableGpioNo, GPIO_CNL_LP_GPP_C14);
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PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
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PcdSet8S (PcdPcie1GpioSupport, NotSupported);
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PcdSet32S (PcdPcie1WakeGpioNo, 0);
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PcdSet8S (PcdPcie1HoldRstExpanderNo, 0);
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PcdSet32S (PcdPcie1HoldRstGpioNo, 0);
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PcdSetBoolS (PcdPcie1HoldRstActive, FALSE);
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PcdSet8S (PcdPcie1PwrEnableExpanderNo, 0);
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PcdSet32S (PcdPcie1PwrEnableGpioNo, 0);
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PcdSetBoolS (PcdPcie1PwrEnableActive, FALSE);
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PcdSet8S (PcdPcie2GpioSupport, NotSupported);
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PcdSet32S (PcdPcie2WakeGpioNo, 0);
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PcdSet8S (PcdPcie2HoldRstExpanderNo, 0);
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PcdSet32S (PcdPcie2HoldRstGpioNo, 0);
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PcdSetBoolS (PcdPcie2HoldRstActive, FALSE);
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PcdSet8S (PcdPcie2PwrEnableExpanderNo, 0);
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PcdSet32S (PcdPcie2PwrEnableGpioNo, 0);
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PcdSetBoolS (PcdPcie2PwrEnableActive, FALSE);
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break;
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default:
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PcdSet8S(PcdRootPortIndex, 0xFF);
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PcdSet8S (PcdPcie0GpioSupport, NotSupported);
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PcdSet32S (PcdPcie0WakeGpioNo, 0);
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PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
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PcdSet32S (PcdPcie0HoldRstGpioNo, 0);
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PcdSetBoolS (PcdPcie0HoldRstActive, FALSE);
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PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
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PcdSet32S (PcdPcie0PwrEnableGpioNo, 0);
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PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
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PcdSet8S (PcdPcie1GpioSupport, NotSupported);
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PcdSet32S (PcdPcie1WakeGpioNo, 0);
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PcdSet8S (PcdPcie1HoldRstExpanderNo, 0);
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PcdSet32S (PcdPcie1HoldRstGpioNo, 0);
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PcdSetBoolS (PcdPcie1HoldRstActive, FALSE);
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PcdSet8S (PcdPcie1PwrEnableExpanderNo, 0);
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PcdSet32S (PcdPcie1PwrEnableGpioNo, 0);
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PcdSetBoolS (PcdPcie1PwrEnableActive, FALSE);
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PcdSet8S (PcdPcie2GpioSupport, NotSupported);
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PcdSet32S (PcdPcie2WakeGpioNo, 0);
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PcdSet8S (PcdPcie2HoldRstExpanderNo, 0);
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PcdSet32S (PcdPcie2HoldRstGpioNo, 0);
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PcdSetBoolS (PcdPcie2HoldRstActive, FALSE);
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PcdSet8S (PcdPcie2PwrEnableExpanderNo, 0);
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PcdSet32S (PcdPcie2PwrEnableGpioNo, 0);
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PcdSetBoolS (PcdPcie2PwrEnableActive, FALSE);
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break;
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}
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return EFI_SUCCESS;
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}
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/**
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SA Display DDI configuration init function for PEI pre-memory phase.
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@param[in] BoardId An unsigned integer represent the board id.
|
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@retval EFI_SUCCESS The function completed successfully.
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**/
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EFI_STATUS
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SaDisplayConfigInit (
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IN UINT16 BoardId
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)
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{
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//
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// Update Display DDI Config
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//
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switch (BoardId) {
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case BoardIdCometLakeULpddr3Rvp:
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PcdSet32S (PcdSaDisplayConfigTable, (UINTN) mWhlErbRowDisplayDdiConfig);
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PcdSet16S (PcdSaDisplayConfigTableSize, sizeof (mWhlErbRowDisplayDdiConfig));
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break;
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default:
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break;
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}
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return EFI_SUCCESS;
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}
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