/** @file
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PCI Host Bridge Library instance for Hisilicon D0x
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Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
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Copyright (c) 2017 - 2018, Linaro Ltd. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PiDxe.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/DevicePathLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/OemMiscLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PciHostBridgeLib.h>
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#include <Library/PlatformPciLib.h>
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#include <Protocol/PciHostBridgeResourceAllocation.h>
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#include <Protocol/PciRootBridgeIo.h>
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#pragma pack(1)
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typedef struct {
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ACPI_HID_DEVICE_PATH AcpiDevicePath;
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EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
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} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
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#pragma pack ()
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STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = {
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{
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{
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ACPI_DEVICE_PATH,
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ACPI_DP,
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{
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(UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
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(UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
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}
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},
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EISA_PNP_ID(0x0A03), // PCI
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0
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}, {
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END_DEVICE_PATH_TYPE,
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END_ENTIRE_DEVICE_PATH_SUBTYPE,
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{
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END_DEVICE_PATH_LENGTH,
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0
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}
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}
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};
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STATIC PCI_ROOT_BRIDGE mRootBridgeTemplate = {
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0, // Segment
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0, // Supports
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0, // Attributes
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TRUE, // DmaAbove4G
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FALSE, // NoExtendedConfigSpace
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FALSE, // ResourceAssigned
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EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes
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EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
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{
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// Bus
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0,
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0
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}, {
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// Io
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0,
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0,
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0
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}, {
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// Mem
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MAX_UINT64,
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0,
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0
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}, {
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// MemAbove4G
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MAX_UINT64,
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0,
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0
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}, {
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// PMem
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MAX_UINT64,
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0,
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0
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}, {
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// PMemAbove4G
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MAX_UINT64,
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0,
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0
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},
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(EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath
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};
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STATIC
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EFI_STATUS
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ConstructRootBridge (
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PCI_ROOT_BRIDGE *Bridge,
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PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Appeture
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)
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{
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EFI_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;
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CopyMem (Bridge, &mRootBridgeTemplate, sizeof *Bridge);
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Bridge->Segment = Appeture->Segment;
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Bridge->Bus.Base = Appeture->BusBase;
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Bridge->Bus.Limit = Appeture->BusLimit;
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Bridge->Io.Base = Appeture->IoBase;
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// According to UEFI 2.7, device address = host address + translation
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Bridge->Io.Translation = Appeture->IoBase - Appeture->CpuIoRegionBase;
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// IoLimit is actually an address in CPU view
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// TODO: improve the definition of PCI_ROOT_BRIDGE_RESOURCE_APPETURE
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Bridge->Io.Limit = Appeture->IoLimit + Bridge->Io.Translation;
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if (Appeture->PciRegionBase > MAX_UINT32) {
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Bridge->MemAbove4G.Base = Appeture->PciRegionBase;
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Bridge->MemAbove4G.Limit = Appeture->PciRegionLimit;
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Bridge->MemAbove4G.Translation = Appeture->PciRegionBase - Appeture->CpuMemRegionBase;
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} else {
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Bridge->Mem.Base = Appeture->PciRegionBase;
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Bridge->Mem.Limit = Appeture->PciRegionLimit;
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Bridge->Mem.Translation = Appeture->PciRegionBase - Appeture->CpuMemRegionBase;
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}
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DevicePath = AllocateCopyPool(sizeof mEfiPciRootBridgeDevicePath, &mEfiPciRootBridgeDevicePath);
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if (DevicePath == NULL) {
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DEBUG ((DEBUG_ERROR, "[%a]:[%dL] AllocatePool failed!\n", __FUNCTION__, __LINE__));
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return EFI_OUT_OF_RESOURCES;
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}
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DevicePath->AcpiDevicePath.UID = Bridge->Segment;
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Bridge->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)DevicePath;
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return EFI_SUCCESS;
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}
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/**
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Return all the root bridge instances in an array.
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@param Count Return the count of root bridge instances.
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@return All the root bridge instances in an array.
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The array should be passed into PciHostBridgeFreeRootBridges()
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when it's not used.
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**/
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PCI_ROOT_BRIDGE *
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EFIAPI
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PciHostBridgeGetRootBridges (
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UINTN *Count
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)
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{
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EFI_STATUS Status;
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UINTN Loop1;
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UINTN Loop2;
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UINT32 PcieRootBridgeMask;
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UINTN RootBridgeCount = 0;
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PCI_ROOT_BRIDGE *Bridges;
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// Set default value to 0 in case we got any error.
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*Count = 0;
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if (!OemIsMpBoot())
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{
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PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask);
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}
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else
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{
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PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask2P);
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}
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for (Loop1 = 0; Loop1 < PCIE_MAX_HOSTBRIDGE; Loop1++) {
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if (((PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * Loop1)) & 0xFF ) == 0) {
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continue;
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}
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for (Loop2 = 0; Loop2 < PCIE_MAX_ROOTBRIDGE; Loop2++) {
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if (!(((PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * Loop1)) >> Loop2 ) & 0x01)) {
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continue;
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}
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RootBridgeCount++;
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}
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}
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Bridges = AllocatePool (RootBridgeCount * sizeof *Bridges);
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if (Bridges == NULL) {
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DEBUG ((DEBUG_ERROR, "[%a:%d] - AllocatePool failed!\n", __FUNCTION__, __LINE__));
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return NULL;
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}
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for (Loop1 = 0; Loop1 < PCIE_MAX_HOSTBRIDGE; Loop1++) {
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if (((PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * Loop1)) & 0xFF ) == 0) {
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continue;
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}
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for (Loop2 = 0; Loop2 < PCIE_MAX_ROOTBRIDGE; Loop2++) {
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if (!(((PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * Loop1)) >> Loop2 ) & 0x01)) {
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continue;
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}
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Status = ConstructRootBridge (&Bridges[*Count], &mResAppeture[Loop1][Loop2]);
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if (EFI_ERROR (Status)) {
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continue;
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}
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(*Count)++;
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}
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}
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if (*Count == 0) {
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FreePool (Bridges);
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return NULL;
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}
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return Bridges;
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}
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/**
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Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
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@param Bridges The root bridge instances array.
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@param Count The count of the array.
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**/
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VOID
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EFIAPI
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PciHostBridgeFreeRootBridges (
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PCI_ROOT_BRIDGE *Bridges,
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UINTN Count
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)
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{
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UINTN Index;
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for (Index = 0; Index < Count; Index++) {
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FreePool (Bridges[Index].DevicePath);
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}
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if (Bridges != NULL) {
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FreePool (Bridges);
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}
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}
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#ifndef MDEPKG_NDEBUG
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STATIC CONST CHAR16 mPciHostBridgeLibAcpiAddressSpaceTypeStr[][4] = {
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L"Mem", L"I/O", L"Bus"
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};
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#endif
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/**
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Inform the platform that the resource conflict happens.
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@param HostBridgeHandle Handle of the Host Bridge.
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@param Configuration Pointer to PCI I/O and PCI memory resource
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descriptors. The Configuration contains the resources
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for all the root bridges. The resource for each root
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bridge is terminated with END descriptor and an
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additional END is appended indicating the end of the
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entire resources. The resource descriptor field
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values follow the description in
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EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
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.SubmitResources().
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**/
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VOID
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EFIAPI
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PciHostBridgeResourceConflict (
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EFI_HANDLE HostBridgeHandle,
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VOID *Configuration
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)
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{
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EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
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UINTN RootBridgeIndex;
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DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));
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RootBridgeIndex = 0;
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Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
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while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
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DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
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for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
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ASSERT (Descriptor->ResType <
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ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr)
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);
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DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
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mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
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Descriptor->AddrLen, Descriptor->AddrRangeMax
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));
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if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
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DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
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Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
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((Descriptor->SpecificFlag &
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EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
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) != 0) ? L" (Prefetchable)" : L""
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));
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}
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}
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//
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// Skip the END descriptor for root bridge
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//
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ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
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Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
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(EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
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);
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}
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}
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