/** @file
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Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef MORELLO_PLATFORM_H_
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#define MORELLO_PLATFORM_H_
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#define MORELLO_DRAM_BLOCK1_SIZE SIZE_2GB
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// ****************************************************************************
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// Platform Memory Map
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// ****************************************************************************
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// SubSystem Peripherals - UART0
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#define MORELLO_UART0_BASE 0x2A400000
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#define MORELLO_UART0_SZ SIZE_64KB
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// SubSystem Peripherals - UART1
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#define MORELLO_UART1_BASE 0x2A410000
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#define MORELLO_UART1_SZ SIZE_64KB
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// SubSystem Peripherals - Generic Watchdog
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#define MORELLO_GENERIC_WDOG_BASE 0x2A440000
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#define MORELLO_GENERIC_WDOG_SZ SIZE_128KB
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// SubSystem Peripherals - GIC(600)
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#define MORELLO_GIC_BASE 0x30000000
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#define MORELLO_GICR_BASE 0x300C0000
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#define MORELLO_GIC_SZ SIZE_256KB
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#define MORELLO_GICR_SZ SIZE_1MB
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// SubSystem non-secure SRAM
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#define MORELLO_NON_SECURE_SRAM_BASE 0x06000000
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#define MORELLO_NON_SECURE_SRAM_SZ SIZE_64KB
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// AXI Expansion peripherals
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#define MORELLO_EXP_PERIPH_BASE 0x1C000000
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#define MORELLO_EXP_PERIPH_BASE_SZ 0x1300000
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// Platform information structure base address
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#define MORELLO_PLAT_INFO_STRUCT_BASE MORELLO_NON_SECURE_SRAM_BASE
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/*
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* Platform information structure stored in Non-secure SRAM. Platform
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* information are passed from the trusted firmware with the below structure
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* format. The elements of MORELLO_PLAT_INFO should be always in sync with
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* the lower level firmware.
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*/
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#pragma pack(1)
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typedef struct {
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UINT64 LocalDdrSize; ///< Local DDR memory size in Bytes
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UINT64 RemoteDdrSize; ///< Remote DDR memory size in Bytes
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UINT8 SlaveCount; ///< Slave count in C2C mode
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UINT8 Mode; ///< 0 - Single Chip, 1 - Chip to Chip (C2C)
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} MORELLO_PLAT_INFO;
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#pragma pack()
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#endif //MORELLO_PLATFORM_H_
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