/** @file
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* Header containing the Xpress-RICH3 PCIe Root Complex specific values
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*
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* Copyright (c) 2011-2015, ARM Ltd. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#ifndef __XPRESS_RICH3_H__
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#define __XPRESS_RICH3_H__
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#include <Protocol/CpuIo2.h>
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#include <Library/PcdLib.h>
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#define PCI_ECAM_BASE FixedPcdGet64 (PcdPciConfigurationSpaceBaseAddress)
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#define PCI_ECAM_SIZE FixedPcdGet64 (PcdPciConfigurationSpaceSize)
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#define PCI_IO_BASE FixedPcdGet64 (PcdPciIoTranslation)
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#define PCI_IO_SIZE FixedPcdGet64 (PcdPciIoSize)
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#define PCI_MEM32_BASE FixedPcdGet64 (PcdPciMmio32Base)
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#define PCI_MEM32_SIZE FixedPcdGet64 (PcdPciMmio32Size)
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#define PCI_MEM64_BASE FixedPcdGet64 (PcdPciMmio64Base)
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#define PCI_MEM64_SIZE FixedPcdGet64 (PcdPciMmio64Size)
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#define PCI_TRACE(txt) DEBUG((EFI_D_VERBOSE, "ARM_PCI: " txt "\n"))
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#define PCIE_ROOTPORT_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Value); }
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#define PCIE_ROOTPORT_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Val); }
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#define PCIE_CONTROL_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieControlBaseAddress)+(Add)),1,&Value); }
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#define PCIE_CONTROL_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieControlBaseAddress)+(Add)),1,&Val); }
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/*
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* Bridge Internal Registers
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*/
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// PCIe Available Credit Settings
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#define PCIE_VC_CRED 0x090
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// PCIe PCI Standard Configuration Identification Settings registers
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#define PCIE_PCI_IDS 0x098
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#define PCIE_PCI_IDS_CLASSCODE_OFFSET 0x4
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// PCIe Specific 2 Capabilities Settings
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#define PCIE_PEX_SPC2 0x0d8
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// PCIe Windows Settings register
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#define PCIE_BAR_WIN 0x0FC
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// Local Processor Interrupt Mask
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#define PCIE_IMASK_LOCAL 0x180
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#define PCIE_BAR_WIN_SUPPORT_IO BIT0
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#define PCIE_BAR_WIN_SUPPORT_IO32 BIT1
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#define PCIE_BAR_WIN_SUPPORT_MEM BIT2
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#define PCIE_BAR_WIN_SUPPORT_MEM64 BIT3
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#define PCIE_INT_MSI BIT28
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#define PCIE_INT_A BIT24
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#define PCIE_INT_B BIT25
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#define PCIE_INT_C BIT26
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#define PCIE_INT_D BIT27
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#define PCIE_INT_INTx (PCIE_INT_A | PCIE_INT_B |\
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PCIE_INT_C | PCIE_INT_D)
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/*
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* PCIe Control Registers
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*/
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#define PCIE_CONTROL_RST_CTL 0x1004
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#define PCIE_CONTROL_RST_STS 0x1008
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/*
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* PCI Express Address Translation registers
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* All are offsets from PcdPcieControlBaseAddress
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*/
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#define VEXPRESS_ATR_PCIE_WIN0 0x600
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#define VEXPRESS_ATR_AXI4_SLV0 0x800
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#define VEXPRESS_ATR_AXI4_SLV1 0x820
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#define PCI_ATR_ENTRY_SIZE 0x20
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#define PCI_ATR_SRC_ADDR_LOW_SIZE 0
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#define PCI_ATR_SRC_ADDR_HI 0x4
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#define PCI_ATR_TRSL_ADDR_LOW 0x8
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#define PCI_ATR_TRSL_ADDR_HI 0xc
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#define PCI_ATR_TRSL_PARAM 0x10
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#define PCI_ATR_TRSLID_AXIDEVICE 0x420004
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#define PCI_ATR_TRSLID_AXIMEMORY 0x4e0004
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#define PCI_ATR_TRSLID_PCIE_CONF 0x000001
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#define PCI_ATR_TRSLID_PCIE_IO 0x020000
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#define PCI_ATR_TRSLID_PCIE_MEMORY 0x000000
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#define PCIE_CONTROL_RST_CTL_RC_REL (1 << 1)
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#define PCIE_CONTROL_RST_CTL_PHY_REL (1 << 0)
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#define PCIE_CONTROL_RST_CTL_RCPHY_REL (PCIE_CONTROL_RST_CTL_RC_REL | PCIE_CONTROL_RST_CTL_PHY_REL)
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#define PCIE_CONTROL_RST_STS_RC_ST (1 << 2)
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#define PCIE_CONTROL_RST_STS_PHY_ST (1 << 1)
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#define PCIE_CONTROL_RST_STS_PLL_ST (1 << 0)
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#define PCIE_CONTROL_RST_STS_RCPHYPLL_OUT (PCIE_CONTROL_RST_STS_RC_ST | PCIE_CONTROL_RST_STS_PHY_ST | PCIE_CONTROL_RST_STS_PLL_ST)
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#define VEXPRESS_BASIC_STATUS 0x18
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#define LINK_UP 0xff
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#endif
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