/** @file
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*
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* Copyright (c) 2013-2020, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include "ArmJunoDxeInternal.h"
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#include <ArmPlatform.h>
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#include <IndustryStandard/Pci.h>
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#include <Protocol/DevicePathFromText.h>
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#include <Protocol/PciIo.h>
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#include <Protocol/PciRootBridgeIo.h>
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#include <Guid/EventGroup.h>
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#include <Guid/GlobalVariable.h>
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#include <Library/ArmShellCmdLib.h>
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#include <Library/AcpiLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DevicePathLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/NonDiscoverableDeviceRegistrationLib.h>
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#include <Library/UefiRuntimeServicesTableLib.h>
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#include <Library/IoLib.h>
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#include <Library/PrintLib.h>
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#ifndef DYNAMIC_TABLES_FRAMEWORK
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// This GUID must match the FILE_GUID in ArmPlatformPkg/ArmJunoPkg/AcpiTables/AcpiTables.inf
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STATIC CONST EFI_GUID mJunoAcpiTableFile = { 0xa1dd808e, 0x1e95, 0x4399, { 0xab, 0xc0, 0x65, 0x3c, 0x82, 0xe8, 0x53, 0x0c } };
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STATIC VOID *mAcpiRegistration = NULL;
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#endif
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STATIC VOID *mPciIoNotificationRegistration = NULL;
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/**
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This function reads PCI ID of the controller.
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@param[in] PciIo PCI IO protocol handle
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@param[in] PciId Looking for specified PCI ID Vendor/Device
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**/
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STATIC
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EFI_STATUS
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ReadMarvellYoukonPciId (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT32 PciId
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)
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{
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UINT32 DevicePciId;
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EFI_STATUS Status;
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Status = PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint32,
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PCI_VENDOR_ID_OFFSET,
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1,
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&DevicePciId);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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if (DevicePciId != PciId) {
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return EFI_NOT_FOUND;
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}
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return EFI_SUCCESS;
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}
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/**
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This function restore the original controller attributes
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@param[in] PciIo PCI IO protocol handle
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@param[in] PciAttr PCI controller attributes.
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@param[in] AcpiResDescriptor ACPI 2.0 resource descriptors for the BAR
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**/
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STATIC
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VOID
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RestorePciDev (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT64 PciAttr
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)
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{
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PciIo->Attributes (
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PciIo,
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EfiPciIoAttributeOperationSet,
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PciAttr,
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NULL
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);
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}
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/**
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This function returns PCI MMIO base address for a controller
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@param[in] PciIo PCI IO protocol handle
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@param[out] PciRegBase PCI base MMIO address
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**/
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STATIC
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EFI_STATUS
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BarIsDeviceMemory (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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OUT UINT32 *PciRegBase
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)
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{
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EFI_STATUS Status;
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EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *AcpiResDescriptor;
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EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *AcpiCurrentDescriptor;
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// Marvell Yukon's Bar0 provides base memory address for control registers
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Status = PciIo->GetBarAttributes (PciIo, PCI_BAR_IDX0, NULL, (VOID**)&AcpiResDescriptor);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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AcpiCurrentDescriptor = AcpiResDescriptor;
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// Search for a memory type descriptor
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while (AcpiCurrentDescriptor->Desc != ACPI_END_TAG_DESCRIPTOR) {
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// Check if Bar is memory type one and fetch a base address
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if (AcpiCurrentDescriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR &&
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AcpiCurrentDescriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM &&
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!(AcpiCurrentDescriptor->SpecificFlag & ACPI_SPECFLAG_PREFETCHABLE)) {
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*PciRegBase = AcpiCurrentDescriptor->AddrRangeMin;
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break;
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} else {
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Status = EFI_UNSUPPORTED;
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}
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AcpiCurrentDescriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) (AcpiCurrentDescriptor + 1);
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}
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gBS->FreePool (AcpiResDescriptor);
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return Status;
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}
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/**
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This function provides PCI MMIO base address, old PCI controller attributes.
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@param[in] PciIo PCI IO protocol handle
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@param[out] PciRegBase PCI base MMIO address
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@param[out] OldPciAttr Old PCI controller attributes.
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**/
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STATIC
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EFI_STATUS
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InitPciDev (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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OUT UINT32 *PciRegBase,
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OUT UINT64 *OldPciAttr
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)
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{
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UINT64 AttrSupports;
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EFI_STATUS Status;
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// Get controller's current attributes
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Status = PciIo->Attributes (
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PciIo,
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EfiPciIoAttributeOperationGet,
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0,
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OldPciAttr);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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// Fetch supported attributes
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Status = PciIo->Attributes (
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PciIo,
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EfiPciIoAttributeOperationSupported,
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0,
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&AttrSupports);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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// Enable EFI_PCI_IO_ATTRIBUTE_IO, EFI_PCI_IO_ATTRIBUTE_MEMORY and
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// EFI_PCI_IO_ATTRIBUTE_BUS_MASTER bits in the PCI Config Header
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AttrSupports &= EFI_PCI_DEVICE_ENABLE;
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Status = PciIo->Attributes (
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PciIo,
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EfiPciIoAttributeOperationEnable,
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AttrSupports,
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NULL);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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Status = BarIsDeviceMemory (PciIo, PciRegBase);
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if (EFI_ERROR (Status)) {
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RestorePciDev (PciIo, *OldPciAttr);
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}
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return Status;
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}
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/**
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This function reads MAC address from IOFPGA and writes it to Marvell Yukon NIC
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@param[in] PciRegBase PCI base MMIO address
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**/
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STATIC
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EFI_STATUS
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WriteMacAddress (
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IN UINT32 PciRegBase
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)
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{
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UINT32 MacHigh;
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UINT32 MacLow;
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// Read MAC address from IOFPGA
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MacHigh= MmioRead32 (ARM_JUNO_SYS_PCIGBE_H);
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MacLow = MmioRead32 (ARM_JUNO_SYS_PCIGBE_L);
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// Set software reset control register to protect from deactivation
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// the config write state
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MmioWrite16 (PciRegBase + R_CONTROL_STATUS, CS_RESET_CLR);
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// Convert to Marvell MAC Address register format
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MacHigh = SwapBytes32 ((MacHigh & 0xFFFF) << 16 |
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(MacLow & 0xFFFF0000) >> 16);
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MacLow = SwapBytes32 (MacLow) >> 16;
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// Set MAC Address
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MmioWrite8 (PciRegBase + R_TST_CTRL_1, TST_CFG_WRITE_ENABLE);
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MmioWrite32 (PciRegBase + R_MAC, MacHigh);
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MmioWrite32 (PciRegBase + R_MAC_MAINT, MacHigh);
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MmioWrite32 (PciRegBase + R_MAC + R_MAC_LOW, MacLow);
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MmioWrite32 (PciRegBase + R_MAC_MAINT + R_MAC_LOW, MacLow);
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MmioWrite8 (PciRegBase + R_TST_CTRL_1, TST_CFG_WRITE_DISABLE);
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// Initiate device reset
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MmioWrite16 (PciRegBase + R_CONTROL_STATUS, CS_RESET_SET);
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MmioWrite16 (PciRegBase + R_CONTROL_STATUS, CS_RESET_CLR);
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return EFI_SUCCESS;
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}
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/**
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The function reads MAC address from Juno IOFPGA registers and writes it
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into Marvell Yukon NIC.
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**/
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STATIC
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EFI_STATUS
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ArmJunoSetNicMacAddress (
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IN EFI_PCI_IO_PROTOCOL *PciIo
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)
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{
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UINT64 OldPciAttr;
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UINT32 PciRegBase;
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EFI_STATUS Status;
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PciRegBase = 0;
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Status = InitPciDev (PciIo, &PciRegBase, &OldPciAttr);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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Status = WriteMacAddress (PciRegBase);
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RestorePciDev (PciIo, OldPciAttr);
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return EFI_SUCCESS;
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}
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/**
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This function is called when a gEfiPciIoProtocolGuid protocol instance is
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registered in the protocol database.
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@param[in] Event Event declared in the entry point of the driver whose
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notification function is being invoked.
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@param[in] Context NULL
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**/
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STATIC
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VOID
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PciIoNotificationEvent (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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EFI_STATUS Status;
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EFI_PCI_IO_PROTOCOL *PciIo;
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Status = gBS->LocateProtocol (&gEfiPciIoProtocolGuid,
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mPciIoNotificationRegistration, (VOID **)&PciIo);
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if (EFI_ERROR (Status)) {
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return;
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}
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Status = ReadMarvellYoukonPciId (PciIo, JUNO_MARVELL_YUKON_ID);
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if (EFI_ERROR (Status)) {
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return;
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}
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Status = ArmJunoSetNicMacAddress (PciIo);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "ArmJunoDxe: Failed to set Marvell Yukon NIC MAC address\n"));
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}
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gBS->CloseEvent (Event);
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}
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EFI_STATUS
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EFIAPI
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ArmJunoEntryPoint (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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EFI_PHYSICAL_ADDRESS HypBase;
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CHAR16 *TextDevicePath;
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UINTN TextDevicePathSize;
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UINT32 JunoRevision;
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//
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// Register the OHCI and EHCI controllers as non-coherent
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// non-discoverable devices.
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//
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Status = RegisterNonDiscoverableMmioDevice (
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NonDiscoverableDeviceTypeOhci,
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NonDiscoverableDeviceDmaTypeNonCoherent,
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NULL,
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NULL,
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1,
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FixedPcdGet32 (PcdSynopsysUsbOhciBaseAddress),
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SIZE_64KB
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);
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ASSERT_EFI_ERROR (Status);
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Status = RegisterNonDiscoverableMmioDevice (
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NonDiscoverableDeviceTypeEhci,
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NonDiscoverableDeviceDmaTypeNonCoherent,
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NULL,
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NULL,
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1,
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FixedPcdGet32 (PcdSynopsysUsbEhciBaseAddress),
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SIZE_64KB
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);
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ASSERT_EFI_ERROR (Status);
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//
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// If a hypervisor has been declared then we need to make sure its region is protected at runtime
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//
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// Note: This code is only a workaround for our dummy hypervisor (ArmPkg/Extra/AArch64ToAArch32Shim/)
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// that does not set up (yet) the stage 2 translation table to hide its own memory to EL1.
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//
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if (FixedPcdGet32 (PcdHypFvSize) != 0) {
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// Ensure the hypervisor region is strictly contained into a EFI_PAGE_SIZE-aligned region.
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// The memory must be a multiple of EFI_PAGE_SIZE to ensure we do not reserve more memory than the hypervisor itself.
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// A UEFI Runtime region size granularity cannot be smaller than EFI_PAGE_SIZE. If the hypervisor size is not rounded
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// to this size then there is a risk some non-runtime memory could be visible to the OS view.
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if (((FixedPcdGet32 (PcdHypFvSize) & EFI_PAGE_MASK) == 0) && ((FixedPcdGet32 (PcdHypFvBaseAddress) & EFI_PAGE_MASK) == 0)) {
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// The memory needs to be declared because the DXE core marked it as reserved and removed it from the memory space
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// as it contains the Firmware.
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Status = gDS->AddMemorySpace (
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EfiGcdMemoryTypeSystemMemory,
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FixedPcdGet32 (PcdHypFvBaseAddress), FixedPcdGet32 (PcdHypFvSize),
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EFI_MEMORY_WB | EFI_MEMORY_RUNTIME
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);
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if (!EFI_ERROR (Status)) {
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// We allocate the memory to ensure it is marked as runtime memory
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HypBase = FixedPcdGet32 (PcdHypFvBaseAddress);
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Status = gBS->AllocatePages (AllocateAddress, EfiRuntimeServicesCode,
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EFI_SIZE_TO_PAGES (FixedPcdGet32 (PcdHypFvSize)), &HypBase);
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}
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} else {
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// The hypervisor must be contained into a EFI_PAGE_SIZE-aligned region and its size must also be aligned
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// on a EFI_PAGE_SIZE boundary (ie: 4KB).
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Status = EFI_UNSUPPORTED;
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ASSERT_EFI_ERROR (Status);
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}
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if (EFI_ERROR (Status)) {
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return Status;
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}
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}
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// Install dynamic Shell command to run baremetal binaries.
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Status = ShellDynCmdRunAxfInstall (ImageHandle);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "ArmJunoDxe: Failed to install ShellDynCmdRunAxf\n"));
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}
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GetJunoRevision(JunoRevision);
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#ifndef DYNAMIC_TABLES_FRAMEWORK
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//
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// Try to install the ACPI Tables
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//
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Status = LocateAndInstallAcpiFromFv (&mJunoAcpiTableFile);
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ASSERT_EFI_ERROR (Status);
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#endif
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//
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// Setup R1/R2 options if not already done.
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//
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if (JunoRevision != JUNO_REVISION_R0) {
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// Enable PCI enumeration
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PcdSetBoolS (PcdPciDisableBusEnumeration, FALSE);
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//
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// Create a protocol notification event handler on the PciIo protocol
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// so we can set the MAC address on the Marvell Yukon as soon as it
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// appears.
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//
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EfiCreateProtocolNotifyEvent (
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&gEfiPciIoProtocolGuid,
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TPL_NOTIFY,
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PciIoNotificationEvent,
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NULL,
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&mPciIoNotificationRegistration
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);
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#ifndef DYNAMIC_TABLES_FRAMEWORK
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// Declare the related ACPI Tables
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EfiCreateProtocolNotifyEvent (
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&gEfiAcpiTableProtocolGuid,
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TPL_CALLBACK,
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AcpiPciNotificationEvent,
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NULL,
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&mAcpiRegistration
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);
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#endif
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}
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//
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// Set up the device path to the FDT.
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//
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TextDevicePath = (CHAR16*)FixedPcdGetPtr (PcdJunoFdtDevicePath);
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if (TextDevicePath != NULL) {
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TextDevicePathSize = StrSize (TextDevicePath);
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Status = PcdSetPtrS (
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PcdFdtDevicePaths,
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&TextDevicePathSize,
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TextDevicePath
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);
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} else {
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Status = EFI_NOT_FOUND;
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}
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if (EFI_ERROR (Status)) {
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DEBUG (
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(EFI_D_ERROR,
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"ArmJunoDxe: Setting of FDT device path in PcdFdtDevicePaths failed - %r\n", Status)
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);
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return Status;
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}
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return Status;
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}
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