/** @file
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Copyright (c) 2017 - 2021, Arm Limited. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Glossary:
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- Cm or CM - Configuration Manager
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- Obj or OBJ - Object
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**/
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#ifndef CONFIGURATION_MANAGER_H__
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#define CONFIGURATION_MANAGER_H__
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/** C array containing the compiled AML template.
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These symbols are defined in the auto generated C file
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containing the AML bytecode array.
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*/
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extern CHAR8 dsdt_aml_code[];
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extern CHAR8 ssdtjunousb_aml_code[];
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extern CHAR8 ssdtpci_aml_code[];
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/** The configuration manager version
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*/
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#define CONFIGURATION_MANAGER_REVISION CREATE_REVISION (1, 0)
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/** The OEM ID
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*/
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#define CFG_MGR_OEM_ID { 'A', 'R', 'M', 'L', 'T', 'D' }
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/** A helper macro for mapping a reference token
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*/
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#define REFERENCE_TOKEN(Field) \
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(CM_OBJECT_TOKEN)((UINT8*)&ArmJunoPlatformRepositoryInfo + \
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OFFSET_OF (EDKII_PLATFORM_REPOSITORY_INFO, Field))
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/** A helper macro for populating the GIC CPU information
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*/
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#define GICC_ENTRY( \
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CPUInterfaceNumber, \
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Mpidr, \
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PmuIrq, \
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VGicIrq, \
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EnergyEfficiency \
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) { \
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CPUInterfaceNumber, /* UINT32 CPUInterfaceNumber */ \
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CPUInterfaceNumber, /* UINT32 AcpiProcessorUid */ \
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EFI_ACPI_6_2_GIC_ENABLED, /* UINT32 Flags */ \
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0, /* UINT32 ParkingProtocolVersion */ \
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PmuIrq, /* UINT32 PerformanceInterruptGsiv */ \
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0, /* UINT64 ParkedAddress */ \
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FixedPcdGet64 ( \
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PcdGicInterruptInterfaceBase \
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), /* UINT64 PhysicalBaseAddress */ \
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0x2C06F000, /* UINT64 GICV */ \
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0x2C04F000, /* UINT64 GICH */ \
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VGicIrq, /* UINT32 VGICMaintenanceInterrupt */ \
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0, /* UINT64 GICRBaseAddress */ \
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Mpidr, /* UINT64 MPIDR */ \
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EnergyEfficiency /* UINT8 ProcessorPowerEfficiencyClass*/ \
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}
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/** A helper macro for populating the Processor Hierarchy Node flags
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*/
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#define PROC_NODE_FLAGS( \
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PhysicalPackage, \
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AcpiProcessorIdValid, \
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ProcessorIsThread, \
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NodeIsLeaf, \
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IdenticalImplementation \
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) \
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( \
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PhysicalPackage | \
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(AcpiProcessorIdValid << 1) | \
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(ProcessorIsThread << 2) | \
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(NodeIsLeaf << 3) | \
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(IdenticalImplementation << 4) \
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)
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/** A helper macro for populating the Cache Type Structure's attributes
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*/
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#define CACHE_ATTRIBUTES( \
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AllocationType, \
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CacheType, \
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WritePolicy \
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) \
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( \
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AllocationType | \
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(CacheType << 2) | \
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(WritePolicy << 4) \
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)
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/** A function that prepares Configuration Manager Objects for returning.
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@param [in] This Pointer to the Configuration Manager Protocol.
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@param [in] CmObjectId The Configuration Manager Object ID.
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@param [in] Token A token for identifying the object.
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@param [out] CmObject Pointer to the Configuration Manager Object
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descriptor describing the requested Object.
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@retval EFI_SUCCESS Success.
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@retval EFI_INVALID_PARAMETER A parameter is invalid.
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@retval EFI_NOT_FOUND The required object information is not found.
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**/
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typedef EFI_STATUS (*CM_OBJECT_HANDLER_PROC) (
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IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
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IN CONST CM_OBJECT_ID CmObjectId,
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IN CONST CM_OBJECT_TOKEN Token,
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IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
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);
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/** The number of CPUs
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*/
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#define PLAT_CPU_COUNT 6
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/** The number of ACPI tables to install
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*/
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#define PLAT_ACPI_TABLE_COUNT 10
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/** The number of platform generic timer blocks
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*/
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#define PLAT_GTBLOCK_COUNT 1
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/** The number of timer frames per generic timer block
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*/
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#define PLAT_GTFRAME_COUNT 2
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/** For all Juno revisions, the cache and processor topology is identical.
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Terms 'big' and 'LITTLE' are used in favour of A72, A57 or A53 to take into
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account that Juno r2 uses Cortex-A72 as 'big' cores, whereas Juno r0 and r1
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have Cortex-A57 as 'big' cores.
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*/
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/** The number of Processor Hierarchy Nodes
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- one package node
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- two cluster nodes ('big' + 'LITTLE')
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- two 'big' cores
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- four 'LITTLE' cores
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*/
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#define PLAT_PROC_HIERARCHY_NODE_COUNT 9
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/** The number of unique cache structures:
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- 'big' core L1 instruction cache
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- 'big' core L1 data cache
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- 'big' core L2 cache
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- 'LITTLE' core L1 instruction cache
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- 'LITTLE' core L1 data cache
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- 'LITTLE' core L2 cache
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*/
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#define PLAT_CACHE_COUNT 6
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/** The number of resources private to the entire 'big' cluster
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- L2 cache
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*/
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#define BIG_CLUSTER_RESOURCE_COUNT 1
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/** The number of resources private to 'big' core instance
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- L1 data cache
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- L1 instruction cache
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*/
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#define BIG_CORE_RESOURCE_COUNT 2
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/** The number of resources private to the entire 'LITTLE' cluster
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- L2 cache
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*/
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#define LITTLE_CLUSTER_RESOURCE_COUNT 1
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/** The number of resources private to each 'LITTLE' core instance
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- L1 data cache
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- L1 instruction cache
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*/
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#define LITTLE_CORE_RESOURCE_COUNT 2
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/** A structure describing the platform configuration
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manager repository information
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*/
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typedef struct PlatformRepositoryInfo {
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/// Configuration Manager Information
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CM_STD_OBJ_CONFIGURATION_MANAGER_INFO CmInfo;
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/// List of ACPI tables
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CM_STD_OBJ_ACPI_TABLE_INFO CmAcpiTableList[PLAT_ACPI_TABLE_COUNT];
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/// Boot architecture information
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CM_ARM_BOOT_ARCH_INFO BootArchInfo;
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/// Power management profile information
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CM_ARM_POWER_MANAGEMENT_PROFILE_INFO PmProfileInfo;
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/// GIC CPU interface information
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CM_ARM_GICC_INFO GicCInfo[PLAT_CPU_COUNT];
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/// GIC distributor information
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CM_ARM_GICD_INFO GicDInfo;
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/// Generic timer information
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CM_ARM_GENERIC_TIMER_INFO GenericTimerInfo;
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/// Generic timer block information
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CM_ARM_GTBLOCK_INFO GTBlockInfo[PLAT_GTBLOCK_COUNT];
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/// Generic timer frame information
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CM_ARM_GTBLOCK_TIMER_FRAME_INFO GTBlock0TimerInfo[PLAT_GTFRAME_COUNT];
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/// Watchdog information
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CM_ARM_GENERIC_WATCHDOG_INFO Watchdog;
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/** Serial port information for the
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serial port console redirection port
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*/
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CM_ARM_SERIAL_PORT_INFO SpcrSerialPort;
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/// Serial port information for the DBG2 UART port
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CM_ARM_SERIAL_PORT_INFO DbgSerialPort;
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/// PCI configuration space information
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CM_ARM_PCI_CONFIG_SPACE_INFO PciConfigInfo;
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/// GIC MSI Frame information
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CM_ARM_GIC_MSI_FRAME_INFO GicMsiFrameInfo;
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// Processor topology information
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CM_ARM_PROC_HIERARCHY_INFO ProcHierarchyInfo[PLAT_PROC_HIERARCHY_NODE_COUNT];
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// Cache information
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CM_ARM_CACHE_INFO CacheInfo[PLAT_CACHE_COUNT];
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// 'big' cluster private resources
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CM_ARM_OBJ_REF BigClusterResources[BIG_CLUSTER_RESOURCE_COUNT];
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// 'big' core private resources
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CM_ARM_OBJ_REF BigCoreResources[BIG_CORE_RESOURCE_COUNT];
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// 'LITTLE' cluster private resources
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CM_ARM_OBJ_REF LittleClusterResources[LITTLE_CLUSTER_RESOURCE_COUNT];
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// 'LITTLE' core private resources
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CM_ARM_OBJ_REF LittleCoreResources[LITTLE_CORE_RESOURCE_COUNT];
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/// Juno Board Revision
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UINT32 JunoRevision;
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} EDKII_PLATFORM_REPOSITORY_INFO;
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#endif // CONFIGURATION_MANAGER_H__
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