/*
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* DTS file for AMD Seattle (Rev.B) Overdrive Development Board
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*
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* Copyright 2015 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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*/
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/dts-v1/;
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/ {
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model = "AMD Seattle (Rev.B) Development Board (Overdrive)";
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compatible = "amd,seattle-overdrive", "amd,seattle";
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interrupt-parent = <&gic>;
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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gic: interrupt-controller@e1101000 {
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compatible = "arm,gic-400", "arm,cortex-a15-gic";
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interrupt-controller;
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#interrupt-cells = <0x3>;
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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reg = <0x0 0xe1110000 0x0 0x1000>,
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<0x0 0xe112f000 0x0 0x2000>,
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<0x0 0xe1140000 0x0 0x2000>,
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<0x0 0xe1160000 0x0 0x2000>;
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interrupts = <0x1 0x9 0xf04>;
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ranges = <0x0 0x0 0x0 0xe1100000 0x0 0x100000>;
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msi: v2m@e0080000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x0 0x80000 0x0 0x1000>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <0x1 0xd 0xff04>,
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<0x1 0xe 0xff04>,
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<0x1 0xb 0xff04>,
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<0x1 0xa 0xff04>;
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};
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smb {
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compatible = "simple-bus";
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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ranges;
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/*
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* dma-ranges is 40-bit address space containing:
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* - GICv2m MSI register is at 0xe0080000
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* - DRAM range [0x8000000000 to 0xffffffffff]
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*/
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dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
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sata_clk: clk333mhz {
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compatible = "fixed-clock";
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#clock-cells = <0x0>;
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clock-frequency = <333000000>;
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clock-output-names = "sataclk_333mhz";
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};
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i2c_clk: clk250mhz_4 {
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compatible = "fixed-clock";
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#clock-cells = <0x0>;
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clock-frequency = <250000000>;
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clock-output-names = "miscclk_250mhz";
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};
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apb_clk: clk100mhz_1 {
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compatible = "fixed-clock";
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#clock-cells = <0x0>;
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clock-frequency = <100000000>;
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clock-output-names = "uartspiclk_100mhz";
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};
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sata0_smmu: smmu@e0200000 {
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compatible = "arm,mmu-401";
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reg = <0 0xe0200000 0 0x10000>;
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#global-interrupts = <1>;
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interrupts = /* Uses combined intr for both
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* global and context
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*/
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<0 332 4>,
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<0 332 4>;
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#iommu-cells = <2>;
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dma-coherent;
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};
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sata1_smmu: smmu@e0c00000 {
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compatible = "arm,mmu-401";
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reg = <0 0xe0c00000 0 0x10000>;
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#global-interrupts = <1>;
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interrupts = /* Uses combined intr for both
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* global and context
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*/
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<0 331 4>,
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<0 331 4>;
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#iommu-cells = <1>;
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dma-coherent;
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};
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sata@e0300000 {
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compatible = "snps,dwc-ahci";
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reg = <0x0 0xe0300000 0x0 0xf0000>;
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interrupts = <0x0 0x163 0x4>;
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clocks = <&sata_clk>;
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dma-coherent;
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iommus = <&sata0_smmu 0x0 0x1f>;
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};
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sata@e0d00000 {
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status = "disabled";
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compatible = "snps,dwc-ahci";
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reg = <0x0 0xe0d00000 0x0 0xf0000>;
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interrupts = <0x0 0x162 0x4>;
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clocks = <&sata_clk>;
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dma-coherent;
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iommus = <&sata1_smmu 0x0e>,
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<&sata1_smmu 0x0f>,
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<&sata1_smmu 0x1e>;
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};
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i2c@e1000000 {
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compatible = "snps,designware-i2c";
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reg = <0x0 0xe1000000 0x0 0x1000>;
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interrupts = <0x0 0x165 0x4>;
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clocks = <&i2c_clk>;
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};
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i2c@e0050000 {
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compatible = "snps,designware-i2c";
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reg = <0x0 0xe0050000 0x0 0x1000>;
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interrupts = <0x0 0x154 0x4>;
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clocks = <&i2c_clk>;
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};
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serial@e1010000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0xe1010000 0x0 0x1000>;
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interrupts = <0x0 0x148 0x4>;
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clocks = <&apb_clk &apb_clk>;
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clock-names = "uartclk", "apb_pclk";
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};
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ssp@e1020000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x0 0xe1020000 0x0 0x1000>;
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spi-controller;
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interrupts = <0x0 0x14a 0x4>;
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clocks = <&apb_clk>;
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clock-names = "apb_pclk";
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};
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ssp@e1030000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x0 0xe1030000 0x0 0x1000>;
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spi-controller;
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interrupts = <0x0 0x149 0x4>;
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clocks = <&apb_clk>;
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clock-names = "apb_pclk";
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num-cs = <0x1>;
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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sdcard@0 {
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compatible = "mmc-spi-slot";
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reg = <0x0>;
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spi-max-frequency = <20000000>;
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voltage-ranges = <3200 3400>;
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pl022,hierarchy = <0x0>;
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pl022,interface = <0x0>;
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pl022,com-mode = <0x0>;
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pl022,rx-level-trig = <0x0>;
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pl022,tx-level-trig = <0x0>;
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};
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};
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gpio@e1050000 { /* [0 : 7] */
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compatible = "arm,pl061", "arm,primecell";
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#gpio-cells = <0x2>;
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reg = <0x0 0xe1050000 0x0 0x1000>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <0x2>;
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interrupts = <0x0 0x166 0x4>;
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clocks = <&apb_clk>;
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clock-names = "apb_pclk";
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};
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gpio@e0020000 { /* [8 : 15] */
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status = "disabled";
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compatible = "arm,pl061", "arm,primecell";
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#gpio-cells = <0x2>;
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reg = <0x0 0xe0020000 0x0 0x1000>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <0x2>;
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interrupts = <0x0 0x16e 0x4>;
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clocks = <&apb_clk>;
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clock-names = "apb_pclk";
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};
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gpio@e0030000 { /* [16 : 23] */
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status = "disabled";
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compatible = "arm,pl061", "arm,primecell";
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#gpio-cells = <0x2>;
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reg = <0x0 0xe0030000 0x0 0x1000>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <0x2>;
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interrupts = <0x0 0x16d 0x4>;
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clocks = <&apb_clk>;
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clock-names = "apb_pclk";
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};
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gpio@e0080000 { /* [24] */
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compatible = "arm,pl061", "arm,primecell";
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#gpio-cells = <0x2>;
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reg = <0x0 0xe0080000 0x0 0x1000>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <0x2>;
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interrupts = <0x0 0x169 0x4>;
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clocks = <&apb_clk>;
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clock-names = "apb_pclk";
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};
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ccp: ccp@e0100000 {
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compatible = "amd,ccp-seattle-v1a";
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reg = <0x0 0xe0100000 0x0 0x10000>;
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interrupts = <0x0 0x3 0x4>;
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dma-coherent;
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amd,zlib-support = <0x1>;
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iommus = <&sata1_smmu 0x00>,
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<&sata1_smmu 0x02>,
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<&sata1_smmu 0x40>,
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<&sata1_smmu 0x42>;
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};
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pcie: pcie@f0000000 {
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compatible = "pci-host-ecam-generic";
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#address-cells = <0x3>;
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#size-cells = <0x2>;
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#interrupt-cells = <0x1>;
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iommu-map = <0x0 &pcie_smmu 0x0 0x10000>;
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device_type = "pci";
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bus-range = <0x0 0x7f>;
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msi-parent = <&msi>;
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reg = <0x0 0xf0000000 0x0 0x10000000>;
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interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
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interrupt-map = <0x1100 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x120 0x1>,
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<0x1100 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x121 0x1>,
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<0x1100 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x122 0x1>,
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<0x1100 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x123 0x1>,
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<0x1200 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x124 0x1>,
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<0x1200 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x125 0x1>,
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<0x1200 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x126 0x1>,
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<0x1200 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x127 0x1>,
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<0x1300 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x128 0x1>,
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<0x1300 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x129 0x1>,
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<0x1300 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12a 0x1>,
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<0x1300 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x12b 0x1>;
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dma-coherent;
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dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
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ranges = <0x1000000 0x0 0x00000000 0x0 0xefff0000 0x00 0x00010000>, /* I/O Memory (size=64K) */
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<0x2000000 0x0 0x40000000 0x0 0x40000000 0x00 0x80000000>, /* 32-bit MMIO (size=2G) */
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<0x3000000 0x1 0x00000000 0x1 0x00000000 0x7f 0x00000000>; /* 64-bit MMIO (size= 124G) */
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};
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pcie_smmu: smmu@e0a00000 {
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compatible = "arm,mmu-401";
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reg = <0 0xe0a00000 0 0x10000>;
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#global-interrupts = <1>;
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interrupts = /* Uses combined intr for both
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* global and context
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*/
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<0 333 4>,
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<0 333 4>;
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#iommu-cells = <1>;
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dma-coherent;
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};
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ccn@e8000000 {
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compatible = "arm,ccn-504";
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reg = <0x0 0xe8000000 0x0 0x1000000>;
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interrupts = <0x0 0x17c 0x4>;
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};
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gwdt@e0bb0000 {
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status = "disabled";
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compatible = "arm,sbsa-gwdt";
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reg = <0x0 0xe0bb0000 0x0 0x10000
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0x0 0xe0bc0000 0x0 0x10000>;
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reg-names = "refresh", "control";
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interrupts = <0x0 0x151 0x4>;
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interrupt-names = "ws0";
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};
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kcs@e0010000 {
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status = "disabled";
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compatible = "ipmi-kcs";
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device_type = "ipmi";
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reg = <0x0 0xe0010000 0 0x8>;
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interrupts = <0 389 4>;
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interrupt-names = "ipmi_kcs";
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reg-size = <1>;
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reg-spacing = <4>;
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};
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xgmacclk0_dma: clk250mhz_0 {
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compatible = "fixed-clock";
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#clock-cells = <0x0>;
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clock-frequency = <250000000>;
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clock-output-names = "xgmacclk0_dma_250mhz";
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};
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xgmacclk0_ptp: clk250mhz_1 {
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compatible = "fixed-clock";
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#clock-cells = <0x0>;
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clock-frequency = <250000000>;
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clock-output-names = "xgmacclk0_ptp_250mhz";
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};
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xgmacclk1_dma: clk250mhz_2 {
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compatible = "fixed-clock";
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#clock-cells = <0x0>;
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clock-frequency = <250000000>;
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clock-output-names = "xgmacclk1_dma_250mhz";
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};
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xgmacclk1_ptp: clk250mhz_3 {
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compatible = "fixed-clock";
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#clock-cells = <0x0>;
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clock-frequency = <250000000>;
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clock-output-names = "xgmacclk1_ptp_250mhz";
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};
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xgmac0_phy: phy@e1240800 {
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status = "disabled";
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compatible = "amd,xgbe-phy-seattle-v1a";
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reg = <0x0 0xe1240800 0x0 0x0400>, /* SERDES RX/TX0 */
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<0x0 0xe1250000 0x0 0x0060>, /* SERDES IR 1/2 */
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<0x0 0xe12500f8 0x0 0x0004>; /* SERDES IR 2/2 */
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interrupts = <0x0 0x143 0x4>;
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amd,speed-set = <0x0>;
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amd,serdes-blwc = <0x1 0x1 0x0>;
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amd,serdes-cdr-rate = <0x2 0x2 0x7>;
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amd,serdes-pq-skew = <0xa 0xa 0x12>;
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amd,serdes-tx-amp = <0xf 0xf 0xa>;
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amd,serdes-dfe-tap-config = <0x3 0x3 0x1>;
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amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>;
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};
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xgmac1_phy: phy@e1240c00 {
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status = "disabled";
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compatible = "amd,xgbe-phy-seattle-v1a";
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reg = <0x0 0xe1240c00 0x0 0x0400>, /* SERDES RX/TX0 */
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<0x0 0xe1250080 0x0 0x0060>, /* SERDES IR 1/2 */
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<0x0 0xe12500fc 0x0 0x0004>; /* SERDES IR 2/2 */
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interrupts = <0x0 0x142 0x4>;
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amd,speed-set = <0x0>;
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amd,serdes-blwc = <0x1 0x1 0x0>;
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amd,serdes-cdr-rate = <0x2 0x2 0x7>;
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amd,serdes-pq-skew = <0xa 0xa 0x12>;
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amd,serdes-tx-amp = <0xf 0xf 0xa>;
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amd,serdes-dfe-tap-config = <0x3 0x3 0x1>;
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amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>;
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};
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xgmac0_smmu: smmu@e0600000 {
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compatible = "arm,mmu-401";
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reg = <0 0xe0600000 0 0x10000>;
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#global-interrupts = <1>;
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interrupts = /* Uses combined intr for both
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* global and context
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*/
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<0 336 4>,
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<0 336 4>;
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#iommu-cells = <2>;
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dma-coherent;
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};
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xgmac1_smmu: smmu@e0800000 {
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compatible = "arm,mmu-401";
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reg = <0 0xe0800000 0 0x10000>;
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#global-interrupts = <1>;
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interrupts = /* Uses combined intr for both
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* global and context
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*/
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<0 335 4>,
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<0 335 4>;
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#iommu-cells = <2>;
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dma-coherent;
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};
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xgmac@e0700000 {
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status = "disabled";
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compatible = "amd,xgbe-seattle-v1a";
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reg = <0x0 0xe0700000 0x0 0x80000 0x0 0xe0780000 0x0 0x80000>;
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interrupts = <0x0 0x145 0x4>,
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<0x0 0x15a 0x1>,
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<0x0 0x15b 0x1>,
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<0x0 0x15c 0x1>,
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<0x0 0x15d 0x1>;
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amd,per-channel-interrupt;
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mac-address = [02 a1 a2 a3 a4 a5];
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clocks = <&xgmacclk0_dma &xgmacclk0_ptp>;
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clock-names = "dma_clk", "ptp_clk";
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phy-handle = <&xgmac0_phy>;
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phy-mode = "xgmii";
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dma-coherent;
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iommus = <&xgmac0_smmu 0x00 0x17>; /* 0-7, 16-23 */
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};
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xgmac@e0900000 {
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status = "disabled";
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compatible = "amd,xgbe-seattle-v1a";
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reg = <0x0 0xe0900000 0x0 0x80000 0x0 0xe0980000 0x0 0x80000>;
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interrupts = <0x0 0x144 0x4>,
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<0x0 0x155 0x1>,
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<0x0 0x156 0x1>,
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<0x0 0x157 0x1>,
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<0x0 0x158 0x1>;
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amd,per-channel-interrupt;
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mac-address = [02 b1 b2 b3 b4 b5];
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clocks = <&xgmacclk1_dma &xgmacclk1_ptp>;
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clock-names = "dma_clk", "ptp_clk";
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phy-handle = <&xgmac1_phy>;
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phy-mode = "xgmii";
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dma-coherent;
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iommus = <&xgmac1_smmu 0x00 0x17>; /* 0-7, 16-23 */
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};
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};
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chosen {
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stdout-path = "/smb/serial@e1010000";
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};
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psci {
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compatible = "arm,psci-0.2", "arm,psci";
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method = "smc";
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};
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};
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