/******************************************************************************
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*
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* Copyright(c) 2007 - 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef __RTW_PWRCTRL_H_
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#define __RTW_PWRCTRL_H_
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#define PS_ACTIVE 0
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#define PS_LPS 1
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#define FW_PWR0 0
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#define FW_PWR1 1
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#define FW_PWR2 2
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#define FW_PWR3 3
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#define HW_PWR0 7
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#define HW_PWR1 6
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#define HW_PWR2 2
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#define HW_PWR3 0
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#define HW_PWR4 8
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#define FW_PWRMSK 0x7
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#define XMIT_ALIVE BIT(0)
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#define RECV_ALIVE BIT(1)
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#define CMD_ALIVE BIT(2)
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#define EVT_ALIVE BIT(3)
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enum power_mgnt {
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PM_PS_MODE_ACTIVE = 0 ,
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PM_PS_MODE_MIN ,
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PM_PS_MODE_MAX ,
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PM_PS_MODE_DTIM , /* PS_MODE_SELF_DEFINED */
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PM_PS_MODE_VOIP ,
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PM_PS_MODE_UAPSD_WMM ,
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PM_PS_MODE_UAPSD ,
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PM_PS_MODE_IBSS ,
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PM_PS_MODE_WWLAN ,
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PM_RADIO_OFF ,
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PM_CARD_DISABLE ,
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PM_PS_MODE_NUM,
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};
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enum lps_level {
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LPS_NORMAL = 0,
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LPS_LCLK,
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LPS_PG,
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LPS_LEVEL_MAX,
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};
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/*
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BIT[2:0] = HW state
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BIT[3] = Protocol PS state, 0: register active state , 1: register sleep state
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BIT[4] = sub-state
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*/
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#define PS_DPS BIT(0)
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#define PS_LCLK (PS_DPS)
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#define PS_RF_OFF BIT(1)
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#define PS_ALL_ON BIT(2)
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#define PS_ST_ACTIVE BIT(3)
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#define PS_ISR_ENABLE BIT(4)
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#define PS_IMR_ENABLE BIT(5)
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#define PS_ACK BIT(6)
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#define PS_TOGGLE BIT(7)
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#define PS_STATE_MASK (0x0F)
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#define PS_STATE_HW_MASK (0x07)
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#define PS_SEQ_MASK (0xc0)
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#define PS_STATE(x) (PS_STATE_MASK & (x))
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#define PS_STATE_HW(x) (PS_STATE_HW_MASK & (x))
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#define PS_SEQ(x) (PS_SEQ_MASK & (x))
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#define PS_STATE_S0 (PS_DPS)
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#define PS_STATE_S1 (PS_LCLK)
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#define PS_STATE_S2 (PS_RF_OFF)
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#define PS_STATE_S3 (PS_ALL_ON)
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#define PS_STATE_S4 ((PS_ST_ACTIVE) | (PS_ALL_ON))
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#define PS_IS_RF_ON(x) ((x) & (PS_ALL_ON))
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#define PS_IS_ACTIVE(x) ((x) & (PS_ST_ACTIVE))
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#define CLR_PS_STATE(x) ((x) = ((x) & (0xF0)))
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struct reportpwrstate_parm {
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unsigned char mode;
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unsigned char state; /* the CPWM value */
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unsigned short rsvd;
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};
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typedef _sema _pwrlock;
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__inline static void _init_pwrlock(_pwrlock *plock)
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{
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_rtw_init_sema(plock, 1);
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}
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__inline static void _free_pwrlock(_pwrlock *plock)
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{
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_rtw_free_sema(plock);
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}
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__inline static void _enter_pwrlock(_pwrlock *plock)
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{
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_rtw_down_sema(plock);
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}
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__inline static void _exit_pwrlock(_pwrlock *plock)
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{
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_rtw_up_sema(plock);
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}
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#define LPS_DELAY_MS 1000 /* 1 sec */
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#define EXE_PWR_NONE 0x01
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#define EXE_PWR_IPS 0x02
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#define EXE_PWR_LPS 0x04
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/* RF state. */
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typedef enum _rt_rf_power_state {
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rf_on, /* RF is on after RFSleep or RFOff */
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rf_sleep, /* 802.11 Power Save mode */
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rf_off, /* HW/SW Radio OFF or Inactive Power Save */
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/* =====Add the new RF state above this line===== */
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rf_max
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} rt_rf_power_state;
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/* ASPM OSC Control bit, added by Roger, 2013.03.29. */
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#define RT_PCI_ASPM_OSC_IGNORE 0 /* PCI ASPM ignore OSC control in default */
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#define RT_PCI_ASPM_OSC_ENABLE BIT0 /* PCI ASPM controlled by OS according to ACPI Spec 5.0 */
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#define RT_PCI_ASPM_OSC_DISABLE BIT1 /* PCI ASPM controlled by driver or BIOS, i.e., force enable ASPM */
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enum _PS_BBRegBackup_ {
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PSBBREG_RF0 = 0,
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PSBBREG_RF1,
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PSBBREG_RF2,
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PSBBREG_AFE0,
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PSBBREG_TOTALCNT
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};
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enum { /* for ips_mode */
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IPS_NONE = 0,
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IPS_NORMAL,
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IPS_LEVEL_2,
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IPS_NUM
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};
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/* Design for pwrctrl_priv.ips_deny, 32 bits for 32 reasons at most */
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typedef enum _PS_DENY_REASON {
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PS_DENY_DRV_INITIAL = 0,
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PS_DENY_SCAN,
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PS_DENY_JOIN,
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PS_DENY_DISCONNECT,
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PS_DENY_SUSPEND,
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PS_DENY_IOCTL,
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PS_DENY_MGNT_TX,
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PS_DENY_MONITOR_MODE,
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PS_DENY_BEAMFORMING, /* Beamforming */
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PS_DENY_DRV_REMOVE = 30,
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PS_DENY_OTHERS = 31
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} PS_DENY_REASON;
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struct rsvd_page_cache_t;
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struct pwrctrl_priv {
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_pwrlock lock;
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_pwrlock check_32k_lock;
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volatile u8 rpwm; /* requested power state for fw */
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volatile u8 cpwm; /* fw current power state. updated when 1. read from HCPWM 2. driver lowers power level */
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volatile u8 tog; /* toggling */
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volatile u8 cpwm_tog; /* toggling */
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u8 rpwm_retry;
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u8 pwr_mode;
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u8 smart_ps;
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u8 bcn_ant_mode;
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u8 dtim;
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#ifdef CONFIG_LPS_CHK_BY_TP
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u8 lps_chk_by_tp;
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u16 lps_tx_tp_th;/*Mbps*/
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u16 lps_rx_tp_th;/*Mbps*/
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u16 lps_bi_tp_th;/*Mbps*//*TRX TP*/
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int lps_chk_cnt_th;
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int lps_chk_cnt;
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u32 lps_tx_pkts;
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u32 lps_rx_pkts;
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#endif
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#ifdef CONFIG_WMMPS_STA
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u8 wmm_smart_ps;
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#endif /* CONFIG_WMMPS_STA */
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u32 alives;
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_workitem cpwm_event;
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_workitem dma_event; /*for handle un-synchronized tx dma*/
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#ifdef CONFIG_LPS_RPWM_TIMER
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u8 brpwmtimeout;
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_workitem rpwmtimeoutwi;
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_timer pwr_rpwm_timer;
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#endif /* CONFIG_LPS_RPWM_TIMER */
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u8 bpower_saving; /* for LPS/IPS */
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u8 b_hw_radio_off;
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u8 reg_rfoff;
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u8 reg_pdnmode; /* powerdown mode */
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u32 rfoff_reason;
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uint ips_enter_cnts;
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uint ips_leave_cnts;
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uint lps_enter_cnts;
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uint lps_leave_cnts;
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u8 ips_mode;
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u8 ips_org_mode;
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u8 ips_mode_req; /* used to accept the mode setting request, will update to ipsmode later */
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uint bips_processing;
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systime ips_deny_time; /* will deny IPS when system time is smaller than this */
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u8 pre_ips_type;/* 0: default flow, 1: carddisbale flow */
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/* ps_deny: if 0, power save is free to go; otherwise deny all kinds of power save. */
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/* Use PS_DENY_REASON to decide reason. */
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/* Don't access this variable directly without control function, */
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/* and this variable should be protected by lock. */
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u32 ps_deny;
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u8 ps_processing; /* temporarily used to mark whether in rtw_ps_processor */
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u8 fw_psmode_iface_id;
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u8 bLeisurePs;
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u8 LpsIdleCount;
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u8 power_mgnt;
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u8 org_power_mgnt;
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u8 bFwCurrentInPSMode;
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systime lps_deny_time; /* will deny LPS when system time is smaller than this */
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s32 pnp_current_pwr_state;
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u8 pnp_bstop_trx;
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u8 bInSuspend;
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#ifdef CONFIG_BTC
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u8 bAutoResume;
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u8 autopm_cnt;
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#endif
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u8 bSupportRemoteWakeup;
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u8 wowlan_wake_reason;
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u8 wowlan_last_wake_reason;
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u8 wowlan_ap_mode;
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u8 wowlan_mode;
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u8 wowlan_p2p_mode;
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u8 wowlan_pno_enable;
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u8 wowlan_in_resume;
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#ifdef CONFIG_GPIO_WAKEUP
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#endif /* CONFIG_GPIO_WAKEUP */
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u8 hst2dev_high_active;
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#ifdef CONFIG_WOWLAN
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#ifdef CONFIG_IPV6
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u8 wowlan_ns_offload_en;
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#endif /*CONFIG_IPV6*/
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u8 wowlan_txpause_status;
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u8 wowlan_pattern_idx;
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u64 wowlan_fw_iv;
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struct rtl_priv_pattern patterns[MAX_WKFM_CAM_NUM];
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_mutex wowlan_pattern_cam_mutex;
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u8 wowlan_aoac_rpt_loc;
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struct aoac_report wowlan_aoac_rpt;
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u8 wowlan_power_mgmt;
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u8 wowlan_lps_level;
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#ifdef CONFIG_LPS_1T1R
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u8 wowlan_lps_1t1r;
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#endif
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#endif /* CONFIG_WOWLAN */
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_timer pwr_state_check_timer;
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int pwr_state_check_interval;
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u8 pwr_state_check_cnts;
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rt_rf_power_state rf_pwrstate;/* cur power state, only for IPS */
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/* rt_rf_power_state current_rfpwrstate; */
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rt_rf_power_state change_rfpwrstate;
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u8 bkeepfwalive;
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u8 brfoffbyhw;
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unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT];
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#ifdef CONFIG_RESUME_IN_WORKQUEUE
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struct workqueue_struct *rtw_workqueue;
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_workitem resume_work;
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#endif
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#ifdef CONFIG_HAS_EARLYSUSPEND
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struct early_suspend early_suspend;
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u8 do_late_resume;
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#endif /* CONFIG_HAS_EARLYSUSPEND */
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#ifdef CONFIG_ANDROID_POWER
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android_early_suspend_t early_suspend;
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u8 do_late_resume;
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#endif
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u8 lps_level_bk;
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u8 lps_level; /*LPS_NORMAL,LPA_CG,LPS_PG*/
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#ifdef CONFIG_LPS_1T1R
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u8 lps_1t1r_bk;
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u8 lps_1t1r;
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#endif
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#ifdef CONFIG_LPS_PG
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struct rsvd_page_cache_t lpspg_info;
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#ifdef CONFIG_RTL8822C
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struct rsvd_page_cache_t lpspg_dpk_info;
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struct rsvd_page_cache_t lpspg_iqk_info;
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#endif
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#endif
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u8 current_lps_hw_port_id;
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#ifdef CONFIG_RTW_CFGVENDOR_LLSTATS
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systime radio_on_start_time;
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systime pwr_saving_start_time;
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u32 pwr_saving_time;
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u32 on_time;
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u32 tx_time;
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u32 rx_time;
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#endif /* CONFIG_RTW_CFGVENDOR_LLSTATS */
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#ifdef CONFIG_LPS_ACK
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struct submit_ctx lps_ack_sctx;
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s8 lps_ack_status;
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_mutex lps_ack_mutex;
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#endif /* CONFIG_LPS_ACK */
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};
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#define rtw_get_ips_mode_req(pwrctl) \
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(pwrctl)->ips_mode_req
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#define rtw_ips_mode_req(pwrctl, ips_mode) \
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(pwrctl)->ips_mode_req = (ips_mode)
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#define RTW_PWR_STATE_CHK_INTERVAL 2000
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#ifdef CONFIG_RTW_IPS
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bool rtw_core_set_ips_state(void *drv_priv, enum rtw_rf_state state);
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#endif
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#ifdef CONFIG_POWER_SAVING
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#define _rtw_set_pwr_state_check_timer(pwrctl, ms) \
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do { \
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/*RTW_INFO("%s _rtw_set_pwr_state_check_timer(%p, %d)\n", __FUNCTION__, (pwrctl), (ms));*/ \
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_set_timer(&(pwrctl)->pwr_state_check_timer, (ms)); \
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} while (0)
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#define rtw_set_pwr_state_check_timer(pwrctl) \
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_rtw_set_pwr_state_check_timer((pwrctl), (pwrctl)->pwr_state_check_interval)
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#endif
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extern void rtw_init_pwrctrl_priv(_adapter *adapter);
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extern void rtw_free_pwrctrl_priv(_adapter *adapter);
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#ifdef CONFIG_LPS_LCLK
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s32 rtw_register_task_alive(_adapter *, u32 task);
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void rtw_unregister_task_alive(_adapter *, u32 task);
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extern s32 rtw_register_tx_alive(_adapter *padapter);
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extern void rtw_unregister_tx_alive(_adapter *padapter);
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extern s32 rtw_register_rx_alive(_adapter *padapter);
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extern void rtw_unregister_rx_alive(_adapter *padapter);
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#if 0 /*#ifdef CONFIG_CORE_CMD_THREAD*/
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extern s32 rtw_register_cmd_alive(_adapter *padapter);
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extern void rtw_unregister_cmd_alive(_adapter *padapter);
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#endif
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extern void cpwm_int_hdl(_adapter *padapter, struct reportpwrstate_parm *preportpwrstate);
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extern void LPS_Leave_check(_adapter *padapter);
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#endif
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extern void LeaveAllPowerSaveMode(_adapter *adapter);
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extern void LeaveAllPowerSaveModeDirect(_adapter *adapter);
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#ifdef CONFIG_IPS
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void _ips_enter(_adapter *padapter);
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void ips_enter(_adapter *padapter);
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int _ips_leave(_adapter *padapter);
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int ips_leave(_adapter *padapter);
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#endif
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#ifdef CONFIG_POWER_SAVING
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void rtw_ps_processor(_adapter *padapter);
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#endif
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#ifdef DBG_CHECK_FW_PS_STATE
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int rtw_fw_ps_state(_adapter *padapter);
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#endif
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#ifdef CONFIG_LPS
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extern const char * const LPS_CTRL_PHYDM;
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void LPS_Enter(_adapter *padapter, const char *msg);
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void LPS_Leave(_adapter *padapter, const char *msg);
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void rtw_leave_lps_and_chk(_adapter *padapter, u8 ps_mode);
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#ifdef CONFIG_CHECK_LEAVE_LPS
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#ifdef CONFIG_LPS_CHK_BY_TP
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void traffic_check_for_leave_lps_by_tp(_adapter *padapter, u8 tx, struct sta_info *sta);
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#endif
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void traffic_check_for_leave_lps(_adapter *padapter, u8 tx, u32 tx_packets);
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#endif /*CONFIG_CHECK_LEAVE_LPS*/
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void rtw_set_ps_mode(_adapter *padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg);
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u8 rtw_set_rpwm(_adapter *padapter, u8 val8);
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#endif /* CONFIG_LPS */
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#ifdef CONFIG_RESUME_IN_WORKQUEUE
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void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv);
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#endif /* CONFIG_RESUME_IN_WORKQUEUE */
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#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
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bool rtw_is_earlysuspend_registered(struct pwrctrl_priv *pwrpriv);
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bool rtw_is_do_late_resume(struct pwrctrl_priv *pwrpriv);
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void rtw_set_do_late_resume(struct pwrctrl_priv *pwrpriv, bool enable);
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void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv);
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void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv);
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#else
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#define rtw_is_earlysuspend_registered(pwrpriv) _FALSE
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#define rtw_is_do_late_resume(pwrpriv) _FALSE
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#define rtw_set_do_late_resume(pwrpriv, enable) do {} while (0)
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#define rtw_register_early_suspend(pwrpriv) do {} while (0)
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#define rtw_unregister_early_suspend(pwrpriv) do {} while (0)
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#endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */
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void rtw_set_ips_deny(_adapter *padapter, u32 ms);
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int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller);
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#define rtw_pwr_wakeup(adapter) _rtw_pwr_wakeup(adapter, RTW_PWR_STATE_CHK_INTERVAL, __FUNCTION__)
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#define rtw_pwr_wakeup_ex(adapter, ips_deffer_ms) _rtw_pwr_wakeup(adapter, ips_deffer_ms, __FUNCTION__)
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int rtw_pm_set_ips(_adapter *padapter, u8 mode);
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int rtw_pm_set_lps(_adapter *padapter, u8 mode);
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int rtw_pm_set_lps_level(_adapter *padapter, u8 level);
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#ifdef CONFIG_LPS_1T1R
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int rtw_pm_set_lps_1t1r(_adapter *padapter, u8 en);
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#endif
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void rtw_set_lps_deny(_adapter *adapter, u32 ms);
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void rtw_ps_deny(_adapter *padapter, PS_DENY_REASON reason);
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void rtw_ps_deny_cancel(_adapter *padapter, PS_DENY_REASON reason);
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u32 rtw_ps_deny_get(_adapter *padapter);
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void rtw_ssmps_enter(_adapter *adapter, struct sta_info *sta);
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void rtw_ssmps_leave(_adapter *adapter, struct sta_info *sta);
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#endif /* __RTL871X_PWRCTRL_H_ */
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