/**
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****************************************************************************************
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*
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* @file rwnx_prof.h
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*
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* Copyright (C) RivieraWaves 2012-2019
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*
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****************************************************************************************
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*/
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#ifndef _RWNX_PROF_H_
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#define _RWNX_PROF_H_
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#include "reg_access.h"
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#include "rwnx_platform.h"
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static inline void rwnx_prof_set(struct rwnx_hw *rwnx_hw, int val)
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{
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struct rwnx_plat *rwnx_plat = rwnx_hw->plat;
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RWNX_REG_WRITE(val, rwnx_plat, RWNX_ADDR_SYSTEM, NXMAC_SW_SET_PROFILING_ADDR);
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}
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static inline void rwnx_prof_clear(struct rwnx_hw *rwnx_hw, int val)
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{
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struct rwnx_plat *rwnx_plat = rwnx_hw->plat;
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RWNX_REG_WRITE(val, rwnx_plat, RWNX_ADDR_SYSTEM, NXMAC_SW_CLEAR_PROFILING_ADDR);
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}
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#if 0
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/* Defines for SW Profiling registers values */
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enum {
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TX_IPC_IRQ,
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TX_IPC_EVT,
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TX_PREP_EVT,
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TX_DMA_IRQ,
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TX_MAC_IRQ,
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TX_PAYL_HDL,
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TX_CFM_EVT,
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TX_IPC_CFM,
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RX_MAC_IRQ, // 8
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RX_TRIGGER_EVT,
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RX_DMA_IRQ,
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RX_DMA_EVT,
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RX_IPC_IND,
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RX_MPDU_XFER,
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DBG_PROF_MAX
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};
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#endif
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enum {
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SW_PROF_HOSTBUF_IDX = 12,
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/****** IPC IRQs related signals ******/
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/* E2A direction */
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SW_PROF_IRQ_E2A_RXDESC = 16, // to make sure we let 16 bits available for LMAC FW
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SW_PROF_IRQ_E2A_TXCFM,
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SW_PROF_IRQ_E2A_DBG,
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SW_PROF_IRQ_E2A_MSG,
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SW_PROF_IPC_MSGPUSH,
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SW_PROF_MSGALLOC,
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SW_PROF_MSGIND,
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SW_PROF_DBGIND,
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/* A2E direction */
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SW_PROF_IRQ_A2E_TXCFM_BACK,
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/****** Driver functions related signals ******/
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SW_PROF_WAIT_QUEUE_STOP,
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SW_PROF_WAIT_QUEUE_WAKEUP,
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SW_PROF_RWNXDATAIND,
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SW_PROF_RWNX_IPC_IRQ_HDLR,
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SW_PROF_RWNX_IPC_THR_IRQ_HDLR,
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SW_PROF_IEEE80211RX,
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SW_PROF_RWNX_PATTERN,
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SW_PROF_MAX
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};
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// [LT]For debug purpose only
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#if (0)
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#define SW_PROF_CHAN_CTXT_CFM_HDL_BIT (21)
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#define SW_PROF_CHAN_CTXT_CFM_BIT (22)
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#define SW_PROF_CHAN_CTXT_CFM_SWDONE_BIT (23)
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#define SW_PROF_CHAN_CTXT_PUSH_BIT (24)
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#define SW_PROF_CHAN_CTXT_QUEUE_BIT (25)
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#define SW_PROF_CHAN_CTXT_TX_BIT (26)
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#define SW_PROF_CHAN_CTXT_TX_PAUSE_BIT (27)
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#define SW_PROF_CHAN_CTXT_PSWTCH_BIT (28)
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#define SW_PROF_CHAN_CTXT_SWTCH_BIT (29)
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// TO DO: update this
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#define REG_SW_SET_PROFILING_CHAN(env, bit) \
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rwnx_prof_set((struct rwnx_hw *)env, BIT(bit))
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#define REG_SW_CLEAR_PROFILING_CHAN(env, bit) \
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rwnx_prof_clear((struct rwnx_hw *)env, BIT(bit))
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#else
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#define SW_PROF_CHAN_CTXT_CFM_HDL_BIT (0)
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#define SW_PROF_CHAN_CTXT_CFM_BIT (0)
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#define SW_PROF_CHAN_CTXT_CFM_SWDONE_BIT (0)
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#define SW_PROF_CHAN_CTXT_PUSH_BIT (0)
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#define SW_PROF_CHAN_CTXT_QUEUE_BIT (0)
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#define SW_PROF_CHAN_CTXT_TX_BIT (0)
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#define SW_PROF_CHAN_CTXT_TX_PAUSE_BIT (0)
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#define SW_PROF_CHAN_CTXT_PSWTCH_BIT (0)
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#define SW_PROF_CHAN_CTXT_SWTCH_BIT (0)
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#define REG_SW_SET_PROFILING_CHAN(env, bit) do {} while (0)
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#define REG_SW_CLEAR_PROFILING_CHAN(env, bit) do {} while (0)
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#endif
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#ifdef CONFIG_RWNX_SW_PROFILING
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/* Macros for SW PRofiling registers access */
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#define REG_SW_SET_PROFILING(env, bit) \
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rwnx_prof_set((struct rwnx_hw *)env, BIT(bit))
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#define REG_SW_SET_HOSTBUF_IDX_PROFILING(env, val) \
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rwnx_prof_set((struct rwnx_hw *)env, val << (SW_PROF_HOSTBUF_IDX))
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#define REG_SW_CLEAR_PROFILING(env, bit) \
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rwnx_prof_clear((struct rwnx_hw *)env, BIT(bit))
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#define REG_SW_CLEAR_HOSTBUF_IDX_PROFILING(env) \
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rwnx_prof_clear((struct rwnx_hw *)env, 0x0F << (SW_PROF_HOSTBUF_IDX))
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#else
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#define REG_SW_SET_PROFILING(env, value) do {} while (0)
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#define REG_SW_CLEAR_PROFILING(env, value) do {} while (0)
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#define REG_SW_SET_HOSTBUF_IDX_PROFILING(env, val) do {} while (0)
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#define REG_SW_CLEAR_HOSTBUF_IDX_PROFILING(env) do {} while (0)
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#endif
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#endif /* _RWNX_PROF_H_ */
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