/** @file
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Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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/*
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* This file contains the assembler code to instantiate a set of stage 2
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* translation tables that make the ECAM space of the Synopsys DesignWare
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* PCIe root complexes appear sane to the OS.
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* - ECAM 'shadows' caused by non TLP filtering root ports are eliminated
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* - MMIO region are mapped with device attributes that supersede write combine
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* attributes that the OS may attempt to use, and which is not supported by
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* the SoC.
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*/
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#define TT_S2_CONT_SHIFT 52
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#define TT_S2_AF (0x1 << 10)
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#define TT_S2_SH_NON_SHAREABLE (0x0 << 8)
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#define TT_S2_AP_RO (0x1 << 6)
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#define TT_S2_AP_RW (0x3 << 6)
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#define TT_S2_MEMATTR_DEVICE_nGRE (0x2 << 2)
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#define TT_S2_MEMATTR_DEVICE_nGnRE (0x1 << 2)
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#define TT_S2_MEMATTR_MEMORY_WB (0xf << 2)
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#define TT_S2_TABLE (0x3 << 0)
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#define TT_S2_L3_PAGE (0x1 << 1)
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#define TT_S2_VALID (0x1 << 0)
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#ifdef __aarch64__
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#define QWORD(x) .quad (x)
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#else
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#define QWORD(x) .long (x), 0
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#endif
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.altmacro
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.macro for, start, count, do, arg2, arg3, arg4
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.if \count == 1
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\do \start, \arg2, \arg3, \arg4
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.elseif \count > 1
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for \start, %(\count / 2), \do, \arg2, \arg3, \arg4
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for %(\start + \count / 2), %((\count + 1) / 2), \do, \arg2, \arg3, \arg4
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.endif
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.endm
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.macro s2_dev_entry, base, shift=30, offset=0, cont=0
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.quad ((\base << \shift) + \offset) | TT_S2_AF | TT_S2_AP_RW | \
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TT_S2_SH_NON_SHAREABLE | TT_S2_MEMATTR_DEVICE_nGRE | \
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TT_S2_VALID | (\cont << TT_S2_CONT_SHIFT)
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.endm
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.macro s2_mem_entry, base, shift=30, offset=0, cont=0
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.quad ((\base << \shift) + \offset) | TT_S2_AF | TT_S2_AP_RW | \
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TT_S2_SH_NON_SHAREABLE | TT_S2_MEMATTR_MEMORY_WB | \
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TT_S2_VALID | (\cont << TT_S2_CONT_SHIFT)
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.endm
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.macro s2_l3_entry, base, offset=0, cont=0
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.quad ((\base << 12) + \offset) | TT_S2_AF | TT_S2_AP_RW | \
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TT_S2_SH_NON_SHAREABLE | TT_S2_MEMATTR_MEMORY_WB | \
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TT_S2_L3_PAGE | TT_S2_VALID | (\cont << TT_S2_CONT_SHIFT)
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.endm
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.macro smmu_l3_entry, base, offset=0, ignore=0
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.quad ((\base << 12) + \offset) | TT_S2_AF | TT_S2_AP_RO | \
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TT_S2_SH_NON_SHAREABLE | TT_S2_MEMATTR_DEVICE_nGnRE | \
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TT_S2_L3_PAGE | TT_S2_VALID
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.endm
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.section ".rodata", "a", %progbits
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/* level 1 */
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s2_mem_entry 0 /* 0x0000_0000 - 0x3fff_ffff */
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QWORD (1f + TT_S2_TABLE) /* 0x4000_0000 - 0x7fff_ffff */
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for 2, 246, s2_mem_entry /* 0x8000_0000 - 0x3d_ffff_ffff */
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for 248, 8, s2_dev_entry /* PCIe MMIO64 */
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for 256, 768, s2_mem_entry /* 0x40_0000_0000 - 0xff_ffff_ffff */
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/* level 2 */
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1:for 0, 256, s2_mem_entry, 21, 0x40000000, 1
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QWORD (2f + TT_S2_TABLE) /* 0x6000_0000 -> RC #0 bus 0 */
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for 1, 15, s2_mem_entry, 21, 0x60000000
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for 0, 48, s2_mem_entry, 21, 0x62000000, 1
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for 0, 64, s2_dev_entry, 21, 0x68000000, 1 /* PCIe MMIO32 */
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QWORD (3f + TT_S2_TABLE) /* 0x7000_0000 -> RC #1 bus 0 */
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for 1, 15, s2_mem_entry, 21, 0x70000000
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for 0, 48, s2_mem_entry, 21, 0x72000000, 1
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for 0, 64, s2_dev_entry, 21, 0x78000000, 1 /* PCIe MMIO32 */
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/* level 3 */
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2:for 0, 8, s2_l3_entry, 0x60000000
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for 0, 8, s2_l3_entry, 0x60010000 /* hide device #1 */
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for 0, 496, s2_l3_entry, 0x60010000, 1
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3:for 0, 8, s2_l3_entry, 0x70000000
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for 0, 8, s2_l3_entry, 0x70010000 /* hide device #1 */
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for 0, 496, s2_l3_entry, 0x70010000, 1
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/* level 3 for north SMMU */
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.org 0x6000
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for 0, 8, smmu_l3_entry, 0xc00060000000
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for 0, 8, smmu_l3_entry, 0xc00060010000 /* hide device #1 */
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for 0, 496, smmu_l3_entry, 0xc00060010000
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for 0, 8, smmu_l3_entry, 0x800070000000
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for 0, 8, smmu_l3_entry, 0x800070010000 /* hide device #1 */
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for 0, 496, smmu_l3_entry, 0x800070010000
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