/** @file
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Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __SYNQUACER_I2C_DXE_H__
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#define __SYNQUACER_I2C_DXE_H__
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#include <PiDxe.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/DevicePathLib.h>
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#include <Library/DxeServicesTableLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/UefiLib.h>
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#include <Library/UefiRuntimeLib.h>
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#include <Protocol/I2cMaster.h>
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#include <Protocol/NonDiscoverableDevice.h>
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extern EFI_COMPONENT_NAME2_PROTOCOL gSynQuacerI2cDriverComponentName2;
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#define SYNQUACER_I2C_SIGNATURE SIGNATURE_32 ('S', 'I', '2', 'C')
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#define SYNQUACER_I2C_FROM_THIS(a) CR ((a), SYNQUACER_I2C_MASTER, \
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I2cMaster, SYNQUACER_I2C_SIGNATURE)
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#pragma pack(1)
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typedef struct {
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VENDOR_DEVICE_PATH Vendor;
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UINT64 MmioBase;
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EFI_DEVICE_PATH_PROTOCOL End;
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} SYNQUACER_I2C_DEVICE_PATH;
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#pragma pack()
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typedef struct {
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UINT32 Signature;
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EFI_I2C_MASTER_PROTOCOL I2cMaster;
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EFI_PHYSICAL_ADDRESS MmioBase;
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SYNQUACER_I2C_DEVICE_PATH DevicePath;
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NON_DISCOVERABLE_DEVICE *Dev;
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EFI_EVENT VirtualAddressChangeEvent;
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BOOLEAN Runtime;
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} SYNQUACER_I2C_MASTER;
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EFI_STATUS
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SynQuacerI2cInit (
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IN EFI_HANDLE DriverBindingHandle,
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IN EFI_HANDLE ControllerHandle
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);
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EFI_STATUS
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SynQuacerI2cRelease (
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IN EFI_HANDLE DriverBindingHandle,
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IN EFI_HANDLE ControllerHandle
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);
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#define REFCLK_RATE FixedPcdGet32 (PcdI2cReferenceClock)
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#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
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#define F_I2C_SPEED_SM 100000
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#define F_I2C_SPEED_FM 400000
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// I2C register adress definitions
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#define F_I2C_REG_BSR (0x00 << 2) // Bus Status Regster
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#define F_I2C_REG_BCR (0x01 << 2) // Bus Control Register
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#define F_I2C_REG_CCR (0x02 << 2) // Clock Control Register
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#define F_I2C_REG_ADR (0x03 << 2) // Address Register
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#define F_I2C_REG_DAR (0x04 << 2) // Data Register
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#define F_I2C_REG_CSR (0x05 << 2) // Expansion CS Register
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#define F_I2C_REG_FSR (0x06 << 2) // Bus Clock Frequency Register
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#define F_I2C_REG_BC2R (0x07 << 2) // Bus Control 2 Register
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// I2C register bit definitions
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#define F_I2C_BSR_FBT BIT0 // First Byte Transfer
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#define F_I2C_BSR_GCA BIT1 // General Call Address
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#define F_I2C_BSR_AAS BIT2 // Address as Slave
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#define F_I2C_BSR_TRX BIT3 // Transfer/Receive
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#define F_I2C_BSR_LRB BIT4 // Last Received Bit
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#define F_I2C_BSR_AL BIT5 // Arbitration Lost
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#define F_I2C_BSR_RSC BIT6 // Repeated Start Condition
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#define F_I2C_BSR_BB BIT7 // Bus Busy
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#define F_I2C_BCR_INT BIT0 // Interrupt
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#define F_I2C_BCR_INTE BIT1 // Interrupt Enable
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#define F_I2C_BCR_GCAA BIT2 // General Call Access Acknowledge
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#define F_I2C_BCR_ACK BIT3 // Acknowledge
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#define F_I2C_BCR_MSS BIT4 // Master Slave Select
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#define F_I2C_BCR_SCC BIT5 // Start Condition Continue
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#define F_I2C_BCR_BEIE BIT6 // Bus Error Interrupt Enable
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#define F_I2C_BCR_BER BIT7 // Bus Error
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#define F_I2C_CCR_CS_MASK 0x1f // CCR Clock Period Select
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#define F_I2C_CCR_EN BIT5 // Enable
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#define F_I2C_CCR_FM BIT6 // Speed Mode Select
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#define F_I2C_CSR_CS_MASK 0x3f // CSR Clock Period Select
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#define F_I2C_BC2R_SCLL BIT0 // SCL Low Drive
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#define F_I2C_BC2R_SDAL BIT1 // SDA Low Drive
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#define F_I2C_BC2R_SCLS BIT4 // SCL Status
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#define F_I2C_BC2R_SDAS BIT5 // SDA Status
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// PCLK frequency
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#define F_I2C_BUS_CLK_FR(rate) ((rate) / 20000000 + 1)
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#define F_I2C_MIN_CLK_RATE (14 * 1000000) // min frequency 14 MHz
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#define F_I2C_MAX_CLK_RATE (200 * 1000000) // max frequency 200 MHz
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#define F_I2C_CLK_RATE_18M (18 * 1000000) // threshold freq 18 MHz
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// STANDARD MODE frequency
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#define F_I2C_CLK_MASTER_STANDARD(rate) \
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DIV_ROUND_UP (DIV_ROUND_UP ((rate), 100000) - 2, 2)
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// FAST MODE frequency
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#define F_I2C_CLK_MASTER_FAST(rate) \
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DIV_ROUND_UP ((DIV_ROUND_UP ((rate), 400000) - 2) * 2, 3)
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// (clkrate <= 18000000)
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// calculate the value of CS bits in CCR register in standard mode
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#define F_I2C_CCR_CS_STANDARD_MAX_18M(rate) \
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((F_I2C_CLK_MASTER_STANDARD (rate) - 65) & F_I2C_CCR_CS_MASK)
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// calculate the value of CS bits in CSR register in standard mode
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#define F_I2C_CSR_CS_STANDARD_MAX_18M(rate) 0x00
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// calculate the value of CS bits in CCR register in fast mode
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#define F_I2C_CCR_CS_FAST_MAX_18M(rate) \
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((F_I2C_CLK_MASTER_FAST (rate) - 1) & F_I2C_CCR_CS_MASK)
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// calculate the value of CS bits in CSR register in fast mode
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#define F_I2C_CSR_CS_FAST_MAX_18M(rate) 0x00
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// (clkrate > 18000000)
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// calculate the value of CS bits in CCR register in standard mode */
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#define F_I2C_CCR_CS_STANDARD_MIN_18M(rate) \
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((F_I2C_CLK_MASTER_STANDARD (rate) - 1) & F_I2C_CCR_CS_MASK)
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// calculate the value of CS bits in CSR register in standard mode
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#define F_I2C_CSR_CS_STANDARD_MIN_18M(rate) \
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(((F_I2C_CLK_MASTER_STANDARD (rate) - 1) >> 5) & F_I2C_CSR_CS_MASK)
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// calculate the value of CS bits in CCR register in fast mode
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#define F_I2C_CCR_CS_FAST_MIN_18M(rate) \
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((F_I2C_CLK_MASTER_FAST (rate) - 1) & F_I2C_CCR_CS_MASK)
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/* calculate the value of CS bits in CSR register in fast mode */
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#define F_I2C_CSR_CS_FAST_MIN_18M(rate) \
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(((F_I2C_CLK_MASTER_FAST (rate) - 1) >> 5) & F_I2C_CSR_CS_MASK)
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#endif
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