/** @file
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SynQuacer DXE platform driver - PCIe support
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Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PlatformDxe.h"
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#define ASMEDIA_VID 0x1b21
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#define ASM1061_PID 0x0612
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#define ASM1182E_PID 0x1182
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#define ASM1184E_PID 0x1184
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#define ASM1061_SSC_OFFSET 0xA10
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#define ASM118x_PCIE_CAPABILITY_OFFSET 0x80
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#define ASM118x_PCIE_LINK_CONTROL_OFFSET (ASM118x_PCIE_CAPABILITY_OFFSET + \
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OFFSET_OF (PCI_CAPABILITY_PCIEXP, \
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LinkControl))
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STATIC VOID *mPciProtocolNotifyRegistration;
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STATIC EFI_EVENT mPciProtocolNotifyEvent;
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#pragma pack(1)
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typedef struct {
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EFI_PCI_CAPABILITY_HDR CapHdr;
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PCI_REG_PCIE_CAPABILITY Pcie;
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} PCIE_CAP;
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#pragma pack()
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STATIC
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VOID
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RetrainAsm1184eDownstreamPort (
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IN EFI_PCI_IO_PROTOCOL *PciIo
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)
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{
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EFI_STATUS Status;
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PCIE_CAP Cap;
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PCI_REG_PCIE_LINK_CONTROL LinkControl;
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UINTN SegmentNumber;
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UINTN BusNumber;
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UINTN DeviceNumber;
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UINTN FunctionNumber;
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UINT8 MaxSpeed;
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//
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// The upstream and downstream ports share the same PID/VID, so check
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// the port type. This assumes the PCIe Express capability block lives
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// at offset 0x80 in the port's config space, which is known to be the
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// case for these particular chips.
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//
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ASSERT (sizeof (Cap) == sizeof (UINT32));
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ASSERT (sizeof (LinkControl) == sizeof (UINT16));
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Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32,
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ASM118x_PCIE_CAPABILITY_OFFSET, 1, &Cap);
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ASSERT_EFI_ERROR (Status);
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ASSERT (Cap.CapHdr.CapabilityID == EFI_PCI_CAPABILITY_ID_PCIEXP);
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if (Cap.Pcie.Bits.DevicePortType != PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT) {
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return;
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}
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Status = PciIo->GetLocation (PciIo, &SegmentNumber, &BusNumber, &DeviceNumber,
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&FunctionNumber);
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ASSERT_EFI_ERROR (Status);
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//
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// Check whether this downstream port is described by any of our 'slot'
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// definitions, and get the maximum speed if this is the case.
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//
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switch (SYNQUACER_PCI_LOCATION (SegmentNumber, BusNumber, DeviceNumber)) {
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case SYNQUACER_PCI_SLOT0_LOCATION:
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MaxSpeed = mHiiSettings->PcieSlot0MaxSpeed;
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break;
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case SYNQUACER_PCI_SLOT1_LOCATION:
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MaxSpeed = mHiiSettings->PcieSlot1MaxSpeed;
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break;
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case SYNQUACER_PCI_SLOT2_LOCATION:
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MaxSpeed = mHiiSettings->PcieSlot2MaxSpeed;
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break;
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default:
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MaxSpeed = PCIE_MAX_SPEED_UNLIMITED;
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}
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if (MaxSpeed == PCIE_MAX_SPEED_GEN1) {
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return;
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}
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DEBUG ((DEBUG_INFO,
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"%a: retraining ASM118x downstream PCIe port at %04x:%02x:%02x to Gen2\n",
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__FUNCTION__, SegmentNumber, BusNumber, DeviceNumber));
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Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16,
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ASM118x_PCIE_LINK_CONTROL_OFFSET, 1, &LinkControl);
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ASSERT_EFI_ERROR (Status);
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LinkControl.Bits.RetrainLink = 1;
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Status = PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16,
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ASM118x_PCIE_LINK_CONTROL_OFFSET, 1, &LinkControl);
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ASSERT_EFI_ERROR (Status);
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}
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STATIC
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VOID
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EnableAsm1061SpreadSpectrum (
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IN EFI_PCI_IO_PROTOCOL *PciIo
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)
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{
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EFI_STATUS Status;
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UINT8 SscVal;
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DEBUG ((DEBUG_INFO, "%a: enabling spread spectrum mode 0 for ASM1061\n",
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__FUNCTION__));
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// SSC mode 0~-4000 ppm, 1:1 modulation
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SscVal = 0;
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Status = PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, ASM1061_SSC_OFFSET, 1,
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&SscVal);
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ASSERT_EFI_ERROR (Status);
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MemoryFence ();
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gBS->Stall (1); // delay at least 100 ns between writes of the same register
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SscVal = 1;
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Status = PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, ASM1061_SSC_OFFSET, 1,
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&SscVal);
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ASSERT_EFI_ERROR (Status);
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}
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STATIC
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VOID
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EFIAPI
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OnPciIoProtocolNotify (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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EFI_HANDLE HandleBuffer;
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UINTN BufferSize;
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UINT16 PciVidPid[2];
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while (TRUE) {
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BufferSize = sizeof (EFI_HANDLE);
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Status = gBS->LocateHandle (ByRegisterNotify, NULL,
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mPciProtocolNotifyRegistration, &BufferSize, &HandleBuffer);
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if (EFI_ERROR (Status)) {
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break;
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}
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Status = gBS->HandleProtocol (HandleBuffer, &gEfiPciIoProtocolGuid,
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(VOID **)&PciIo);
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ASSERT_EFI_ERROR (Status);
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Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_VENDOR_ID_OFFSET,
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ARRAY_SIZE (PciVidPid), &PciVidPid);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_WARN, "%a: failed to read PCI vendor/product ID - %r\n",
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__FUNCTION__, Status));
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continue;
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}
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if (PciVidPid[0] != ASMEDIA_VID) {
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continue;
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}
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switch (PciVidPid[1]) {
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case ASM1061_PID:
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//
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// The ASM1061 SATA controller as integrated into the DeveloperBox design
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// emits too much electromagnetic radiation. So enable spread spectrum
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// mode.
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//
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EnableAsm1061SpreadSpectrum (PciIo);
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break;
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case ASM1182E_PID:
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case ASM1184E_PID:
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//
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// The ASM1184E 4-port PCIe switch on the DeveloperBox board (and its
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// 2-port sibling of which samples were used in development) needs a
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// little nudge to get it to train the downstream links at Gen2 speed.
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//
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RetrainAsm1184eDownstreamPort (PciIo);
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break;
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}
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}
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}
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EFI_STATUS
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EFIAPI
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RegisterPcieNotifier (
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VOID
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)
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{
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mPciProtocolNotifyEvent = EfiCreateProtocolNotifyEvent (
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&gEfiPciIoProtocolGuid,
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TPL_CALLBACK,
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OnPciIoProtocolNotify,
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NULL,
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&mPciProtocolNotifyRegistration);
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return EFI_SUCCESS;
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}
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