/** @file
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Socionext FIP006 Register List
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Copyright (c) 2017, Socionext Inc. All rights reserved.<BR>
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Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __EFI_FIP006_REG_H__
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#define __EFI_FIP006_REG_H__
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#define FIP006_REG_MCTRL 0x00 // Module Control
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typedef union {
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UINT32 Raw : 32;
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struct {
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BOOLEAN MEN : 1;
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BOOLEAN CSEN : 1;
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#define MCTRL_CSEN_DIRECT 0
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#define MCTRL_CSEN_CS 1
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BOOLEAN CDSS : 1;
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#define MCTRL_CDSS_IHCLK 0
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#define MCTRL_CDSS_IPCLK 1
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BOOLEAN MES : 1;
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#define MCTRL_MES_READY 1
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UINT8 : 4;
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UINT8 : 8;
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UINT8 : 8;
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UINT8 : 8;
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};
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} FIP006_MCTRL;
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#define FIP006_REG_PCC0 0x04 // Peripheral Communication Control 0
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#define FIP006_REG_PCC1 0x08 // Peripheral Communication Control 1
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#define FIP006_REG_PCC2 0x0C // Peripheral Communication Control 2
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#define FIP006_REG_PCC3 0x10 // Peripheral Communication Control 3
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typedef union {
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UINT32 Raw : 32;
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struct {
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BOOLEAN CPHA : 1;
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BOOLEAN CPOL : 1;
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BOOLEAN ACES : 1;
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BOOLEAN RTM : 1;
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BOOLEAN SSPOL : 1;
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UINT8 SS2CD : 2;
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BOOLEAN SDIR : 1;
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#define PCC_SDIR_MS_BIT 0
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#define PCC_SDIR_LS_BIT 1
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BOOLEAN SENDIAN : 1;
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#define PCC_SENDIAN_BIG 0
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#define PCC_SENDIAN_LITTLE 1
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UINT8 CDRS : 7;
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BOOLEAN SAFESYNC : 1;
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UINT8 WRDSEL : 4;
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UINT8 RDDSEL : 2;
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UINT8 : 1;
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UINT8 : 8;
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} Reg;
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} FIP006_PCC;
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typedef FIP006_PCC FIP006_PCC0, FIP006_PCC1, FIP006_PCC2, FIP006_PCC3;
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#define FIP006_REG_TXF 0x14 // Tx Interrupt Flag
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#define TXF_TSSRS BIT6
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#define TXF_TFMTS BIT5
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#define TXF_TFLETS BIT4
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#define TXF_TFUS BIT3
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#define TXF_TFOS BIT2
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#define TXF_TFES BIT1
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#define TXF_TFFS BIT0
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#define FIP006_REG_TXE 0x18 // Tx Interrupt Enable
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#define TXE_TSSRE BIT6
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#define TXE_TFMTE BIT5
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#define TXE_TFLETE BIT4
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#define TXE_TFUE BIT3
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#define TXE_TFOE BIT2
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#define TXE_TFEE BIT1
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#define TXE_TFFE BIT0
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#define FIP006_REG_TXC 0x1C // Tx Interrupt Clear
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#define TXC_TSSRC BIT6
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#define TXC_TFMTC BIT5
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#define TXC_TFLETC BIT4
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#define TXC_TFUC BIT3
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#define TXC_TFOC BIT2
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#define TXC_TFEC BIT1
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#define TXC_TFFC BIT0
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#define FIP006_REG_RXF 0x20 // Rx Interrupt Flag
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#define RXF_RSSRS BIT6
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#define RXF_RFMTS BIT5
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#define RXF_RFLETS BIT4
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#define RXF_RFUS BIT3
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#define RXF_RFOS BIT2
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#define RXF_RFES BIT1
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#define RXF_RFFS BIT0
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#define FIP006_REG_RXE 0x24 // Rx Interrupt Enable
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#define RXE_RSSRE BIT6
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#define RXE_RFMTE BIT5
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#define RXE_RFLETE BIT4
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#define RXE_RFUE BIT3
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#define RXE_RFOE BIT2
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#define RXE_RFEE BIT1
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#define RXE_RFFE BIT0
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#define FIP006_REG_RXC 0x28 // Rx Interrupt Clear
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#define RXC_RSSRC BIT6
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#define RXC_RFMTC BIT5
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#define RXC_RFLETC BIT4
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#define RXC_RFUC BIT3
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#define RXC_RFOC BIT2
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#define RXC_RFEC BIT1
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#define RXC_RFFC BIT0
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#define FIP006_REG_FAULTF 0x2C // Error Interrupt Status
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#define FAULTF_DRCBSFS BIT4
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#define FAULTF_DWCBSFS BIT3
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#define FAULTF_PVFS BIT2
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#define FAULTF_WAFS BIT1
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#define FAULTF_UMAFS BIT0
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#define FIP006_REG_FAULTC 0x30 // Error Interrupt Clear
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#define FAULTC_DRCBSFC BIT4
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#define FAULTC_DWCBSFC BIT3
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#define FAULTC_PVFC BIT2
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#define FAULTC_WAFC BIT1
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#define FAULTC_UMAFC BIT0
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#define FIP006_REG_DM_CFG 0x34 // Direct Mode DMA Configuration
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#define DM_CFG_MSTARTEN BIT2
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#define DM_CFG_SSDC BIT1
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#define FIP006_REG_DM_DMA 0x35 // Direct Mode DMA Enable
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#define DM_DMA_TXDMAEN BIT1
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#define DM_DMA_RXDMAEN BIT0
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#define FIP006_REG_DM_START 0x38 // Direct Mode Start Transmission
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#define DM_START BIT0
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#define FIP006_REG_DM_STOP 0x39 // Direct Mode Stop Transmission
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#define DM_STOP BIT0
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#define FIP006_REG_DM_PSEL 0x3A // Direct Mode Peripheral Select
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#define DM_PSEL (BIT1 | BIT0)
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#define FIP006_REG_DM_TRP 0x3B // Direct Mode Transmission Protocol
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#define DM_TRP (BIT3 | BIT2 | BIT1 | BIT0)
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#define FIP006_REG_DM_BCC 0x3C // Direct Mode Byte Count Control
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#define FIP006_REG_DM_BCS 0x3E // Direct Mode Byte Count Status
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#define FIP006_REG_DM_STATUS 0x40 // Direct Mode Status
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#define DM_STATUS_TXFLEVEL (BIT20 | BIT19 | BIT18 | BIT17 | BIT16)
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#define DM_STATUS_RXFLEVEL (BIT20 | BIT19 | BIT18 | BIT17 | BIT16)
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#define DM_STATUS_TXACTIVE BIT1
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#define DM_STATUS_RXACTIVE BIT0
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#define FIP006_REG_FIFO_CFG 0x4C // FIFO Configuration
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#define FIFO_CFG_TXFLSH BIT12
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#define FIFO_CFG_RXFLSH BIT11
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#define FIFO_CFG_TXCTRL BIT10
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#define FIFO_CFG_FWIDTH (BIT9 | BIT8)
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#define FIFO_CFG_TXFTH (BIT7 | BIT6 | BIT5 | BIT4)
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#define FIFO_CFG_RXFTH (BIT3 | BIT2 | BIT1 | BIT0)
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#define FIP006_REG_FIFO_TX 0x50 // 16 32-bit Tx FIFO
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#define FIP006_REG_FIFO_RX 0x90 // 16 32-bit Rx FIFO
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#define FIP006_REG_CS_CFG 0xD0 // Command Sequencer Configuration
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typedef union {
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UINT32 Raw : 32;
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struct {
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BOOLEAN SRAM : 1;
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#define CS_CFG_SRAM_RO 0
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#define CS_CFG_SRAM_RW 1
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UINT8 MBM : 2;
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#define CS_CFG_MBM_SINGLE 0
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#define CS_CFG_MBM_DUAL 1
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#define CS_CFG_MBM_QUAD 2
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BOOLEAN SPICHNG : 1;
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BOOLEAN BOOTEN : 1;
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BOOLEAN BSEL : 1;
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UINT8 : 2;
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BOOLEAN SSEL0EN : 1;
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BOOLEAN SSEL1EN : 1;
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BOOLEAN SSEL2EN : 1;
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BOOLEAN SSEL3EN : 1;
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UINT8 : 4;
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BOOLEAN MSEL : 4;
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UINT8 : 4;
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UINT8 : 8;
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} Reg;
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} FIP006_CS_CFG;
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#define FIP006_REG_CS_ITIME 0xD4 // Command Sequencer Idle Timer
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typedef union {
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UINT32 Raw : 32;
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struct {
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UINT16 ITIME : 16;
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UINT16 : 16;
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} Reg;
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} FIP006_CS_ITIME;
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#define FIP006_REG_CS_AEXT 0xD8 // Command Sequencer Address Extension
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typedef union {
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UINT32 Raw : 32;
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struct {
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UINT16 : 13;
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UINT32 AEXT : 19;
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} Reg;
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} FIP006_CS_AEXT;
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#define FIP006_REG_CS_RD 0xDC // Command Sequencer Read Control
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#define CS_RD_DEPTH 8
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#define FIP006_REG_CS_WR 0xEC // Command Sequencer Write Control
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#define CS_WR_DEPTH 8
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typedef union {
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UINT16 Raw : 16;
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struct {
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BOOLEAN DEC : 1;
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UINT8 TRP : 2;
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BOOLEAN CONT : 1;
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UINT8 : 4;
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union {
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UINT8 Data : 8;
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struct {
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UINT8 Data : 3;
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UINT8 : 5;
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} Cmd;
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} Payload;
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} Reg;
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} FIP006_CS_CMD;
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typedef FIP006_CS_CMD FIP006_CS_RD, FIP006_CS_WR;
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#define FIP006_REG_MID 0xFC // Command Sequencer Module ID
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typedef UINT32 FIP006_MID;
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#endif
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