/**@file
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Build up platform processor information of SiFive U54 core.
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Copyright (c) 2019 - 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <IndustryStandard/RiscVOpensbi.h>
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//
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// The Library classes this module consumes
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//
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/FirmwareContextProcessorSpecificLib.h>
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#include <Library/HobLib.h>
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#include <Library/PcdLib.h>
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#include <Library/RiscVEdk2SbiLib.h>
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#include <RiscVImpl.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_platform.h>
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#include <sbi/sbi_scratch.h>
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/**
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Function to build core specific information HOB for U54 or E51 core.
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@param ParentProcessorGuid Parent processor of this core. ParentProcessorGuid
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could be the same as CoreGuid if one processor has
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only one core.
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@param ParentProcessorUid Unique ID of pysical processor which owns this core.
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@param HartId Hart ID of this core.
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@param IsBootHart TRUE means this is the boot HART.
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@param IsManagementCore TRUE means this is for the E51 management core, not U54
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@param GuidHobData Pointer to RISC_V_PROCESSOR_SPECIFIC_HOB_DATA.
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@return EFI_SUCCESS The PEIM initialized successfully.
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EFI_UNSUPPORTED HART is ignored by platform.
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EFI_NOT_FOUND Processor specific data hob is not available.
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**/
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EFI_STATUS
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EFIAPI
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CreateU54E51CoreProcessorSpecificDataHob (
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IN EFI_GUID *ParentProcessorGuid,
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IN UINTN ParentProcessorUid,
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IN UINTN HartId,
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IN BOOLEAN IsBootHart,
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IN BOOLEAN IsManagementCore,
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OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobData
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)
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{
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RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *CoreGuidHob;
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EFI_GUID *ProcessorSpecDataHobGuid;
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RISC_V_PROCESSOR_SPECIFIC_HOB_DATA ProcessorSpecDataHob;
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EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
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EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific;
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DEBUG ((DEBUG_INFO, "%a: Entry.\n", __FUNCTION__));
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if (GuidHobData == NULL) {
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return EFI_INVALID_PARAMETER;
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}
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SbiGetFirmwareContext (&FirmwareContext);
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ASSERT (FirmwareContext != NULL);
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if (FirmwareContext == NULL) {
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DEBUG ((DEBUG_ERROR, "Failed to get the pointer of EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT of hart %d\n", HartId));
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return EFI_NOT_FOUND;
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}
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DEBUG ((DEBUG_INFO, " Firmware Context is at 0x%x.\n", FirmwareContext));
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FirmwareContextHartSpecific = FirmwareContext->HartSpecific[HartId];
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DEBUG ((DEBUG_INFO, " Firmware Context Hart specific is at 0x%x.\n", FirmwareContextHartSpecific));
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if (FirmwareContextHartSpecific == NULL) {
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DEBUG ((DEBUG_INFO, " This hart: %d is ignored by platform.\n", HartId));
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return EFI_UNSUPPORTED;
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}
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//
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// Build up RISC_V_PROCESSOR_SPECIFIC_HOB_DATA.
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//
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CommonFirmwareContextHartSpecificInfo (
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FirmwareContextHartSpecific,
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ParentProcessorGuid,
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ParentProcessorUid,
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(EFI_GUID *)PcdGetPtr (PcdSiFiveU54CoreGuid),
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HartId,
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IsBootHart,
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&ProcessorSpecDataHob
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);
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ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L = TO_BE_FILLED;
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ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_H = TO_BE_FILLED;
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ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_L = TO_BE_FILLED;
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ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_H = TO_BE_FILLED;
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ProcessorSpecDataHob.ProcessorSpecificData.HartXlen = RegisterLen64;
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ProcessorSpecDataHob.ProcessorSpecificData.MachineModeXlen = RegisterLen64;
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ProcessorSpecDataHob.ProcessorSpecificData.UserModeXlen = RegisterLen64;
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if (IsManagementCore) {
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// Configuration for E51
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ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen = RegisterUnsupported;
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} else {
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// Configuration for U54
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ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen = RegisterLen64;
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}
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DebugPrintHartSpecificInfo (&ProcessorSpecDataHob);
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//
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// Build GUID HOB for core, this is for SMBIOS type 44
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//
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ProcessorSpecDataHobGuid = PcdGetPtr (PcdProcessorSpecificDataGuidHobGuid);
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CoreGuidHob = (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *)BuildGuidDataHob (ProcessorSpecDataHobGuid, (VOID *)&ProcessorSpecDataHob, sizeof (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA));
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if (CoreGuidHob == NULL) {
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DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core.\n"));
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ASSERT (FALSE);
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}
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*GuidHobData = CoreGuidHob;
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return EFI_SUCCESS;
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}
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/**
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Function to build cache related SMBIOS information. RISC-V SMBIOS DXE driver collects
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this information and builds SMBIOS Type 7 record.
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The caller can adjust the allocated hob data to their needs.
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@param ProcessorUid Unique ID of physical processor which owns this core.
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@param L1CacheDataHobPtr Pointer to allocated HOB data.
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**/
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VOID
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EFIAPI
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CreateU54SmbiosType7L1DataHob (
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IN UINTN ProcessorUid,
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OUT RISC_V_PROCESSOR_TYPE7_HOB_DATA **L1CacheDataHobPtr
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)
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{
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EFI_GUID *GuidPtr;
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RISC_V_PROCESSOR_TYPE7_HOB_DATA L1CacheDataHob;
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//
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// Build up SMBIOS type 7 L1 cache record.
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//
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ZeroMem((VOID *)&L1CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
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L1CacheDataHob.PrcessorGuid = *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MCCoreplexGuid));
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L1CacheDataHob.ProcessorUid = ProcessorUid;
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L1CacheDataHob.SmbiosType7Cache.SocketDesignation = TO_BE_FILLED_BY_VENDOR;
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L1CacheDataHob.SmbiosType7Cache.CacheConfiguration = RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 | \
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RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \
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RISC_V_CACHE_CONFIGURATION_ENABLED | \
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RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;
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L1CacheDataHob.SmbiosType7Cache.MaximumCacheSize = TO_BE_FILLED_BY_VENDOR;
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L1CacheDataHob.SmbiosType7Cache.InstalledSize = TO_BE_FILLED_BY_VENDOR;
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L1CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown = 1;
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L1CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown = 1;
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L1CacheDataHob.SmbiosType7Cache.CacheSpeed = TO_BE_FILLED_BY_VENDOR;
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L1CacheDataHob.SmbiosType7Cache.ErrorCorrectionType = TO_BE_FILLED_BY_VENDOR;
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L1CacheDataHob.SmbiosType7Cache.SystemCacheType = CacheTypeUnified;
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L1CacheDataHob.SmbiosType7Cache.Associativity = TO_BE_FILLED_BY_VENDOR;
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GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);
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*L1CacheDataHobPtr = (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&L1CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
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if (L1CacheDataHobPtr == NULL) {
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DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5 MC Coreplex L1 cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n"));
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ASSERT (FALSE);
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}
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}
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/**
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Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collects
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this information and builds SMBIOS Type 4 record.
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The caller can adjust the allocated hob data to their needs.
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@param ProcessorUid Unique ID of physical processor which owns this core.
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@param ProcessorDataHobPtr Pointer to allocated HOB data.
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**/
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VOID
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EFIAPI
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CreateU54SmbiosType4DataHob (
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IN UINTN ProcessorUid,
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OUT RISC_V_PROCESSOR_TYPE4_HOB_DATA **ProcessorDataHobPtr
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)
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{
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EFI_GUID *GuidPtr;
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RISC_V_PROCESSOR_TYPE4_HOB_DATA ProcessorDataHob;
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//
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// Build up SMBIOS type 4 record.
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//
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ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DATA));
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ProcessorDataHob.PrcessorGuid = *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MCCoreplexGuid));
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ProcessorDataHob.ProcessorUid = ProcessorUid;
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ProcessorDataHob.SmbiosType4Processor.Socket = TO_BE_FILLED_BY_VENDOR;
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ProcessorDataHob.SmbiosType4Processor.ProcessorType = CentralProcessor;
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ProcessorDataHob.SmbiosType4Processor.ProcessorFamily = ProcessorFamilyIndicatorFamily2;
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ProcessorDataHob.SmbiosType4Processor.ProcessorManufacturer = TO_BE_FILLED_BY_VENDOR;
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SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, sizeof (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE);
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ProcessorDataHob.SmbiosType4Processor.ProcessorVersion = TO_BE_FILLED_BY_VENDOR;
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ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability3_3V = 1;
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ProcessorDataHob.SmbiosType4Processor.ExternalClock = TO_BE_FILLED_BY_VENDOR;
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ProcessorDataHob.SmbiosType4Processor.MaxSpeed = TO_BE_FILLED_BY_VENDOR;
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ProcessorDataHob.SmbiosType4Processor.CurrentSpeed = TO_BE_FILLED_BY_VENDOR;
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ProcessorDataHob.SmbiosType4Processor.Status = TO_BE_FILLED_BY_CODE;
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ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade = TO_BE_FILLED_BY_VENDOR;
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ProcessorDataHob.SmbiosType4Processor.L1CacheHandle = TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER;
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ProcessorDataHob.SmbiosType4Processor.L2CacheHandle = TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER;
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ProcessorDataHob.SmbiosType4Processor.L3CacheHandle = 0xffff;
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ProcessorDataHob.SmbiosType4Processor.SerialNumber = TO_BE_FILLED_BY_CODE;
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ProcessorDataHob.SmbiosType4Processor.AssetTag = TO_BE_FILLED_BY_VENDOR;
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ProcessorDataHob.SmbiosType4Processor.PartNumber = TO_BE_FILLED_BY_VENDOR;
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ProcessorDataHob.SmbiosType4Processor.CoreCount = (UINT8)FixedPcdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported);
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ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount = (UINT8)FixedPcdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported);
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ProcessorDataHob.SmbiosType4Processor.ThreadCount = (UINT8)FixedPcdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported);
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ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics = (UINT16)(1 << 2); // 64-bit capable
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ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 = ProcessorFamilyRiscVRV64;
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ProcessorDataHob.SmbiosType4Processor.CoreCount2 = 0;
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ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 = 0;
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ProcessorDataHob.SmbiosType4Processor.ThreadCount2 = 0;
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GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid);
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*ProcessorDataHobPtr = (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DATA));
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if (ProcessorDataHobPtr == NULL) {
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DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5MC Coreplex RISC_V_PROCESSOR_TYPE4_HOB_DATA.\n"));
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ASSERT (FALSE);
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}
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}
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