/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*/
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#ifndef __SOC_H
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#define __SOC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define uint8_t UINT8
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#define uint16_t UINT16
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#define uint32_t UINT32
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#define uint64_t UINT64
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#define HAL_ASSERT ASSERT
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#define HAL_CPUDelayUs MicroSecondDelay
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#define __WEAK
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#define HAL_DivU64 DivU64x32
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/* IO definitions (access restrictions to peripheral registers) */
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/*!< brief Defines 'read only' permissions */
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#ifdef __cplusplus
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#define __I volatile
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#else
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#define __I volatile const
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#endif
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/*!< brief Defines 'write only' permissions */
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#define __O volatile
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/*!< brief Defines 'read / write' permissions */
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#define __IO volatile
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/**< Write the register */
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#define WRITE_REG(REG, VAL) ((*(volatile uint32_t *)&(REG)) = (VAL))
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/**< Read the register */
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#define READ_REG(REG) ((*(volatile const uint32_t *)&(REG)))
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#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))
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/* ================================================================================ */
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/* ================ Processor and Core Peripheral Section ================ */
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/* ================================================================================ */
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#include "RK3588.h"
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#define RK3588_PERIPH_BASE 0xF0000000
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#define RK3588_PERIPH_SZ 0x10000000
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/******************************************CRU*******************************************/
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#define PLL_INPUT_OSC_RATE (24 * 1000 * 1000)
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#define CLK(mux, div) \
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(((mux) & 0x0F0F00FFU) | (((div) & 0xFFU) << 8) | (((div) & 0x0F0F0000U) << 4))
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#ifndef __ASSEMBLY__
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typedef enum CLOCK_Name {
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CLK_INVALID = 0U,
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PLL_LPLL,
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PLL_B0PLL,
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PLL_B1PLL,
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PLL_CPLL,
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PLL_GPLL,
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PLL_NPLL,
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PLL_V0PLL,
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PLL_PPLL,
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PLL_AUPLL,
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CCLK_EMMC = CLK(CCLK_EMMC_SEL, CCLK_EMMC_DIV),
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SCLK_SFC = CLK(SCLK_SFC_SEL, SCLK_SFC_DIV),
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CCLK_SRC_SDIO = CLK(CCLK_SRC_SDIO_SEL, CCLK_SRC_SDIO_DIV),
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BCLK_EMMC = CLK(BCLK_EMMC_SEL, BCLK_EMMC_DIV),
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CLK_REF_PIPE_PHY0 = CLK(CLK_REF_PIPE_PHY0_SEL, CLK_REF_PIPE_PHY0_PLL_SRC_DIV),
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CLK_REF_PIPE_PHY1 = CLK(CLK_REF_PIPE_PHY1_SEL, CLK_REF_PIPE_PHY1_PLL_SRC_DIV),
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CLK_REF_PIPE_PHY2 = CLK(CLK_REF_PIPE_PHY2_SEL, CLK_REF_PIPE_PHY2_PLL_SRC_DIV),
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} eCLOCK_Name;
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#endif
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __SOC_H */
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