/** @file
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*
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* Copyright (c) 2021, Rockchip Ltd. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#ifndef __RK3568_REGS_PERI_H__
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#define __RK3568_REGS_PERI_H__
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#define SC_PERIPH_CLKEN3 0x230
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#define SC_PERIPH_RSTEN3 0x330
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#define SC_PERIPH_RSTDIS0 0x304
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#define SC_PERIPH_RSTDIS3 0x334
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#define SC_PERIPH_RSTSTAT3 0x338
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/* SC_PERIPH_RSTEN0/RSTDIS0/RSTSTAT0 */
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#define PERIPH_RST0_MMC2 (1 << 2)
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/* SC_PERIPH_RSTEN3/RSTDIS3/RSTSTAT3 */
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#define PERIPH_RST3_CSSYS (1 << 0)
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#define PERIPH_RST3_I2C0 (1 << 1)
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#define PERIPH_RST3_I2C1 (1 << 2)
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#define PERIPH_RST3_I2C2 (1 << 3)
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#define PERIPH_RST3_I2C3 (1 << 4)
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#define PERIPH_RST3_UART1 (1 << 5)
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#define PERIPH_RST3_UART2 (1 << 6)
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#define PERIPH_RST3_UART3 (1 << 7)
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#define PERIPH_RST3_UART4 (1 << 8)
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#define PERIPH_RST3_SSP (1 << 9)
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#define PERIPH_RST3_PWM (1 << 10)
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#define PERIPH_RST3_BLPWM (1 << 11)
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#define PERIPH_RST3_TSENSOR (1 << 12)
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#define PERIPH_RST3_DAPB (1 << 18)
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#define PERIPH_RST3_HKADC (1 << 19)
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#define PERIPH_RST3_CODEC_SSI (1 << 20)
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#define PERIPH_RST3_PMUSSI1 (1 << 22)
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//#define PMUSSI_REG(x) (PMUSSI_BASE + ((x) << 2))
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//#define PMUSSI_ONOFF8_REG (PMUSSI_BASE + (0x1c << 2))
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//#define PMUSSI_ONOFF8_EN_32KB BIT6
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#endif /* __HI6220_REGS_PERI_H__ */
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