/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
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*/
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#ifndef __RK3568_H
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#define __RK3568_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/****************************************************************************************/
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/* */
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/* Module Structure Section */
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/* */
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/****************************************************************************************/
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#ifndef __ASSEMBLY__
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/* GRF Register Structure Define */
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struct GRF_REG {
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__IO uint32_t GPIO0A_IOMUX_L; /* Address Offset: 0x0000 */
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__IO uint32_t GPIO0A_IOMUX_H; /* Address Offset: 0x0004 */
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__IO uint32_t GPIO0B_IOMUX_L; /* Address Offset: 0x0008 */
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__IO uint32_t GPIO0B_IOMUX_H; /* Address Offset: 0x000C */
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__IO uint32_t GPIO0C_IOMUX_L; /* Address Offset: 0x0010 */
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__IO uint32_t GPIO0C_IOMUX_H; /* Address Offset: 0x0014 */
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__IO uint32_t GPIO0D_IOMUX_L; /* Address Offset: 0x0018 */
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__IO uint32_t GPIO0D_IOMUX_H; /* Address Offset: 0x001C */
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__IO uint32_t GPIO0A_P; /* Address Offset: 0x0020 */
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__IO uint32_t GPIO0B_P; /* Address Offset: 0x0024 */
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__IO uint32_t GPIO0C_P; /* Address Offset: 0x0028 */
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__IO uint32_t GPIO0D_P; /* Address Offset: 0x002C */
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__IO uint32_t GPIO0A_IE; /* Address Offset: 0x0030 */
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__IO uint32_t GPIO0B_IE; /* Address Offset: 0x0034 */
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__IO uint32_t GPIO0C_IE; /* Address Offset: 0x0038 */
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__IO uint32_t GPIO0D_IE; /* Address Offset: 0x003C */
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__IO uint32_t GPIO0A_OPD; /* Address Offset: 0x0040 */
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__IO uint32_t GPIO0B_OPD; /* Address Offset: 0x0044 */
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__IO uint32_t GPIO0C_OPD; /* Address Offset: 0x0048 */
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__IO uint32_t GPIO0D_OPD; /* Address Offset: 0x004C */
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__IO uint32_t GPIO0A_SUS; /* Address Offset: 0x0050 */
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__IO uint32_t GPIO0B_SUS; /* Address Offset: 0x0054 */
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__IO uint32_t GPIO0C_SUS; /* Address Offset: 0x0058 */
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__IO uint32_t GPIO0D_SUS; /* Address Offset: 0x005C */
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__IO uint32_t GPIO0A_SL; /* Address Offset: 0x0060 */
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__IO uint32_t GPIO0B_SL; /* Address Offset: 0x0064 */
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__IO uint32_t GPIO0C_SL; /* Address Offset: 0x0068 */
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__IO uint32_t GPIO0D_SL; /* Address Offset: 0x006C */
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__IO uint32_t GPIO0A_DS_0; /* Address Offset: 0x0070 */
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__IO uint32_t GPIO0A_DS_1; /* Address Offset: 0x0074 */
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__IO uint32_t GPIO0A_DS_2; /* Address Offset: 0x0078 */
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__IO uint32_t GPIO0A_DS_3; /* Address Offset: 0x007C */
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__IO uint32_t GPIO0B_DS_0; /* Address Offset: 0x0080 */
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__IO uint32_t GPIO0B_DS_1; /* Address Offset: 0x0084 */
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__IO uint32_t GPIO0B_DS_2; /* Address Offset: 0x0088 */
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__IO uint32_t GPIO0B_DS_3; /* Address Offset: 0x008C */
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__IO uint32_t GPIO0C_DS_0; /* Address Offset: 0x0090 */
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__IO uint32_t GPIO0C_DS_1; /* Address Offset: 0x0094 */
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__IO uint32_t GPIO0C_DS_2; /* Address Offset: 0x0098 */
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__IO uint32_t GPIO0C_DS_3; /* Address Offset: 0x009C */
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__IO uint32_t GPIO0D_DS_0; /* Address Offset: 0x00A0 */
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__IO uint32_t GPIO0D_DS_1; /* Address Offset: 0x00A4 */
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__IO uint32_t GPIO0D_DS_2; /* Address Offset: 0x00A8 */
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__IO uint32_t GPIO0D_DS_3; /* Address Offset: 0x00AC */
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uint32_t RESERVED00B0[20]; /* Address Offset: 0x00B0 */
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__IO uint32_t SOC_CON0; /* Address Offset: 0x0100 */
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__IO uint32_t SOC_CON1; /* Address Offset: 0x0104 */
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__IO uint32_t SOC_CON2; /* Address Offset: 0x0108 */
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__IO uint32_t SOC_CON3; /* Address Offset: 0x010C */
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__IO uint32_t SOC_CON4; /* Address Offset: 0x0110 */
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__IO uint32_t SOC_CON5; /* Address Offset: 0x0114 */
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uint32_t RESERVED0118[2]; /* Address Offset: 0x0118 */
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__I uint32_t SOC_STATUS; /* Address Offset: 0x0120 */
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uint32_t RESERVED0124[7]; /* Address Offset: 0x0124 */
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__IO uint32_t IO_VSEL0; /* Address Offset: 0x0140 */
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__IO uint32_t IO_VSEL1; /* Address Offset: 0x0144 */
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__IO uint32_t IO_VSEL2; /* Address Offset: 0x0148 */
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uint32_t RESERVED014C[13]; /* Address Offset: 0x014C */
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__IO uint32_t DLL_CON0; /* Address Offset: 0x0180 */
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uint32_t RESERVED0184[31]; /* Address Offset: 0x0184 */
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__IO uint32_t OS_REG0; /* Address Offset: 0x0200 */
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__IO uint32_t OS_REG1; /* Address Offset: 0x0204 */
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__IO uint32_t OS_REG2; /* Address Offset: 0x0208 */
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__IO uint32_t OS_REG3; /* Address Offset: 0x020C */
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__IO uint32_t OS_REG4; /* Address Offset: 0x0210 */
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__IO uint32_t OS_REG5; /* Address Offset: 0x0214 */
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__IO uint32_t OS_REG6; /* Address Offset: 0x0218 */
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__IO uint32_t OS_REG7; /* Address Offset: 0x021C */
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__IO uint32_t OS_REG8; /* Address Offset: 0x0220 */
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__IO uint32_t OS_REG9; /* Address Offset: 0x0224 */
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__IO uint32_t OS_REG10; /* Address Offset: 0x0228 */
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__IO uint32_t OS_REG11; /* Address Offset: 0x022C */
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__IO uint32_t RESET_FUNCTION_STATUS; /* Address Offset: 0x0230 */
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__IO uint32_t RESET_FUNCTION_CLR; /* Address Offset: 0x0234 */
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uint32_t RESERVED0238[82]; /* Address Offset: 0x0238 */
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__IO uint32_t SIG_DETECT_CON; /* Address Offset: 0x0380 */
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uint32_t RESERVED0384[3]; /* Address Offset: 0x0384 */
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__IO uint32_t SIG_DETECT_STATUS; /* Address Offset: 0x0390 */
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uint32_t RESERVED0394[3]; /* Address Offset: 0x0394 */
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__IO uint32_t SIG_DETECT_STATUS_CLEAR; /* Address Offset: 0x03A0 */
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uint32_t RESERVED03A4[3]; /* Address Offset: 0x03A4 */
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__IO uint32_t SDMMC_DET_COUNTER; /* Address Offset: 0x03B0 */
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uint32_t RESERVED03B4[65299]; /* Address Offset: 0x03B4 */
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__IO uint32_t GPIO1A_IOMUX_L; /* Address Offset: 0x40000 */
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__IO uint32_t GPIO1A_IOMUX_H; /* Address Offset: 0x40004 */
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__IO uint32_t GPIO1B_IOMUX_L; /* Address Offset: 0x40008 */
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__IO uint32_t GPIO1B_IOMUX_H; /* Address Offset: 0x4000C */
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__IO uint32_t GPIO1C_IOMUX_L; /* Address Offset: 0x40010 */
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__IO uint32_t GPIO1C_IOMUX_H; /* Address Offset: 0x40014 */
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__IO uint32_t GPIO1D_IOMUX_L; /* Address Offset: 0x40018 */
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__IO uint32_t GPIO1D_IOMUX_H; /* Address Offset: 0x4001C */
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__IO uint32_t GPIO2A_IOMUX_L; /* Address Offset: 0x40020 */
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__IO uint32_t GPIO2A_IOMUX_H; /* Address Offset: 0x40024 */
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__IO uint32_t GPIO2B_IOMUX_L; /* Address Offset: 0x40028 */
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__IO uint32_t GPIO2B_IOMUX_H; /* Address Offset: 0x4002C */
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__IO uint32_t GPIO2C_IOMUX_L; /* Address Offset: 0x40030 */
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__IO uint32_t GPIO2C_IOMUX_H; /* Address Offset: 0x40034 */
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__IO uint32_t GPIO2D_IOMUX_L; /* Address Offset: 0x40038 */
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__IO uint32_t GPIO2D_IOMUX_H; /* Address Offset: 0x4003C */
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__IO uint32_t GPIO3A_IOMUX_L; /* Address Offset: 0x40040 */
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__IO uint32_t GPIO3A_IOMUX_H; /* Address Offset: 0x40044 */
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__IO uint32_t GPIO3B_IOMUX_L; /* Address Offset: 0x40048 */
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__IO uint32_t GPIO3B_IOMUX_H; /* Address Offset: 0x4004C */
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__IO uint32_t GPIO3C_IOMUX_L; /* Address Offset: 0x40050 */
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__IO uint32_t GPIO3C_IOMUX_H; /* Address Offset: 0x40054 */
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__IO uint32_t GPIO3D_IOMUX_L; /* Address Offset: 0x40058 */
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__IO uint32_t GPIO3D_IOMUX_H; /* Address Offset: 0x4005C */
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__IO uint32_t GPIO4A_IOMUX_L; /* Address Offset: 0x40060 */
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__IO uint32_t GPIO4A_IOMUX_H; /* Address Offset: 0x40064 */
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__IO uint32_t GPIO4B_IOMUX_L; /* Address Offset: 0x40068 */
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__IO uint32_t GPIO4B_IOMUX_H; /* Address Offset: 0x4006C */
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__IO uint32_t GPIO4C_IOMUX_L; /* Address Offset: 0x40070 */
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__IO uint32_t GPIO4C_IOMUX_H; /* Address Offset: 0x40074 */
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__IO uint32_t GPIO4D_IOMUX_L; /* Address Offset: 0x40078 */
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__IO uint32_t GPIO4D_IOMUX_H; /* Address Offset: 0x4007C */
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__IO uint32_t GPIO1A_P; /* Address Offset: 0x40080 */
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__IO uint32_t GPIO1B_P; /* Address Offset: 0x40084 */
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__IO uint32_t GPIO1C_P; /* Address Offset: 0x40088 */
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__IO uint32_t GPIO1D_P; /* Address Offset: 0x4008C */
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__IO uint32_t GPIO2A_P; /* Address Offset: 0x40090 */
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__IO uint32_t GPIO2B_P; /* Address Offset: 0x40094 */
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__IO uint32_t GPIO2C_P; /* Address Offset: 0x40098 */
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__IO uint32_t GPIO2D_P; /* Address Offset: 0x4009C */
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__IO uint32_t GPIO3A_P; /* Address Offset: 0x400A0 */
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__IO uint32_t GPIO3B_P; /* Address Offset: 0x400A4 */
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__IO uint32_t GPIO3C_P; /* Address Offset: 0x400A8 */
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__IO uint32_t GPIO3D_P; /* Address Offset: 0x400AC */
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__IO uint32_t GPIO4A_P; /* Address Offset: 0x400B0 */
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__IO uint32_t GPIO4B_P; /* Address Offset: 0x400B4 */
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__IO uint32_t GPIO4C_P; /* Address Offset: 0x400B8 */
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__IO uint32_t GPIO4D_P; /* Address Offset: 0x400BC */
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__IO uint32_t GPIO1A_IE; /* Address Offset: 0x400C0 */
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__IO uint32_t GPIO1B_IE; /* Address Offset: 0x400C4 */
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__IO uint32_t GPIO1C_IE; /* Address Offset: 0x400C8 */
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__IO uint32_t GPIO1D_IE; /* Address Offset: 0x400CC */
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__IO uint32_t GPIO2A_IE; /* Address Offset: 0x400D0 */
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__IO uint32_t GPIO2B_IE; /* Address Offset: 0x400D4 */
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__IO uint32_t GPIO2C_IE; /* Address Offset: 0x400D8 */
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__IO uint32_t GPIO2D_IE; /* Address Offset: 0x400DC */
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__IO uint32_t GPIO3A_IE; /* Address Offset: 0x400E0 */
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__IO uint32_t GPIO3B_IE; /* Address Offset: 0x400E4 */
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__IO uint32_t GPIO3C_IE; /* Address Offset: 0x400E8 */
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__IO uint32_t GPIO3D_IE; /* Address Offset: 0x400EC */
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__IO uint32_t GPIO4A_IE; /* Address Offset: 0x400F0 */
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__IO uint32_t GPIO4B_IE; /* Address Offset: 0x400F4 */
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__IO uint32_t GPIO4C_IE; /* Address Offset: 0x400F8 */
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__IO uint32_t GPIO4D_IE; /* Address Offset: 0x400FC */
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__IO uint32_t GPIO1A_OPD; /* Address Offset: 0x40100 */
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__IO uint32_t GPIO1B_OPD; /* Address Offset: 0x40104 */
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__IO uint32_t GPIO1C_OPD; /* Address Offset: 0x40108 */
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__IO uint32_t GPIO1D_OPD; /* Address Offset: 0x4010C */
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__IO uint32_t GPIO2A_OPD; /* Address Offset: 0x40110 */
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__IO uint32_t GPIO2B_OPD; /* Address Offset: 0x40114 */
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__IO uint32_t GPIO2C_OPD; /* Address Offset: 0x40118 */
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__IO uint32_t GPIO2D_OPD; /* Address Offset: 0x4011C */
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__IO uint32_t GPIO3A_OPD; /* Address Offset: 0x40120 */
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__IO uint32_t GPIO3B_OPD; /* Address Offset: 0x40124 */
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__IO uint32_t GPIO3C_OPD; /* Address Offset: 0x40128 */
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__IO uint32_t GPIO3D_OPD; /* Address Offset: 0x4012C */
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__IO uint32_t GPIO4A_OPD; /* Address Offset: 0x40130 */
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__IO uint32_t GPIO4B_OPD; /* Address Offset: 0x40134 */
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__IO uint32_t GPIO4C_OPD; /* Address Offset: 0x40138 */
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__IO uint32_t GPIO4D_OPD; /* Address Offset: 0x4013C */
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__IO uint32_t GPIO1A_SUS; /* Address Offset: 0x40140 */
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__IO uint32_t GPIO1B_SUS; /* Address Offset: 0x40144 */
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__IO uint32_t GPIO1C_SUS; /* Address Offset: 0x40148 */
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__IO uint32_t GPIO1D_SUS; /* Address Offset: 0x4014C */
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__IO uint32_t GPIO2A_SUS; /* Address Offset: 0x40150 */
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__IO uint32_t GPIO2B_SUS; /* Address Offset: 0x40154 */
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__IO uint32_t GPIO2C_SUS; /* Address Offset: 0x40158 */
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__IO uint32_t GPIO2D_SUS; /* Address Offset: 0x4015C */
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__IO uint32_t GPIO3A_SUS; /* Address Offset: 0x40160 */
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__IO uint32_t GPIO3B_SUS; /* Address Offset: 0x40164 */
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__IO uint32_t GPIO3C_SUS; /* Address Offset: 0x40168 */
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__IO uint32_t GPIO3D_SUS; /* Address Offset: 0x4016C */
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__IO uint32_t GPIO4A_SUS; /* Address Offset: 0x40170 */
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__IO uint32_t GPIO4B_SUS; /* Address Offset: 0x40174 */
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__IO uint32_t GPIO4C_SUS; /* Address Offset: 0x40178 */
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__IO uint32_t GPIO4D_SUS; /* Address Offset: 0x4017C */
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__IO uint32_t GPIO1A_SL; /* Address Offset: 0x40180 */
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__IO uint32_t GPIO1B_SL; /* Address Offset: 0x40184 */
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__IO uint32_t GPIO1C_SL; /* Address Offset: 0x40188 */
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__IO uint32_t GPIO1D_SL; /* Address Offset: 0x4018C */
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__IO uint32_t GPIO2A_SL; /* Address Offset: 0x40190 */
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__IO uint32_t GPIO2B_SL; /* Address Offset: 0x40194 */
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__IO uint32_t GPIO2C_SL; /* Address Offset: 0x40198 */
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__IO uint32_t GPIO2D_SL; /* Address Offset: 0x4019C */
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__IO uint32_t GPIO3A_SL; /* Address Offset: 0x401A0 */
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__IO uint32_t GPIO3B_SL; /* Address Offset: 0x401A4 */
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__IO uint32_t GPIO3C_SL; /* Address Offset: 0x401A8 */
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__IO uint32_t GPIO3D_SL; /* Address Offset: 0x401AC */
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__IO uint32_t GPIO4A_SL; /* Address Offset: 0x401B0 */
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__IO uint32_t GPIO4B_SL; /* Address Offset: 0x401B4 */
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__IO uint32_t GPIO4C_SL; /* Address Offset: 0x401B8 */
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__IO uint32_t GPIO4D_SL; /* Address Offset: 0x401BC */
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uint32_t RESERVED401C0[16]; /* Address Offset: 0x401C0 */
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__IO uint32_t GPIO1A_DS_0; /* Address Offset: 0x40200 */
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__IO uint32_t GPIO1A_DS_1; /* Address Offset: 0x40204 */
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__IO uint32_t GPIO1A_DS_2; /* Address Offset: 0x40208 */
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__IO uint32_t GPIO1A_DS_3; /* Address Offset: 0x4020C */
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__IO uint32_t GPIO1B_DS_0; /* Address Offset: 0x40210 */
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__IO uint32_t GPIO1B_DS_1; /* Address Offset: 0x40214 */
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__IO uint32_t GPIO1B_DS_2; /* Address Offset: 0x40218 */
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__IO uint32_t GPIO1B_DS_3; /* Address Offset: 0x4021C */
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__IO uint32_t GPIO1C_DS_0; /* Address Offset: 0x40220 */
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__IO uint32_t GPIO1C_DS_1; /* Address Offset: 0x40224 */
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__IO uint32_t GPIO1C_DS_2; /* Address Offset: 0x40228 */
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__IO uint32_t GPIO1C_DS_3; /* Address Offset: 0x4022C */
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__IO uint32_t GPIO1D_DS_0; /* Address Offset: 0x40230 */
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__IO uint32_t GPIO1D_DS_1; /* Address Offset: 0x40234 */
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__IO uint32_t GPIO1D_DS_2; /* Address Offset: 0x40238 */
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__IO uint32_t GPIO1D_DS_3; /* Address Offset: 0x4023C */
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__IO uint32_t GPIO2A_DS_0; /* Address Offset: 0x40240 */
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__IO uint32_t GPIO2A_DS_1; /* Address Offset: 0x40244 */
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__IO uint32_t GPIO2A_DS_2; /* Address Offset: 0x40248 */
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__IO uint32_t GPIO2A_DS_3; /* Address Offset: 0x4024C */
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__IO uint32_t GPIO2B_DS_0; /* Address Offset: 0x40250 */
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__IO uint32_t GPIO2B_DS_1; /* Address Offset: 0x40254 */
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__IO uint32_t GPIO2B_DS_2; /* Address Offset: 0x40258 */
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__IO uint32_t GPIO2B_DS_3; /* Address Offset: 0x4025C */
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__IO uint32_t GPIO2C_DS_0; /* Address Offset: 0x40260 */
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__IO uint32_t GPIO2C_DS_1; /* Address Offset: 0x40264 */
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__IO uint32_t GPIO2C_DS_2; /* Address Offset: 0x40268 */
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__IO uint32_t GPIO2C_DS_3; /* Address Offset: 0x4026C */
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__IO uint32_t GPIO2D_DS_0; /* Address Offset: 0x40270 */
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__IO uint32_t GPIO2D_DS_1; /* Address Offset: 0x40274 */
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__IO uint32_t GPIO2D_DS_2; /* Address Offset: 0x40278 */
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__IO uint32_t GPIO2D_DS_3; /* Address Offset: 0x4027C */
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__IO uint32_t GPIO3A_DS_0; /* Address Offset: 0x40280 */
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__IO uint32_t GPIO3A_DS_1; /* Address Offset: 0x40284 */
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__IO uint32_t GPIO3A_DS_2; /* Address Offset: 0x40288 */
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__IO uint32_t GPIO3A_DS_3; /* Address Offset: 0x4028C */
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__IO uint32_t GPIO3B_DS_0; /* Address Offset: 0x40290 */
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__IO uint32_t GPIO3B_DS_1; /* Address Offset: 0x40294 */
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__IO uint32_t GPIO3B_DS_2; /* Address Offset: 0x40298 */
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__IO uint32_t GPIO3B_DS_3; /* Address Offset: 0x4029C */
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__IO uint32_t GPIO3C_DS_0; /* Address Offset: 0x402A0 */
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__IO uint32_t GPIO3C_DS_1; /* Address Offset: 0x402A4 */
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__IO uint32_t GPIO3C_DS_2; /* Address Offset: 0x402A8 */
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__IO uint32_t GPIO3C_DS_3; /* Address Offset: 0x402AC */
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__IO uint32_t GPIO3D_DS_0; /* Address Offset: 0x402B0 */
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__IO uint32_t GPIO3D_DS_1; /* Address Offset: 0x402B4 */
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__IO uint32_t GPIO3D_DS_2; /* Address Offset: 0x402B8 */
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__IO uint32_t GPIO3D_DS_3; /* Address Offset: 0x402BC */
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__IO uint32_t GPIO4A_DS_0; /* Address Offset: 0x402C0 */
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__IO uint32_t GPIO4A_DS_1; /* Address Offset: 0x402C4 */
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__IO uint32_t GPIO4A_DS_2; /* Address Offset: 0x402C8 */
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__IO uint32_t GPIO4A_DS_3; /* Address Offset: 0x402CC */
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__IO uint32_t GPIO4B_DS_0; /* Address Offset: 0x402D0 */
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__IO uint32_t GPIO4B_DS_1; /* Address Offset: 0x402D4 */
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__IO uint32_t GPIO4B_DS_2; /* Address Offset: 0x402D8 */
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__IO uint32_t GPIO4B_DS_3; /* Address Offset: 0x402DC */
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__IO uint32_t GPIO4C_DS_0; /* Address Offset: 0x402E0 */
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__IO uint32_t GPIO4C_DS_1; /* Address Offset: 0x402E4 */
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__IO uint32_t GPIO4C_DS_2; /* Address Offset: 0x402E8 */
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__IO uint32_t GPIO4C_DS_3; /* Address Offset: 0x402EC */
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__IO uint32_t GPIO4D_DS_0; /* Address Offset: 0x402F0 */
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__IO uint32_t GPIO4D_DS_1; /* Address Offset: 0x402F4 */
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__IO uint32_t GPIO4D_DS_2; /* Address Offset: 0x402F8 */
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__IO uint32_t GPIO4D_DS_3; /* Address Offset: 0x402FC */
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__IO uint32_t IOFUNC_SEL0; /* Address Offset: 0x40300 */
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__IO uint32_t IOFUNC_SEL1; /* Address Offset: 0x40304 */
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__IO uint32_t IOFUNC_SEL2; /* Address Offset: 0x40308 */
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__IO uint32_t IOFUNC_SEL3; /* Address Offset: 0x4030C */
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__IO uint32_t IOFUNC_SEL4; /* Address Offset: 0x40310 */
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__IO uint32_t IOFUNC_SEL5; /* Address Offset: 0x40314 */
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uint32_t RESERVED40318[10]; /* Address Offset: 0x40318 */
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__IO uint32_t VI_CON0; /* Address Offset: 0x40340 */
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__IO uint32_t VI_CON1; /* Address Offset: 0x40344 */
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__IO uint32_t VI_STATUS0; /* Address Offset: 0x40348 */
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uint32_t RESERVED4034C[5]; /* Address Offset: 0x4034C */
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__IO uint32_t VO_CON0; /* Address Offset: 0x40360 */
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__IO uint32_t VO_CON1; /* Address Offset: 0x40364 */
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__IO uint32_t VO_CON2; /* Address Offset: 0x40368 */
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uint32_t RESERVED4036C[5]; /* Address Offset: 0x4036C */
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__IO uint32_t MAC0_CON0; /* Address Offset: 0x40380 */
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__IO uint32_t MAC0_CON1; /* Address Offset: 0x40384 */
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__IO uint32_t MAC1_CON0; /* Address Offset: 0x40388 */
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__IO uint32_t MAC1_CON1; /* Address Offset: 0x4038C */
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uint32_t RESERVED40390[4]; /* Address Offset: 0x40390 */
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__IO uint32_t BIU_CON0; /* Address Offset: 0x403A0 */
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__IO uint32_t BIU_CON1; /* Address Offset: 0x403A4 */
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__IO uint32_t BIU_CON2; /* Address Offset: 0x403A8 */
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uint32_t RESERVED403AC[5]; /* Address Offset: 0x403AC */
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__IO uint32_t GIC_CON0; /* Address Offset: 0x403C0 */
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__IO uint32_t GIC_CON1; /* Address Offset: 0x403C4 */
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__IO uint32_t GIC_CON2; /* Address Offset: 0x403C8 */
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uint32_t RESERVED403CC[9]; /* Address Offset: 0x403CC */
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__IO uint32_t GPU_CON0; /* Address Offset: 0x403F0 */
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__IO uint32_t GPU_CON1; /* Address Offset: 0x403F4 */
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uint32_t RESERVED403F8[2]; /* Address Offset: 0x403F8 */
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__IO uint32_t CPU_CON0; /* Address Offset: 0x40400 */
|
uint32_t RESERVED40404[7]; /* Address Offset: 0x40404 */
|
__IO uint32_t CPU_STATUS0; /* Address Offset: 0x40420 */
|
uint32_t RESERVED40424[55]; /* Address Offset: 0x40424 */
|
__IO uint32_t SOC_CON10; /* Address Offset: 0x40500 */
|
__IO uint32_t SOC_CON11; /* Address Offset: 0x40504 */
|
__IO uint32_t SOC_CON12; /* Address Offset: 0x40508 */
|
__IO uint32_t SOC_CON13; /* Address Offset: 0x4050C */
|
__IO uint32_t SOC_CON14; /* Address Offset: 0x40510 */
|
__IO uint32_t SOC_CON15; /* Address Offset: 0x40514 */
|
__IO uint32_t SOC_CON16; /* Address Offset: 0x40518 */
|
uint32_t RESERVED4051C[25]; /* Address Offset: 0x4051C */
|
__IO uint32_t SOC_STATUS0; /* Address Offset: 0x40580 */
|
uint32_t RESERVED40584[15]; /* Address Offset: 0x40584 */
|
__IO uint32_t RAM_CON; /* Address Offset: 0x405C0 */
|
__IO uint32_t CORE_RAM_CON; /* Address Offset: 0x405C4 */
|
uint32_t RESERVED405C8[14]; /* Address Offset: 0x405C8 */
|
__IO uint32_t TSADC_CON; /* Address Offset: 0x40600 */
|
uint32_t RESERVED40604[3]; /* Address Offset: 0x40604 */
|
__IO uint32_t SARADC_CON; /* Address Offset: 0x40610 */
|
uint32_t RESERVED40614[59]; /* Address Offset: 0x40614 */
|
__IO uint32_t GPUPVTPLL_CON0; /* Address Offset: 0x40700 */
|
__IO uint32_t GPUPVTPLL_CON1; /* Address Offset: 0x40704 */
|
__IO uint32_t GPUPVTPLL_CON2; /* Address Offset: 0x40708 */
|
__IO uint32_t GPUPVTPLL_CON3; /* Address Offset: 0x4070C */
|
uint32_t RESERVED40710[12]; /* Address Offset: 0x40710 */
|
__IO uint32_t NPUPVTPLL_CON0; /* Address Offset: 0x40740 */
|
__IO uint32_t NPUPVTPLL_CON1; /* Address Offset: 0x40744 */
|
__IO uint32_t NPUPVTPLL_CON2; /* Address Offset: 0x40748 */
|
__IO uint32_t NPUPVTPLL_CON3; /* Address Offset: 0x4074C */
|
uint32_t RESERVED40750[44]; /* Address Offset: 0x40750 */
|
__IO uint32_t CHIP_ID; /* Address Offset: 0x40800 */
|
uint32_t RESERVED40804[15]; /* Address Offset: 0x40804 */
|
__IO uint32_t GPIO1C5_DS; /* Address Offset: 0x40840 */
|
__IO uint32_t GPIO2A2_DS; /* Address Offset: 0x40844 */
|
__IO uint32_t GPIO2B0_DS; /* Address Offset: 0x40848 */
|
__IO uint32_t GPIO3A0_DS; /* Address Offset: 0x4084C */
|
__IO uint32_t GPIO3A6_DS; /* Address Offset: 0x40850 */
|
__IO uint32_t GPIO4A0_DS; /* Address Offset: 0x40854 */
|
uint32_t RESERVED40858[42]; /* Address Offset: 0x40858 */
|
__IO uint32_t DMAC0_CON0; /* Address Offset: 0x40900 */
|
__IO uint32_t DMAC0_CON1; /* Address Offset: 0x40904 */
|
__IO uint32_t DMAC0_CON2; /* Address Offset: 0x40908 */
|
__IO uint32_t DMAC0_CON3; /* Address Offset: 0x4090C */
|
__IO uint32_t DMAC0_CON4; /* Address Offset: 0x40910 */
|
__IO uint32_t DMAC0_CON5; /* Address Offset: 0x40914 */
|
__IO uint32_t DMAC0_CON6; /* Address Offset: 0x40918 */
|
__IO uint32_t DMAC0_CON7; /* Address Offset: 0x4091C */
|
__IO uint32_t DMAC0_CON8; /* Address Offset: 0x40920 */
|
__IO uint32_t DMAC0_CON9; /* Address Offset: 0x40924 */
|
uint32_t RESERVED40928[6]; /* Address Offset: 0x40928 */
|
__IO uint32_t DMAC1_CON0; /* Address Offset: 0x40940 */
|
__IO uint32_t DMAC1_CON1; /* Address Offset: 0x40944 */
|
__IO uint32_t DMAC1_CON2; /* Address Offset: 0x40948 */
|
__IO uint32_t DMAC1_CON3; /* Address Offset: 0x4094C */
|
__IO uint32_t DMAC1_CON4; /* Address Offset: 0x40950 */
|
__IO uint32_t DMAC1_CON5; /* Address Offset: 0x40954 */
|
__IO uint32_t DMAC1_CON6; /* Address Offset: 0x40958 */
|
__IO uint32_t DMAC1_CON7; /* Address Offset: 0x4095C */
|
__IO uint32_t DMAC1_CON8; /* Address Offset: 0x40960 */
|
__IO uint32_t DMAC1_CON9; /* Address Offset: 0x40964 */
|
};
|
/* PMUCRU Register Structure Define */
|
struct PMUCRU_REG {
|
__IO uint32_t PPLL_CON[5]; /* Address Offset: 0x0000 */
|
uint32_t RESERVED0014[11]; /* Address Offset: 0x0014 */
|
__IO uint32_t HPLL_CON[5]; /* Address Offset: 0x0040 */
|
uint32_t RESERVED0054[11]; /* Address Offset: 0x0054 */
|
__IO uint32_t MODE_CON00; /* Address Offset: 0x0080 */
|
uint32_t RESERVED0084[31]; /* Address Offset: 0x0084 */
|
__IO uint32_t CRU_CLKSEL_CON[10]; /* Address Offset: 0x0100 */
|
uint32_t RESERVED0128[22]; /* Address Offset: 0x0128 */
|
__IO uint32_t CRU_CLKGATE_CON[3]; /* Address Offset: 0x0180 */
|
uint32_t RESERVED018C[29]; /* Address Offset: 0x018C */
|
__IO uint32_t CRU_SOFTRST_CON[1]; /* Address Offset: 0x0200 */
|
};
|
/* TIMER Register Structure Define */
|
struct TIMER_REG {
|
__IO uint32_t LOAD_COUNT[2]; /* Address Offset: 0x0000 */
|
__I uint32_t CURRENT_VALUE[2]; /* Address Offset: 0x0008 */
|
__IO uint32_t CONTROLREG; /* Address Offset: 0x0010 */
|
uint32_t RESERVED0014; /* Address Offset: 0x0014 */
|
__IO uint32_t INTSTATUS; /* Address Offset: 0x0018 */
|
};
|
/* CRU Register Structure Define */
|
struct CRU_REG {
|
__IO uint32_t APLL_CON[5]; /* Address Offset: 0x0000 */
|
uint32_t RESERVED0014[3]; /* Address Offset: 0x0014 */
|
__IO uint32_t DPLL_CON[5]; /* Address Offset: 0x0020 */
|
uint32_t RESERVED0034[3]; /* Address Offset: 0x0034 */
|
__IO uint32_t GPLL_CON[5]; /* Address Offset: 0x0040 */
|
uint32_t RESERVED0054[3]; /* Address Offset: 0x0054 */
|
__IO uint32_t CPLL_CON[5]; /* Address Offset: 0x0060 */
|
uint32_t RESERVED0074[3]; /* Address Offset: 0x0074 */
|
__IO uint32_t NPLL_CON[2]; /* Address Offset: 0x0080 */
|
uint32_t RESERVED0088[6]; /* Address Offset: 0x0088 */
|
__IO uint32_t VPLL_CON[2]; /* Address Offset: 0x00A0 */
|
uint32_t RESERVED00A8[6]; /* Address Offset: 0x00A8 */
|
__IO uint32_t MODE_CON00; /* Address Offset: 0x00C0 */
|
__IO uint32_t MISC_CON[3]; /* Address Offset: 0x00C4 */
|
__IO uint32_t GLB_CNT_TH; /* Address Offset: 0x00D0 */
|
__IO uint32_t GLB_SRST_FST; /* Address Offset: 0x00D4 */
|
__IO uint32_t GLB_SRST_SND; /* Address Offset: 0x00D8 */
|
__IO uint32_t GLB_RST_CON; /* Address Offset: 0x00DC */
|
__IO uint32_t GLB_RST_ST; /* Address Offset: 0x00E0 */
|
uint32_t RESERVED00E4[7]; /* Address Offset: 0x00E4 */
|
__IO uint32_t CRU_CLKSEL_CON[85]; /* Address Offset: 0x0100 */
|
uint32_t RESERVED0254[43]; /* Address Offset: 0x0254 */
|
__IO uint32_t CRU_CLKGATE_CON[36]; /* Address Offset: 0x0300 */
|
uint32_t RESERVED0390[28]; /* Address Offset: 0x0390 */
|
__IO uint32_t CRU_SOFTRST_CON[30]; /* Address Offset: 0x0400 */
|
uint32_t RESERVED0478[2]; /* Address Offset: 0x0478 */
|
__IO uint32_t SSGTBL0_3; /* Address Offset: 0x0480 */
|
__IO uint32_t SSGTBL4_7; /* Address Offset: 0x0484 */
|
__IO uint32_t SSGTBL8_11; /* Address Offset: 0x0488 */
|
__IO uint32_t SSGTBL12_15; /* Address Offset: 0x048C */
|
__IO uint32_t SSGTBL16_19; /* Address Offset: 0x0490 */
|
__IO uint32_t SSGTBL20_23; /* Address Offset: 0x0494 */
|
__IO uint32_t SSGTBL24_27; /* Address Offset: 0x0498 */
|
__IO uint32_t SSGTBL28_31; /* Address Offset: 0x049C */
|
__IO uint32_t SSGTBL32_35; /* Address Offset: 0x04A0 */
|
__IO uint32_t SSGTBL36_39; /* Address Offset: 0x04A4 */
|
__IO uint32_t SSGTBL40_43; /* Address Offset: 0x04A8 */
|
__IO uint32_t SSGTBL44_47; /* Address Offset: 0x04AC */
|
__IO uint32_t SSGTBL48_51; /* Address Offset: 0x04B0 */
|
__IO uint32_t SSGTBL52_55; /* Address Offset: 0x04B4 */
|
__IO uint32_t SSGTBL56_59; /* Address Offset: 0x04B8 */
|
__IO uint32_t SSGTBL60_63; /* Address Offset: 0x04BC */
|
__IO uint32_t SSGTBL64_67; /* Address Offset: 0x04C0 */
|
__IO uint32_t SSGTBL68_71; /* Address Offset: 0x04C4 */
|
__IO uint32_t SSGTBL72_75; /* Address Offset: 0x04C8 */
|
__IO uint32_t SSGTBL76_79; /* Address Offset: 0x04CC */
|
__IO uint32_t SSGTBL80_83; /* Address Offset: 0x04D0 */
|
__IO uint32_t SSGTBL84_87; /* Address Offset: 0x04D4 */
|
__IO uint32_t SSGTBL88_91; /* Address Offset: 0x04D8 */
|
__IO uint32_t SSGTBL92_95; /* Address Offset: 0x04DC */
|
__IO uint32_t SSGTBL96_99; /* Address Offset: 0x04E0 */
|
__IO uint32_t SSGTBL100_103; /* Address Offset: 0x04E4 */
|
__IO uint32_t SSGTBL104_107; /* Address Offset: 0x04E8 */
|
__IO uint32_t SSGTBL108_111; /* Address Offset: 0x04EC */
|
__IO uint32_t SSGTBL112_115; /* Address Offset: 0x04F0 */
|
__IO uint32_t SSGTBL116_119; /* Address Offset: 0x04F4 */
|
__IO uint32_t SSGTBL120_123; /* Address Offset: 0x04F8 */
|
__IO uint32_t SSGTBL124_127; /* Address Offset: 0x04FC */
|
__IO uint32_t AUTOCS_CORE_CON0; /* Address Offset: 0x0500 */
|
__IO uint32_t AUTOCS_CORE_CON1; /* Address Offset: 0x0504 */
|
__IO uint32_t AUTOCS_GPU_CON0; /* Address Offset: 0x0508 */
|
__IO uint32_t AUTOCS_GPU_CON1; /* Address Offset: 0x050C */
|
__IO uint32_t AUTOCS_BUS_CON0; /* Address Offset: 0x0510 */
|
__IO uint32_t AUTOCS_BUS_CON1; /* Address Offset: 0x0514 */
|
__IO uint32_t AUTOCS_TOP_CON0; /* Address Offset: 0x0518 */
|
__IO uint32_t AUTOCS_TOP_CON1; /* Address Offset: 0x051C */
|
__IO uint32_t AUTOCS_RKVDEC_CON0; /* Address Offset: 0x0520 */
|
__IO uint32_t AUTOCS_RKVDEC_CON1; /* Address Offset: 0x0524 */
|
__IO uint32_t AUTOCS_RKVENC_CON0; /* Address Offset: 0x0528 */
|
__IO uint32_t AUTOCS_RKVENC_CON1; /* Address Offset: 0x052C */
|
__IO uint32_t AUTOCS_VPU_CON0; /* Address Offset: 0x0530 */
|
__IO uint32_t AUTOCS_VPU_CON1; /* Address Offset: 0x0534 */
|
__IO uint32_t AUTOCS_PERI_CON0; /* Address Offset: 0x0538 */
|
__IO uint32_t AUTOCS_PERI_CON1; /* Address Offset: 0x053C */
|
__IO uint32_t AUTOCS_GPLL_CON0; /* Address Offset: 0x0540 */
|
__IO uint32_t AUTOCS_GPLL_CON1; /* Address Offset: 0x0544 */
|
__IO uint32_t AUTOCS_CPLL_CON0; /* Address Offset: 0x0548 */
|
__IO uint32_t AUTOCS_CPLL_CON1; /* Address Offset: 0x054C */
|
uint32_t RESERVED0550[12]; /* Address Offset: 0x0550 */
|
__IO uint32_t SDMMC0_CON[2]; /* Address Offset: 0x0580 */
|
__IO uint32_t SDMMC1_CON[2]; /* Address Offset: 0x0588 */
|
__IO uint32_t SDMMC2_CON[2]; /* Address Offset: 0x0590 */
|
__IO uint32_t EMMC_CON[2]; /* Address Offset: 0x0598 */
|
};
|
/* I2C Register Structure Define */
|
struct I2C_REG {
|
__IO uint32_t CON; /* Address Offset: 0x0000 */
|
__IO uint32_t CLKDIV; /* Address Offset: 0x0004 */
|
__IO uint32_t MRXADDR; /* Address Offset: 0x0008 */
|
__IO uint32_t MRXRADDR; /* Address Offset: 0x000C */
|
__IO uint32_t MTXCNT; /* Address Offset: 0x0010 */
|
__IO uint32_t MRXCNT; /* Address Offset: 0x0014 */
|
__IO uint32_t IEN; /* Address Offset: 0x0018 */
|
__IO uint32_t IPD; /* Address Offset: 0x001C */
|
__I uint32_t FCNT; /* Address Offset: 0x0020 */
|
__IO uint32_t SCL_OE_DB; /* Address Offset: 0x0024 */
|
uint32_t RESERVED0028[54]; /* Address Offset: 0x0028 */
|
__IO uint32_t TXDATA[8]; /* Address Offset: 0x0100 */
|
uint32_t RESERVED0120[56]; /* Address Offset: 0x0120 */
|
__I uint32_t RXDATA[8]; /* Address Offset: 0x0200 */
|
__I uint32_t ST; /* Address Offset: 0x0220 */
|
__IO uint32_t DBGCTRL; /* Address Offset: 0x0224 */
|
};
|
/* UART Register Structure Define */
|
struct UART_REG {
|
union {
|
__I uint32_t RBR; /* Address Offset: 0x0000 */
|
__IO uint32_t DLL; /* Address Offset: 0x0000 */
|
__O uint32_t THR; /* Address Offset: 0x0000 */
|
};
|
union {
|
__IO uint32_t DLH; /* Address Offset: 0x0004 */
|
__IO uint32_t IER; /* Address Offset: 0x0004 */
|
};
|
union {
|
__O uint32_t FCR; /* Address Offset: 0x0008 */
|
__I uint32_t IIR; /* Address Offset: 0x0008 */
|
};
|
__IO uint32_t LCR; /* Address Offset: 0x000C */
|
__IO uint32_t MCR; /* Address Offset: 0x0010 */
|
__I uint32_t LSR; /* Address Offset: 0x0014 */
|
__I uint32_t MSR; /* Address Offset: 0x0018 */
|
__IO uint32_t SCR; /* Address Offset: 0x001C */
|
uint32_t RESERVED0020[4]; /* Address Offset: 0x0020 */
|
union {
|
__I uint32_t SRBR; /* Address Offset: 0x0030 */
|
__O uint32_t STHR; /* Address Offset: 0x0030 */
|
};
|
uint32_t RESERVED0034[15]; /* Address Offset: 0x0034 */
|
__IO uint32_t FAR; /* Address Offset: 0x0070 */
|
__I uint32_t TFR; /* Address Offset: 0x0074 */
|
__O uint32_t RFW; /* Address Offset: 0x0078 */
|
__I uint32_t USR; /* Address Offset: 0x007C */
|
__I uint32_t TFL; /* Address Offset: 0x0080 */
|
__I uint32_t RFL; /* Address Offset: 0x0084 */
|
__O uint32_t SRR; /* Address Offset: 0x0088 */
|
__IO uint32_t SRTS; /* Address Offset: 0x008C */
|
__IO uint32_t SBCR; /* Address Offset: 0x0090 */
|
__IO uint32_t SDMAM; /* Address Offset: 0x0094 */
|
__IO uint32_t SFE; /* Address Offset: 0x0098 */
|
__IO uint32_t SRT; /* Address Offset: 0x009C */
|
__IO uint32_t STET; /* Address Offset: 0x00A0 */
|
__IO uint32_t HTX; /* Address Offset: 0x00A4 */
|
__O uint32_t DMASA; /* Address Offset: 0x00A8 */
|
uint32_t RESERVED00AC[18]; /* Address Offset: 0x00AC */
|
__I uint32_t CPR; /* Address Offset: 0x00F4 */
|
__I uint32_t UCV; /* Address Offset: 0x00F8 */
|
__I uint32_t CTR; /* Address Offset: 0x00FC */
|
};
|
/* GPIO Register Structure Define */
|
struct GPIO_REG {
|
__IO uint32_t SWPORT_DR_L; /* Address Offset: 0x0000 */
|
__IO uint32_t SWPORT_DR_H; /* Address Offset: 0x0004 */
|
__IO uint32_t SWPORT_DDR_L; /* Address Offset: 0x0008 */
|
__IO uint32_t SWPORT_DDR_H; /* Address Offset: 0x000C */
|
__IO uint32_t INT_EN_L; /* Address Offset: 0x0010 */
|
__IO uint32_t INT_EN_H; /* Address Offset: 0x0014 */
|
__IO uint32_t INT_MASK_L; /* Address Offset: 0x0018 */
|
__IO uint32_t INT_MASK_H; /* Address Offset: 0x001C */
|
__IO uint32_t INT_TYPE_L; /* Address Offset: 0x0020 */
|
__IO uint32_t INT_TYPE_H; /* Address Offset: 0x0024 */
|
__IO uint32_t INT_POLARITY_L; /* Address Offset: 0x0028 */
|
__IO uint32_t INT_POLARITY_H; /* Address Offset: 0x002C */
|
__IO uint32_t INT_BOTHEDGE_L; /* Address Offset: 0x0030 */
|
__IO uint32_t INT_BOTHEDGE_H; /* Address Offset: 0x0034 */
|
__IO uint32_t DEBOUNCE_L; /* Address Offset: 0x0038 */
|
__IO uint32_t DEBOUNCE_H; /* Address Offset: 0x003C */
|
__IO uint32_t DBCLK_DIV_EN_L; /* Address Offset: 0x0040 */
|
__IO uint32_t DBCLK_DIV_EN_H; /* Address Offset: 0x0044 */
|
__IO uint32_t DBCLK_DIV_CON; /* Address Offset: 0x0048 */
|
uint32_t RESERVED004C; /* Address Offset: 0x004C */
|
__I uint32_t INT_STATUS; /* Address Offset: 0x0050 */
|
uint32_t RESERVED0054; /* Address Offset: 0x0054 */
|
__I uint32_t INT_RAWSTATUS; /* Address Offset: 0x0058 */
|
uint32_t RESERVED005C; /* Address Offset: 0x005C */
|
__IO uint32_t PORT_EOI_L; /* Address Offset: 0x0060 */
|
__IO uint32_t PORT_EOI_H; /* Address Offset: 0x0064 */
|
uint32_t RESERVED0068[2]; /* Address Offset: 0x0068 */
|
__I uint32_t EXT_PORT; /* Address Offset: 0x0070 */
|
uint32_t RESERVED0074; /* Address Offset: 0x0074 */
|
__I uint32_t VER_ID; /* Address Offset: 0x0078 */
|
};
|
/* PWM Register Structure Define */
|
struct PWM_CHANNEL {
|
__I uint32_t CNT;
|
__IO uint32_t PERIOD_HPR;
|
__IO uint32_t DUTY_LPR;
|
__IO uint32_t CTRL;
|
};
|
struct PWM_REG {
|
struct PWM_CHANNEL CHANNELS[4]; /* Address Offset: 0x0000 */
|
__IO uint32_t INTSTS; /* Address Offset: 0x0040 */
|
__IO uint32_t INT_EN; /* Address Offset: 0x0044 */
|
uint32_t RESERVED0048[2]; /* Address Offset: 0x0048 */
|
__IO uint32_t FIFO_CTRL; /* Address Offset: 0x0050 */
|
__IO uint32_t FIFO_INTSTS; /* Address Offset: 0x0054 */
|
__IO uint32_t FIFO_TOUTTHR; /* Address Offset: 0x0058 */
|
__IO uint32_t VERSION_ID; /* Address Offset: 0x005C */
|
__I uint32_t FIFO; /* Address Offset: 0x0060 */
|
uint32_t RESERVED0064[7]; /* Address Offset: 0x0064 */
|
__IO uint32_t PWRMATCH_CTRL; /* Address Offset: 0x0080 */
|
__IO uint32_t PWRMATCH_LPRE; /* Address Offset: 0x0084 */
|
__IO uint32_t PWRMATCH_HPRE; /* Address Offset: 0x0088 */
|
__IO uint32_t PWRMATCH_LD; /* Address Offset: 0x008C */
|
__IO uint32_t PWRMATCH_HD_ZERO; /* Address Offset: 0x0090 */
|
__IO uint32_t PWRMATCH_HD_ONE; /* Address Offset: 0x0094 */
|
__IO uint32_t PWRMATCH_VALUE[10]; /* Address Offset: 0x0098 */
|
uint32_t RESERVED00C0[3]; /* Address Offset: 0x00C0 */
|
__I uint32_t PWM3_PWRCAPTURE_VALUE; /* Address Offset: 0x00CC */
|
__IO uint32_t FILTER_CTRL; /* Address Offset: 0x00D0 */
|
};
|
/* PMU Register Structure Define */
|
struct PMU_REG {
|
__I uint32_t VERSION; /* Address Offset: 0x0000 */
|
__IO uint32_t PWR_CON; /* Address Offset: 0x0004 */
|
__I uint32_t MAIN_PWR_STATE; /* Address Offset: 0x0008 */
|
__IO uint32_t INT_MASK_CON; /* Address Offset: 0x000C */
|
__IO uint32_t WAKEUP_INT_CON; /* Address Offset: 0x0010 */
|
__I uint32_t WAKEUP_INT_ST; /* Address Offset: 0x0014 */
|
__IO uint32_t WAKEUP_EDGE_CON; /* Address Offset: 0x0018 */
|
__IO uint32_t WAKEUP_EDGE_ST; /* Address Offset: 0x001C */
|
uint32_t RESERVED0020[8]; /* Address Offset: 0x0020 */
|
__IO uint32_t BUS_IDLE_CON0; /* Address Offset: 0x0040 */
|
__IO uint32_t BUS_IDLE_CON1; /* Address Offset: 0x0044 */
|
uint32_t RESERVED0048[2]; /* Address Offset: 0x0048 */
|
__IO uint32_t BUS_IDLE_SFTCON0; /* Address Offset: 0x0050 */
|
__IO uint32_t BUS_IDLE_SFTCON1; /* Address Offset: 0x0054 */
|
uint32_t RESERVED0058[2]; /* Address Offset: 0x0058 */
|
__I uint32_t BUS_IDLE_ACK; /* Address Offset: 0x0060 */
|
uint32_t RESERVED0064; /* Address Offset: 0x0064 */
|
__I uint32_t BUS_IDLE_ST; /* Address Offset: 0x0068 */
|
uint32_t RESERVED006C; /* Address Offset: 0x006C */
|
__IO uint32_t NOC_AUTO_CON0; /* Address Offset: 0x0070 */
|
__IO uint32_t NOC_AUTO_CON1; /* Address Offset: 0x0074 */
|
uint32_t RESERVED0078[2]; /* Address Offset: 0x0078 */
|
__IO uint32_t DDR_PWR_CON; /* Address Offset: 0x0080 */
|
__IO uint32_t DDR_PWR_SFTCON; /* Address Offset: 0x0084 */
|
__I uint32_t DDR_PWR_STATE; /* Address Offset: 0x0088 */
|
__I uint32_t DDR_PWR_ST; /* Address Offset: 0x008C */
|
__IO uint32_t PWR_GATE_CON; /* Address Offset: 0x0090 */
|
__I uint32_t PWR_GATE_STATE; /* Address Offset: 0x0094 */
|
__I uint32_t PWR_DWN_ST; /* Address Offset: 0x0098 */
|
uint32_t RESERVED009C; /* Address Offset: 0x009C */
|
__IO uint32_t PWR_GATE_SFTCON; /* Address Offset: 0x00A0 */
|
uint32_t RESERVED00A4; /* Address Offset: 0x00A4 */
|
__IO uint32_t VOL_GATE_SFTCON; /* Address Offset: 0x00A8 */
|
uint32_t RESERVED00AC; /* Address Offset: 0x00AC */
|
__IO uint32_t CRU_PWR_CON; /* Address Offset: 0x00B0 */
|
__IO uint32_t CRU_PWR_SFTCON; /* Address Offset: 0x00B4 */
|
__I uint32_t CRU_PWR_STATE; /* Address Offset: 0x00B8 */
|
uint32_t RESERVED00BC; /* Address Offset: 0x00BC */
|
__IO uint32_t PLLPD_CON; /* Address Offset: 0x00C0 */
|
__IO uint32_t PLLPD_SFTCON; /* Address Offset: 0x00C4 */
|
uint32_t RESERVED00C8[2]; /* Address Offset: 0x00C8 */
|
__IO uint32_t INFO_TX_CON; /* Address Offset: 0x00D0 */
|
uint32_t RESERVED00D4[11]; /* Address Offset: 0x00D4 */
|
__IO uint32_t DSU_STABLE_CNT; /* Address Offset: 0x0100 */
|
__IO uint32_t PMIC_STABLE_CNT; /* Address Offset: 0x0104 */
|
__IO uint32_t OSC_STABLE_CNT; /* Address Offset: 0x0108 */
|
__IO uint32_t WAKEUP_RSTCLR_CNT; /* Address Offset: 0x010C */
|
__IO uint32_t PLL_LOCK_CNT; /* Address Offset: 0x0110 */
|
uint32_t RESERVED0114; /* Address Offset: 0x0114 */
|
__IO uint32_t DSU_PWRUP_CNT; /* Address Offset: 0x0118 */
|
__IO uint32_t DSU_PWRDN_CNT; /* Address Offset: 0x011C */
|
__IO uint32_t GPU_VOLUP_CNT; /* Address Offset: 0x0120 */
|
__IO uint32_t GPU_VOLDN_CNT; /* Address Offset: 0x0124 */
|
__IO uint32_t WAKEUP_TIMEOUT_CNT; /* Address Offset: 0x0128 */
|
__IO uint32_t PWM_SWITCH_CNT; /* Address Offset: 0x012C */
|
__IO uint32_t DBG_RST_CNT; /* Address Offset: 0x0130 */
|
uint32_t RESERVED0134[19]; /* Address Offset: 0x0134 */
|
__IO uint32_t SYS_REG0; /* Address Offset: 0x0180 */
|
__IO uint32_t SYS_REG1; /* Address Offset: 0x0184 */
|
__IO uint32_t SYS_REG2; /* Address Offset: 0x0188 */
|
__IO uint32_t SYS_REG3; /* Address Offset: 0x018C */
|
__IO uint32_t SYS_REG4; /* Address Offset: 0x0190 */
|
__IO uint32_t SYS_REG5; /* Address Offset: 0x0194 */
|
__IO uint32_t SYS_REG6; /* Address Offset: 0x0198 */
|
__IO uint32_t SYS_REG7; /* Address Offset: 0x019C */
|
uint32_t RESERVED01A0[88]; /* Address Offset: 0x01A0 */
|
__IO uint32_t DSU_PWR_CON; /* Address Offset: 0x0300 */
|
__IO uint32_t DSU_PWR_SFTCON; /* Address Offset: 0x0304 */
|
__IO uint32_t DSU_AUTO_CON; /* Address Offset: 0x0308 */
|
__I uint32_t DSU_PWR_STATE; /* Address Offset: 0x030C */
|
__IO uint32_t CPU_AUTO_PWR_CON0; /* Address Offset: 0x0310 */
|
__IO uint32_t CPU_AUTO_PWR_CON1; /* Address Offset: 0x0314 */
|
__IO uint32_t CPU_PWR_SFTCON; /* Address Offset: 0x0318 */
|
__I uint32_t CLUSTER_PWR_ST; /* Address Offset: 0x031C */
|
__IO uint32_t CLUSTER_IDLE_CON; /* Address Offset: 0x0320 */
|
__IO uint32_t CLUSTER_IDLE_SFTCON; /* Address Offset: 0x0324 */
|
__I uint32_t CLUSTER_IDLE_ACK; /* Address Offset: 0x0328 */
|
__I uint32_t CLUSTER_IDLE_ST; /* Address Offset: 0x032C */
|
__IO uint32_t DBG_PWR_CON; /* Address Offset: 0x0330 */
|
};
|
/* SPINLOCK Register Structure Define */
|
struct SPINLOCK_REG {
|
__IO uint32_t STATUS[64]; /* Address Offset: 0x0000 */
|
};
|
/* GMAC Register Structure Define */
|
struct GMAC_REG {
|
__IO uint32_t MAC_CONFIGURATION; /* Address Offset: 0x0000 */
|
__IO uint32_t MAC_EXT_CONFIGURATION; /* Address Offset: 0x0004 */
|
__IO uint32_t MAC_PACKET_FILTER; /* Address Offset: 0x0008 */
|
__IO uint32_t MAC_WATCHDOG_TIMEOUT; /* Address Offset: 0x000C */
|
__IO uint32_t MAC_HASH_TABLE_REG0; /* Address Offset: 0x0010 */
|
__IO uint32_t MAC_HASH_TABLE_REG1; /* Address Offset: 0x0014 */
|
uint32_t RESERVED0018[14]; /* Address Offset: 0x0018 */
|
__IO uint32_t MAC_VLAN_TAG; /* Address Offset: 0x0050 */
|
uint32_t RESERVED0054[7]; /* Address Offset: 0x0054 */
|
__IO uint32_t MAC_Q0_TX_FLOW_CTRL; /* Address Offset: 0x0070 */
|
uint32_t RESERVED0074[7]; /* Address Offset: 0x0074 */
|
__IO uint32_t MAC_RX_FLOW_CTRL; /* Address Offset: 0x0090 */
|
uint32_t RESERVED0094[7]; /* Address Offset: 0x0094 */
|
__I uint32_t MAC_INTERRUPT_STATUS; /* Address Offset: 0x00B0 */
|
__IO uint32_t MAC_INTERRUPT_ENABLE; /* Address Offset: 0x00B4 */
|
__I uint32_t MAC_RX_TX_STATUS; /* Address Offset: 0x00B8 */
|
uint32_t RESERVED00BC; /* Address Offset: 0x00BC */
|
__IO uint32_t MAC_PMT_CONTROL_STATUS; /* Address Offset: 0x00C0 */
|
__IO uint32_t RWK_FILTER0_BYTE_MASK; /* Address Offset: 0x00C4 */
|
__IO uint32_t RWK_FILTER1_BYTE_MASK; /* Address Offset: 0x00C8 */
|
union {
|
__IO uint32_t RWK_FILTER2_BYTE_MASK; /* Address Offset: 0x00CC */
|
__IO uint32_t RWK_FILTER3_BYTE_MASK; /* Address Offset: 0x00CC */
|
};
|
union {
|
__IO uint32_t RWK_FILTER01_CRC; /* Address Offset: 0x00D0 */
|
__IO uint32_t MAC_LPI_CONTROL_STATUS; /* Address Offset: 0x00D0 */
|
};
|
union {
|
__IO uint32_t RWK_FILTER23_CRC; /* Address Offset: 0x00D4 */
|
__IO uint32_t MAC_LPI_TIMERS_CONTROL; /* Address Offset: 0x00D4 */
|
};
|
union {
|
__IO uint32_t RWK_FILTER_OFFSET; /* Address Offset: 0x00D8 */
|
__IO uint32_t MAC_LPI_ENTRY_TIMER; /* Address Offset: 0x00D8 */
|
};
|
union {
|
__IO uint32_t RWK_FILTER_COMMAND; /* Address Offset: 0x00DC */
|
__IO uint32_t MAC_1US_TIC_COUNTER; /* Address Offset: 0x00DC */
|
};
|
uint32_t RESERVED00E0[6]; /* Address Offset: 0x00E0 */
|
__IO uint32_t MAC_PHYIF_CONTROL_STATUS; /* Address Offset: 0x00F8 */
|
uint32_t RESERVED00FC[5]; /* Address Offset: 0x00FC */
|
__IO uint32_t MAC_VERSION; /* Address Offset: 0x0110 */
|
__I uint32_t MAC_DEBUG; /* Address Offset: 0x0114 */
|
uint32_t RESERVED0118; /* Address Offset: 0x0118 */
|
__I uint32_t MAC_HW_FEATURE0; /* Address Offset: 0x011C */
|
__I uint32_t MAC_HW_FEATURE1; /* Address Offset: 0x0120 */
|
__I uint32_t MAC_HW_FEATURE2; /* Address Offset: 0x0124 */
|
__IO uint32_t MAC_HW_FEATURE3; /* Address Offset: 0x0128 */
|
uint32_t RESERVED012C[53]; /* Address Offset: 0x012C */
|
__IO uint32_t MAC_MDIO_ADDRESS; /* Address Offset: 0x0200 */
|
__IO uint32_t MAC_MDIO_DATA; /* Address Offset: 0x0204 */
|
uint32_t RESERVED0208[10]; /* Address Offset: 0x0208 */
|
__IO uint32_t MAC_CSR_SW_CTRL; /* Address Offset: 0x0230 */
|
uint32_t RESERVED0234[51]; /* Address Offset: 0x0234 */
|
__IO uint32_t MAC_ADDRESS0_HIGH; /* Address Offset: 0x0300 */
|
__IO uint32_t MAC_ADDRESS0_LOW; /* Address Offset: 0x0304 */
|
uint32_t RESERVED0308[254]; /* Address Offset: 0x0308 */
|
__IO uint32_t MMC_CONTROL; /* Address Offset: 0x0700 */
|
__I uint32_t MMC_RX_INTERRUPT; /* Address Offset: 0x0704 */
|
__I uint32_t MMC_TX_INTERRUPT; /* Address Offset: 0x0708 */
|
__IO uint32_t MMC_RX_INTERRUPT_MASK; /* Address Offset: 0x070C */
|
__IO uint32_t MMC_TX_INTERRUPT_MASK; /* Address Offset: 0x0710 */
|
__I uint32_t TX_OCTET_COUNT_GOOD_BAD; /* Address Offset: 0x0714 */
|
__I uint32_t TX_PACKET_COUNT_GOOD_BAD; /* Address Offset: 0x0718 */
|
uint32_t RESERVED071C[11]; /* Address Offset: 0x071C */
|
__I uint32_t TX_UNDERFLOW_ERROR_PACKETS; /* Address Offset: 0x0748 */
|
uint32_t RESERVED074C[5]; /* Address Offset: 0x074C */
|
__I uint32_t TX_CARRIER_ERROR_PACKETS; /* Address Offset: 0x0760 */
|
__I uint32_t TX_OCTET_COUNT_GOOD; /* Address Offset: 0x0764 */
|
__I uint32_t TX_PACKET_COUNT_GOOD; /* Address Offset: 0x0768 */
|
uint32_t RESERVED076C[5]; /* Address Offset: 0x076C */
|
__I uint32_t RX_PACKETS_COUNT_GOOD_BAD; /* Address Offset: 0x0780 */
|
__I uint32_t RX_OCTET_COUNT_GOOD_BAD; /* Address Offset: 0x0784 */
|
__I uint32_t RX_OCTET_COUNT_GOOD; /* Address Offset: 0x0788 */
|
uint32_t RESERVED078C; /* Address Offset: 0x078C */
|
__I uint32_t RX_MULTICAST_PACKETS_GOOD; /* Address Offset: 0x0790 */
|
__I uint32_t RX_CRC_ERROR_PACKETS; /* Address Offset: 0x0794 */
|
uint32_t RESERVED0798[12]; /* Address Offset: 0x0798 */
|
__I uint32_t RX_LENGTH_ERROR_PACKETS; /* Address Offset: 0x07C8 */
|
uint32_t RESERVED07CC[2]; /* Address Offset: 0x07CC */
|
__I uint32_t RX_FIFO_OVERFLOW_PACKETS; /* Address Offset: 0x07D4 */
|
uint32_t RESERVED07D8[10]; /* Address Offset: 0x07D8 */
|
__IO uint32_t MMC_IPC_RX_INTERRUPT_MASK; /* Address Offset: 0x0800 */
|
uint32_t RESERVED0804; /* Address Offset: 0x0804 */
|
__I uint32_t MMC_IPC_RX_INTERRUPT; /* Address Offset: 0x0808 */
|
uint32_t RESERVED080C; /* Address Offset: 0x080C */
|
__I uint32_t RXIPV4_GOOD_PACKETS; /* Address Offset: 0x0810 */
|
__I uint32_t RXIPV4_HEADER_ERROR_PACKETS; /* Address Offset: 0x0814 */
|
uint32_t RESERVED0818[3]; /* Address Offset: 0x0818 */
|
__I uint32_t RXIPV6_GOOD_PACKETS; /* Address Offset: 0x0824 */
|
__I uint32_t RXIPV6_HEADER_ERROR_PACKETS; /* Address Offset: 0x0828 */
|
uint32_t RESERVED082C[2]; /* Address Offset: 0x082C */
|
__I uint32_t RXUDP_ERROR_PACKETS; /* Address Offset: 0x0834 */
|
uint32_t RESERVED0838; /* Address Offset: 0x0838 */
|
__I uint32_t RXTCP_ERROR_PACKETS; /* Address Offset: 0x083C */
|
uint32_t RESERVED0840; /* Address Offset: 0x0840 */
|
__I uint32_t RXICMP_ERROR_PACKETS; /* Address Offset: 0x0844 */
|
uint32_t RESERVED0848[3]; /* Address Offset: 0x0848 */
|
__I uint32_t RXIPV4_HEADER_ERROR_OCTETS; /* Address Offset: 0x0854 */
|
uint32_t RESERVED0858[4]; /* Address Offset: 0x0858 */
|
__I uint32_t RXIPV6_HEADER_ERROR_OCTETS; /* Address Offset: 0x0868 */
|
uint32_t RESERVED086C[2]; /* Address Offset: 0x086C */
|
__I uint32_t RXUDP_ERROR_OCTETS; /* Address Offset: 0x0874 */
|
uint32_t RESERVED0878; /* Address Offset: 0x0878 */
|
__I uint32_t RXTCP_ERROR_OCTETS; /* Address Offset: 0x087C */
|
uint32_t RESERVED0880; /* Address Offset: 0x0880 */
|
__I uint32_t RXICMP_ERROR_OCTETS; /* Address Offset: 0x0884 */
|
uint32_t RESERVED0888[158]; /* Address Offset: 0x0888 */
|
__IO uint32_t MAC_TIMESTAMP_CONTROL; /* Address Offset: 0x0B00 */
|
__IO uint32_t MAC_SUB_SECOND_INCREMENT; /* Address Offset: 0x0B04 */
|
__IO uint32_t MAC_SYSTEM_TIME_SECS; /* Address Offset: 0x0B08 */
|
__IO uint32_t MAC_SYSTEM_TIME_NS; /* Address Offset: 0x0B0C */
|
__IO uint32_t MAC_SYS_TIME_SECS_UPDATE; /* Address Offset: 0x0B10 */
|
__IO uint32_t MAC_SYS_TIME_NS_UPDATE; /* Address Offset: 0x0B14 */
|
__IO uint32_t MAC_TIMESTAMP_ADDEND; /* Address Offset: 0x0B18 */
|
uint32_t RESERVED0B1C; /* Address Offset: 0x0B1C */
|
__I uint32_t MAC_TIMESTAMP_STATUS; /* Address Offset: 0x0B20 */
|
uint32_t RESERVED0B24[3]; /* Address Offset: 0x0B24 */
|
__I uint32_t MAC_TX_TS_STATUS_NS; /* Address Offset: 0x0B30 */
|
__I uint32_t MAC_TX_TS_STATUS_SECS; /* Address Offset: 0x0B34 */
|
uint32_t RESERVED0B38[2]; /* Address Offset: 0x0B38 */
|
__IO uint32_t MAC_AUXILIARY_CONTROL; /* Address Offset: 0x0B40 */
|
uint32_t RESERVED0B44; /* Address Offset: 0x0B44 */
|
__I uint32_t MAC_AUXILIARY_TS_NS; /* Address Offset: 0x0B48 */
|
__IO uint32_t MAC_AUXILIARY_TS_SECS; /* Address Offset: 0x0B4C */
|
uint32_t RESERVED0B50[2]; /* Address Offset: 0x0B50 */
|
__IO uint32_t MAC_TS_INGRESS_CORR_NS; /* Address Offset: 0x0B58 */
|
__IO uint32_t MAC_TS_EGRESS_CORR_NS; /* Address Offset: 0x0B5C */
|
uint32_t RESERVED0B60[2]; /* Address Offset: 0x0B60 */
|
__I uint32_t MAC_TS_INGRESS_LATENCY; /* Address Offset: 0x0B68 */
|
__I uint32_t MAC_TS_EGRESS_LATENCY; /* Address Offset: 0x0B6C */
|
__IO uint32_t MAC_PPS_CONTROL; /* Address Offset: 0x0B70 */
|
uint32_t RESERVED0B74[37]; /* Address Offset: 0x0B74 */
|
__IO uint32_t MTL_DBG_CTL; /* Address Offset: 0x0C08 */
|
__IO uint32_t MTL_DBG_STS; /* Address Offset: 0x0C0C */
|
__IO uint32_t MTL_FIFO_DEBUG_DATA; /* Address Offset: 0x0C10 */
|
uint32_t RESERVED0C14[3]; /* Address Offset: 0x0C14 */
|
__I uint32_t MTL_INTERRUPT_STATUS; /* Address Offset: 0x0C20 */
|
uint32_t RESERVED0C24[55]; /* Address Offset: 0x0C24 */
|
__IO uint32_t MTL_TXQ0_OPERATION_MODE; /* Address Offset: 0x0D00 */
|
__I uint32_t MTL_TXQ0_UNDERFLOW; /* Address Offset: 0x0D04 */
|
__I uint32_t MTL_TXQ0_DEBUG; /* Address Offset: 0x0D08 */
|
uint32_t RESERVED0D0C[8]; /* Address Offset: 0x0D0C */
|
__IO uint32_t MTL_Q0_INTERRUPT_CTRL_STATUS; /* Address Offset: 0x0D2C */
|
__IO uint32_t MTL_RXQ0_OPERATION_MODE; /* Address Offset: 0x0D30 */
|
__I uint32_t MTL_RXQ0_MISS_PKT_OVF_CNT; /* Address Offset: 0x0D34 */
|
__I uint32_t MTL_RXQ0_DEBUG; /* Address Offset: 0x0D38 */
|
uint32_t RESERVED0D3C[177]; /* Address Offset: 0x0D3C */
|
__IO uint32_t DMA_MODE; /* Address Offset: 0x1000 */
|
__IO uint32_t DMA_SYSBUS_MODE; /* Address Offset: 0x1004 */
|
__I uint32_t DMA_INTERRUPT_STATUS; /* Address Offset: 0x1008 */
|
__I uint32_t DMA_DEBUG_STATUS0; /* Address Offset: 0x100C */
|
uint32_t RESERVED1010[12]; /* Address Offset: 0x1010 */
|
__IO uint32_t AXI_LPI_ENTRY_INTERVAL; /* Address Offset: 0x1040 */
|
uint32_t RESERVED1044[47]; /* Address Offset: 0x1044 */
|
__IO uint32_t DMA_CH0_CONTROL; /* Address Offset: 0x1100 */
|
__IO uint32_t DMA_CH0_TX_CONTROL; /* Address Offset: 0x1104 */
|
__IO uint32_t DMA_CH0_RX_CONTROL; /* Address Offset: 0x1108 */
|
uint32_t RESERVED110C[2]; /* Address Offset: 0x110C */
|
__IO uint32_t DMA_CH0_TXDESC_LIST_ADDRESS; /* Address Offset: 0x1114 */
|
uint32_t RESERVED1118; /* Address Offset: 0x1118 */
|
__IO uint32_t DMA_CH0_RXDESC_LIST_ADDRESS; /* Address Offset: 0x111C */
|
__IO uint32_t DMA_CH0_TXDESC_TAIL_POINTER; /* Address Offset: 0x1120 */
|
uint32_t RESERVED1124; /* Address Offset: 0x1124 */
|
__IO uint32_t DMA_CH0_RXDESC_TAIL_POINTER; /* Address Offset: 0x1128 */
|
__IO uint32_t DMA_CH0_TXDESC_RING_LENGTH; /* Address Offset: 0x112C */
|
__IO uint32_t DMA_CH0_RXDESC_RING_LENGTH; /* Address Offset: 0x1130 */
|
__IO uint32_t DMA_CH0_INTERRUPT_ENABLE; /* Address Offset: 0x1134 */
|
__IO uint32_t DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER; /* Address Offset: 0x1138 */
|
uint32_t RESERVED113C[2]; /* Address Offset: 0x113C */
|
__I uint32_t DMA_CH0_CURRENT_APP_TXDESC; /* Address Offset: 0x1144 */
|
uint32_t RESERVED1148; /* Address Offset: 0x1148 */
|
__I uint32_t DMA_CH0_CURRENT_APP_RXDESC; /* Address Offset: 0x114C */
|
uint32_t RESERVED1150; /* Address Offset: 0x1150 */
|
__I uint32_t DMA_CH0_CURRENT_APP_TXBUFFER; /* Address Offset: 0x1154 */
|
uint32_t RESERVED1158; /* Address Offset: 0x1158 */
|
__I uint32_t DMA_CH0_CURRENT_APP_RXBUFFER; /* Address Offset: 0x115C */
|
__IO uint32_t DMA_CH0_STATUS; /* Address Offset: 0x1160 */
|
__I uint32_t DMA_CH0_MISS_FRAME_CNT; /* Address Offset: 0x1164 */
|
__I uint32_t DMA_CH0_RX_ERI_CNT; /* Address Offset: 0x1168 */
|
};
|
/* FSPI Register Structure Define */
|
struct FSPI_REG {
|
__IO uint32_t CTRL0; /* Address Offset: 0x0000 */
|
__IO uint32_t IMR; /* Address Offset: 0x0004 */
|
__IO uint32_t ICLR; /* Address Offset: 0x0008 */
|
__IO uint32_t FTLR; /* Address Offset: 0x000C */
|
__IO uint32_t RCVR; /* Address Offset: 0x0010 */
|
__IO uint32_t AX0; /* Address Offset: 0x0014 */
|
__IO uint32_t ABIT0; /* Address Offset: 0x0018 */
|
__IO uint32_t ISR; /* Address Offset: 0x001C */
|
__IO uint32_t FSR; /* Address Offset: 0x0020 */
|
__I uint32_t SR; /* Address Offset: 0x0024 */
|
__I uint32_t RISR; /* Address Offset: 0x0028 */
|
__I uint32_t VER; /* Address Offset: 0x002C */
|
__IO uint32_t QOP; /* Address Offset: 0x0030 */
|
__IO uint32_t EXT_CTRL; /* Address Offset: 0x0034 */
|
uint32_t RESERVED0038; /* Address Offset: 0x0038 */
|
__IO uint32_t DLL_CTRL0; /* Address Offset: 0x003C */
|
uint32_t RESERVED0040; /* Address Offset: 0x0040 */
|
__IO uint32_t EXT_AX; /* Address Offset: 0x0044 */
|
__IO uint32_t SCLK_INATM_CNT; /* Address Offset: 0x0048 */
|
uint32_t RESERVED004C; /* Address Offset: 0x004C */
|
__O uint32_t XMMC_WCMD0; /* Address Offset: 0x0050 */
|
__O uint32_t XMMC_RCMD0; /* Address Offset: 0x0054 */
|
__IO uint32_t XMMC_CTRL; /* Address Offset: 0x0058 */
|
__IO uint32_t MODE; /* Address Offset: 0x005C */
|
__IO uint32_t DEVRGN; /* Address Offset: 0x0060 */
|
__IO uint32_t DEVSIZE0; /* Address Offset: 0x0064 */
|
__IO uint32_t TME0; /* Address Offset: 0x0068 */
|
uint32_t RESERVED006C; /* Address Offset: 0x006C */
|
__IO uint32_t XMMC_RX_WTMRK; /* Address Offset: 0x0070 */
|
uint32_t RESERVED0074[3]; /* Address Offset: 0x0074 */
|
__IO uint32_t DMATR; /* Address Offset: 0x0080 */
|
__IO uint32_t DMAADDR; /* Address Offset: 0x0084 */
|
__IO uint32_t LEN_CTRL; /* Address Offset: 0x0088 */
|
__IO uint32_t LEN_EXT; /* Address Offset: 0x008C */
|
uint32_t RESERVED0090; /* Address Offset: 0x0090 */
|
__IO uint32_t XMMCSR; /* Address Offset: 0x0094 */
|
uint32_t RESERVED0098[26]; /* Address Offset: 0x0098 */
|
__O uint32_t CMD; /* Address Offset: 0x0100 */
|
__O uint32_t ADDR; /* Address Offset: 0x0104 */
|
__IO uint32_t DATA; /* Address Offset: 0x0108 */
|
uint32_t RESERVED010C[61]; /* Address Offset: 0x010C */
|
__IO uint32_t CTRL1; /* Address Offset: 0x0200 */
|
uint32_t RESERVED0204[4]; /* Address Offset: 0x0204 */
|
__IO uint32_t AX1; /* Address Offset: 0x0214 */
|
__IO uint32_t ABIT1; /* Address Offset: 0x0218 */
|
uint32_t RESERVED021C[8]; /* Address Offset: 0x021C */
|
__IO uint32_t DLL_CTRL1; /* Address Offset: 0x023C */
|
uint32_t RESERVED0240[4]; /* Address Offset: 0x0240 */
|
__O uint32_t XMMC_WCMD1; /* Address Offset: 0x0250 */
|
__O uint32_t XMMC_RCMD1; /* Address Offset: 0x0254 */
|
uint32_t RESERVED0258[3]; /* Address Offset: 0x0258 */
|
__IO uint32_t DEVSIZE1; /* Address Offset: 0x0264 */
|
__IO uint32_t TME1; /* Address Offset: 0x0268 */
|
};
|
/* DMA Register Structure Define */
|
struct DMA_CHANNEL_STATUS {
|
__I uint32_t CSR;
|
__I uint32_t CPC;
|
};
|
struct DMA_CHANNEL_CONFIG {
|
__I uint32_t SAR;
|
__I uint32_t DAR;
|
__I uint32_t CCR;
|
__I uint32_t LC0;
|
__I uint32_t LC1;
|
uint32_t PADDING[3];
|
};
|
struct DMA_REG {
|
__I uint32_t DSR; /* Address Offset: 0x0000 */
|
__I uint32_t DPC; /* Address Offset: 0x0004 */
|
uint32_t RESERVED0008[6]; /* Address Offset: 0x0008 */
|
__IO uint32_t INTEN; /* Address Offset: 0x0020 */
|
__I uint32_t EVENT_RIS; /* Address Offset: 0x0024 */
|
__I uint32_t INTMIS; /* Address Offset: 0x0028 */
|
__O uint32_t INTCLR; /* Address Offset: 0x002C */
|
__I uint32_t FSRD; /* Address Offset: 0x0030 */
|
__I uint32_t FSRC; /* Address Offset: 0x0034 */
|
__IO uint32_t FTRD; /* Address Offset: 0x0038 */
|
uint32_t RESERVED003C; /* Address Offset: 0x003C */
|
__I uint32_t FTR[6]; /* Address Offset: 0x0040 */
|
uint32_t RESERVED0058[42]; /* Address Offset: 0x0058 */
|
struct DMA_CHANNEL_STATUS CHAN_STS[8]; /* Address Offset: 0x0100 */
|
uint32_t RESERVED0140[176]; /* Address Offset: 0x0140 */
|
struct DMA_CHANNEL_CONFIG CHAN_CFG[8]; /* Address Offset: 0x0400 */
|
uint32_t RESERVED0500[512]; /* Address Offset: 0x0500 */
|
__I uint32_t DBGSTATUS; /* Address Offset: 0x0D00 */
|
__O uint32_t DBGCMD; /* Address Offset: 0x0D04 */
|
__O uint32_t DBGINST[2]; /* Address Offset: 0x0D08 */
|
uint32_t RESERVED0D10[60]; /* Address Offset: 0x0D10 */
|
__I uint32_t CR[5]; /* Address Offset: 0x0E00 */
|
__I uint32_t CRDN; /* Address Offset: 0x0E14 */
|
uint32_t RESERVED0E18[26]; /* Address Offset: 0x0E18 */
|
__IO uint32_t WD; /* Address Offset: 0x0E80 */
|
};
|
/* CAN Register Structure Define */
|
struct CAN_REG {
|
__IO uint32_t MODE; /* Address Offset: 0x0000 */
|
__IO uint32_t CMD; /* Address Offset: 0x0004 */
|
__I uint32_t STATE; /* Address Offset: 0x0008 */
|
__IO uint32_t INT; /* Address Offset: 0x000C */
|
__IO uint32_t INT_MASK; /* Address Offset: 0x0010 */
|
__IO uint32_t DMA_CTRL; /* Address Offset: 0x0014 */
|
__IO uint32_t BITTIMING; /* Address Offset: 0x0018 */
|
uint32_t RESERVED001C[3]; /* Address Offset: 0x001C */
|
__I uint32_t ARBITFAIL; /* Address Offset: 0x0028 */
|
__IO uint32_t ERROR_CODE; /* Address Offset: 0x002C */
|
uint32_t RESERVED0030; /* Address Offset: 0x0030 */
|
__I uint32_t RXERRORCNT; /* Address Offset: 0x0034 */
|
__I uint32_t TXERRORCNT; /* Address Offset: 0x0038 */
|
__IO uint32_t IDCODE; /* Address Offset: 0x003C */
|
__IO uint32_t IDMASK; /* Address Offset: 0x0040 */
|
uint32_t RESERVED0044[3]; /* Address Offset: 0x0044 */
|
__IO uint32_t TXFRAMEINFO; /* Address Offset: 0x0050 */
|
__IO uint32_t TXID; /* Address Offset: 0x0054 */
|
__IO uint32_t TXDATA0; /* Address Offset: 0x0058 */
|
__IO uint32_t TXDATA1; /* Address Offset: 0x005C */
|
__I uint32_t RXFRAMEINFO; /* Address Offset: 0x0060 */
|
__I uint32_t RXID; /* Address Offset: 0x0064 */
|
__I uint32_t RXDATA0; /* Address Offset: 0x0068 */
|
__I uint32_t RXDATA1; /* Address Offset: 0x006C */
|
__I uint32_t RTL_VERSION; /* Address Offset: 0x0070 */
|
uint32_t RESERVED0074[35]; /* Address Offset: 0x0074 */
|
__IO uint32_t FD_NOMINAL_BITTIMING; /* Address Offset: 0x0100 */
|
__IO uint32_t FD_DATA_BITTIMING; /* Address Offset: 0x0104 */
|
__IO uint32_t TRANSMIT_DELAY_COMPENSATION; /* Address Offset: 0x0108 */
|
__IO uint32_t TIMESTAMP_CTRL; /* Address Offset: 0x010C */
|
__IO uint32_t TIMESTAMP; /* Address Offset: 0x0110 */
|
__IO uint32_t TXEVENT_FIFO_CTRL; /* Address Offset: 0x0114 */
|
__IO uint32_t RX_FIFO_CTRL; /* Address Offset: 0x0118 */
|
__IO uint32_t AFR_CTRL; /* Address Offset: 0x011C */
|
__IO uint32_t IDCODE0; /* Address Offset: 0x0120 */
|
__IO uint32_t IDMASK0; /* Address Offset: 0x0124 */
|
__IO uint32_t IDCODE1; /* Address Offset: 0x0128 */
|
__IO uint32_t IDMASK1; /* Address Offset: 0x012C */
|
__IO uint32_t IDCODE2; /* Address Offset: 0x0130 */
|
__IO uint32_t IDMASK2; /* Address Offset: 0x0134 */
|
__IO uint32_t IDCODE3; /* Address Offset: 0x0138 */
|
__IO uint32_t IDMASK3; /* Address Offset: 0x013C */
|
__IO uint32_t IDCODE4; /* Address Offset: 0x0140 */
|
__IO uint32_t IDMASK4; /* Address Offset: 0x0144 */
|
uint32_t RESERVED0148[46]; /* Address Offset: 0x0148 */
|
__IO uint32_t FD_TXFRAMEINFO; /* Address Offset: 0x0200 */
|
__IO uint32_t FD_TXID; /* Address Offset: 0x0204 */
|
__IO uint32_t FD_TXDATA[16]; /* Address Offset: 0x0208 */
|
uint32_t RESERVED0248[46]; /* Address Offset: 0x0248 */
|
__IO uint32_t FD_RXFRAMEINFO; /* Address Offset: 0x0300 */
|
__I uint32_t FD_RXID; /* Address Offset: 0x0304 */
|
__I uint32_t FD_RXTIMESTAMP; /* Address Offset: 0x0308 */
|
__I uint32_t FD_RXDATA[16]; /* Address Offset: 0x030C */
|
uint32_t RESERVED034C[45]; /* Address Offset: 0x034C */
|
__I uint32_t RX_FIFO_RDATA; /* Address Offset: 0x0400 */
|
uint32_t RESERVED0404[63]; /* Address Offset: 0x0404 */
|
__I uint32_t TXE_FIFO_RDATA; /* Address Offset: 0x0500 */
|
};
|
/* WDT Register Structure Define */
|
struct WDT_REG {
|
__IO uint32_t CR; /* Address Offset: 0x0000 */
|
__IO uint32_t TORR; /* Address Offset: 0x0004 */
|
__I uint32_t CCVR; /* Address Offset: 0x0008 */
|
__O uint32_t CRR; /* Address Offset: 0x000C */
|
__I uint32_t STAT; /* Address Offset: 0x0010 */
|
__I uint32_t EOI; /* Address Offset: 0x0014 */
|
};
|
/* SPI Register Structure Define */
|
struct SPI_REG {
|
__IO uint32_t CTRLR[2]; /* Address Offset: 0x0000 */
|
__IO uint32_t ENR; /* Address Offset: 0x0008 */
|
__IO uint32_t SER; /* Address Offset: 0x000C */
|
__IO uint32_t BAUDR; /* Address Offset: 0x0010 */
|
__IO uint32_t TXFTLR; /* Address Offset: 0x0014 */
|
__IO uint32_t RXFTLR; /* Address Offset: 0x0018 */
|
__I uint32_t TXFLR; /* Address Offset: 0x001C */
|
__I uint32_t RXFLR; /* Address Offset: 0x0020 */
|
__I uint32_t SR; /* Address Offset: 0x0024 */
|
__IO uint32_t IPR; /* Address Offset: 0x0028 */
|
__IO uint32_t IMR; /* Address Offset: 0x002C */
|
__IO uint32_t ISR; /* Address Offset: 0x0030 */
|
__IO uint32_t RISR; /* Address Offset: 0x0034 */
|
__O uint32_t ICR; /* Address Offset: 0x0038 */
|
__IO uint32_t DMACR; /* Address Offset: 0x003C */
|
__IO uint32_t DMATDLR; /* Address Offset: 0x0040 */
|
__IO uint32_t DMARDLR; /* Address Offset: 0x0044 */
|
uint32_t RESERVED0048; /* Address Offset: 0x0048 */
|
__IO uint32_t TIMEOUT; /* Address Offset: 0x004C */
|
__IO uint32_t BYPASS; /* Address Offset: 0x0050 */
|
uint32_t RESERVED0054[235]; /* Address Offset: 0x0054 */
|
__O uint32_t TXDR; /* Address Offset: 0x0400 */
|
uint32_t RESERVED0404[255]; /* Address Offset: 0x0404 */
|
__I uint32_t RXDR; /* Address Offset: 0x0800 */
|
};
|
/* TSADC Register Structure Define */
|
struct TSADC_REG {
|
__IO uint32_t USER_CON; /* Address Offset: 0x0000 */
|
__IO uint32_t AUTO_CON; /* Address Offset: 0x0004 */
|
__IO uint32_t INT_EN; /* Address Offset: 0x0008 */
|
__IO uint32_t INT_PD; /* Address Offset: 0x000C */
|
uint32_t RESERVED0010[4]; /* Address Offset: 0x0010 */
|
__I uint32_t DATA[2]; /* Address Offset: 0x0020 */
|
uint32_t RESERVED0028[2]; /* Address Offset: 0x0028 */
|
__IO uint32_t COMP_INT[2]; /* Address Offset: 0x0030 */
|
uint32_t RESERVED0038[2]; /* Address Offset: 0x0038 */
|
__IO uint32_t COMP_SHUT[2]; /* Address Offset: 0x0040 */
|
uint32_t RESERVED0048[6]; /* Address Offset: 0x0048 */
|
__IO uint32_t HIGHT_INT_DEBOUNCE; /* Address Offset: 0x0060 */
|
__IO uint32_t HIGHT_TSHUT_DEBOUNCE; /* Address Offset: 0x0064 */
|
__IO uint32_t AUTO_PERIOD; /* Address Offset: 0x0068 */
|
__IO uint32_t AUTO_PERIOD_HT; /* Address Offset: 0x006C */
|
uint32_t RESERVED0070[4]; /* Address Offset: 0x0070 */
|
__IO uint32_t COMP_LOW_INT[2]; /* Address Offset: 0x0080 */
|
};
|
/* MBOX Register Structure Define */
|
struct MBOX_CMD_DAT {
|
__IO uint32_t CMD;
|
__IO uint32_t DATA;
|
};
|
struct MBOX_REG {
|
__IO uint32_t A2B_INTEN; /* Address Offset: 0x0000 */
|
__IO uint32_t A2B_STATUS; /* Address Offset: 0x0004 */
|
struct MBOX_CMD_DAT A2B[4]; /* Address Offset: 0x0008 */
|
__IO uint32_t B2A_INTEN; /* Address Offset: 0x0028 */
|
__IO uint32_t B2A_STATUS; /* Address Offset: 0x002C */
|
struct MBOX_CMD_DAT B2A[4]; /* Address Offset: 0x0030 */
|
uint32_t RESERVED0050[44]; /* Address Offset: 0x0050 */
|
__IO uint32_t ATOMIC_LOCK[32]; /* Address Offset: 0x0100 */
|
};
|
#endif /* __ASSEMBLY__ */
|
/****************************************************************************************/
|
/* */
|
/* Module Address Section */
|
/* */
|
/****************************************************************************************/
|
/* Memory Base */
|
#define GRF_BASE 0xFDC20000U /* GRF base address */
|
#define PMUCRU_BASE 0xFDD00000U /* PMUCRU base address */
|
#define TIMER6_BASE 0xFDD1C000U /* TIMER6 base address */
|
#define TIMER7_BASE 0xFDD1C020U /* TIMER7 base address */
|
#define CRU_BASE 0xFDD20000U /* CRU base address */
|
#define I2C0_BASE 0xFDD40000U /* I2C0 base address */
|
#define UART0_BASE 0xFDD50000U /* UART0 base address */
|
#define GPIO0_BASE 0xFDD60000U /* GPIO0 base address */
|
#define PWM0_BASE 0xFDD70000U /* PWM0 base address */
|
#define PMU_BASE 0xFDD90000U /* PMU base address */
|
#define SPINLOCK_BASE 0xFDE30000U /* SPINLOCK base address */
|
#define GMAC1_BASE 0xFE010000U /* GMAC1 base address */
|
#define GMAC0_BASE 0xFE2A0000U /* GMAC0 base address */
|
#define FSPI_BASE 0xFE300000U /* FSPI base address */
|
#define DMA0_BASE 0xFE530000U /* DMA0 base address */
|
#define DMA1_BASE 0xFE550000U /* DMA1 base address */
|
#define CAN0_BASE 0xFE570000U /* CAN0 base address */
|
#define CAN1_BASE 0xFE580000U /* CAN1 base address */
|
#define CAN2_BASE 0xFE590000U /* CAN2 base address */
|
#define I2C1_BASE 0xFE5A0000U /* I2C1 base address */
|
#define I2C2_BASE 0xFE5B0000U /* I2C2 base address */
|
#define I2C3_BASE 0xFE5C0000U /* I2C3 base address */
|
#define I2C4_BASE 0xFE5D0000U /* I2C4 base address */
|
#define I2C5_BASE 0xFE5E0000U /* I2C5 base address */
|
#define TIMER0_BASE 0xFE5F0000U /* TIMER0 base address */
|
#define TIMER1_BASE 0xFE5F0020U /* TIMER1 base address */
|
#define TIMER2_BASE 0xFE5F0040U /* TIMER2 base address */
|
#define TIMER3_BASE 0xFE5F0060U /* TIMER3 base address */
|
#define TIMER4_BASE 0xFE5F0080U /* TIMER4 base address */
|
#define TIMER5_BASE 0xFE5F00A0U /* TIMER5 base address */
|
#define WDT_BASE 0xFE600000U /* WDT base address */
|
#define SPI0_BASE 0xFE610000U /* SPI0 base address */
|
#define SPI1_BASE 0xFE620000U /* SPI1 base address */
|
#define SPI2_BASE 0xFE630000U /* SPI2 base address */
|
#define SPI3_BASE 0xFE640000U /* SPI3 base address */
|
#define UART1_BASE 0xFE650000U /* UART1 base address */
|
#define UART2_BASE 0xFE660000U /* UART2 base address */
|
#define UART3_BASE 0xFE670000U /* UART3 base address */
|
#define UART4_BASE 0xFE680000U /* UART4 base address */
|
#define UART5_BASE 0xFE690000U /* UART5 base address */
|
#define UART6_BASE 0xFE6A0000U /* UART6 base address */
|
#define UART7_BASE 0xFE6B0000U /* UART7 base address */
|
#define UART8_BASE 0xFE6C0000U /* UART8 base address */
|
#define UART9_BASE 0xFE6D0000U /* UART9 base address */
|
#define PWM1_BASE 0xFE6E0000U /* PWM1 base address */
|
#define PWM2_BASE 0xFE6F0000U /* PWM2 base address */
|
#define PWM3_BASE 0xFE700000U /* PWM3 base address */
|
#define TSADC_BASE 0xFE710000U /* TSADC base address */
|
#define GPIO1_BASE 0xFE740000U /* GPIO1 base address */
|
#define GPIO2_BASE 0xFE750000U /* GPIO2 base address */
|
#define GPIO3_BASE 0xFE760000U /* GPIO3 base address */
|
#define GPIO4_BASE 0xFE770000U /* GPIO4 base address */
|
#define MBOX0_BASE 0xFE780000U /* MBOX0 base address */
|
/****************************************************************************************/
|
/* */
|
/* Module Variable Section */
|
/* */
|
/****************************************************************************************/
|
/* Module Variable Define */
|
|
#define GRF ((struct GRF_REG *) GRF_BASE)
|
#define PMUCRU ((struct PMUCRU_REG *) PMUCRU_BASE)
|
#define TIMER6 ((struct TIMER_REG *) TIMER6_BASE)
|
#define TIMER7 ((struct TIMER_REG *) TIMER7_BASE)
|
#define CRU ((struct CRU_REG *) CRU_BASE)
|
#define I2C0 ((struct I2C_REG *) I2C0_BASE)
|
#define UART0 ((struct UART_REG *) UART0_BASE)
|
#define GPIO0 ((struct GPIO_REG *) GPIO0_BASE)
|
#define PWM0 ((struct PWM_REG *) PWM0_BASE)
|
#define PMU ((struct PMU_REG *) PMU_BASE)
|
#define SPINLOCK ((struct SPINLOCK_REG *) SPINLOCK_BASE)
|
#define GMAC1 ((struct GMAC_REG *) GMAC1_BASE)
|
#define GMAC0 ((struct GMAC_REG *) GMAC0_BASE)
|
#define FSPI ((struct FSPI_REG *) FSPI_BASE)
|
#define DMA0 ((struct DMA_REG *) DMA0_BASE)
|
#define DMA1 ((struct DMA_REG *) DMA1_BASE)
|
#define CAN0 ((struct CAN_REG *) CAN0_BASE)
|
#define CAN1 ((struct CAN_REG *) CAN1_BASE)
|
#define CAN2 ((struct CAN_REG *) CAN2_BASE)
|
#define I2C1 ((struct I2C_REG *) I2C1_BASE)
|
#define I2C2 ((struct I2C_REG *) I2C2_BASE)
|
#define I2C3 ((struct I2C_REG *) I2C3_BASE)
|
#define I2C4 ((struct I2C_REG *) I2C4_BASE)
|
#define I2C5 ((struct I2C_REG *) I2C5_BASE)
|
#define TIMER0 ((struct TIMER_REG *) TIMER0_BASE)
|
#define TIMER1 ((struct TIMER_REG *) TIMER1_BASE)
|
#define TIMER2 ((struct TIMER_REG *) TIMER2_BASE)
|
#define TIMER3 ((struct TIMER_REG *) TIMER3_BASE)
|
#define TIMER4 ((struct TIMER_REG *) TIMER4_BASE)
|
#define TIMER5 ((struct TIMER_REG *) TIMER5_BASE)
|
#define WDT ((struct WDT_REG *) WDT_BASE)
|
#define SPI0 ((struct SPI_REG *) SPI0_BASE)
|
#define SPI1 ((struct SPI_REG *) SPI1_BASE)
|
#define SPI2 ((struct SPI_REG *) SPI2_BASE)
|
#define SPI3 ((struct SPI_REG *) SPI3_BASE)
|
#define UART1 ((struct UART_REG *) UART1_BASE)
|
#define UART2 ((struct UART_REG *) UART2_BASE)
|
#define UART3 ((struct UART_REG *) UART3_BASE)
|
#define UART4 ((struct UART_REG *) UART4_BASE)
|
#define UART5 ((struct UART_REG *) UART5_BASE)
|
#define UART6 ((struct UART_REG *) UART6_BASE)
|
#define UART7 ((struct UART_REG *) UART7_BASE)
|
#define UART8 ((struct UART_REG *) UART8_BASE)
|
#define UART9 ((struct UART_REG *) UART9_BASE)
|
#define PWM1 ((struct PWM_REG *) PWM1_BASE)
|
#define PWM2 ((struct PWM_REG *) PWM2_BASE)
|
#define PWM3 ((struct PWM_REG *) PWM3_BASE)
|
#define TSADC ((struct TSADC_REG *) TSADC_BASE)
|
#define GPIO1 ((struct GPIO_REG *) GPIO1_BASE)
|
#define GPIO2 ((struct GPIO_REG *) GPIO2_BASE)
|
#define GPIO3 ((struct GPIO_REG *) GPIO3_BASE)
|
#define GPIO4 ((struct GPIO_REG *) GPIO4_BASE)
|
#define MBOX0 ((struct MBOX_REG *) MBOX0_BASE)
|
|
#define IS_GRF_INSTANCE(instance) ((instance) == GRF)
|
#define IS_PMUCRU_INSTANCE(instance) ((instance) == PMUCRU)
|
#define IS_CRU_INSTANCE(instance) ((instance) == CRU)
|
#define IS_PMU_INSTANCE(instance) ((instance) == PMU)
|
#define IS_SPINLOCK_INSTANCE(instance) ((instance) == SPINLOCK)
|
#define IS_FSPI_INSTANCE(instance) ((instance) == FSPI)
|
#define IS_WDT_INSTANCE(instance) ((instance) == WDT)
|
#define IS_TSADC_INSTANCE(instance) ((instance) == TSADC)
|
#define IS_TIMER_INSTANCE(instance) (((instance) == TIMER6) || ((instance) == TIMER7) || ((instance) == TIMER0) || ((instance) == TIMER1) || ((instance) == TIMER2) || ((instance) == TIMER3) || ((instance) == TIMER4) || ((instance) == TIMER5))
|
#define IS_I2C_INSTANCE(instance) (((instance) == I2C0) || ((instance) == I2C1) || ((instance) == I2C2) || ((instance) == I2C3) || ((instance) == I2C4) || ((instance) == I2C5))
|
#define IS_UART_INSTANCE(instance) (((instance) == UART0) || ((instance) == UART1) || ((instance) == UART2) || ((instance) == UART3) || ((instance) == UART4) || ((instance) == UART5) || ((instance) == UART6) || ((instance) == UART7) || ((instance) == UART8) || ((instance) == UART9))
|
#define IS_GPIO_INSTANCE(instance) (((instance) == GPIO0) || ((instance) == GPIO1) || ((instance) == GPIO2) || ((instance) == GPIO3) || ((instance) == GPIO4))
|
#define IS_PWM_INSTANCE(instance) (((instance) == PWM0) || ((instance) == PWM1) || ((instance) == PWM2) || ((instance) == PWM3))
|
#define IS_GMAC_INSTANCE(instance) (((instance) == GMAC1) || ((instance) == GMAC0))
|
#define IS_DMA_INSTANCE(instance) (((instance) == DMA0) || ((instance) == DMA1))
|
#define IS_CAN_INSTANCE(instance) (((instance) == CAN0) || ((instance) == CAN1) || ((instance) == CAN2))
|
#define IS_SPI_INSTANCE(instance) (((instance) == SPI0) || ((instance) == SPI1) || ((instance) == SPI2) || ((instance) == SPI3))
|
#define IS_MBOX_INSTANCE(instance) ((instance) == MBOX0)
|
/****************************************************************************************/
|
/* */
|
/* Register Bitmap Section */
|
/* */
|
/****************************************************************************************/
|
/******************************************GRF*******************************************/
|
/* GPIO0A_IOMUX_L */
|
#define GRF_GPIO0A_IOMUX_L_OFFSET (0x0U)
|
#define GRF_GPIO0A_IOMUX_L_GPIO0A0_SEL_SHIFT (0U)
|
#define GRF_GPIO0A_IOMUX_L_GPIO0A0_SEL_MASK (0x7U << GRF_GPIO0A_IOMUX_L_GPIO0A0_SEL_SHIFT) /* 0x00000007 */
|
#define GRF_GPIO0A_IOMUX_L_GPIO0A1_SEL_SHIFT (4U)
|
#define GRF_GPIO0A_IOMUX_L_GPIO0A1_SEL_MASK (0x7U << GRF_GPIO0A_IOMUX_L_GPIO0A1_SEL_SHIFT) /* 0x00000070 */
|
#define GRF_GPIO0A_IOMUX_L_GPIO0A2_SEL_SHIFT (8U)
|
#define GRF_GPIO0A_IOMUX_L_GPIO0A2_SEL_MASK (0x7U << GRF_GPIO0A_IOMUX_L_GPIO0A2_SEL_SHIFT) /* 0x00000700 */
|
#define GRF_GPIO0A_IOMUX_L_GPIO0A3_SEL_SHIFT (12U)
|
#define GRF_GPIO0A_IOMUX_L_GPIO0A3_SEL_MASK (0x7U << GRF_GPIO0A_IOMUX_L_GPIO0A3_SEL_SHIFT) /* 0x00007000 */
|
/* GPIO0A_IOMUX_H */
|
#define GRF_GPIO0A_IOMUX_H_OFFSET (0x4U)
|
#define GRF_GPIO0A_IOMUX_H_GPIO0A4_SEL_SHIFT (0U)
|
#define GRF_GPIO0A_IOMUX_H_GPIO0A4_SEL_MASK (0x7U << GRF_GPIO0A_IOMUX_H_GPIO0A4_SEL_SHIFT) /* 0x00000007 */
|
#define GRF_GPIO0A_IOMUX_H_GPIO0A5_SEL_SHIFT (4U)
|
#define GRF_GPIO0A_IOMUX_H_GPIO0A5_SEL_MASK (0x7U << GRF_GPIO0A_IOMUX_H_GPIO0A5_SEL_SHIFT) /* 0x00000070 */
|
#define GRF_GPIO0A_IOMUX_H_GPIO0A6_SEL_SHIFT (8U)
|
#define GRF_GPIO0A_IOMUX_H_GPIO0A6_SEL_MASK (0x7U << GRF_GPIO0A_IOMUX_H_GPIO0A6_SEL_SHIFT) /* 0x00000700 */
|
#define GRF_GPIO0A_IOMUX_H_GPIO0A7_SEL_SHIFT (12U)
|
#define GRF_GPIO0A_IOMUX_H_GPIO0A7_SEL_MASK (0x7U << GRF_GPIO0A_IOMUX_H_GPIO0A7_SEL_SHIFT) /* 0x00007000 */
|
/* GPIO0B_IOMUX_L */
|
#define GRF_GPIO0B_IOMUX_L_OFFSET (0x8U)
|
#define GRF_GPIO0B_IOMUX_L_GPIO0B0_SEL_SHIFT (0U)
|
#define GRF_GPIO0B_IOMUX_L_GPIO0B0_SEL_MASK (0x7U << GRF_GPIO0B_IOMUX_L_GPIO0B0_SEL_SHIFT) /* 0x00000007 */
|
#define GRF_GPIO0B_IOMUX_L_GPIO0B1_SEL_SHIFT (4U)
|
#define GRF_GPIO0B_IOMUX_L_GPIO0B1_SEL_MASK (0x7U << GRF_GPIO0B_IOMUX_L_GPIO0B1_SEL_SHIFT) /* 0x00000070 */
|
#define GRF_GPIO0B_IOMUX_L_GPIO0B2_SEL_SHIFT (8U)
|
#define GRF_GPIO0B_IOMUX_L_GPIO0B2_SEL_MASK (0x7U << GRF_GPIO0B_IOMUX_L_GPIO0B2_SEL_SHIFT) /* 0x00000700 */
|
#define GRF_GPIO0B_IOMUX_L_GPIO0B3_SEL_SHIFT (12U)
|
#define GRF_GPIO0B_IOMUX_L_GPIO0B3_SEL_MASK (0x7U << GRF_GPIO0B_IOMUX_L_GPIO0B3_SEL_SHIFT) /* 0x00007000 */
|
/* GPIO0B_IOMUX_H */
|
#define GRF_GPIO0B_IOMUX_H_OFFSET (0xCU)
|
#define GRF_GPIO0B_IOMUX_H_GPIO0B4_SEL_SHIFT (0U)
|
#define GRF_GPIO0B_IOMUX_H_GPIO0B4_SEL_MASK (0x7U << GRF_GPIO0B_IOMUX_H_GPIO0B4_SEL_SHIFT) /* 0x00000007 */
|
#define GRF_GPIO0B_IOMUX_H_GPIO0B5_SEL_SHIFT (4U)
|
#define GRF_GPIO0B_IOMUX_H_GPIO0B5_SEL_MASK (0x7U << GRF_GPIO0B_IOMUX_H_GPIO0B5_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO0B_IOMUX_H_GPIO0B6_SEL_SHIFT (8U)
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#define GRF_GPIO0B_IOMUX_H_GPIO0B6_SEL_MASK (0x7U << GRF_GPIO0B_IOMUX_H_GPIO0B6_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO0B_IOMUX_H_GPIO0B7_SEL_SHIFT (12U)
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#define GRF_GPIO0B_IOMUX_H_GPIO0B7_SEL_MASK (0x7U << GRF_GPIO0B_IOMUX_H_GPIO0B7_SEL_SHIFT) /* 0x00007000 */
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/* GPIO0C_IOMUX_L */
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#define GRF_GPIO0C_IOMUX_L_OFFSET (0x10U)
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#define GRF_GPIO0C_IOMUX_L_GPIO0C0_SEL_SHIFT (0U)
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#define GRF_GPIO0C_IOMUX_L_GPIO0C0_SEL_MASK (0x7U << GRF_GPIO0C_IOMUX_L_GPIO0C0_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO0C_IOMUX_L_GPIO0C1_SEL_SHIFT (4U)
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#define GRF_GPIO0C_IOMUX_L_GPIO0C1_SEL_MASK (0x7U << GRF_GPIO0C_IOMUX_L_GPIO0C1_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO0C_IOMUX_L_GPIO0C2_SEL_SHIFT (8U)
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#define GRF_GPIO0C_IOMUX_L_GPIO0C2_SEL_MASK (0x7U << GRF_GPIO0C_IOMUX_L_GPIO0C2_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO0C_IOMUX_L_GPIO0C3_SEL_SHIFT (12U)
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#define GRF_GPIO0C_IOMUX_L_GPIO0C3_SEL_MASK (0x7U << GRF_GPIO0C_IOMUX_L_GPIO0C3_SEL_SHIFT) /* 0x00007000 */
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/* GPIO0C_IOMUX_H */
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#define GRF_GPIO0C_IOMUX_H_OFFSET (0x14U)
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#define GRF_GPIO0C_IOMUX_H_GPIO0C4_SEL_SHIFT (0U)
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#define GRF_GPIO0C_IOMUX_H_GPIO0C4_SEL_MASK (0x7U << GRF_GPIO0C_IOMUX_H_GPIO0C4_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO0C_IOMUX_H_GPIO0C5_SEL_SHIFT (4U)
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#define GRF_GPIO0C_IOMUX_H_GPIO0C5_SEL_MASK (0x7U << GRF_GPIO0C_IOMUX_H_GPIO0C5_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO0C_IOMUX_H_GPIO0C6_SEL_SHIFT (8U)
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#define GRF_GPIO0C_IOMUX_H_GPIO0C6_SEL_MASK (0x7U << GRF_GPIO0C_IOMUX_H_GPIO0C6_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO0C_IOMUX_H_GPIO0C7_SEL_SHIFT (12U)
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#define GRF_GPIO0C_IOMUX_H_GPIO0C7_SEL_MASK (0x7U << GRF_GPIO0C_IOMUX_H_GPIO0C7_SEL_SHIFT) /* 0x00007000 */
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/* GPIO0D_IOMUX_L */
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#define GRF_GPIO0D_IOMUX_L_OFFSET (0x18U)
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#define GRF_GPIO0D_IOMUX_L_GPIO0D0_SEL_SHIFT (0U)
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#define GRF_GPIO0D_IOMUX_L_GPIO0D0_SEL_MASK (0x7U << GRF_GPIO0D_IOMUX_L_GPIO0D0_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO0D_IOMUX_L_GPIO0D1_SEL_SHIFT (4U)
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#define GRF_GPIO0D_IOMUX_L_GPIO0D1_SEL_MASK (0x7U << GRF_GPIO0D_IOMUX_L_GPIO0D1_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO0D_IOMUX_L_GPIO0D3_SEL_SHIFT (12U)
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#define GRF_GPIO0D_IOMUX_L_GPIO0D3_SEL_MASK (0x7U << GRF_GPIO0D_IOMUX_L_GPIO0D3_SEL_SHIFT) /* 0x00007000 */
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/* GPIO0D_IOMUX_H */
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#define GRF_GPIO0D_IOMUX_H_OFFSET (0x1CU)
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#define GRF_GPIO0D_IOMUX_H_GPIO0D4_SEL_SHIFT (0U)
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#define GRF_GPIO0D_IOMUX_H_GPIO0D4_SEL_MASK (0x7U << GRF_GPIO0D_IOMUX_H_GPIO0D4_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO0D_IOMUX_H_GPIO0D5_SEL_SHIFT (4U)
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#define GRF_GPIO0D_IOMUX_H_GPIO0D5_SEL_MASK (0x7U << GRF_GPIO0D_IOMUX_H_GPIO0D5_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO0D_IOMUX_H_GPIO0D6_SEL_SHIFT (8U)
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#define GRF_GPIO0D_IOMUX_H_GPIO0D6_SEL_MASK (0x7U << GRF_GPIO0D_IOMUX_H_GPIO0D6_SEL_SHIFT) /* 0x00000700 */
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/* GPIO0A_P */
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#define GRF_GPIO0A_P_OFFSET (0x20U)
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#define GRF_GPIO0A_P_GPIO0A0_P_SHIFT (0U)
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#define GRF_GPIO0A_P_GPIO0A0_P_MASK (0x3U << GRF_GPIO0A_P_GPIO0A0_P_SHIFT) /* 0x00000003 */
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#define GRF_GPIO0A_P_GPIO0A1_P_SHIFT (2U)
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#define GRF_GPIO0A_P_GPIO0A1_P_MASK (0x3U << GRF_GPIO0A_P_GPIO0A1_P_SHIFT) /* 0x0000000C */
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#define GRF_GPIO0A_P_GPIO0A2_P_SHIFT (4U)
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#define GRF_GPIO0A_P_GPIO0A2_P_MASK (0x3U << GRF_GPIO0A_P_GPIO0A2_P_SHIFT) /* 0x00000030 */
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#define GRF_GPIO0A_P_GPIO0A3_P_SHIFT (6U)
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#define GRF_GPIO0A_P_GPIO0A3_P_MASK (0x3U << GRF_GPIO0A_P_GPIO0A3_P_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO0A_P_GPIO0A4_P_SHIFT (8U)
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#define GRF_GPIO0A_P_GPIO0A4_P_MASK (0x3U << GRF_GPIO0A_P_GPIO0A4_P_SHIFT) /* 0x00000300 */
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#define GRF_GPIO0A_P_GPIO0A5_P_SHIFT (10U)
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#define GRF_GPIO0A_P_GPIO0A5_P_MASK (0x3U << GRF_GPIO0A_P_GPIO0A5_P_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO0A_P_GPIO0A6_P_SHIFT (12U)
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#define GRF_GPIO0A_P_GPIO0A6_P_MASK (0x3U << GRF_GPIO0A_P_GPIO0A6_P_SHIFT) /* 0x00003000 */
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#define GRF_GPIO0A_P_GPIO0A7_P_SHIFT (14U)
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#define GRF_GPIO0A_P_GPIO0A7_P_MASK (0x3U << GRF_GPIO0A_P_GPIO0A7_P_SHIFT) /* 0x0000C000 */
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/* GPIO0B_P */
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#define GRF_GPIO0B_P_OFFSET (0x24U)
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#define GRF_GPIO0B_P_GPIO0B0_P_SHIFT (0U)
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#define GRF_GPIO0B_P_GPIO0B0_P_MASK (0x3U << GRF_GPIO0B_P_GPIO0B0_P_SHIFT) /* 0x00000003 */
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#define GRF_GPIO0B_P_GPIO0B1_P_SHIFT (2U)
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#define GRF_GPIO0B_P_GPIO0B1_P_MASK (0x3U << GRF_GPIO0B_P_GPIO0B1_P_SHIFT) /* 0x0000000C */
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#define GRF_GPIO0B_P_GPIO0B2_P_SHIFT (4U)
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#define GRF_GPIO0B_P_GPIO0B2_P_MASK (0x3U << GRF_GPIO0B_P_GPIO0B2_P_SHIFT) /* 0x00000030 */
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#define GRF_GPIO0B_P_GPIO0B3_P_SHIFT (6U)
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#define GRF_GPIO0B_P_GPIO0B3_P_MASK (0x3U << GRF_GPIO0B_P_GPIO0B3_P_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO0B_P_GPIO0B4_P_SHIFT (8U)
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#define GRF_GPIO0B_P_GPIO0B4_P_MASK (0x3U << GRF_GPIO0B_P_GPIO0B4_P_SHIFT) /* 0x00000300 */
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#define GRF_GPIO0B_P_GPIO0B5_P_SHIFT (10U)
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#define GRF_GPIO0B_P_GPIO0B5_P_MASK (0x3U << GRF_GPIO0B_P_GPIO0B5_P_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO0B_P_GPIO0B6_P_SHIFT (12U)
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#define GRF_GPIO0B_P_GPIO0B6_P_MASK (0x3U << GRF_GPIO0B_P_GPIO0B6_P_SHIFT) /* 0x00003000 */
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#define GRF_GPIO0B_P_GPIO0B7_P_SHIFT (14U)
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#define GRF_GPIO0B_P_GPIO0B7_P_MASK (0x3U << GRF_GPIO0B_P_GPIO0B7_P_SHIFT) /* 0x0000C000 */
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/* GPIO0C_P */
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#define GRF_GPIO0C_P_OFFSET (0x28U)
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#define GRF_GPIO0C_P_GPIO0C0_P_SHIFT (0U)
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#define GRF_GPIO0C_P_GPIO0C0_P_MASK (0x3U << GRF_GPIO0C_P_GPIO0C0_P_SHIFT) /* 0x00000003 */
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#define GRF_GPIO0C_P_GPIO0C1_P_SHIFT (2U)
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#define GRF_GPIO0C_P_GPIO0C1_P_MASK (0x3U << GRF_GPIO0C_P_GPIO0C1_P_SHIFT) /* 0x0000000C */
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#define GRF_GPIO0C_P_GPIO0C2_P_SHIFT (4U)
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#define GRF_GPIO0C_P_GPIO0C2_P_MASK (0x3U << GRF_GPIO0C_P_GPIO0C2_P_SHIFT) /* 0x00000030 */
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#define GRF_GPIO0C_P_GPIO0C3_P_SHIFT (6U)
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#define GRF_GPIO0C_P_GPIO0C3_P_MASK (0x3U << GRF_GPIO0C_P_GPIO0C3_P_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO0C_P_GPIO0C4_P_SHIFT (8U)
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#define GRF_GPIO0C_P_GPIO0C4_P_MASK (0x3U << GRF_GPIO0C_P_GPIO0C4_P_SHIFT) /* 0x00000300 */
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#define GRF_GPIO0C_P_GPIO0C5_P_SHIFT (10U)
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#define GRF_GPIO0C_P_GPIO0C5_P_MASK (0x3U << GRF_GPIO0C_P_GPIO0C5_P_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO0C_P_GPIO0C6_P_SHIFT (12U)
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#define GRF_GPIO0C_P_GPIO0C6_P_MASK (0x3U << GRF_GPIO0C_P_GPIO0C6_P_SHIFT) /* 0x00003000 */
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#define GRF_GPIO0C_P_GPIO0C7_P_SHIFT (14U)
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#define GRF_GPIO0C_P_GPIO0C7_P_MASK (0x3U << GRF_GPIO0C_P_GPIO0C7_P_SHIFT) /* 0x0000C000 */
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/* GPIO0D_P */
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#define GRF_GPIO0D_P_OFFSET (0x2CU)
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#define GRF_GPIO0D_P_GPIO0D0_P_SHIFT (0U)
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#define GRF_GPIO0D_P_GPIO0D0_P_MASK (0x3U << GRF_GPIO0D_P_GPIO0D0_P_SHIFT) /* 0x00000003 */
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#define GRF_GPIO0D_P_GPIO0D1_P_SHIFT (2U)
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#define GRF_GPIO0D_P_GPIO0D1_P_MASK (0x3U << GRF_GPIO0D_P_GPIO0D1_P_SHIFT) /* 0x0000000C */
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#define GRF_GPIO0D_P_GPIO0D2_P_SHIFT (4U)
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#define GRF_GPIO0D_P_GPIO0D2_P_MASK (0x3U << GRF_GPIO0D_P_GPIO0D2_P_SHIFT) /* 0x00000030 */
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#define GRF_GPIO0D_P_GPIO0D3_P_SHIFT (6U)
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#define GRF_GPIO0D_P_GPIO0D3_P_MASK (0x3U << GRF_GPIO0D_P_GPIO0D3_P_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO0D_P_GPIO0D4_P_SHIFT (8U)
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#define GRF_GPIO0D_P_GPIO0D4_P_MASK (0x3U << GRF_GPIO0D_P_GPIO0D4_P_SHIFT) /* 0x00000300 */
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#define GRF_GPIO0D_P_GPIO0D5_P_SHIFT (10U)
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#define GRF_GPIO0D_P_GPIO0D5_P_MASK (0x3U << GRF_GPIO0D_P_GPIO0D5_P_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO0D_P_GPIO0D6_P_SHIFT (12U)
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#define GRF_GPIO0D_P_GPIO0D6_P_MASK (0x3U << GRF_GPIO0D_P_GPIO0D6_P_SHIFT) /* 0x00003000 */
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/* GPIO0A_IE */
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#define GRF_GPIO0A_IE_OFFSET (0x30U)
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#define GRF_GPIO0A_IE_GPIO0A0_IE_SHIFT (0U)
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#define GRF_GPIO0A_IE_GPIO0A0_IE_MASK (0x3U << GRF_GPIO0A_IE_GPIO0A0_IE_SHIFT) /* 0x00000003 */
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#define GRF_GPIO0A_IE_GPIO0A1_IE_SHIFT (2U)
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#define GRF_GPIO0A_IE_GPIO0A1_IE_MASK (0x3U << GRF_GPIO0A_IE_GPIO0A1_IE_SHIFT) /* 0x0000000C */
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#define GRF_GPIO0A_IE_GPIO0A2_IE_SHIFT (4U)
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#define GRF_GPIO0A_IE_GPIO0A2_IE_MASK (0x3U << GRF_GPIO0A_IE_GPIO0A2_IE_SHIFT) /* 0x00000030 */
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#define GRF_GPIO0A_IE_GPIO0A3_IE_SHIFT (6U)
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#define GRF_GPIO0A_IE_GPIO0A3_IE_MASK (0x3U << GRF_GPIO0A_IE_GPIO0A3_IE_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO0A_IE_GPIO0A4_IE_SHIFT (8U)
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#define GRF_GPIO0A_IE_GPIO0A4_IE_MASK (0x3U << GRF_GPIO0A_IE_GPIO0A4_IE_SHIFT) /* 0x00000300 */
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#define GRF_GPIO0A_IE_GPIO0A5_IE_SHIFT (10U)
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#define GRF_GPIO0A_IE_GPIO0A5_IE_MASK (0x3U << GRF_GPIO0A_IE_GPIO0A5_IE_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO0A_IE_GPIO0A6_IE_SHIFT (12U)
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#define GRF_GPIO0A_IE_GPIO0A6_IE_MASK (0x3U << GRF_GPIO0A_IE_GPIO0A6_IE_SHIFT) /* 0x00003000 */
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#define GRF_GPIO0A_IE_GPIO0A7_IE_SHIFT (14U)
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#define GRF_GPIO0A_IE_GPIO0A7_IE_MASK (0x3U << GRF_GPIO0A_IE_GPIO0A7_IE_SHIFT) /* 0x0000C000 */
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/* GPIO0B_IE */
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#define GRF_GPIO0B_IE_OFFSET (0x34U)
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#define GRF_GPIO0B_IE_GPIO0B0_IE_SHIFT (0U)
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#define GRF_GPIO0B_IE_GPIO0B0_IE_MASK (0x3U << GRF_GPIO0B_IE_GPIO0B0_IE_SHIFT) /* 0x00000003 */
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#define GRF_GPIO0B_IE_GPIO0B1_IE_SHIFT (2U)
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#define GRF_GPIO0B_IE_GPIO0B1_IE_MASK (0x3U << GRF_GPIO0B_IE_GPIO0B1_IE_SHIFT) /* 0x0000000C */
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#define GRF_GPIO0B_IE_GPIO0B2_IE_SHIFT (4U)
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#define GRF_GPIO0B_IE_GPIO0B2_IE_MASK (0x3U << GRF_GPIO0B_IE_GPIO0B2_IE_SHIFT) /* 0x00000030 */
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#define GRF_GPIO0B_IE_GPIO0B3_IE_SHIFT (6U)
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#define GRF_GPIO0B_IE_GPIO0B3_IE_MASK (0x3U << GRF_GPIO0B_IE_GPIO0B3_IE_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO0B_IE_GPIO0B4_IE_SHIFT (8U)
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#define GRF_GPIO0B_IE_GPIO0B4_IE_MASK (0x3U << GRF_GPIO0B_IE_GPIO0B4_IE_SHIFT) /* 0x00000300 */
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#define GRF_GPIO0B_IE_GPIO0B5_IE_SHIFT (10U)
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#define GRF_GPIO0B_IE_GPIO0B5_IE_MASK (0x3U << GRF_GPIO0B_IE_GPIO0B5_IE_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO0B_IE_GPIO0B6_IE_SHIFT (12U)
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#define GRF_GPIO0B_IE_GPIO0B6_IE_MASK (0x3U << GRF_GPIO0B_IE_GPIO0B6_IE_SHIFT) /* 0x00003000 */
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#define GRF_GPIO0B_IE_GPIO0B7_IE_SHIFT (14U)
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#define GRF_GPIO0B_IE_GPIO0B7_IE_MASK (0x3U << GRF_GPIO0B_IE_GPIO0B7_IE_SHIFT) /* 0x0000C000 */
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/* GPIO0C_IE */
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#define GRF_GPIO0C_IE_OFFSET (0x38U)
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#define GRF_GPIO0C_IE_GPIO0C0_IE_SHIFT (0U)
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#define GRF_GPIO0C_IE_GPIO0C0_IE_MASK (0x3U << GRF_GPIO0C_IE_GPIO0C0_IE_SHIFT) /* 0x00000003 */
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#define GRF_GPIO0C_IE_GPIO0C1_IE_SHIFT (2U)
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#define GRF_GPIO0C_IE_GPIO0C1_IE_MASK (0x3U << GRF_GPIO0C_IE_GPIO0C1_IE_SHIFT) /* 0x0000000C */
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#define GRF_GPIO0C_IE_GPIO0C2_IE_SHIFT (4U)
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#define GRF_GPIO0C_IE_GPIO0C2_IE_MASK (0x3U << GRF_GPIO0C_IE_GPIO0C2_IE_SHIFT) /* 0x00000030 */
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#define GRF_GPIO0C_IE_GPIO0C3_IE_SHIFT (6U)
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#define GRF_GPIO0C_IE_GPIO0C3_IE_MASK (0x3U << GRF_GPIO0C_IE_GPIO0C3_IE_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO0C_IE_GPIO0C4_IE_SHIFT (8U)
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#define GRF_GPIO0C_IE_GPIO0C4_IE_MASK (0x3U << GRF_GPIO0C_IE_GPIO0C4_IE_SHIFT) /* 0x00000300 */
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#define GRF_GPIO0C_IE_GPIO0C5_IE_SHIFT (10U)
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#define GRF_GPIO0C_IE_GPIO0C5_IE_MASK (0x3U << GRF_GPIO0C_IE_GPIO0C5_IE_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO0C_IE_GPIO0C6_IE_SHIFT (12U)
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#define GRF_GPIO0C_IE_GPIO0C6_IE_MASK (0x3U << GRF_GPIO0C_IE_GPIO0C6_IE_SHIFT) /* 0x00003000 */
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#define GRF_GPIO0C_IE_GPIO0C7_IE_SHIFT (14U)
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#define GRF_GPIO0C_IE_GPIO0C7_IE_MASK (0x3U << GRF_GPIO0C_IE_GPIO0C7_IE_SHIFT) /* 0x0000C000 */
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/* GPIO0D_IE */
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#define GRF_GPIO0D_IE_OFFSET (0x3CU)
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#define GRF_GPIO0D_IE_GPIO0D0_IE_SHIFT (0U)
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#define GRF_GPIO0D_IE_GPIO0D0_IE_MASK (0x3U << GRF_GPIO0D_IE_GPIO0D0_IE_SHIFT) /* 0x00000003 */
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#define GRF_GPIO0D_IE_GPIO0D1_IE_SHIFT (2U)
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#define GRF_GPIO0D_IE_GPIO0D1_IE_MASK (0x3U << GRF_GPIO0D_IE_GPIO0D1_IE_SHIFT) /* 0x0000000C */
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/* GPIO0A_OPD */
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#define GRF_GPIO0A_OPD_OFFSET (0x40U)
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#define GRF_GPIO0A_OPD_GPIO0A0_OPD_SHIFT (0U)
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#define GRF_GPIO0A_OPD_GPIO0A0_OPD_MASK (0x1U << GRF_GPIO0A_OPD_GPIO0A0_OPD_SHIFT) /* 0x00000001 */
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#define GRF_GPIO0A_OPD_GPIO0A1_OPD_SHIFT (1U)
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#define GRF_GPIO0A_OPD_GPIO0A1_OPD_MASK (0x1U << GRF_GPIO0A_OPD_GPIO0A1_OPD_SHIFT) /* 0x00000002 */
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#define GRF_GPIO0A_OPD_GPIO0A2_OPD_SHIFT (2U)
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#define GRF_GPIO0A_OPD_GPIO0A2_OPD_MASK (0x1U << GRF_GPIO0A_OPD_GPIO0A2_OPD_SHIFT) /* 0x00000004 */
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#define GRF_GPIO0A_OPD_GPIO0A3_OPD_SHIFT (3U)
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#define GRF_GPIO0A_OPD_GPIO0A3_OPD_MASK (0x1U << GRF_GPIO0A_OPD_GPIO0A3_OPD_SHIFT) /* 0x00000008 */
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#define GRF_GPIO0A_OPD_GPIO0A4_OPD_SHIFT (4U)
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#define GRF_GPIO0A_OPD_GPIO0A4_OPD_MASK (0x1U << GRF_GPIO0A_OPD_GPIO0A4_OPD_SHIFT) /* 0x00000010 */
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#define GRF_GPIO0A_OPD_GPIO0A5_OPD_SHIFT (5U)
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#define GRF_GPIO0A_OPD_GPIO0A5_OPD_MASK (0x1U << GRF_GPIO0A_OPD_GPIO0A5_OPD_SHIFT) /* 0x00000020 */
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#define GRF_GPIO0A_OPD_GPIO0A6_OPD_SHIFT (6U)
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#define GRF_GPIO0A_OPD_GPIO0A6_OPD_MASK (0x1U << GRF_GPIO0A_OPD_GPIO0A6_OPD_SHIFT) /* 0x00000040 */
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#define GRF_GPIO0A_OPD_GPIO0A7_OPD_SHIFT (7U)
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#define GRF_GPIO0A_OPD_GPIO0A7_OPD_MASK (0x1U << GRF_GPIO0A_OPD_GPIO0A7_OPD_SHIFT) /* 0x00000080 */
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/* GPIO0B_OPD */
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#define GRF_GPIO0B_OPD_OFFSET (0x44U)
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#define GRF_GPIO0B_OPD_GPIO0B0_OPD_SHIFT (0U)
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#define GRF_GPIO0B_OPD_GPIO0B0_OPD_MASK (0x1U << GRF_GPIO0B_OPD_GPIO0B0_OPD_SHIFT) /* 0x00000001 */
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#define GRF_GPIO0B_OPD_GPIO0B1_OPD_SHIFT (1U)
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#define GRF_GPIO0B_OPD_GPIO0B1_OPD_MASK (0x1U << GRF_GPIO0B_OPD_GPIO0B1_OPD_SHIFT) /* 0x00000002 */
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#define GRF_GPIO0B_OPD_GPIO0B2_OPD_SHIFT (2U)
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#define GRF_GPIO0B_OPD_GPIO0B2_OPD_MASK (0x1U << GRF_GPIO0B_OPD_GPIO0B2_OPD_SHIFT) /* 0x00000004 */
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#define GRF_GPIO0B_OPD_GPIO0B3_OPD_SHIFT (3U)
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#define GRF_GPIO0B_OPD_GPIO0B3_OPD_MASK (0x1U << GRF_GPIO0B_OPD_GPIO0B3_OPD_SHIFT) /* 0x00000008 */
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#define GRF_GPIO0B_OPD_GPIO0B4_OPD_SHIFT (4U)
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#define GRF_GPIO0B_OPD_GPIO0B4_OPD_MASK (0x1U << GRF_GPIO0B_OPD_GPIO0B4_OPD_SHIFT) /* 0x00000010 */
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#define GRF_GPIO0B_OPD_GPIO0B5_OPD_SHIFT (5U)
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#define GRF_GPIO0B_OPD_GPIO0B5_OPD_MASK (0x1U << GRF_GPIO0B_OPD_GPIO0B5_OPD_SHIFT) /* 0x00000020 */
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#define GRF_GPIO0B_OPD_GPIO0B6_OPD_SHIFT (6U)
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#define GRF_GPIO0B_OPD_GPIO0B6_OPD_MASK (0x1U << GRF_GPIO0B_OPD_GPIO0B6_OPD_SHIFT) /* 0x00000040 */
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#define GRF_GPIO0B_OPD_GPIO0B7_OPD_SHIFT (7U)
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#define GRF_GPIO0B_OPD_GPIO0B7_OPD_MASK (0x1U << GRF_GPIO0B_OPD_GPIO0B7_OPD_SHIFT) /* 0x00000080 */
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/* GPIO0C_OPD */
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#define GRF_GPIO0C_OPD_OFFSET (0x48U)
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#define GRF_GPIO0C_OPD_GPIO0C0_OPD_SHIFT (0U)
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#define GRF_GPIO0C_OPD_GPIO0C0_OPD_MASK (0x1U << GRF_GPIO0C_OPD_GPIO0C0_OPD_SHIFT) /* 0x00000001 */
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#define GRF_GPIO0C_OPD_GPIO0C1_OPD_SHIFT (1U)
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#define GRF_GPIO0C_OPD_GPIO0C1_OPD_MASK (0x1U << GRF_GPIO0C_OPD_GPIO0C1_OPD_SHIFT) /* 0x00000002 */
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#define GRF_GPIO0C_OPD_GPIO0C2_OPD_SHIFT (2U)
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#define GRF_GPIO0C_OPD_GPIO0C2_OPD_MASK (0x1U << GRF_GPIO0C_OPD_GPIO0C2_OPD_SHIFT) /* 0x00000004 */
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#define GRF_GPIO0C_OPD_GPIO0C3_OPD_SHIFT (3U)
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#define GRF_GPIO0C_OPD_GPIO0C3_OPD_MASK (0x1U << GRF_GPIO0C_OPD_GPIO0C3_OPD_SHIFT) /* 0x00000008 */
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#define GRF_GPIO0C_OPD_GPIO0C4_OPD_SHIFT (4U)
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#define GRF_GPIO0C_OPD_GPIO0C4_OPD_MASK (0x1U << GRF_GPIO0C_OPD_GPIO0C4_OPD_SHIFT) /* 0x00000010 */
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#define GRF_GPIO0C_OPD_GPIO0C5_OPD_SHIFT (5U)
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#define GRF_GPIO0C_OPD_GPIO0C5_OPD_MASK (0x1U << GRF_GPIO0C_OPD_GPIO0C5_OPD_SHIFT) /* 0x00000020 */
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#define GRF_GPIO0C_OPD_GPIO0C6_OPD_SHIFT (6U)
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#define GRF_GPIO0C_OPD_GPIO0C6_OPD_MASK (0x1U << GRF_GPIO0C_OPD_GPIO0C6_OPD_SHIFT) /* 0x00000040 */
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#define GRF_GPIO0C_OPD_GPIO0C7_OPD_SHIFT (7U)
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#define GRF_GPIO0C_OPD_GPIO0C7_OPD_MASK (0x1U << GRF_GPIO0C_OPD_GPIO0C7_OPD_SHIFT) /* 0x00000080 */
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/* GPIO0D_OPD */
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#define GRF_GPIO0D_OPD_OFFSET (0x4CU)
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#define GRF_GPIO0D_OPD_GPIO0D0_OPD_SHIFT (0U)
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#define GRF_GPIO0D_OPD_GPIO0D0_OPD_MASK (0x1U << GRF_GPIO0D_OPD_GPIO0D0_OPD_SHIFT) /* 0x00000001 */
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#define GRF_GPIO0D_OPD_GPIO0D1_OPD_SHIFT (1U)
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#define GRF_GPIO0D_OPD_GPIO0D1_OPD_MASK (0x1U << GRF_GPIO0D_OPD_GPIO0D1_OPD_SHIFT) /* 0x00000002 */
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/* GPIO0A_SUS */
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#define GRF_GPIO0A_SUS_OFFSET (0x50U)
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#define GRF_GPIO0A_SUS_GPIO0A0_SUS_SHIFT (0U)
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#define GRF_GPIO0A_SUS_GPIO0A0_SUS_MASK (0x1U << GRF_GPIO0A_SUS_GPIO0A0_SUS_SHIFT) /* 0x00000001 */
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#define GRF_GPIO0A_SUS_GPIO0A1_SUS_SHIFT (1U)
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#define GRF_GPIO0A_SUS_GPIO0A1_SUS_MASK (0x1U << GRF_GPIO0A_SUS_GPIO0A1_SUS_SHIFT) /* 0x00000002 */
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#define GRF_GPIO0A_SUS_GPIO0A2_SUS_SHIFT (2U)
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#define GRF_GPIO0A_SUS_GPIO0A2_SUS_MASK (0x1U << GRF_GPIO0A_SUS_GPIO0A2_SUS_SHIFT) /* 0x00000004 */
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#define GRF_GPIO0A_SUS_GPIO0A3_SUS_SHIFT (3U)
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#define GRF_GPIO0A_SUS_GPIO0A3_SUS_MASK (0x1U << GRF_GPIO0A_SUS_GPIO0A3_SUS_SHIFT) /* 0x00000008 */
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#define GRF_GPIO0A_SUS_GPIO0A4_SUS_SHIFT (4U)
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#define GRF_GPIO0A_SUS_GPIO0A4_SUS_MASK (0x1U << GRF_GPIO0A_SUS_GPIO0A4_SUS_SHIFT) /* 0x00000010 */
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#define GRF_GPIO0A_SUS_GPIO0A5_SUS_SHIFT (5U)
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#define GRF_GPIO0A_SUS_GPIO0A5_SUS_MASK (0x1U << GRF_GPIO0A_SUS_GPIO0A5_SUS_SHIFT) /* 0x00000020 */
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#define GRF_GPIO0A_SUS_GPIO0A6_SUS_SHIFT (6U)
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#define GRF_GPIO0A_SUS_GPIO0A6_SUS_MASK (0x1U << GRF_GPIO0A_SUS_GPIO0A6_SUS_SHIFT) /* 0x00000040 */
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#define GRF_GPIO0A_SUS_GPIO0A7_SUS_SHIFT (7U)
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#define GRF_GPIO0A_SUS_GPIO0A7_SUS_MASK (0x1U << GRF_GPIO0A_SUS_GPIO0A7_SUS_SHIFT) /* 0x00000080 */
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/* GPIO0B_SUS */
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#define GRF_GPIO0B_SUS_OFFSET (0x54U)
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#define GRF_GPIO0B_SUS_GPIO0B0_SUS_SHIFT (0U)
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#define GRF_GPIO0B_SUS_GPIO0B0_SUS_MASK (0x1U << GRF_GPIO0B_SUS_GPIO0B0_SUS_SHIFT) /* 0x00000001 */
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#define GRF_GPIO0B_SUS_GPIO0B1_SUS_SHIFT (1U)
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#define GRF_GPIO0B_SUS_GPIO0B1_SUS_MASK (0x1U << GRF_GPIO0B_SUS_GPIO0B1_SUS_SHIFT) /* 0x00000002 */
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#define GRF_GPIO0B_SUS_GPIO0B2_SUS_SHIFT (2U)
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#define GRF_GPIO0B_SUS_GPIO0B2_SUS_MASK (0x1U << GRF_GPIO0B_SUS_GPIO0B2_SUS_SHIFT) /* 0x00000004 */
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#define GRF_GPIO0B_SUS_GPIO0B3_SUS_SHIFT (3U)
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#define GRF_GPIO0B_SUS_GPIO0B3_SUS_MASK (0x1U << GRF_GPIO0B_SUS_GPIO0B3_SUS_SHIFT) /* 0x00000008 */
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#define GRF_GPIO0B_SUS_GPIO0B4_SUS_SHIFT (4U)
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#define GRF_GPIO0B_SUS_GPIO0B4_SUS_MASK (0x1U << GRF_GPIO0B_SUS_GPIO0B4_SUS_SHIFT) /* 0x00000010 */
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#define GRF_GPIO0B_SUS_GPIO0B5_SUS_SHIFT (5U)
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#define GRF_GPIO0B_SUS_GPIO0B5_SUS_MASK (0x1U << GRF_GPIO0B_SUS_GPIO0B5_SUS_SHIFT) /* 0x00000020 */
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#define GRF_GPIO0B_SUS_GPIO0B6_SUS_SHIFT (6U)
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#define GRF_GPIO0B_SUS_GPIO0B6_SUS_MASK (0x1U << GRF_GPIO0B_SUS_GPIO0B6_SUS_SHIFT) /* 0x00000040 */
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#define GRF_GPIO0B_SUS_GPIO0B7_SUS_SHIFT (7U)
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#define GRF_GPIO0B_SUS_GPIO0B7_SUS_MASK (0x1U << GRF_GPIO0B_SUS_GPIO0B7_SUS_SHIFT) /* 0x00000080 */
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/* GPIO0C_SUS */
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#define GRF_GPIO0C_SUS_OFFSET (0x58U)
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#define GRF_GPIO0C_SUS_GPIO0C0_SUS_SHIFT (0U)
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#define GRF_GPIO0C_SUS_GPIO0C0_SUS_MASK (0x1U << GRF_GPIO0C_SUS_GPIO0C0_SUS_SHIFT) /* 0x00000001 */
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#define GRF_GPIO0C_SUS_GPIO0C1_SUS_SHIFT (1U)
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#define GRF_GPIO0C_SUS_GPIO0C1_SUS_MASK (0x1U << GRF_GPIO0C_SUS_GPIO0C1_SUS_SHIFT) /* 0x00000002 */
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#define GRF_GPIO0C_SUS_GPIO0C2_SUS_SHIFT (2U)
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#define GRF_GPIO0C_SUS_GPIO0C2_SUS_MASK (0x1U << GRF_GPIO0C_SUS_GPIO0C2_SUS_SHIFT) /* 0x00000004 */
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#define GRF_GPIO0C_SUS_GPIO0C3_SUS_SHIFT (3U)
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#define GRF_GPIO0C_SUS_GPIO0C3_SUS_MASK (0x1U << GRF_GPIO0C_SUS_GPIO0C3_SUS_SHIFT) /* 0x00000008 */
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#define GRF_GPIO0C_SUS_GPIO0C4_SUS_SHIFT (4U)
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#define GRF_GPIO0C_SUS_GPIO0C4_SUS_MASK (0x1U << GRF_GPIO0C_SUS_GPIO0C4_SUS_SHIFT) /* 0x00000010 */
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#define GRF_GPIO0C_SUS_GPIO0C5_SUS_SHIFT (5U)
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#define GRF_GPIO0C_SUS_GPIO0C5_SUS_MASK (0x1U << GRF_GPIO0C_SUS_GPIO0C5_SUS_SHIFT) /* 0x00000020 */
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#define GRF_GPIO0C_SUS_GPIO0C6_SUS_SHIFT (6U)
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#define GRF_GPIO0C_SUS_GPIO0C6_SUS_MASK (0x1U << GRF_GPIO0C_SUS_GPIO0C6_SUS_SHIFT) /* 0x00000040 */
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#define GRF_GPIO0C_SUS_GPIO0C7_SUS_SHIFT (7U)
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#define GRF_GPIO0C_SUS_GPIO0C7_SUS_MASK (0x1U << GRF_GPIO0C_SUS_GPIO0C7_SUS_SHIFT) /* 0x00000080 */
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/* GPIO0D_SUS */
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#define GRF_GPIO0D_SUS_OFFSET (0x5CU)
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#define GRF_GPIO0D_SUS_GPIO0D0_SUS_SHIFT (0U)
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#define GRF_GPIO0D_SUS_GPIO0D0_SUS_MASK (0x1U << GRF_GPIO0D_SUS_GPIO0D0_SUS_SHIFT) /* 0x00000001 */
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#define GRF_GPIO0D_SUS_GPIO0D1_SUS_SHIFT (1U)
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#define GRF_GPIO0D_SUS_GPIO0D1_SUS_MASK (0x1U << GRF_GPIO0D_SUS_GPIO0D1_SUS_SHIFT) /* 0x00000002 */
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/* GPIO0A_SL */
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#define GRF_GPIO0A_SL_OFFSET (0x60U)
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#define GRF_GPIO0A_SL_GPIO0A0_SL_SHIFT (0U)
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#define GRF_GPIO0A_SL_GPIO0A0_SL_MASK (0x3U << GRF_GPIO0A_SL_GPIO0A0_SL_SHIFT) /* 0x00000003 */
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#define GRF_GPIO0A_SL_GPIO0A1_SL_SHIFT (2U)
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#define GRF_GPIO0A_SL_GPIO0A1_SL_MASK (0x3U << GRF_GPIO0A_SL_GPIO0A1_SL_SHIFT) /* 0x0000000C */
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#define GRF_GPIO0A_SL_GPIO0A2_SL_SHIFT (4U)
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#define GRF_GPIO0A_SL_GPIO0A2_SL_MASK (0x3U << GRF_GPIO0A_SL_GPIO0A2_SL_SHIFT) /* 0x00000030 */
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#define GRF_GPIO0A_SL_GPIO0A3_SL_SHIFT (6U)
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#define GRF_GPIO0A_SL_GPIO0A3_SL_MASK (0x3U << GRF_GPIO0A_SL_GPIO0A3_SL_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO0A_SL_GPIO0A4_SL_SHIFT (8U)
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#define GRF_GPIO0A_SL_GPIO0A4_SL_MASK (0x3U << GRF_GPIO0A_SL_GPIO0A4_SL_SHIFT) /* 0x00000300 */
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#define GRF_GPIO0A_SL_GPIO0A5_SL_SHIFT (10U)
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#define GRF_GPIO0A_SL_GPIO0A5_SL_MASK (0x3U << GRF_GPIO0A_SL_GPIO0A5_SL_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO0A_SL_GPIO0A6_SL_SHIFT (12U)
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#define GRF_GPIO0A_SL_GPIO0A6_SL_MASK (0x3U << GRF_GPIO0A_SL_GPIO0A6_SL_SHIFT) /* 0x00003000 */
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#define GRF_GPIO0A_SL_GPIO0A7_SL_SHIFT (14U)
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#define GRF_GPIO0A_SL_GPIO0A7_SL_MASK (0x3U << GRF_GPIO0A_SL_GPIO0A7_SL_SHIFT) /* 0x0000C000 */
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/* GPIO0B_SL */
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#define GRF_GPIO0B_SL_OFFSET (0x64U)
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#define GRF_GPIO0B_SL_GPIO0B0_SL_SHIFT (0U)
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#define GRF_GPIO0B_SL_GPIO0B0_SL_MASK (0x3U << GRF_GPIO0B_SL_GPIO0B0_SL_SHIFT) /* 0x00000003 */
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#define GRF_GPIO0B_SL_GPIO0B1_SL_SHIFT (2U)
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#define GRF_GPIO0B_SL_GPIO0B1_SL_MASK (0x3U << GRF_GPIO0B_SL_GPIO0B1_SL_SHIFT) /* 0x0000000C */
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#define GRF_GPIO0B_SL_GPIO0B2_SL_SHIFT (4U)
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#define GRF_GPIO0B_SL_GPIO0B2_SL_MASK (0x3U << GRF_GPIO0B_SL_GPIO0B2_SL_SHIFT) /* 0x00000030 */
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#define GRF_GPIO0B_SL_GPIO0B3_SL_SHIFT (6U)
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#define GRF_GPIO0B_SL_GPIO0B3_SL_MASK (0x3U << GRF_GPIO0B_SL_GPIO0B3_SL_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO0B_SL_GPIO0B4_SL_SHIFT (8U)
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#define GRF_GPIO0B_SL_GPIO0B4_SL_MASK (0x3U << GRF_GPIO0B_SL_GPIO0B4_SL_SHIFT) /* 0x00000300 */
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#define GRF_GPIO0B_SL_GPIO0B5_SL_SHIFT (10U)
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#define GRF_GPIO0B_SL_GPIO0B5_SL_MASK (0x3U << GRF_GPIO0B_SL_GPIO0B5_SL_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO0B_SL_GPIO0B6_SL_SHIFT (12U)
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#define GRF_GPIO0B_SL_GPIO0B6_SL_MASK (0x3U << GRF_GPIO0B_SL_GPIO0B6_SL_SHIFT) /* 0x00003000 */
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#define GRF_GPIO0B_SL_GPIO0B7_SL_SHIFT (14U)
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#define GRF_GPIO0B_SL_GPIO0B7_SL_MASK (0x3U << GRF_GPIO0B_SL_GPIO0B7_SL_SHIFT) /* 0x0000C000 */
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/* GPIO0C_SL */
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#define GRF_GPIO0C_SL_OFFSET (0x68U)
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#define GRF_GPIO0C_SL_GPIO0C0_SL_SHIFT (0U)
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#define GRF_GPIO0C_SL_GPIO0C0_SL_MASK (0x3U << GRF_GPIO0C_SL_GPIO0C0_SL_SHIFT) /* 0x00000003 */
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#define GRF_GPIO0C_SL_GPIO0C1_SL_SHIFT (2U)
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#define GRF_GPIO0C_SL_GPIO0C1_SL_MASK (0x3U << GRF_GPIO0C_SL_GPIO0C1_SL_SHIFT) /* 0x0000000C */
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#define GRF_GPIO0C_SL_GPIO0C2_SL_SHIFT (4U)
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#define GRF_GPIO0C_SL_GPIO0C2_SL_MASK (0x3U << GRF_GPIO0C_SL_GPIO0C2_SL_SHIFT) /* 0x00000030 */
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#define GRF_GPIO0C_SL_GPIO0C3_SL_SHIFT (6U)
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#define GRF_GPIO0C_SL_GPIO0C3_SL_MASK (0x3U << GRF_GPIO0C_SL_GPIO0C3_SL_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO0C_SL_GPIO0C4_SL_SHIFT (8U)
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#define GRF_GPIO0C_SL_GPIO0C4_SL_MASK (0x3U << GRF_GPIO0C_SL_GPIO0C4_SL_SHIFT) /* 0x00000300 */
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#define GRF_GPIO0C_SL_GPIO0C5_SL_SHIFT (10U)
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#define GRF_GPIO0C_SL_GPIO0C5_SL_MASK (0x3U << GRF_GPIO0C_SL_GPIO0C5_SL_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO0C_SL_GPIO0C6_SL_SHIFT (12U)
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#define GRF_GPIO0C_SL_GPIO0C6_SL_MASK (0x3U << GRF_GPIO0C_SL_GPIO0C6_SL_SHIFT) /* 0x00003000 */
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#define GRF_GPIO0C_SL_GPIO0C7_SL_SHIFT (14U)
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#define GRF_GPIO0C_SL_GPIO0C7_SL_MASK (0x3U << GRF_GPIO0C_SL_GPIO0C7_SL_SHIFT) /* 0x0000C000 */
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/* GPIO0D_SL */
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#define GRF_GPIO0D_SL_OFFSET (0x6CU)
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#define GRF_GPIO0D_SL_GPIO0D0_SL_SHIFT (0U)
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#define GRF_GPIO0D_SL_GPIO0D0_SL_MASK (0x3U << GRF_GPIO0D_SL_GPIO0D0_SL_SHIFT) /* 0x00000003 */
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#define GRF_GPIO0D_SL_GPIO0D1_SL_SHIFT (2U)
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#define GRF_GPIO0D_SL_GPIO0D1_SL_MASK (0x3U << GRF_GPIO0D_SL_GPIO0D1_SL_SHIFT) /* 0x0000000C */
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#define GRF_GPIO0D_SL_GPIO0D2_SL_SHIFT (4U)
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#define GRF_GPIO0D_SL_GPIO0D2_SL_MASK (0x3U << GRF_GPIO0D_SL_GPIO0D2_SL_SHIFT) /* 0x00000030 */
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#define GRF_GPIO0D_SL_GPIO0D3_SL_SHIFT (6U)
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#define GRF_GPIO0D_SL_GPIO0D3_SL_MASK (0x3U << GRF_GPIO0D_SL_GPIO0D3_SL_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO0D_SL_GPIO0D4_SL_SHIFT (8U)
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#define GRF_GPIO0D_SL_GPIO0D4_SL_MASK (0x3U << GRF_GPIO0D_SL_GPIO0D4_SL_SHIFT) /* 0x00000300 */
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#define GRF_GPIO0D_SL_GPIO0D5_SL_SHIFT (10U)
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#define GRF_GPIO0D_SL_GPIO0D5_SL_MASK (0x3U << GRF_GPIO0D_SL_GPIO0D5_SL_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO0D_SL_GPIO0D6_SL_SHIFT (12U)
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#define GRF_GPIO0D_SL_GPIO0D6_SL_MASK (0x3U << GRF_GPIO0D_SL_GPIO0D6_SL_SHIFT) /* 0x00003000 */
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#define GRF_GPIO0D_SL_GPIO0D7_SL_SHIFT (14U)
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#define GRF_GPIO0D_SL_GPIO0D7_SL_MASK (0x3U << GRF_GPIO0D_SL_GPIO0D7_SL_SHIFT) /* 0x0000C000 */
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/* GPIO0A_DS_0 */
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#define GRF_GPIO0A_DS_0_OFFSET (0x70U)
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#define GRF_GPIO0A_DS_0_GPIO0A0_DS_SHIFT (0U)
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#define GRF_GPIO0A_DS_0_GPIO0A0_DS_MASK (0x3FU << GRF_GPIO0A_DS_0_GPIO0A0_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO0A_DS_0_GPIO0A1_DS_SHIFT (8U)
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#define GRF_GPIO0A_DS_0_GPIO0A1_DS_MASK (0x3FU << GRF_GPIO0A_DS_0_GPIO0A1_DS_SHIFT) /* 0x00003F00 */
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/* GPIO0A_DS_1 */
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#define GRF_GPIO0A_DS_1_OFFSET (0x74U)
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#define GRF_GPIO0A_DS_1_GPIO0A2_DS_SHIFT (0U)
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#define GRF_GPIO0A_DS_1_GPIO0A2_DS_MASK (0x3FU << GRF_GPIO0A_DS_1_GPIO0A2_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO0A_DS_1_GPIO0A3_DS_SHIFT (8U)
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#define GRF_GPIO0A_DS_1_GPIO0A3_DS_MASK (0x3FU << GRF_GPIO0A_DS_1_GPIO0A3_DS_SHIFT) /* 0x00003F00 */
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/* GPIO0A_DS_2 */
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#define GRF_GPIO0A_DS_2_OFFSET (0x78U)
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#define GRF_GPIO0A_DS_2_GPIO0A4_DS_SHIFT (0U)
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#define GRF_GPIO0A_DS_2_GPIO0A4_DS_MASK (0x3FU << GRF_GPIO0A_DS_2_GPIO0A4_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO0A_DS_2_GPIO0A5_DS_SHIFT (8U)
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#define GRF_GPIO0A_DS_2_GPIO0A5_DS_MASK (0x3FU << GRF_GPIO0A_DS_2_GPIO0A5_DS_SHIFT) /* 0x00003F00 */
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/* GPIO0A_DS_3 */
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#define GRF_GPIO0A_DS_3_OFFSET (0x7CU)
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#define GRF_GPIO0A_DS_3_GPIO0A6_DS_SHIFT (0U)
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#define GRF_GPIO0A_DS_3_GPIO0A6_DS_MASK (0x3FU << GRF_GPIO0A_DS_3_GPIO0A6_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO0A_DS_3_GPIO0A7_DS_SHIFT (8U)
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#define GRF_GPIO0A_DS_3_GPIO0A7_DS_MASK (0x3FU << GRF_GPIO0A_DS_3_GPIO0A7_DS_SHIFT) /* 0x00003F00 */
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/* GPIO0B_DS_0 */
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#define GRF_GPIO0B_DS_0_OFFSET (0x80U)
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#define GRF_GPIO0B_DS_0_GPIO0B0_DS_SHIFT (0U)
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#define GRF_GPIO0B_DS_0_GPIO0B0_DS_MASK (0x3FU << GRF_GPIO0B_DS_0_GPIO0B0_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO0B_DS_0_GPIO0B1_DS_SHIFT (8U)
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#define GRF_GPIO0B_DS_0_GPIO0B1_DS_MASK (0x3FU << GRF_GPIO0B_DS_0_GPIO0B1_DS_SHIFT) /* 0x00003F00 */
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/* GPIO0B_DS_1 */
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#define GRF_GPIO0B_DS_1_OFFSET (0x84U)
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#define GRF_GPIO0B_DS_1_GPIO0B2_DS_SHIFT (0U)
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#define GRF_GPIO0B_DS_1_GPIO0B2_DS_MASK (0x3FU << GRF_GPIO0B_DS_1_GPIO0B2_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO0B_DS_1_GPIO0B3_DS_SHIFT (8U)
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#define GRF_GPIO0B_DS_1_GPIO0B3_DS_MASK (0x3FU << GRF_GPIO0B_DS_1_GPIO0B3_DS_SHIFT) /* 0x00003F00 */
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/* GPIO0B_DS_2 */
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#define GRF_GPIO0B_DS_2_OFFSET (0x88U)
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#define GRF_GPIO0B_DS_2_GPIO0B4_DS_SHIFT (0U)
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#define GRF_GPIO0B_DS_2_GPIO0B4_DS_MASK (0x3FU << GRF_GPIO0B_DS_2_GPIO0B4_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO0B_DS_2_GPIO0B5_DS_SHIFT (8U)
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#define GRF_GPIO0B_DS_2_GPIO0B5_DS_MASK (0x3FU << GRF_GPIO0B_DS_2_GPIO0B5_DS_SHIFT) /* 0x00003F00 */
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/* GPIO0B_DS_3 */
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#define GRF_GPIO0B_DS_3_OFFSET (0x8CU)
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#define GRF_GPIO0B_DS_3_GPIO0B6_DS_SHIFT (0U)
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#define GRF_GPIO0B_DS_3_GPIO0B6_DS_MASK (0x3FU << GRF_GPIO0B_DS_3_GPIO0B6_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO0B_DS_3_GPIO0B7_DS_SHIFT (8U)
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#define GRF_GPIO0B_DS_3_GPIO0B7_DS_MASK (0x3FU << GRF_GPIO0B_DS_3_GPIO0B7_DS_SHIFT) /* 0x00003F00 */
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/* GPIO0C_DS_0 */
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#define GRF_GPIO0C_DS_0_OFFSET (0x90U)
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#define GRF_GPIO0C_DS_0_GPIO0C0_DS_SHIFT (0U)
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#define GRF_GPIO0C_DS_0_GPIO0C0_DS_MASK (0x3FU << GRF_GPIO0C_DS_0_GPIO0C0_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO0C_DS_0_GPIO0C1_DS_SHIFT (8U)
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#define GRF_GPIO0C_DS_0_GPIO0C1_DS_MASK (0x3FU << GRF_GPIO0C_DS_0_GPIO0C1_DS_SHIFT) /* 0x00003F00 */
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/* GPIO0C_DS_1 */
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#define GRF_GPIO0C_DS_1_OFFSET (0x94U)
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#define GRF_GPIO0C_DS_1_GPIO0C2_DS_SHIFT (0U)
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#define GRF_GPIO0C_DS_1_GPIO0C2_DS_MASK (0x3FU << GRF_GPIO0C_DS_1_GPIO0C2_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO0C_DS_1_GPIO0C3_DS_SHIFT (8U)
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#define GRF_GPIO0C_DS_1_GPIO0C3_DS_MASK (0x3FU << GRF_GPIO0C_DS_1_GPIO0C3_DS_SHIFT) /* 0x00003F00 */
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/* GPIO0C_DS_2 */
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#define GRF_GPIO0C_DS_2_OFFSET (0x98U)
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#define GRF_GPIO0C_DS_2_GPIO0C4_DS_SHIFT (0U)
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#define GRF_GPIO0C_DS_2_GPIO0C4_DS_MASK (0x3FU << GRF_GPIO0C_DS_2_GPIO0C4_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO0C_DS_2_GPIO0C5_DS_SHIFT (8U)
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#define GRF_GPIO0C_DS_2_GPIO0C5_DS_MASK (0x3FU << GRF_GPIO0C_DS_2_GPIO0C5_DS_SHIFT) /* 0x00003F00 */
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/* GPIO0C_DS_3 */
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#define GRF_GPIO0C_DS_3_OFFSET (0x9CU)
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#define GRF_GPIO0C_DS_3_GPIO0C6_DS_SHIFT (0U)
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#define GRF_GPIO0C_DS_3_GPIO0C6_DS_MASK (0x3FU << GRF_GPIO0C_DS_3_GPIO0C6_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO0C_DS_3_GPIO0C7_DS_SHIFT (8U)
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#define GRF_GPIO0C_DS_3_GPIO0C7_DS_MASK (0x3FU << GRF_GPIO0C_DS_3_GPIO0C7_DS_SHIFT) /* 0x00003F00 */
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/* GPIO0D_DS_0 */
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#define GRF_GPIO0D_DS_0_OFFSET (0xA0U)
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#define GRF_GPIO0D_DS_0_GPIO0D0_DS_SHIFT (0U)
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#define GRF_GPIO0D_DS_0_GPIO0D0_DS_MASK (0x3FU << GRF_GPIO0D_DS_0_GPIO0D0_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO0D_DS_0_GPIO0D1_DS_SHIFT (8U)
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#define GRF_GPIO0D_DS_0_GPIO0D1_DS_MASK (0x3FU << GRF_GPIO0D_DS_0_GPIO0D1_DS_SHIFT) /* 0x00003F00 */
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/* SOC_CON0 */
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#define GRF_SOC_CON0_OFFSET (0x100U)
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#define GRF_SOC_CON0_CON_32K_IOE_SHIFT (0U)
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#define GRF_SOC_CON0_CON_32K_IOE_MASK (0x1U << GRF_SOC_CON0_CON_32K_IOE_SHIFT) /* 0x00000001 */
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#define GRF_SOC_CON0_I2C0_IOMUX_SEL_SHIFT (1U)
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#define GRF_SOC_CON0_I2C0_IOMUX_SEL_MASK (0x1U << GRF_SOC_CON0_I2C0_IOMUX_SEL_SHIFT) /* 0x00000002 */
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#define GRF_SOC_CON0_APLL_OSC_SOURCE_SEL_SHIFT (2U)
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#define GRF_SOC_CON0_APLL_OSC_SOURCE_SEL_MASK (0x1U << GRF_SOC_CON0_APLL_OSC_SOURCE_SEL_SHIFT) /* 0x00000004 */
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#define GRF_SOC_CON0_DPLL_OSC_SOURCE_SEL_SHIFT (3U)
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#define GRF_SOC_CON0_DPLL_OSC_SOURCE_SEL_MASK (0x1U << GRF_SOC_CON0_DPLL_OSC_SOURCE_SEL_SHIFT) /* 0x00000008 */
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#define GRF_SOC_CON0_UART0_RTS_SEL_SHIFT (5U)
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#define GRF_SOC_CON0_UART0_RTS_SEL_MASK (0x1U << GRF_SOC_CON0_UART0_RTS_SEL_SHIFT) /* 0x00000020 */
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#define GRF_SOC_CON0_UART0_CTS_SEL_SHIFT (6U)
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#define GRF_SOC_CON0_UART0_CTS_SEL_MASK (0x1U << GRF_SOC_CON0_UART0_CTS_SEL_SHIFT) /* 0x00000040 */
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#define GRF_SOC_CON0_GRF_CON_PMIC_SLEEP_SEL_SHIFT (7U)
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#define GRF_SOC_CON0_GRF_CON_PMIC_SLEEP_SEL_MASK (0x1U << GRF_SOC_CON0_GRF_CON_PMIC_SLEEP_SEL_SHIFT) /* 0x00000080 */
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#define GRF_SOC_CON0_DDRPHY_BUFFEREN_SEL_SHIFT (12U)
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#define GRF_SOC_CON0_DDRPHY_BUFFEREN_SEL_MASK (0x1U << GRF_SOC_CON0_DDRPHY_BUFFEREN_SEL_SHIFT) /* 0x00001000 */
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#define GRF_SOC_CON0_DDRPHY_BUFFEREN_CORE_SHIFT (13U)
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#define GRF_SOC_CON0_DDRPHY_BUFFEREN_CORE_MASK (0x1U << GRF_SOC_CON0_DDRPHY_BUFFEREN_CORE_SHIFT) /* 0x00002000 */
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#define GRF_SOC_CON0_PVTM_FRQ_DONE_SHIFT (14U)
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#define GRF_SOC_CON0_PVTM_FRQ_DONE_MASK (0x1U << GRF_SOC_CON0_PVTM_FRQ_DONE_SHIFT) /* 0x00004000 */
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/* SOC_CON1 */
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#define GRF_SOC_CON1_OFFSET (0x104U)
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#define GRF_SOC_CON1_RESETN_HOLD_SHIFT (0U)
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#define GRF_SOC_CON1_RESETN_HOLD_MASK (0xFFFFU << GRF_SOC_CON1_RESETN_HOLD_SHIFT) /* 0x0000FFFF */
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/* SOC_CON2 */
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#define GRF_SOC_CON2_OFFSET (0x108U)
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#define GRF_SOC_CON2_RESETN_HOLD_SHIFT (0U)
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#define GRF_SOC_CON2_RESETN_HOLD_MASK (0xFFU << GRF_SOC_CON2_RESETN_HOLD_SHIFT) /* 0x000000FF */
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/* SOC_CON3 */
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#define GRF_SOC_CON3_OFFSET (0x10CU)
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#define GRF_SOC_CON3_TSADC_SHUT_RESET_TRIGGER_EN_SHIFT (0U)
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#define GRF_SOC_CON3_TSADC_SHUT_RESET_TRIGGER_EN_MASK (0x1U << GRF_SOC_CON3_TSADC_SHUT_RESET_TRIGGER_EN_SHIFT) /* 0x00000001 */
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#define GRF_SOC_CON3_WDT_SHUT_RESET_TRIGGER_EN_SHIFT (1U)
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#define GRF_SOC_CON3_WDT_SHUT_RESET_TRIGGER_EN_MASK (0x1U << GRF_SOC_CON3_WDT_SHUT_RESET_TRIGGER_EN_SHIFT) /* 0x00000002 */
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#define GRF_SOC_CON3_DDRIO_RET_EN_SHIFT (2U)
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#define GRF_SOC_CON3_DDRIO_RET_EN_MASK (0x1U << GRF_SOC_CON3_DDRIO_RET_EN_SHIFT) /* 0x00000004 */
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#define GRF_SOC_CON3_SREF_ENTER_EN_SHIFT (3U)
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#define GRF_SOC_CON3_SREF_ENTER_EN_MASK (0x1U << GRF_SOC_CON3_SREF_ENTER_EN_SHIFT) /* 0x00000008 */
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#define GRF_SOC_CON3_DDRC_GATING_EN_SHIFT (4U)
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#define GRF_SOC_CON3_DDRC_GATING_EN_MASK (0x1U << GRF_SOC_CON3_DDRC_GATING_EN_SHIFT) /* 0x00000010 */
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#define GRF_SOC_CON3_DDR_IO_RET_DE_REQ_SHIFT (5U)
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#define GRF_SOC_CON3_DDR_IO_RET_DE_REQ_MASK (0x1U << GRF_SOC_CON3_DDR_IO_RET_DE_REQ_SHIFT) /* 0x00000020 */
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#define GRF_SOC_CON3_DDR_IO_RET_CFG_SHIFT (6U)
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#define GRF_SOC_CON3_DDR_IO_RET_CFG_MASK (0x1U << GRF_SOC_CON3_DDR_IO_RET_CFG_SHIFT) /* 0x00000040 */
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#define GRF_SOC_CON3_DDR_IO_RET_OEN_CFG_SHIFT (7U)
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#define GRF_SOC_CON3_DDR_IO_RET_OEN_CFG_MASK (0x1U << GRF_SOC_CON3_DDR_IO_RET_OEN_CFG_SHIFT) /* 0x00000080 */
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#define GRF_SOC_CON3_UPCTL_C_SYSREQ_CFG_SHIFT (8U)
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#define GRF_SOC_CON3_UPCTL_C_SYSREQ_CFG_MASK (0x1U << GRF_SOC_CON3_UPCTL_C_SYSREQ_CFG_SHIFT) /* 0x00000100 */
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#define GRF_SOC_CON3_CORE_WFI_EN_SHIFT (9U)
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#define GRF_SOC_CON3_CORE_WFI_EN_MASK (0x1U << GRF_SOC_CON3_CORE_WFI_EN_SHIFT) /* 0x00000200 */
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#define GRF_SOC_CON3_CORE_OFF_EN_SHIFT (10U)
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#define GRF_SOC_CON3_CORE_OFF_EN_MASK (0x1U << GRF_SOC_CON3_CORE_OFF_EN_SHIFT) /* 0x00000400 */
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#define GRF_SOC_CON3_CORE_RET_EN_SHIFT (11U)
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#define GRF_SOC_CON3_CORE_RET_EN_MASK (0x1U << GRF_SOC_CON3_CORE_RET_EN_SHIFT) /* 0x00000800 */
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#define GRF_SOC_CON3_CORE_PACTIVE_EN_SHIFT (12U)
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#define GRF_SOC_CON3_CORE_PACTIVE_EN_MASK (0x1U << GRF_SOC_CON3_CORE_PACTIVE_EN_SHIFT) /* 0x00001000 */
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#define GRF_SOC_CON3_DSU_OFF_EN_SHIFT (13U)
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#define GRF_SOC_CON3_DSU_OFF_EN_MASK (0x1U << GRF_SOC_CON3_DSU_OFF_EN_SHIFT) /* 0x00002000 */
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#define GRF_SOC_CON3_DSU_RET_EN_SHIFT (14U)
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#define GRF_SOC_CON3_DSU_RET_EN_MASK (0x1U << GRF_SOC_CON3_DSU_RET_EN_SHIFT) /* 0x00004000 */
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#define GRF_SOC_CON3_DSU_PACTIVE_EN_SHIFT (15U)
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#define GRF_SOC_CON3_DSU_PACTIVE_EN_MASK (0x1U << GRF_SOC_CON3_DSU_PACTIVE_EN_SHIFT) /* 0x00008000 */
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/* SOC_CON4 */
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#define GRF_SOC_CON4_OFFSET (0x110U)
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#define GRF_SOC_CON4_PWM0_IOMUX_SEL_SHIFT (0U)
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#define GRF_SOC_CON4_PWM0_IOMUX_SEL_MASK (0x3U << GRF_SOC_CON4_PWM0_IOMUX_SEL_SHIFT) /* 0x00000003 */
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#define GRF_SOC_CON4_PWM1_IOMUX_SEL_SHIFT (2U)
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#define GRF_SOC_CON4_PWM1_IOMUX_SEL_MASK (0x3U << GRF_SOC_CON4_PWM1_IOMUX_SEL_SHIFT) /* 0x0000000C */
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#define GRF_SOC_CON4_PWM2_IOMUX_SEL_SHIFT (4U)
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#define GRF_SOC_CON4_PWM2_IOMUX_SEL_MASK (0x3U << GRF_SOC_CON4_PWM2_IOMUX_SEL_SHIFT) /* 0x00000030 */
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#define GRF_SOC_CON4_GPU_PWREN_POL_SHIFT (10U)
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#define GRF_SOC_CON4_GPU_PWREN_POL_MASK (0x3U << GRF_SOC_CON4_GPU_PWREN_POL_SHIFT) /* 0x00000C00 */
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#define GRF_SOC_CON4_SPRA_HD_WTSEL_SHIFT (12U)
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#define GRF_SOC_CON4_SPRA_HD_WTSEL_MASK (0x3U << GRF_SOC_CON4_SPRA_HD_WTSEL_SHIFT) /* 0x00003000 */
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#define GRF_SOC_CON4_SPRA_HD_RTSEL_SHIFT (14U)
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#define GRF_SOC_CON4_SPRA_HD_RTSEL_MASK (0x3U << GRF_SOC_CON4_SPRA_HD_RTSEL_SHIFT) /* 0x0000C000 */
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/* SOC_CON5 */
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#define GRF_SOC_CON5_OFFSET (0x114U)
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#define GRF_SOC_CON5_OUT2CHIP_RST_INIT_SHIFT (0U)
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#define GRF_SOC_CON5_OUT2CHIP_RST_INIT_MASK (0x1FFFU << GRF_SOC_CON5_OUT2CHIP_RST_INIT_SHIFT) /* 0x00001FFF */
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/* SOC_STATUS */
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#define GRF_SOC_STATUS_OFFSET (0x120U)
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#define GRF_SOC_STATUS (0x0U)
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#define GRF_SOC_STATUS_WFI_STATUS_SHIFT (0U)
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#define GRF_SOC_STATUS_WFI_STATUS_MASK (0xFU << GRF_SOC_STATUS_WFI_STATUS_SHIFT) /* 0x0000000F */
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/* IO_VSEL0 */
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#define GRF_IO_VSEL0_OFFSET (0x140U)
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#define GRF_IO_VSEL0_VCCIO2_VOLTAGE_CONTROL_SELECT_SHIFT (0U)
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#define GRF_IO_VSEL0_VCCIO2_VOLTAGE_CONTROL_SELECT_MASK (0x1U << GRF_IO_VSEL0_VCCIO2_VOLTAGE_CONTROL_SELECT_SHIFT) /* 0x00000001 */
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#define GRF_IO_VSEL0_POC_VCCIO1_SEL18_SHIFT (1U)
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#define GRF_IO_VSEL0_POC_VCCIO1_SEL18_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO1_SEL18_SHIFT) /* 0x00000002 */
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#define GRF_IO_VSEL0_POC_VCCIO2_SEL18_SHIFT (2U)
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#define GRF_IO_VSEL0_POC_VCCIO2_SEL18_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO2_SEL18_SHIFT) /* 0x00000004 */
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#define GRF_IO_VSEL0_POC_VCCIO3_SEL18_SHIFT (3U)
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#define GRF_IO_VSEL0_POC_VCCIO3_SEL18_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO3_SEL18_SHIFT) /* 0x00000008 */
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#define GRF_IO_VSEL0_POC_VCCIO4_SEL18_SHIFT (4U)
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#define GRF_IO_VSEL0_POC_VCCIO4_SEL18_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO4_SEL18_SHIFT) /* 0x00000010 */
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#define GRF_IO_VSEL0_POC_VCCIO5_SEL18_SHIFT (5U)
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#define GRF_IO_VSEL0_POC_VCCIO5_SEL18_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO5_SEL18_SHIFT) /* 0x00000020 */
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#define GRF_IO_VSEL0_POC_VCCIO6_SEL18_SHIFT (6U)
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#define GRF_IO_VSEL0_POC_VCCIO6_SEL18_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO6_SEL18_SHIFT) /* 0x00000040 */
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#define GRF_IO_VSEL0_POC_VCCIO7_SEL18_SHIFT (7U)
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#define GRF_IO_VSEL0_POC_VCCIO7_SEL18_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO7_SEL18_SHIFT) /* 0x00000080 */
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#define GRF_IO_VSEL0_POC_VCCIO1_SEL25_SHIFT (8U)
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#define GRF_IO_VSEL0_POC_VCCIO1_SEL25_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO1_SEL25_SHIFT) /* 0x00000100 */
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#define GRF_IO_VSEL0_POC_VCCIO2_SEL25_SHIFT (9U)
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#define GRF_IO_VSEL0_POC_VCCIO2_SEL25_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO2_SEL25_SHIFT) /* 0x00000200 */
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#define GRF_IO_VSEL0_POC_VCCIO3_SEL25_SHIFT (10U)
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#define GRF_IO_VSEL0_POC_VCCIO3_SEL25_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO3_SEL25_SHIFT) /* 0x00000400 */
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#define GRF_IO_VSEL0_POC_VCCIO4_SEL25_SHIFT (11U)
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#define GRF_IO_VSEL0_POC_VCCIO4_SEL25_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO4_SEL25_SHIFT) /* 0x00000800 */
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#define GRF_IO_VSEL0_POC_VCCIO5_SEL25_SHIFT (12U)
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#define GRF_IO_VSEL0_POC_VCCIO5_SEL25_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO5_SEL25_SHIFT) /* 0x00001000 */
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#define GRF_IO_VSEL0_POC_VCCIO6_SEL25_SHIFT (13U)
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#define GRF_IO_VSEL0_POC_VCCIO6_SEL25_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO6_SEL25_SHIFT) /* 0x00002000 */
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#define GRF_IO_VSEL0_POC_VCCIO7_SEL25_SHIFT (14U)
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#define GRF_IO_VSEL0_POC_VCCIO7_SEL25_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO7_SEL25_SHIFT) /* 0x00004000 */
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/* IO_VSEL1 */
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#define GRF_IO_VSEL1_OFFSET (0x144U)
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#define GRF_IO_VSEL1_POC_VCCIO1_SEL33_SHIFT (1U)
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#define GRF_IO_VSEL1_POC_VCCIO1_SEL33_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO1_SEL33_SHIFT) /* 0x00000002 */
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#define GRF_IO_VSEL1_POC_VCCIO2_SEL33_SHIFT (2U)
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#define GRF_IO_VSEL1_POC_VCCIO2_SEL33_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO2_SEL33_SHIFT) /* 0x00000004 */
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#define GRF_IO_VSEL1_POC_VCCIO3_SEL33_SHIFT (3U)
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#define GRF_IO_VSEL1_POC_VCCIO3_SEL33_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO3_SEL33_SHIFT) /* 0x00000008 */
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#define GRF_IO_VSEL1_POC_VCCIO4_SEL33_SHIFT (4U)
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#define GRF_IO_VSEL1_POC_VCCIO4_SEL33_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO4_SEL33_SHIFT) /* 0x00000010 */
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#define GRF_IO_VSEL1_POC_VCCIO5_SEL33_SHIFT (5U)
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#define GRF_IO_VSEL1_POC_VCCIO5_SEL33_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO5_SEL33_SHIFT) /* 0x00000020 */
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#define GRF_IO_VSEL1_POC_VCCIO6_SEL33_SHIFT (6U)
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#define GRF_IO_VSEL1_POC_VCCIO6_SEL33_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO6_SEL33_SHIFT) /* 0x00000040 */
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#define GRF_IO_VSEL1_POC_VCCIO7_SEL33_SHIFT (7U)
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#define GRF_IO_VSEL1_POC_VCCIO7_SEL33_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO7_SEL33_SHIFT) /* 0x00000080 */
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#define GRF_IO_VSEL1_POC_VCCIO1_IDDQ_SHIFT (8U)
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#define GRF_IO_VSEL1_POC_VCCIO1_IDDQ_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO1_IDDQ_SHIFT) /* 0x00000100 */
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#define GRF_IO_VSEL1_POC_VCCIO2_IDDQ_SHIFT (9U)
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#define GRF_IO_VSEL1_POC_VCCIO2_IDDQ_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO2_IDDQ_SHIFT) /* 0x00000200 */
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#define GRF_IO_VSEL1_POC_VCCIO3_IDDQ_SHIFT (10U)
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#define GRF_IO_VSEL1_POC_VCCIO3_IDDQ_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO3_IDDQ_SHIFT) /* 0x00000400 */
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#define GRF_IO_VSEL1_POC_VCCIO4_IDDQ_SHIFT (11U)
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#define GRF_IO_VSEL1_POC_VCCIO4_IDDQ_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO4_IDDQ_SHIFT) /* 0x00000800 */
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#define GRF_IO_VSEL1_POC_VCCIO5_IDDQ_SHIFT (12U)
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#define GRF_IO_VSEL1_POC_VCCIO5_IDDQ_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO5_IDDQ_SHIFT) /* 0x00001000 */
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#define GRF_IO_VSEL1_POC_VCCIO6_IDDQ_SHIFT (13U)
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#define GRF_IO_VSEL1_POC_VCCIO6_IDDQ_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO6_IDDQ_SHIFT) /* 0x00002000 */
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#define GRF_IO_VSEL1_POC_VCCIO7_IDDQ_SHIFT (14U)
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#define GRF_IO_VSEL1_POC_VCCIO7_IDDQ_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO7_IDDQ_SHIFT) /* 0x00004000 */
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/* IO_VSEL2 */
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#define GRF_IO_VSEL2_OFFSET (0x148U)
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#define GRF_IO_VSEL2_POC_PMUIO2_SEL18_SHIFT (1U)
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#define GRF_IO_VSEL2_POC_PMUIO2_SEL18_MASK (0x1U << GRF_IO_VSEL2_POC_PMUIO2_SEL18_SHIFT) /* 0x00000002 */
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#define GRF_IO_VSEL2_POC_PMUIO2_SEL25_SHIFT (3U)
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#define GRF_IO_VSEL2_POC_PMUIO2_SEL25_MASK (0x1U << GRF_IO_VSEL2_POC_PMUIO2_SEL25_SHIFT) /* 0x00000008 */
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#define GRF_IO_VSEL2_POC_PMUIO2_SEL33_SHIFT (5U)
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#define GRF_IO_VSEL2_POC_PMUIO2_SEL33_MASK (0x1U << GRF_IO_VSEL2_POC_PMUIO2_SEL33_SHIFT) /* 0x00000020 */
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#define GRF_IO_VSEL2_POC_PMUIO1_IDDQ_SHIFT (6U)
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#define GRF_IO_VSEL2_POC_PMUIO1_IDDQ_MASK (0x1U << GRF_IO_VSEL2_POC_PMUIO1_IDDQ_SHIFT) /* 0x00000040 */
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#define GRF_IO_VSEL2_POC_PMUIO2_IDDQ_SHIFT (7U)
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#define GRF_IO_VSEL2_POC_PMUIO2_IDDQ_MASK (0x1U << GRF_IO_VSEL2_POC_PMUIO2_IDDQ_SHIFT) /* 0x00000080 */
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/* DLL_CON0 */
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#define GRF_DLL_CON0_OFFSET (0x180U)
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#define GRF_DLL_CON0_PVTM_CLKOUT_DIV_SHIFT (0U)
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#define GRF_DLL_CON0_PVTM_CLKOUT_DIV_MASK (0xFFFU << GRF_DLL_CON0_PVTM_CLKOUT_DIV_SHIFT) /* 0x00000FFF */
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/* OS_REG0 */
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#define GRF_OS_REG0_OFFSET (0x200U)
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#define GRF_OS_REG0_PMU_OS_REG0_SHIFT (0U)
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#define GRF_OS_REG0_PMU_OS_REG0_MASK (0xFFFFFFFFU << GRF_OS_REG0_PMU_OS_REG0_SHIFT) /* 0xFFFFFFFF */
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/* OS_REG1 */
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#define GRF_OS_REG1_OFFSET (0x204U)
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#define GRF_OS_REG1_PMU_OS_REG1_SHIFT (0U)
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#define GRF_OS_REG1_PMU_OS_REG1_MASK (0xFFFFFFFFU << GRF_OS_REG1_PMU_OS_REG1_SHIFT) /* 0xFFFFFFFF */
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/* OS_REG2 */
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#define GRF_OS_REG2_OFFSET (0x208U)
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#define GRF_OS_REG2_PMU_OS_REG2_SHIFT (0U)
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#define GRF_OS_REG2_PMU_OS_REG2_MASK (0xFFFFFFFFU << GRF_OS_REG2_PMU_OS_REG2_SHIFT) /* 0xFFFFFFFF */
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/* OS_REG3 */
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#define GRF_OS_REG3_OFFSET (0x20CU)
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#define GRF_OS_REG3_PMU_OS_REG3_SHIFT (0U)
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#define GRF_OS_REG3_PMU_OS_REG3_MASK (0xFFFFFFFFU << GRF_OS_REG3_PMU_OS_REG3_SHIFT) /* 0xFFFFFFFF */
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/* OS_REG4 */
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#define GRF_OS_REG4_OFFSET (0x210U)
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#define GRF_OS_REG4_PMU_OS_REG4_SHIFT (0U)
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#define GRF_OS_REG4_PMU_OS_REG4_MASK (0xFFFFFFFFU << GRF_OS_REG4_PMU_OS_REG4_SHIFT) /* 0xFFFFFFFF */
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/* OS_REG5 */
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#define GRF_OS_REG5_OFFSET (0x214U)
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#define GRF_OS_REG5_PMU_OS_REG5_SHIFT (0U)
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#define GRF_OS_REG5_PMU_OS_REG5_MASK (0xFFFFFFFFU << GRF_OS_REG5_PMU_OS_REG5_SHIFT) /* 0xFFFFFFFF */
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/* OS_REG6 */
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#define GRF_OS_REG6_OFFSET (0x218U)
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#define GRF_OS_REG6_PMU_OS_REG6_SHIFT (0U)
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#define GRF_OS_REG6_PMU_OS_REG6_MASK (0xFFFFFFFFU << GRF_OS_REG6_PMU_OS_REG6_SHIFT) /* 0xFFFFFFFF */
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/* OS_REG7 */
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#define GRF_OS_REG7_OFFSET (0x21CU)
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#define GRF_OS_REG7_PMU_OS_REG7_SHIFT (0U)
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#define GRF_OS_REG7_PMU_OS_REG7_MASK (0xFFFFFFFFU << GRF_OS_REG7_PMU_OS_REG7_SHIFT) /* 0xFFFFFFFF */
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/* OS_REG8 */
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#define GRF_OS_REG8_OFFSET (0x220U)
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#define GRF_OS_REG8_PMU_OS_REG8_SHIFT (0U)
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#define GRF_OS_REG8_PMU_OS_REG8_MASK (0xFFFFFFFFU << GRF_OS_REG8_PMU_OS_REG8_SHIFT) /* 0xFFFFFFFF */
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/* OS_REG9 */
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#define GRF_OS_REG9_OFFSET (0x224U)
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#define GRF_OS_REG9_PMU_OS_REG9_SHIFT (0U)
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#define GRF_OS_REG9_PMU_OS_REG9_MASK (0xFFFFFFFFU << GRF_OS_REG9_PMU_OS_REG9_SHIFT) /* 0xFFFFFFFF */
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/* OS_REG10 */
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#define GRF_OS_REG10_OFFSET (0x228U)
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#define GRF_OS_REG10_PMU_OS_REG10_SHIFT (0U)
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#define GRF_OS_REG10_PMU_OS_REG10_MASK (0xFFFFFFFFU << GRF_OS_REG10_PMU_OS_REG10_SHIFT) /* 0xFFFFFFFF */
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/* OS_REG11 */
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#define GRF_OS_REG11_OFFSET (0x22CU)
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#define GRF_OS_REG11_PMU_OS_REG11_SHIFT (0U)
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#define GRF_OS_REG11_PMU_OS_REG11_MASK (0xFFFFFFFFU << GRF_OS_REG11_PMU_OS_REG11_SHIFT) /* 0xFFFFFFFF */
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/* RESET_FUNCTION_STATUS */
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#define GRF_RESET_FUNCTION_STATUS_OFFSET (0x230U)
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#define GRF_RESET_FUNCTION_STATUS_FIRST_RESET_SRC_SHIFT (0U)
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#define GRF_RESET_FUNCTION_STATUS_FIRST_RESET_SRC_MASK (0x1U << GRF_RESET_FUNCTION_STATUS_FIRST_RESET_SRC_SHIFT) /* 0x00000001 */
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#define GRF_RESET_FUNCTION_STATUS_WDT_RESET_SRC_SHIFT (1U)
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#define GRF_RESET_FUNCTION_STATUS_WDT_RESET_SRC_MASK (0x1U << GRF_RESET_FUNCTION_STATUS_WDT_RESET_SRC_SHIFT) /* 0x00000002 */
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#define GRF_RESET_FUNCTION_STATUS_TSADC_SHUT_RESET_SRC_SHIFT (2U)
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#define GRF_RESET_FUNCTION_STATUS_TSADC_SHUT_RESET_SRC_MASK (0x1U << GRF_RESET_FUNCTION_STATUS_TSADC_SHUT_RESET_SRC_SHIFT) /* 0x00000004 */
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#define GRF_RESET_FUNCTION_STATUS_DDR_FAIL_SAFE_SRC_SHIFT (3U)
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#define GRF_RESET_FUNCTION_STATUS_DDR_FAIL_SAFE_SRC_MASK (0x1U << GRF_RESET_FUNCTION_STATUS_DDR_FAIL_SAFE_SRC_SHIFT) /* 0x00000008 */
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/* RESET_FUNCTION_CLR */
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#define GRF_RESET_FUNCTION_CLR_OFFSET (0x234U)
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#define GRF_RESET_FUNCTION_CLR_FIRST_RESET_SRC_CLR_SHIFT (0U)
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#define GRF_RESET_FUNCTION_CLR_FIRST_RESET_SRC_CLR_MASK (0x1U << GRF_RESET_FUNCTION_CLR_FIRST_RESET_SRC_CLR_SHIFT) /* 0x00000001 */
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#define GRF_RESET_FUNCTION_CLR_WDT_RESET_SRC_CLR_SHIFT (1U)
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#define GRF_RESET_FUNCTION_CLR_WDT_RESET_SRC_CLR_MASK (0x1U << GRF_RESET_FUNCTION_CLR_WDT_RESET_SRC_CLR_SHIFT) /* 0x00000002 */
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#define GRF_RESET_FUNCTION_CLR_TSADC_SHUT_RESET_SRC_CLR_SHIFT (2U)
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#define GRF_RESET_FUNCTION_CLR_TSADC_SHUT_RESET_SRC_CLR_MASK (0x1U << GRF_RESET_FUNCTION_CLR_TSADC_SHUT_RESET_SRC_CLR_SHIFT) /* 0x00000004 */
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#define GRF_RESET_FUNCTION_CLR_DDR_FAIL_SAFE_SRC_CLR_SHIFT (3U)
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#define GRF_RESET_FUNCTION_CLR_DDR_FAIL_SAFE_SRC_CLR_MASK (0x1U << GRF_RESET_FUNCTION_CLR_DDR_FAIL_SAFE_SRC_CLR_SHIFT) /* 0x00000008 */
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/* SIG_DETECT_CON */
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#define GRF_SIG_DETECT_CON_OFFSET (0x380U)
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#define GRF_SIG_DETECT_CON_SDMMC0_DETECTN_POS_IRQ_MSK_SHIFT (0U)
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#define GRF_SIG_DETECT_CON_SDMMC0_DETECTN_POS_IRQ_MSK_MASK (0x1U << GRF_SIG_DETECT_CON_SDMMC0_DETECTN_POS_IRQ_MSK_SHIFT) /* 0x00000001 */
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#define GRF_SIG_DETECT_CON_SDMMC0_DETECTN_NEG_IRQ_MSK_SHIFT (1U)
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#define GRF_SIG_DETECT_CON_SDMMC0_DETECTN_NEG_IRQ_MSK_MASK (0x1U << GRF_SIG_DETECT_CON_SDMMC0_DETECTN_NEG_IRQ_MSK_SHIFT) /* 0x00000002 */
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#define GRF_SIG_DETECT_CON_SDMMC1_DETECTN_POS_IRQ_MSK_SHIFT (2U)
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#define GRF_SIG_DETECT_CON_SDMMC1_DETECTN_POS_IRQ_MSK_MASK (0x1U << GRF_SIG_DETECT_CON_SDMMC1_DETECTN_POS_IRQ_MSK_SHIFT) /* 0x00000004 */
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#define GRF_SIG_DETECT_CON_SDMMC1_DETECTN_NEG_IRQ_MSK_SHIFT (3U)
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#define GRF_SIG_DETECT_CON_SDMMC1_DETECTN_NEG_IRQ_MSK_MASK (0x1U << GRF_SIG_DETECT_CON_SDMMC1_DETECTN_NEG_IRQ_MSK_SHIFT) /* 0x00000008 */
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#define GRF_SIG_DETECT_CON_SDMMC2_DETECTN_POS_IRQ_MSK_SHIFT (4U)
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#define GRF_SIG_DETECT_CON_SDMMC2_DETECTN_POS_IRQ_MSK_MASK (0x1U << GRF_SIG_DETECT_CON_SDMMC2_DETECTN_POS_IRQ_MSK_SHIFT) /* 0x00000010 */
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#define GRF_SIG_DETECT_CON_SDMMC2_DETECTN_NEG_IRQ_MSK_SHIFT (5U)
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#define GRF_SIG_DETECT_CON_SDMMC2_DETECTN_NEG_IRQ_MSK_MASK (0x1U << GRF_SIG_DETECT_CON_SDMMC2_DETECTN_NEG_IRQ_MSK_SHIFT) /* 0x00000020 */
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/* SIG_DETECT_STATUS */
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#define GRF_SIG_DETECT_STATUS_OFFSET (0x390U)
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#define GRF_SIG_DETECT_STATUS_SDMMC0_DETECTN_POS_IRQ_SHIFT (0U)
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#define GRF_SIG_DETECT_STATUS_SDMMC0_DETECTN_POS_IRQ_MASK (0x1U << GRF_SIG_DETECT_STATUS_SDMMC0_DETECTN_POS_IRQ_SHIFT) /* 0x00000001 */
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#define GRF_SIG_DETECT_STATUS_SDMMC0_DETECTN_NEG_IRQ_SHIFT (1U)
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#define GRF_SIG_DETECT_STATUS_SDMMC0_DETECTN_NEG_IRQ_MASK (0x1U << GRF_SIG_DETECT_STATUS_SDMMC0_DETECTN_NEG_IRQ_SHIFT) /* 0x00000002 */
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#define GRF_SIG_DETECT_STATUS_SDMMC1_DETECTN_POS_IRQ_SHIFT (2U)
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#define GRF_SIG_DETECT_STATUS_SDMMC1_DETECTN_POS_IRQ_MASK (0x1U << GRF_SIG_DETECT_STATUS_SDMMC1_DETECTN_POS_IRQ_SHIFT) /* 0x00000004 */
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#define GRF_SIG_DETECT_STATUS_SDMMC1_DETECTN_NEG_IRQ_SHIFT (3U)
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#define GRF_SIG_DETECT_STATUS_SDMMC1_DETECTN_NEG_IRQ_MASK (0x1U << GRF_SIG_DETECT_STATUS_SDMMC1_DETECTN_NEG_IRQ_SHIFT) /* 0x00000008 */
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#define GRF_SIG_DETECT_STATUS_SDMMC2_DETECTN_POS_IRQ_SHIFT (4U)
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#define GRF_SIG_DETECT_STATUS_SDMMC2_DETECTN_POS_IRQ_MASK (0x1U << GRF_SIG_DETECT_STATUS_SDMMC2_DETECTN_POS_IRQ_SHIFT) /* 0x00000010 */
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#define GRF_SIG_DETECT_STATUS_SDMMC2_DETECTN_NEG_IRQ_SHIFT (5U)
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#define GRF_SIG_DETECT_STATUS_SDMMC2_DETECTN_NEG_IRQ_MASK (0x1U << GRF_SIG_DETECT_STATUS_SDMMC2_DETECTN_NEG_IRQ_SHIFT) /* 0x00000020 */
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/* SIG_DETECT_STATUS_CLEAR */
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#define GRF_SIG_DETECT_STATUS_CLEAR_OFFSET (0x3A0U)
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#define GRF_SIG_DETECT_STATUS_CLEAR_SDMMC0_DETECTN_POS_IRQ_CLR_SHIFT (0U)
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#define GRF_SIG_DETECT_STATUS_CLEAR_SDMMC0_DETECTN_POS_IRQ_CLR_MASK (0x1U << GRF_SIG_DETECT_STATUS_CLEAR_SDMMC0_DETECTN_POS_IRQ_CLR_SHIFT) /* 0x00000001 */
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#define GRF_SIG_DETECT_STATUS_CLEAR_SDMMC0_DETECTN_NEG_IRQ_CLR_SHIFT (1U)
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#define GRF_SIG_DETECT_STATUS_CLEAR_SDMMC0_DETECTN_NEG_IRQ_CLR_MASK (0x1U << GRF_SIG_DETECT_STATUS_CLEAR_SDMMC0_DETECTN_NEG_IRQ_CLR_SHIFT) /* 0x00000002 */
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#define GRF_SIG_DETECT_STATUS_CLEAR_SDMMC1_DETECTN_POS_IRQ_CLR_SHIFT (2U)
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#define GRF_SIG_DETECT_STATUS_CLEAR_SDMMC1_DETECTN_POS_IRQ_CLR_MASK (0x1U << GRF_SIG_DETECT_STATUS_CLEAR_SDMMC1_DETECTN_POS_IRQ_CLR_SHIFT) /* 0x00000004 */
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#define GRF_SIG_DETECT_STATUS_CLEAR_SDMMC1_DETECTN_NEG_IRQ_CLR_SHIFT (3U)
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#define GRF_SIG_DETECT_STATUS_CLEAR_SDMMC1_DETECTN_NEG_IRQ_CLR_MASK (0x1U << GRF_SIG_DETECT_STATUS_CLEAR_SDMMC1_DETECTN_NEG_IRQ_CLR_SHIFT) /* 0x00000008 */
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#define GRF_SIG_DETECT_STATUS_CLEAR_SDMMC2_DETECTN_POS_IRQ_CLR_SHIFT (4U)
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#define GRF_SIG_DETECT_STATUS_CLEAR_SDMMC2_DETECTN_POS_IRQ_CLR_MASK (0x1U << GRF_SIG_DETECT_STATUS_CLEAR_SDMMC2_DETECTN_POS_IRQ_CLR_SHIFT) /* 0x00000010 */
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#define GRF_SIG_DETECT_STATUS_CLEAR_SDMMC2_DETECTN_NEG_IRQ_CLR_SHIFT (5U)
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#define GRF_SIG_DETECT_STATUS_CLEAR_SDMMC2_DETECTN_NEG_IRQ_CLR_MASK (0x1U << GRF_SIG_DETECT_STATUS_CLEAR_SDMMC2_DETECTN_NEG_IRQ_CLR_SHIFT) /* 0x00000020 */
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/* SDMMC_DET_COUNTER */
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#define GRF_SDMMC_DET_COUNTER_OFFSET (0x3B0U)
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#define GRF_SDMMC_DET_COUNTER_SDMMC_DETECTN_COUNT_SHIFT (0U)
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#define GRF_SDMMC_DET_COUNTER_SDMMC_DETECTN_COUNT_MASK (0xFFFFFU << GRF_SDMMC_DET_COUNTER_SDMMC_DETECTN_COUNT_SHIFT) /* 0x000FFFFF */
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/* GPIO1A_IOMUX_L */
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#define GRF_GPIO1A_IOMUX_L_OFFSET (0x40000U)
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#define GRF_GPIO1A_IOMUX_L_GPIO1A0_SEL_SHIFT (0U)
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#define GRF_GPIO1A_IOMUX_L_GPIO1A0_SEL_MASK (0x7U << GRF_GPIO1A_IOMUX_L_GPIO1A0_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO1A_IOMUX_L_GPIO1A1_SEL_SHIFT (4U)
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#define GRF_GPIO1A_IOMUX_L_GPIO1A1_SEL_MASK (0x7U << GRF_GPIO1A_IOMUX_L_GPIO1A1_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO1A_IOMUX_L_GPIO1A2_SEL_SHIFT (8U)
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#define GRF_GPIO1A_IOMUX_L_GPIO1A2_SEL_MASK (0x7U << GRF_GPIO1A_IOMUX_L_GPIO1A2_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO1A_IOMUX_L_GPIO1A3_SEL_SHIFT (12U)
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#define GRF_GPIO1A_IOMUX_L_GPIO1A3_SEL_MASK (0x7U << GRF_GPIO1A_IOMUX_L_GPIO1A3_SEL_SHIFT) /* 0x00007000 */
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/* GPIO1A_IOMUX_H */
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#define GRF_GPIO1A_IOMUX_H_OFFSET (0x40004U)
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#define GRF_GPIO1A_IOMUX_H_GPIO1A4_SEL_SHIFT (0U)
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#define GRF_GPIO1A_IOMUX_H_GPIO1A4_SEL_MASK (0x7U << GRF_GPIO1A_IOMUX_H_GPIO1A4_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO1A_IOMUX_H_GPIO1A5_SEL_SHIFT (4U)
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#define GRF_GPIO1A_IOMUX_H_GPIO1A5_SEL_MASK (0x7U << GRF_GPIO1A_IOMUX_H_GPIO1A5_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO1A_IOMUX_H_GPIO1A6_SEL_SHIFT (8U)
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#define GRF_GPIO1A_IOMUX_H_GPIO1A6_SEL_MASK (0x7U << GRF_GPIO1A_IOMUX_H_GPIO1A6_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO1A_IOMUX_H_GPIO1A7_SEL_SHIFT (12U)
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#define GRF_GPIO1A_IOMUX_H_GPIO1A7_SEL_MASK (0x7U << GRF_GPIO1A_IOMUX_H_GPIO1A7_SEL_SHIFT) /* 0x00007000 */
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/* GPIO1B_IOMUX_L */
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#define GRF_GPIO1B_IOMUX_L_OFFSET (0x40008U)
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#define GRF_GPIO1B_IOMUX_L_GPIO1B0_SEL_SHIFT (0U)
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#define GRF_GPIO1B_IOMUX_L_GPIO1B0_SEL_MASK (0x7U << GRF_GPIO1B_IOMUX_L_GPIO1B0_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO1B_IOMUX_L_GPIO1B1_SEL_SHIFT (4U)
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#define GRF_GPIO1B_IOMUX_L_GPIO1B1_SEL_MASK (0x7U << GRF_GPIO1B_IOMUX_L_GPIO1B1_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO1B_IOMUX_L_GPIO1B2_SEL_SHIFT (8U)
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#define GRF_GPIO1B_IOMUX_L_GPIO1B2_SEL_MASK (0x7U << GRF_GPIO1B_IOMUX_L_GPIO1B2_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO1B_IOMUX_L_GPIO1B3_SEL_SHIFT (12U)
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#define GRF_GPIO1B_IOMUX_L_GPIO1B3_SEL_MASK (0x7U << GRF_GPIO1B_IOMUX_L_GPIO1B3_SEL_SHIFT) /* 0x00007000 */
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/* GPIO1B_IOMUX_H */
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#define GRF_GPIO1B_IOMUX_H_OFFSET (0x4000CU)
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#define GRF_GPIO1B_IOMUX_H_GPIO1B4_SEL_SHIFT (0U)
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#define GRF_GPIO1B_IOMUX_H_GPIO1B4_SEL_MASK (0x7U << GRF_GPIO1B_IOMUX_H_GPIO1B4_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO1B_IOMUX_H_GPIO1B5_SEL_SHIFT (4U)
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#define GRF_GPIO1B_IOMUX_H_GPIO1B5_SEL_MASK (0x7U << GRF_GPIO1B_IOMUX_H_GPIO1B5_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO1B_IOMUX_H_GPIO1B6_SEL_SHIFT (8U)
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#define GRF_GPIO1B_IOMUX_H_GPIO1B6_SEL_MASK (0x7U << GRF_GPIO1B_IOMUX_H_GPIO1B6_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO1B_IOMUX_H_GPIO1B7_SEL_SHIFT (12U)
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#define GRF_GPIO1B_IOMUX_H_GPIO1B7_SEL_MASK (0x7U << GRF_GPIO1B_IOMUX_H_GPIO1B7_SEL_SHIFT) /* 0x00007000 */
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/* GPIO1C_IOMUX_L */
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#define GRF_GPIO1C_IOMUX_L_OFFSET (0x40010U)
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#define GRF_GPIO1C_IOMUX_L_GPIO1C0_SEL_SHIFT (0U)
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#define GRF_GPIO1C_IOMUX_L_GPIO1C0_SEL_MASK (0x7U << GRF_GPIO1C_IOMUX_L_GPIO1C0_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO1C_IOMUX_L_GPIO1C1_SEL_SHIFT (4U)
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#define GRF_GPIO1C_IOMUX_L_GPIO1C1_SEL_MASK (0x7U << GRF_GPIO1C_IOMUX_L_GPIO1C1_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO1C_IOMUX_L_GPIO1C2_SEL_SHIFT (8U)
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#define GRF_GPIO1C_IOMUX_L_GPIO1C2_SEL_MASK (0x7U << GRF_GPIO1C_IOMUX_L_GPIO1C2_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO1C_IOMUX_L_GPIO1C3_SEL_SHIFT (12U)
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#define GRF_GPIO1C_IOMUX_L_GPIO1C3_SEL_MASK (0x7U << GRF_GPIO1C_IOMUX_L_GPIO1C3_SEL_SHIFT) /* 0x00007000 */
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/* GPIO1C_IOMUX_H */
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#define GRF_GPIO1C_IOMUX_H_OFFSET (0x40014U)
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#define GRF_GPIO1C_IOMUX_H_GPIO1C4_SEL_SHIFT (0U)
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#define GRF_GPIO1C_IOMUX_H_GPIO1C4_SEL_MASK (0x7U << GRF_GPIO1C_IOMUX_H_GPIO1C4_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO1C_IOMUX_H_GPIO1C5_SEL_SHIFT (4U)
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#define GRF_GPIO1C_IOMUX_H_GPIO1C5_SEL_MASK (0x7U << GRF_GPIO1C_IOMUX_H_GPIO1C5_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO1C_IOMUX_H_GPIO1C6_SEL_SHIFT (8U)
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#define GRF_GPIO1C_IOMUX_H_GPIO1C6_SEL_MASK (0x7U << GRF_GPIO1C_IOMUX_H_GPIO1C6_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO1C_IOMUX_H_GPIO1C7_SEL_SHIFT (12U)
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#define GRF_GPIO1C_IOMUX_H_GPIO1C7_SEL_MASK (0x7U << GRF_GPIO1C_IOMUX_H_GPIO1C7_SEL_SHIFT) /* 0x00007000 */
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/* GPIO1D_IOMUX_L */
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#define GRF_GPIO1D_IOMUX_L_OFFSET (0x40018U)
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#define GRF_GPIO1D_IOMUX_L_GPIO1D0_SEL_SHIFT (0U)
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#define GRF_GPIO1D_IOMUX_L_GPIO1D0_SEL_MASK (0x7U << GRF_GPIO1D_IOMUX_L_GPIO1D0_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO1D_IOMUX_L_GPIO1D1_SEL_SHIFT (4U)
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#define GRF_GPIO1D_IOMUX_L_GPIO1D1_SEL_MASK (0x7U << GRF_GPIO1D_IOMUX_L_GPIO1D1_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO1D_IOMUX_L_GPIO1D2_SEL_SHIFT (8U)
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#define GRF_GPIO1D_IOMUX_L_GPIO1D2_SEL_MASK (0x7U << GRF_GPIO1D_IOMUX_L_GPIO1D2_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO1D_IOMUX_L_GPIO1D3_SEL_SHIFT (12U)
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#define GRF_GPIO1D_IOMUX_L_GPIO1D3_SEL_MASK (0x7U << GRF_GPIO1D_IOMUX_L_GPIO1D3_SEL_SHIFT) /* 0x00007000 */
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/* GPIO1D_IOMUX_H */
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#define GRF_GPIO1D_IOMUX_H_OFFSET (0x4001CU)
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#define GRF_GPIO1D_IOMUX_H_GPIO1D4_SEL_SHIFT (0U)
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#define GRF_GPIO1D_IOMUX_H_GPIO1D4_SEL_MASK (0x7U << GRF_GPIO1D_IOMUX_H_GPIO1D4_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO1D_IOMUX_H_GPIO1D5_SEL_SHIFT (4U)
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#define GRF_GPIO1D_IOMUX_H_GPIO1D5_SEL_MASK (0x7U << GRF_GPIO1D_IOMUX_H_GPIO1D5_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO1D_IOMUX_H_GPIO1D6_SEL_SHIFT (8U)
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#define GRF_GPIO1D_IOMUX_H_GPIO1D6_SEL_MASK (0x7U << GRF_GPIO1D_IOMUX_H_GPIO1D6_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO1D_IOMUX_H_GPIO1D7_SEL_SHIFT (12U)
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#define GRF_GPIO1D_IOMUX_H_GPIO1D7_SEL_MASK (0x7U << GRF_GPIO1D_IOMUX_H_GPIO1D7_SEL_SHIFT) /* 0x00007000 */
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/* GPIO2A_IOMUX_L */
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#define GRF_GPIO2A_IOMUX_L_OFFSET (0x40020U)
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#define GRF_GPIO2A_IOMUX_L_GPIO2A0_SEL_SHIFT (0U)
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#define GRF_GPIO2A_IOMUX_L_GPIO2A0_SEL_MASK (0x7U << GRF_GPIO2A_IOMUX_L_GPIO2A0_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO2A_IOMUX_L_GPIO2A1_SEL_SHIFT (4U)
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#define GRF_GPIO2A_IOMUX_L_GPIO2A1_SEL_MASK (0x7U << GRF_GPIO2A_IOMUX_L_GPIO2A1_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO2A_IOMUX_L_GPIO2A2_SEL_SHIFT (8U)
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#define GRF_GPIO2A_IOMUX_L_GPIO2A2_SEL_MASK (0x7U << GRF_GPIO2A_IOMUX_L_GPIO2A2_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO2A_IOMUX_L_GPIO2A3_SEL_SHIFT (12U)
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#define GRF_GPIO2A_IOMUX_L_GPIO2A3_SEL_MASK (0x7U << GRF_GPIO2A_IOMUX_L_GPIO2A3_SEL_SHIFT) /* 0x00007000 */
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/* GPIO2A_IOMUX_H */
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#define GRF_GPIO2A_IOMUX_H_OFFSET (0x40024U)
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#define GRF_GPIO2A_IOMUX_H_GPIO2A4_SEL_SHIFT (0U)
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#define GRF_GPIO2A_IOMUX_H_GPIO2A4_SEL_MASK (0x7U << GRF_GPIO2A_IOMUX_H_GPIO2A4_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO2A_IOMUX_H_GPIO2A5_SEL_SHIFT (4U)
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#define GRF_GPIO2A_IOMUX_H_GPIO2A5_SEL_MASK (0x7U << GRF_GPIO2A_IOMUX_H_GPIO2A5_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO2A_IOMUX_H_GPIO2A6_SEL_SHIFT (8U)
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#define GRF_GPIO2A_IOMUX_H_GPIO2A6_SEL_MASK (0x7U << GRF_GPIO2A_IOMUX_H_GPIO2A6_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO2A_IOMUX_H_GPIO2A7_SEL_SHIFT (12U)
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#define GRF_GPIO2A_IOMUX_H_GPIO2A7_SEL_MASK (0x7U << GRF_GPIO2A_IOMUX_H_GPIO2A7_SEL_SHIFT) /* 0x00007000 */
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/* GPIO2B_IOMUX_L */
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#define GRF_GPIO2B_IOMUX_L_OFFSET (0x40028U)
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#define GRF_GPIO2B_IOMUX_L_GPIO2B0_SEL_SHIFT (0U)
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#define GRF_GPIO2B_IOMUX_L_GPIO2B0_SEL_MASK (0x7U << GRF_GPIO2B_IOMUX_L_GPIO2B0_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO2B_IOMUX_L_GPIO2B1_SEL_SHIFT (4U)
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#define GRF_GPIO2B_IOMUX_L_GPIO2B1_SEL_MASK (0x7U << GRF_GPIO2B_IOMUX_L_GPIO2B1_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO2B_IOMUX_L_GPIO2B2_SEL_SHIFT (8U)
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#define GRF_GPIO2B_IOMUX_L_GPIO2B2_SEL_MASK (0x7U << GRF_GPIO2B_IOMUX_L_GPIO2B2_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO2B_IOMUX_L_GPIO2B3_SEL_SHIFT (12U)
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#define GRF_GPIO2B_IOMUX_L_GPIO2B3_SEL_MASK (0x7U << GRF_GPIO2B_IOMUX_L_GPIO2B3_SEL_SHIFT) /* 0x00007000 */
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/* GPIO2B_IOMUX_H */
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#define GRF_GPIO2B_IOMUX_H_OFFSET (0x4002CU)
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#define GRF_GPIO2B_IOMUX_H_GPIO2B4_SEL_SHIFT (0U)
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#define GRF_GPIO2B_IOMUX_H_GPIO2B4_SEL_MASK (0x7U << GRF_GPIO2B_IOMUX_H_GPIO2B4_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO2B_IOMUX_H_GPIO2B5_SEL_SHIFT (4U)
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#define GRF_GPIO2B_IOMUX_H_GPIO2B5_SEL_MASK (0x7U << GRF_GPIO2B_IOMUX_H_GPIO2B5_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO2B_IOMUX_H_GPIO2B6_SEL_SHIFT (8U)
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#define GRF_GPIO2B_IOMUX_H_GPIO2B6_SEL_MASK (0x7U << GRF_GPIO2B_IOMUX_H_GPIO2B6_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO2B_IOMUX_H_GPIO2B7_SEL_SHIFT (12U)
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#define GRF_GPIO2B_IOMUX_H_GPIO2B7_SEL_MASK (0x7U << GRF_GPIO2B_IOMUX_H_GPIO2B7_SEL_SHIFT) /* 0x00007000 */
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/* GPIO2C_IOMUX_L */
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#define GRF_GPIO2C_IOMUX_L_OFFSET (0x40030U)
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#define GRF_GPIO2C_IOMUX_L_GPIO2C0_SEL_SHIFT (0U)
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#define GRF_GPIO2C_IOMUX_L_GPIO2C0_SEL_MASK (0x7U << GRF_GPIO2C_IOMUX_L_GPIO2C0_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO2C_IOMUX_L_GPIO2C1_SEL_SHIFT (4U)
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#define GRF_GPIO2C_IOMUX_L_GPIO2C1_SEL_MASK (0x7U << GRF_GPIO2C_IOMUX_L_GPIO2C1_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO2C_IOMUX_L_GPIO2C2_SEL_SHIFT (8U)
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#define GRF_GPIO2C_IOMUX_L_GPIO2C2_SEL_MASK (0x7U << GRF_GPIO2C_IOMUX_L_GPIO2C2_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO2C_IOMUX_L_GPIO2C3_SEL_SHIFT (12U)
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#define GRF_GPIO2C_IOMUX_L_GPIO2C3_SEL_MASK (0x7U << GRF_GPIO2C_IOMUX_L_GPIO2C3_SEL_SHIFT) /* 0x00007000 */
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/* GPIO2C_IOMUX_H */
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#define GRF_GPIO2C_IOMUX_H_OFFSET (0x40034U)
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#define GRF_GPIO2C_IOMUX_H_GPIO2C4_SEL_SHIFT (0U)
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#define GRF_GPIO2C_IOMUX_H_GPIO2C4_SEL_MASK (0x7U << GRF_GPIO2C_IOMUX_H_GPIO2C4_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO2C_IOMUX_H_GPIO2C5_SEL_SHIFT (4U)
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#define GRF_GPIO2C_IOMUX_H_GPIO2C5_SEL_MASK (0x7U << GRF_GPIO2C_IOMUX_H_GPIO2C5_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO2C_IOMUX_H_GPIO2C6_SEL_SHIFT (8U)
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#define GRF_GPIO2C_IOMUX_H_GPIO2C6_SEL_MASK (0x7U << GRF_GPIO2C_IOMUX_H_GPIO2C6_SEL_SHIFT) /* 0x00000700 */
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/* GPIO2D_IOMUX_L */
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#define GRF_GPIO2D_IOMUX_L_OFFSET (0x40038U)
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#define GRF_GPIO2D_IOMUX_L_GPIO2D0_SEL_SHIFT (0U)
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#define GRF_GPIO2D_IOMUX_L_GPIO2D0_SEL_MASK (0x7U << GRF_GPIO2D_IOMUX_L_GPIO2D0_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO2D_IOMUX_L_GPIO2D1_SEL_SHIFT (4U)
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#define GRF_GPIO2D_IOMUX_L_GPIO2D1_SEL_MASK (0x7U << GRF_GPIO2D_IOMUX_L_GPIO2D1_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO2D_IOMUX_L_GPIO2D2_SEL_SHIFT (8U)
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#define GRF_GPIO2D_IOMUX_L_GPIO2D2_SEL_MASK (0x7U << GRF_GPIO2D_IOMUX_L_GPIO2D2_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO2D_IOMUX_L_GPIO2D3_SEL_SHIFT (12U)
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#define GRF_GPIO2D_IOMUX_L_GPIO2D3_SEL_MASK (0x7U << GRF_GPIO2D_IOMUX_L_GPIO2D3_SEL_SHIFT) /* 0x00007000 */
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/* GPIO2D_IOMUX_H */
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#define GRF_GPIO2D_IOMUX_H_OFFSET (0x4003CU)
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#define GRF_GPIO2D_IOMUX_H_GPIO2D4_SEL_SHIFT (0U)
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#define GRF_GPIO2D_IOMUX_H_GPIO2D4_SEL_MASK (0x7U << GRF_GPIO2D_IOMUX_H_GPIO2D4_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO2D_IOMUX_H_GPIO2D5_SEL_SHIFT (4U)
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#define GRF_GPIO2D_IOMUX_H_GPIO2D5_SEL_MASK (0x7U << GRF_GPIO2D_IOMUX_H_GPIO2D5_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO2D_IOMUX_H_GPIO2D6_SEL_SHIFT (8U)
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#define GRF_GPIO2D_IOMUX_H_GPIO2D6_SEL_MASK (0x7U << GRF_GPIO2D_IOMUX_H_GPIO2D6_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO2D_IOMUX_H_GPIO2D7_SEL_SHIFT (12U)
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#define GRF_GPIO2D_IOMUX_H_GPIO2D7_SEL_MASK (0x7U << GRF_GPIO2D_IOMUX_H_GPIO2D7_SEL_SHIFT) /* 0x00007000 */
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/* GPIO3A_IOMUX_L */
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#define GRF_GPIO3A_IOMUX_L_OFFSET (0x40040U)
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#define GRF_GPIO3A_IOMUX_L_GPIO3A0_SEL_SHIFT (0U)
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#define GRF_GPIO3A_IOMUX_L_GPIO3A0_SEL_MASK (0x7U << GRF_GPIO3A_IOMUX_L_GPIO3A0_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO3A_IOMUX_L_GPIO3A1_SEL_SHIFT (4U)
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#define GRF_GPIO3A_IOMUX_L_GPIO3A1_SEL_MASK (0x7U << GRF_GPIO3A_IOMUX_L_GPIO3A1_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO3A_IOMUX_L_GPIO3A2_SEL_SHIFT (8U)
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#define GRF_GPIO3A_IOMUX_L_GPIO3A2_SEL_MASK (0x7U << GRF_GPIO3A_IOMUX_L_GPIO3A2_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO3A_IOMUX_L_GPIO3A3_SEL_SHIFT (12U)
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#define GRF_GPIO3A_IOMUX_L_GPIO3A3_SEL_MASK (0x7U << GRF_GPIO3A_IOMUX_L_GPIO3A3_SEL_SHIFT) /* 0x00007000 */
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/* GPIO3A_IOMUX_H */
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#define GRF_GPIO3A_IOMUX_H_OFFSET (0x40044U)
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#define GRF_GPIO3A_IOMUX_H_GPIO3A4_SEL_SHIFT (0U)
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#define GRF_GPIO3A_IOMUX_H_GPIO3A4_SEL_MASK (0x7U << GRF_GPIO3A_IOMUX_H_GPIO3A4_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO3A_IOMUX_H_GPIO3A5_SEL_SHIFT (4U)
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#define GRF_GPIO3A_IOMUX_H_GPIO3A5_SEL_MASK (0x7U << GRF_GPIO3A_IOMUX_H_GPIO3A5_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO3A_IOMUX_H_GPIO3A6_SEL_SHIFT (8U)
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#define GRF_GPIO3A_IOMUX_H_GPIO3A6_SEL_MASK (0x7U << GRF_GPIO3A_IOMUX_H_GPIO3A6_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO3A_IOMUX_H_GPIO3A7_SEL_SHIFT (12U)
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#define GRF_GPIO3A_IOMUX_H_GPIO3A7_SEL_MASK (0x7U << GRF_GPIO3A_IOMUX_H_GPIO3A7_SEL_SHIFT) /* 0x00007000 */
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/* GPIO3B_IOMUX_L */
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#define GRF_GPIO3B_IOMUX_L_OFFSET (0x40048U)
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#define GRF_GPIO3B_IOMUX_L_GPIO3B0_SEL_SHIFT (0U)
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#define GRF_GPIO3B_IOMUX_L_GPIO3B0_SEL_MASK (0x7U << GRF_GPIO3B_IOMUX_L_GPIO3B0_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO3B_IOMUX_L_GPIO3B1_SEL_SHIFT (4U)
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#define GRF_GPIO3B_IOMUX_L_GPIO3B1_SEL_MASK (0x7U << GRF_GPIO3B_IOMUX_L_GPIO3B1_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO3B_IOMUX_L_GPIO3B2_SEL_SHIFT (8U)
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#define GRF_GPIO3B_IOMUX_L_GPIO3B2_SEL_MASK (0x7U << GRF_GPIO3B_IOMUX_L_GPIO3B2_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO3B_IOMUX_L_GPIO3B3_SEL_SHIFT (12U)
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#define GRF_GPIO3B_IOMUX_L_GPIO3B3_SEL_MASK (0x7U << GRF_GPIO3B_IOMUX_L_GPIO3B3_SEL_SHIFT) /* 0x00007000 */
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/* GPIO3B_IOMUX_H */
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#define GRF_GPIO3B_IOMUX_H_OFFSET (0x4004CU)
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#define GRF_GPIO3B_IOMUX_H_GPIO3B4_SEL_SHIFT (0U)
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#define GRF_GPIO3B_IOMUX_H_GPIO3B4_SEL_MASK (0x7U << GRF_GPIO3B_IOMUX_H_GPIO3B4_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO3B_IOMUX_H_GPIO3B5_SEL_SHIFT (4U)
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#define GRF_GPIO3B_IOMUX_H_GPIO3B5_SEL_MASK (0x7U << GRF_GPIO3B_IOMUX_H_GPIO3B5_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO3B_IOMUX_H_GPIO3B6_SEL_SHIFT (8U)
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#define GRF_GPIO3B_IOMUX_H_GPIO3B6_SEL_MASK (0x7U << GRF_GPIO3B_IOMUX_H_GPIO3B6_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO3B_IOMUX_H_GPIO3B7_SEL_SHIFT (12U)
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#define GRF_GPIO3B_IOMUX_H_GPIO3B7_SEL_MASK (0x7U << GRF_GPIO3B_IOMUX_H_GPIO3B7_SEL_SHIFT) /* 0x00007000 */
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/* GPIO3C_IOMUX_L */
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#define GRF_GPIO3C_IOMUX_L_OFFSET (0x40050U)
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#define GRF_GPIO3C_IOMUX_L_GPIO3C0_SEL_SHIFT (0U)
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#define GRF_GPIO3C_IOMUX_L_GPIO3C0_SEL_MASK (0x7U << GRF_GPIO3C_IOMUX_L_GPIO3C0_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO3C_IOMUX_L_GPIO3C1_SEL_SHIFT (4U)
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#define GRF_GPIO3C_IOMUX_L_GPIO3C1_SEL_MASK (0x7U << GRF_GPIO3C_IOMUX_L_GPIO3C1_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO3C_IOMUX_L_GPIO3C2_SEL_SHIFT (8U)
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#define GRF_GPIO3C_IOMUX_L_GPIO3C2_SEL_MASK (0x7U << GRF_GPIO3C_IOMUX_L_GPIO3C2_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO3C_IOMUX_L_GPIO3C3_SEL_SHIFT (12U)
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#define GRF_GPIO3C_IOMUX_L_GPIO3C3_SEL_MASK (0x7U << GRF_GPIO3C_IOMUX_L_GPIO3C3_SEL_SHIFT) /* 0x00007000 */
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/* GPIO3C_IOMUX_H */
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#define GRF_GPIO3C_IOMUX_H_OFFSET (0x40054U)
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#define GRF_GPIO3C_IOMUX_H_GPIO3C4_SEL_SHIFT (0U)
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#define GRF_GPIO3C_IOMUX_H_GPIO3C4_SEL_MASK (0x7U << GRF_GPIO3C_IOMUX_H_GPIO3C4_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO3C_IOMUX_H_GPIO3C5_SEL_SHIFT (4U)
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#define GRF_GPIO3C_IOMUX_H_GPIO3C5_SEL_MASK (0x7U << GRF_GPIO3C_IOMUX_H_GPIO3C5_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO3C_IOMUX_H_GPIO3C6_SEL_SHIFT (8U)
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#define GRF_GPIO3C_IOMUX_H_GPIO3C6_SEL_MASK (0x7U << GRF_GPIO3C_IOMUX_H_GPIO3C6_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO3C_IOMUX_H_GPIO3C7_SEL_SHIFT (12U)
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#define GRF_GPIO3C_IOMUX_H_GPIO3C7_SEL_MASK (0x7U << GRF_GPIO3C_IOMUX_H_GPIO3C7_SEL_SHIFT) /* 0x00007000 */
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/* GPIO3D_IOMUX_L */
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#define GRF_GPIO3D_IOMUX_L_OFFSET (0x40058U)
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#define GRF_GPIO3D_IOMUX_L_GPIO3D0_SEL_SHIFT (0U)
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#define GRF_GPIO3D_IOMUX_L_GPIO3D0_SEL_MASK (0x7U << GRF_GPIO3D_IOMUX_L_GPIO3D0_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO3D_IOMUX_L_GPIO3D1_SEL_SHIFT (4U)
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#define GRF_GPIO3D_IOMUX_L_GPIO3D1_SEL_MASK (0x7U << GRF_GPIO3D_IOMUX_L_GPIO3D1_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO3D_IOMUX_L_GPIO3D2_SEL_SHIFT (8U)
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#define GRF_GPIO3D_IOMUX_L_GPIO3D2_SEL_MASK (0x7U << GRF_GPIO3D_IOMUX_L_GPIO3D2_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO3D_IOMUX_L_GPIO3D3_SEL_SHIFT (12U)
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#define GRF_GPIO3D_IOMUX_L_GPIO3D3_SEL_MASK (0x7U << GRF_GPIO3D_IOMUX_L_GPIO3D3_SEL_SHIFT) /* 0x00007000 */
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/* GPIO3D_IOMUX_H */
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#define GRF_GPIO3D_IOMUX_H_OFFSET (0x4005CU)
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#define GRF_GPIO3D_IOMUX_H_GPIO3D4_SEL_SHIFT (0U)
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#define GRF_GPIO3D_IOMUX_H_GPIO3D4_SEL_MASK (0x7U << GRF_GPIO3D_IOMUX_H_GPIO3D4_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO3D_IOMUX_H_GPIO3D5_SEL_SHIFT (4U)
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#define GRF_GPIO3D_IOMUX_H_GPIO3D5_SEL_MASK (0x7U << GRF_GPIO3D_IOMUX_H_GPIO3D5_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO3D_IOMUX_H_GPIO3D6_SEL_SHIFT (8U)
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#define GRF_GPIO3D_IOMUX_H_GPIO3D6_SEL_MASK (0x7U << GRF_GPIO3D_IOMUX_H_GPIO3D6_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO3D_IOMUX_H_GPIO3D7_SEL_SHIFT (12U)
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#define GRF_GPIO3D_IOMUX_H_GPIO3D7_SEL_MASK (0x7U << GRF_GPIO3D_IOMUX_H_GPIO3D7_SEL_SHIFT) /* 0x00007000 */
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/* GPIO4A_IOMUX_L */
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#define GRF_GPIO4A_IOMUX_L_OFFSET (0x40060U)
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#define GRF_GPIO4A_IOMUX_L_GPIO4A0_SEL_SHIFT (0U)
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#define GRF_GPIO4A_IOMUX_L_GPIO4A0_SEL_MASK (0x7U << GRF_GPIO4A_IOMUX_L_GPIO4A0_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO4A_IOMUX_L_GPIO4A1_SEL_SHIFT (4U)
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#define GRF_GPIO4A_IOMUX_L_GPIO4A1_SEL_MASK (0x7U << GRF_GPIO4A_IOMUX_L_GPIO4A1_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO4A_IOMUX_L_GPIO4A2_SEL_SHIFT (8U)
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#define GRF_GPIO4A_IOMUX_L_GPIO4A2_SEL_MASK (0x7U << GRF_GPIO4A_IOMUX_L_GPIO4A2_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO4A_IOMUX_L_GPIO4A3_SEL_SHIFT (12U)
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#define GRF_GPIO4A_IOMUX_L_GPIO4A3_SEL_MASK (0x7U << GRF_GPIO4A_IOMUX_L_GPIO4A3_SEL_SHIFT) /* 0x00007000 */
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/* GPIO4A_IOMUX_H */
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#define GRF_GPIO4A_IOMUX_H_OFFSET (0x40064U)
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#define GRF_GPIO4A_IOMUX_H_GPIO4A4_SEL_SHIFT (0U)
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#define GRF_GPIO4A_IOMUX_H_GPIO4A4_SEL_MASK (0x7U << GRF_GPIO4A_IOMUX_H_GPIO4A4_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO4A_IOMUX_H_GPIO4A5_SEL_SHIFT (4U)
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#define GRF_GPIO4A_IOMUX_H_GPIO4A5_SEL_MASK (0x7U << GRF_GPIO4A_IOMUX_H_GPIO4A5_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO4A_IOMUX_H_GPIO4A6_SEL_SHIFT (8U)
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#define GRF_GPIO4A_IOMUX_H_GPIO4A6_SEL_MASK (0x7U << GRF_GPIO4A_IOMUX_H_GPIO4A6_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO4A_IOMUX_H_GPIO4A7_SEL_SHIFT (12U)
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#define GRF_GPIO4A_IOMUX_H_GPIO4A7_SEL_MASK (0x7U << GRF_GPIO4A_IOMUX_H_GPIO4A7_SEL_SHIFT) /* 0x00007000 */
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/* GPIO4B_IOMUX_L */
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#define GRF_GPIO4B_IOMUX_L_OFFSET (0x40068U)
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#define GRF_GPIO4B_IOMUX_L_GPIO4B0_SEL_SHIFT (0U)
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#define GRF_GPIO4B_IOMUX_L_GPIO4B0_SEL_MASK (0x7U << GRF_GPIO4B_IOMUX_L_GPIO4B0_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO4B_IOMUX_L_GPIO4B1_SEL_SHIFT (4U)
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#define GRF_GPIO4B_IOMUX_L_GPIO4B1_SEL_MASK (0x7U << GRF_GPIO4B_IOMUX_L_GPIO4B1_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO4B_IOMUX_L_GPIO4B2_SEL_SHIFT (8U)
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#define GRF_GPIO4B_IOMUX_L_GPIO4B2_SEL_MASK (0x7U << GRF_GPIO4B_IOMUX_L_GPIO4B2_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO4B_IOMUX_L_GPIO4B3_SEL_SHIFT (12U)
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#define GRF_GPIO4B_IOMUX_L_GPIO4B3_SEL_MASK (0x7U << GRF_GPIO4B_IOMUX_L_GPIO4B3_SEL_SHIFT) /* 0x00007000 */
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/* GPIO4B_IOMUX_H */
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#define GRF_GPIO4B_IOMUX_H_OFFSET (0x4006CU)
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#define GRF_GPIO4B_IOMUX_H_GPIO4B4_SEL_SHIFT (0U)
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#define GRF_GPIO4B_IOMUX_H_GPIO4B4_SEL_MASK (0x7U << GRF_GPIO4B_IOMUX_H_GPIO4B4_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO4B_IOMUX_H_GPIO4B5_SEL_SHIFT (4U)
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#define GRF_GPIO4B_IOMUX_H_GPIO4B5_SEL_MASK (0x7U << GRF_GPIO4B_IOMUX_H_GPIO4B5_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO4B_IOMUX_H_GPIO4B6_SEL_SHIFT (8U)
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#define GRF_GPIO4B_IOMUX_H_GPIO4B6_SEL_MASK (0x7U << GRF_GPIO4B_IOMUX_H_GPIO4B6_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO4B_IOMUX_H_GPIO4B7_SEL_SHIFT (12U)
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#define GRF_GPIO4B_IOMUX_H_GPIO4B7_SEL_MASK (0x7U << GRF_GPIO4B_IOMUX_H_GPIO4B7_SEL_SHIFT) /* 0x00007000 */
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/* GPIO4C_IOMUX_L */
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#define GRF_GPIO4C_IOMUX_L_OFFSET (0x40070U)
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#define GRF_GPIO4C_IOMUX_L_GPIO4C0_SEL_SHIFT (0U)
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#define GRF_GPIO4C_IOMUX_L_GPIO4C0_SEL_MASK (0x7U << GRF_GPIO4C_IOMUX_L_GPIO4C0_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO4C_IOMUX_L_GPIO4C1_SEL_SHIFT (4U)
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#define GRF_GPIO4C_IOMUX_L_GPIO4C1_SEL_MASK (0x7U << GRF_GPIO4C_IOMUX_L_GPIO4C1_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO4C_IOMUX_L_GPIO4C2_SEL_SHIFT (8U)
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#define GRF_GPIO4C_IOMUX_L_GPIO4C2_SEL_MASK (0x7U << GRF_GPIO4C_IOMUX_L_GPIO4C2_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO4C_IOMUX_L_GPIO4C3_SEL_SHIFT (12U)
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#define GRF_GPIO4C_IOMUX_L_GPIO4C3_SEL_MASK (0x7U << GRF_GPIO4C_IOMUX_L_GPIO4C3_SEL_SHIFT) /* 0x00007000 */
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/* GPIO4C_IOMUX_H */
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#define GRF_GPIO4C_IOMUX_H_OFFSET (0x40074U)
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#define GRF_GPIO4C_IOMUX_H_GPIO4C4_SEL_SHIFT (0U)
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#define GRF_GPIO4C_IOMUX_H_GPIO4C4_SEL_MASK (0x7U << GRF_GPIO4C_IOMUX_H_GPIO4C4_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO4C_IOMUX_H_GPIO4C5_SEL_SHIFT (4U)
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#define GRF_GPIO4C_IOMUX_H_GPIO4C5_SEL_MASK (0x7U << GRF_GPIO4C_IOMUX_H_GPIO4C5_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO4C_IOMUX_H_GPIO4C6_SEL_SHIFT (8U)
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#define GRF_GPIO4C_IOMUX_H_GPIO4C6_SEL_MASK (0x7U << GRF_GPIO4C_IOMUX_H_GPIO4C6_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPIO4C_IOMUX_H_GPIO4C7_SEL_SHIFT (12U)
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#define GRF_GPIO4C_IOMUX_H_GPIO4C7_SEL_MASK (0x7U << GRF_GPIO4C_IOMUX_H_GPIO4C7_SEL_SHIFT) /* 0x00007000 */
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/* GPIO4D_IOMUX_L */
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#define GRF_GPIO4D_IOMUX_L_OFFSET (0x40078U)
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#define GRF_GPIO4D_IOMUX_L_GPIO4D0_SEL_SHIFT (0U)
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#define GRF_GPIO4D_IOMUX_L_GPIO4D0_SEL_MASK (0x7U << GRF_GPIO4D_IOMUX_L_GPIO4D0_SEL_SHIFT) /* 0x00000007 */
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#define GRF_GPIO4D_IOMUX_L_GPIO4D1_SEL_SHIFT (4U)
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#define GRF_GPIO4D_IOMUX_L_GPIO4D1_SEL_MASK (0x7U << GRF_GPIO4D_IOMUX_L_GPIO4D1_SEL_SHIFT) /* 0x00000070 */
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#define GRF_GPIO4D_IOMUX_L_GPIO4D2_SEL_SHIFT (8U)
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#define GRF_GPIO4D_IOMUX_L_GPIO4D2_SEL_MASK (0x7U << GRF_GPIO4D_IOMUX_L_GPIO4D2_SEL_SHIFT) /* 0x00000700 */
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/* GPIO1A_P */
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#define GRF_GPIO1A_P_OFFSET (0x40080U)
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#define GRF_GPIO1A_P_GPIO1A0_P_SHIFT (0U)
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#define GRF_GPIO1A_P_GPIO1A0_P_MASK (0x3U << GRF_GPIO1A_P_GPIO1A0_P_SHIFT) /* 0x00000003 */
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#define GRF_GPIO1A_P_GPIO1A1_P_SHIFT (2U)
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#define GRF_GPIO1A_P_GPIO1A1_P_MASK (0x3U << GRF_GPIO1A_P_GPIO1A1_P_SHIFT) /* 0x0000000C */
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#define GRF_GPIO1A_P_GPIO1A2_P_SHIFT (4U)
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#define GRF_GPIO1A_P_GPIO1A2_P_MASK (0x3U << GRF_GPIO1A_P_GPIO1A2_P_SHIFT) /* 0x00000030 */
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#define GRF_GPIO1A_P_GPIO1A3_P_SHIFT (6U)
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#define GRF_GPIO1A_P_GPIO1A3_P_MASK (0x3U << GRF_GPIO1A_P_GPIO1A3_P_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO1A_P_GPIO1A4_P_SHIFT (8U)
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#define GRF_GPIO1A_P_GPIO1A4_P_MASK (0x3U << GRF_GPIO1A_P_GPIO1A4_P_SHIFT) /* 0x00000300 */
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#define GRF_GPIO1A_P_GPIO1A5_P_SHIFT (10U)
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#define GRF_GPIO1A_P_GPIO1A5_P_MASK (0x3U << GRF_GPIO1A_P_GPIO1A5_P_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO1A_P_GPIO1A6_P_SHIFT (12U)
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#define GRF_GPIO1A_P_GPIO1A6_P_MASK (0x3U << GRF_GPIO1A_P_GPIO1A6_P_SHIFT) /* 0x00003000 */
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#define GRF_GPIO1A_P_GPIO1A7_P_SHIFT (14U)
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#define GRF_GPIO1A_P_GPIO1A7_P_MASK (0x3U << GRF_GPIO1A_P_GPIO1A7_P_SHIFT) /* 0x0000C000 */
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/* GPIO1B_P */
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#define GRF_GPIO1B_P_OFFSET (0x40084U)
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#define GRF_GPIO1B_P_GPIO1B0_P_SHIFT (0U)
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#define GRF_GPIO1B_P_GPIO1B0_P_MASK (0x3U << GRF_GPIO1B_P_GPIO1B0_P_SHIFT) /* 0x00000003 */
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#define GRF_GPIO1B_P_GPIO1B1_P_SHIFT (2U)
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#define GRF_GPIO1B_P_GPIO1B1_P_MASK (0x3U << GRF_GPIO1B_P_GPIO1B1_P_SHIFT) /* 0x0000000C */
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#define GRF_GPIO1B_P_GPIO1B2_P_SHIFT (4U)
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#define GRF_GPIO1B_P_GPIO1B2_P_MASK (0x3U << GRF_GPIO1B_P_GPIO1B2_P_SHIFT) /* 0x00000030 */
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#define GRF_GPIO1B_P_GPIO1B3_P_SHIFT (6U)
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#define GRF_GPIO1B_P_GPIO1B3_P_MASK (0x3U << GRF_GPIO1B_P_GPIO1B3_P_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO1B_P_GPIO1B4_P_SHIFT (8U)
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#define GRF_GPIO1B_P_GPIO1B4_P_MASK (0x3U << GRF_GPIO1B_P_GPIO1B4_P_SHIFT) /* 0x00000300 */
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#define GRF_GPIO1B_P_GPIO1B5_P_SHIFT (10U)
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#define GRF_GPIO1B_P_GPIO1B5_P_MASK (0x3U << GRF_GPIO1B_P_GPIO1B5_P_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO1B_P_GPIO1B6_P_SHIFT (12U)
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#define GRF_GPIO1B_P_GPIO1B6_P_MASK (0x3U << GRF_GPIO1B_P_GPIO1B6_P_SHIFT) /* 0x00003000 */
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#define GRF_GPIO1B_P_GPIO1B7_P_SHIFT (14U)
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#define GRF_GPIO1B_P_GPIO1B7_P_MASK (0x3U << GRF_GPIO1B_P_GPIO1B7_P_SHIFT) /* 0x0000C000 */
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/* GPIO1C_P */
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#define GRF_GPIO1C_P_OFFSET (0x40088U)
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#define GRF_GPIO1C_P_GPIO1C0_P_SHIFT (0U)
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#define GRF_GPIO1C_P_GPIO1C0_P_MASK (0x3U << GRF_GPIO1C_P_GPIO1C0_P_SHIFT) /* 0x00000003 */
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#define GRF_GPIO1C_P_GPIO1C1_P_SHIFT (2U)
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#define GRF_GPIO1C_P_GPIO1C1_P_MASK (0x3U << GRF_GPIO1C_P_GPIO1C1_P_SHIFT) /* 0x0000000C */
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#define GRF_GPIO1C_P_GPIO1C2_P_SHIFT (4U)
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#define GRF_GPIO1C_P_GPIO1C2_P_MASK (0x3U << GRF_GPIO1C_P_GPIO1C2_P_SHIFT) /* 0x00000030 */
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#define GRF_GPIO1C_P_GPIO1C3_P_SHIFT (6U)
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#define GRF_GPIO1C_P_GPIO1C3_P_MASK (0x3U << GRF_GPIO1C_P_GPIO1C3_P_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO1C_P_GPIO1C4_P_SHIFT (8U)
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#define GRF_GPIO1C_P_GPIO1C4_P_MASK (0x3U << GRF_GPIO1C_P_GPIO1C4_P_SHIFT) /* 0x00000300 */
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#define GRF_GPIO1C_P_GPIO1C5_P_SHIFT (10U)
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#define GRF_GPIO1C_P_GPIO1C5_P_MASK (0x3U << GRF_GPIO1C_P_GPIO1C5_P_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO1C_P_GPIO1C6_P_SHIFT (12U)
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#define GRF_GPIO1C_P_GPIO1C6_P_MASK (0x3U << GRF_GPIO1C_P_GPIO1C6_P_SHIFT) /* 0x00003000 */
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#define GRF_GPIO1C_P_GPIO1C7_P_SHIFT (14U)
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#define GRF_GPIO1C_P_GPIO1C7_P_MASK (0x3U << GRF_GPIO1C_P_GPIO1C7_P_SHIFT) /* 0x0000C000 */
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/* GPIO1D_P */
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#define GRF_GPIO1D_P_OFFSET (0x4008CU)
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#define GRF_GPIO1D_P_GPIO1D0_P_SHIFT (0U)
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#define GRF_GPIO1D_P_GPIO1D0_P_MASK (0x3U << GRF_GPIO1D_P_GPIO1D0_P_SHIFT) /* 0x00000003 */
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#define GRF_GPIO1D_P_GPIO1D1_P_SHIFT (2U)
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#define GRF_GPIO1D_P_GPIO1D1_P_MASK (0x3U << GRF_GPIO1D_P_GPIO1D1_P_SHIFT) /* 0x0000000C */
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#define GRF_GPIO1D_P_GPIO1D2_P_SHIFT (4U)
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#define GRF_GPIO1D_P_GPIO1D2_P_MASK (0x3U << GRF_GPIO1D_P_GPIO1D2_P_SHIFT) /* 0x00000030 */
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#define GRF_GPIO1D_P_GPIO1D3_P_SHIFT (6U)
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#define GRF_GPIO1D_P_GPIO1D3_P_MASK (0x3U << GRF_GPIO1D_P_GPIO1D3_P_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO1D_P_GPIO1D4_P_SHIFT (8U)
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#define GRF_GPIO1D_P_GPIO1D4_P_MASK (0x3U << GRF_GPIO1D_P_GPIO1D4_P_SHIFT) /* 0x00000300 */
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#define GRF_GPIO1D_P_GPIO1D5_P_SHIFT (10U)
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#define GRF_GPIO1D_P_GPIO1D5_P_MASK (0x3U << GRF_GPIO1D_P_GPIO1D5_P_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO1D_P_GPIO1D6_P_SHIFT (12U)
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#define GRF_GPIO1D_P_GPIO1D6_P_MASK (0x3U << GRF_GPIO1D_P_GPIO1D6_P_SHIFT) /* 0x00003000 */
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#define GRF_GPIO1D_P_GPIO1D7_P_SHIFT (14U)
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#define GRF_GPIO1D_P_GPIO1D7_P_MASK (0x3U << GRF_GPIO1D_P_GPIO1D7_P_SHIFT) /* 0x0000C000 */
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/* GPIO2A_P */
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#define GRF_GPIO2A_P_OFFSET (0x40090U)
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#define GRF_GPIO2A_P_GPIO2A0_P_SHIFT (0U)
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#define GRF_GPIO2A_P_GPIO2A0_P_MASK (0x3U << GRF_GPIO2A_P_GPIO2A0_P_SHIFT) /* 0x00000003 */
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#define GRF_GPIO2A_P_GPIO2A1_P_SHIFT (2U)
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#define GRF_GPIO2A_P_GPIO2A1_P_MASK (0x3U << GRF_GPIO2A_P_GPIO2A1_P_SHIFT) /* 0x0000000C */
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#define GRF_GPIO2A_P_GPIO2A2_P_SHIFT (4U)
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#define GRF_GPIO2A_P_GPIO2A2_P_MASK (0x3U << GRF_GPIO2A_P_GPIO2A2_P_SHIFT) /* 0x00000030 */
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#define GRF_GPIO2A_P_GPIO2A3_P_SHIFT (6U)
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#define GRF_GPIO2A_P_GPIO2A3_P_MASK (0x3U << GRF_GPIO2A_P_GPIO2A3_P_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO2A_P_GPIO2A4_P_SHIFT (8U)
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#define GRF_GPIO2A_P_GPIO2A4_P_MASK (0x3U << GRF_GPIO2A_P_GPIO2A4_P_SHIFT) /* 0x00000300 */
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#define GRF_GPIO2A_P_GPIO2A5_P_SHIFT (10U)
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#define GRF_GPIO2A_P_GPIO2A5_P_MASK (0x3U << GRF_GPIO2A_P_GPIO2A5_P_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO2A_P_GPIO2A6_P_SHIFT (12U)
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#define GRF_GPIO2A_P_GPIO2A6_P_MASK (0x3U << GRF_GPIO2A_P_GPIO2A6_P_SHIFT) /* 0x00003000 */
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#define GRF_GPIO2A_P_GPIO2A7_P_SHIFT (14U)
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#define GRF_GPIO2A_P_GPIO2A7_P_MASK (0x3U << GRF_GPIO2A_P_GPIO2A7_P_SHIFT) /* 0x0000C000 */
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/* GPIO2B_P */
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#define GRF_GPIO2B_P_OFFSET (0x40094U)
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#define GRF_GPIO2B_P_GPIO2B0_P_SHIFT (0U)
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#define GRF_GPIO2B_P_GPIO2B0_P_MASK (0x3U << GRF_GPIO2B_P_GPIO2B0_P_SHIFT) /* 0x00000003 */
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#define GRF_GPIO2B_P_GPIO2B1_P_SHIFT (2U)
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#define GRF_GPIO2B_P_GPIO2B1_P_MASK (0x3U << GRF_GPIO2B_P_GPIO2B1_P_SHIFT) /* 0x0000000C */
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#define GRF_GPIO2B_P_GPIO2B2_P_SHIFT (4U)
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#define GRF_GPIO2B_P_GPIO2B2_P_MASK (0x3U << GRF_GPIO2B_P_GPIO2B2_P_SHIFT) /* 0x00000030 */
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#define GRF_GPIO2B_P_GPIO2B3_P_SHIFT (6U)
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#define GRF_GPIO2B_P_GPIO2B3_P_MASK (0x3U << GRF_GPIO2B_P_GPIO2B3_P_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO2B_P_GPIO2B4_P_SHIFT (8U)
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#define GRF_GPIO2B_P_GPIO2B4_P_MASK (0x3U << GRF_GPIO2B_P_GPIO2B4_P_SHIFT) /* 0x00000300 */
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#define GRF_GPIO2B_P_GPIO2B5_P_SHIFT (10U)
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#define GRF_GPIO2B_P_GPIO2B5_P_MASK (0x3U << GRF_GPIO2B_P_GPIO2B5_P_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO2B_P_GPIO2B6_P_SHIFT (12U)
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#define GRF_GPIO2B_P_GPIO2B6_P_MASK (0x3U << GRF_GPIO2B_P_GPIO2B6_P_SHIFT) /* 0x00003000 */
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#define GRF_GPIO2B_P_GPIO2B7_P_SHIFT (14U)
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#define GRF_GPIO2B_P_GPIO2B7_P_MASK (0x3U << GRF_GPIO2B_P_GPIO2B7_P_SHIFT) /* 0x0000C000 */
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/* GPIO2C_P */
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#define GRF_GPIO2C_P_OFFSET (0x40098U)
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#define GRF_GPIO2C_P_GPIO2C0_P_SHIFT (0U)
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#define GRF_GPIO2C_P_GPIO2C0_P_MASK (0x3U << GRF_GPIO2C_P_GPIO2C0_P_SHIFT) /* 0x00000003 */
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#define GRF_GPIO2C_P_GPIO2C1_P_SHIFT (2U)
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#define GRF_GPIO2C_P_GPIO2C1_P_MASK (0x3U << GRF_GPIO2C_P_GPIO2C1_P_SHIFT) /* 0x0000000C */
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#define GRF_GPIO2C_P_GPIO2C2_P_SHIFT (4U)
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#define GRF_GPIO2C_P_GPIO2C2_P_MASK (0x3U << GRF_GPIO2C_P_GPIO2C2_P_SHIFT) /* 0x00000030 */
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#define GRF_GPIO2C_P_GPIO2C3_P_SHIFT (6U)
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#define GRF_GPIO2C_P_GPIO2C3_P_MASK (0x3U << GRF_GPIO2C_P_GPIO2C3_P_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO2C_P_GPIO2C4_P_SHIFT (8U)
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#define GRF_GPIO2C_P_GPIO2C4_P_MASK (0x3U << GRF_GPIO2C_P_GPIO2C4_P_SHIFT) /* 0x00000300 */
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#define GRF_GPIO2C_P_GPIO2C5_P_SHIFT (10U)
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#define GRF_GPIO2C_P_GPIO2C5_P_MASK (0x3U << GRF_GPIO2C_P_GPIO2C5_P_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO2C_P_GPIO2C6_P_SHIFT (12U)
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#define GRF_GPIO2C_P_GPIO2C6_P_MASK (0x3U << GRF_GPIO2C_P_GPIO2C6_P_SHIFT) /* 0x00003000 */
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#define GRF_GPIO2C_P_GPIO2C7_P_SHIFT (14U)
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#define GRF_GPIO2C_P_GPIO2C7_P_MASK (0x3U << GRF_GPIO2C_P_GPIO2C7_P_SHIFT) /* 0x0000C000 */
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/* GPIO2D_P */
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#define GRF_GPIO2D_P_OFFSET (0x4009CU)
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#define GRF_GPIO2D_P_GPIO2D0_P_SHIFT (0U)
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#define GRF_GPIO2D_P_GPIO2D0_P_MASK (0x3U << GRF_GPIO2D_P_GPIO2D0_P_SHIFT) /* 0x00000003 */
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#define GRF_GPIO2D_P_GPIO2D1_P_SHIFT (2U)
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#define GRF_GPIO2D_P_GPIO2D1_P_MASK (0x3U << GRF_GPIO2D_P_GPIO2D1_P_SHIFT) /* 0x0000000C */
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#define GRF_GPIO2D_P_GPIO2D2_P_SHIFT (4U)
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#define GRF_GPIO2D_P_GPIO2D2_P_MASK (0x3U << GRF_GPIO2D_P_GPIO2D2_P_SHIFT) /* 0x00000030 */
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#define GRF_GPIO2D_P_GPIO2D3_P_SHIFT (6U)
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#define GRF_GPIO2D_P_GPIO2D3_P_MASK (0x3U << GRF_GPIO2D_P_GPIO2D3_P_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO2D_P_GPIO2D4_P_SHIFT (8U)
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#define GRF_GPIO2D_P_GPIO2D4_P_MASK (0x3U << GRF_GPIO2D_P_GPIO2D4_P_SHIFT) /* 0x00000300 */
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#define GRF_GPIO2D_P_GPIO2D5_P_SHIFT (10U)
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#define GRF_GPIO2D_P_GPIO2D5_P_MASK (0x3U << GRF_GPIO2D_P_GPIO2D5_P_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO2D_P_GPIO2D6_P_SHIFT (12U)
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#define GRF_GPIO2D_P_GPIO2D6_P_MASK (0x3U << GRF_GPIO2D_P_GPIO2D6_P_SHIFT) /* 0x00003000 */
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#define GRF_GPIO2D_P_GPIO2D7_P_SHIFT (14U)
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#define GRF_GPIO2D_P_GPIO2D7_P_MASK (0x3U << GRF_GPIO2D_P_GPIO2D7_P_SHIFT) /* 0x0000C000 */
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/* GPIO3A_P */
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#define GRF_GPIO3A_P_OFFSET (0x400A0U)
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#define GRF_GPIO3A_P_GPIO3A0_P_SHIFT (0U)
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#define GRF_GPIO3A_P_GPIO3A0_P_MASK (0x3U << GRF_GPIO3A_P_GPIO3A0_P_SHIFT) /* 0x00000003 */
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#define GRF_GPIO3A_P_GPIO3A1_P_SHIFT (2U)
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#define GRF_GPIO3A_P_GPIO3A1_P_MASK (0x3U << GRF_GPIO3A_P_GPIO3A1_P_SHIFT) /* 0x0000000C */
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#define GRF_GPIO3A_P_GPIO3A2_P_SHIFT (4U)
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#define GRF_GPIO3A_P_GPIO3A2_P_MASK (0x3U << GRF_GPIO3A_P_GPIO3A2_P_SHIFT) /* 0x00000030 */
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#define GRF_GPIO3A_P_GPIO3A3_P_SHIFT (6U)
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#define GRF_GPIO3A_P_GPIO3A3_P_MASK (0x3U << GRF_GPIO3A_P_GPIO3A3_P_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO3A_P_GPIO3A4_P_SHIFT (8U)
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#define GRF_GPIO3A_P_GPIO3A4_P_MASK (0x3U << GRF_GPIO3A_P_GPIO3A4_P_SHIFT) /* 0x00000300 */
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#define GRF_GPIO3A_P_GPIO3A5_P_SHIFT (10U)
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#define GRF_GPIO3A_P_GPIO3A5_P_MASK (0x3U << GRF_GPIO3A_P_GPIO3A5_P_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO3A_P_GPIO3A6_P_SHIFT (12U)
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#define GRF_GPIO3A_P_GPIO3A6_P_MASK (0x3U << GRF_GPIO3A_P_GPIO3A6_P_SHIFT) /* 0x00003000 */
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#define GRF_GPIO3A_P_GPIO3A7_P_SHIFT (14U)
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#define GRF_GPIO3A_P_GPIO3A7_P_MASK (0x3U << GRF_GPIO3A_P_GPIO3A7_P_SHIFT) /* 0x0000C000 */
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/* GPIO3B_P */
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#define GRF_GPIO3B_P_OFFSET (0x400A4U)
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#define GRF_GPIO3B_P_GPIO3B0_P_SHIFT (0U)
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#define GRF_GPIO3B_P_GPIO3B0_P_MASK (0x3U << GRF_GPIO3B_P_GPIO3B0_P_SHIFT) /* 0x00000003 */
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#define GRF_GPIO3B_P_GPIO3B1_P_SHIFT (2U)
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#define GRF_GPIO3B_P_GPIO3B1_P_MASK (0x3U << GRF_GPIO3B_P_GPIO3B1_P_SHIFT) /* 0x0000000C */
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#define GRF_GPIO3B_P_GPIO3B2_P_SHIFT (4U)
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#define GRF_GPIO3B_P_GPIO3B2_P_MASK (0x3U << GRF_GPIO3B_P_GPIO3B2_P_SHIFT) /* 0x00000030 */
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#define GRF_GPIO3B_P_GPIO3B3_P_SHIFT (6U)
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#define GRF_GPIO3B_P_GPIO3B3_P_MASK (0x3U << GRF_GPIO3B_P_GPIO3B3_P_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO3B_P_GPIO3B4_P_SHIFT (8U)
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#define GRF_GPIO3B_P_GPIO3B4_P_MASK (0x3U << GRF_GPIO3B_P_GPIO3B4_P_SHIFT) /* 0x00000300 */
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#define GRF_GPIO3B_P_GPIO3B5_P_SHIFT (10U)
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#define GRF_GPIO3B_P_GPIO3B5_P_MASK (0x3U << GRF_GPIO3B_P_GPIO3B5_P_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO3B_P_GPIO3B6_P_SHIFT (12U)
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#define GRF_GPIO3B_P_GPIO3B6_P_MASK (0x3U << GRF_GPIO3B_P_GPIO3B6_P_SHIFT) /* 0x00003000 */
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#define GRF_GPIO3B_P_GPIO3B7_P_SHIFT (14U)
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#define GRF_GPIO3B_P_GPIO3B7_P_MASK (0x3U << GRF_GPIO3B_P_GPIO3B7_P_SHIFT) /* 0x0000C000 */
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/* GPIO3C_P */
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#define GRF_GPIO3C_P_OFFSET (0x400A8U)
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#define GRF_GPIO3C_P_GPIO3C0_P_SHIFT (0U)
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#define GRF_GPIO3C_P_GPIO3C0_P_MASK (0x3U << GRF_GPIO3C_P_GPIO3C0_P_SHIFT) /* 0x00000003 */
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#define GRF_GPIO3C_P_GPIO3C1_P_SHIFT (2U)
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#define GRF_GPIO3C_P_GPIO3C1_P_MASK (0x3U << GRF_GPIO3C_P_GPIO3C1_P_SHIFT) /* 0x0000000C */
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#define GRF_GPIO3C_P_GPIO3C2_P_SHIFT (4U)
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#define GRF_GPIO3C_P_GPIO3C2_P_MASK (0x3U << GRF_GPIO3C_P_GPIO3C2_P_SHIFT) /* 0x00000030 */
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#define GRF_GPIO3C_P_GPIO3C3_P_SHIFT (6U)
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#define GRF_GPIO3C_P_GPIO3C3_P_MASK (0x3U << GRF_GPIO3C_P_GPIO3C3_P_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO3C_P_GPIO3C4_P_SHIFT (8U)
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#define GRF_GPIO3C_P_GPIO3C4_P_MASK (0x3U << GRF_GPIO3C_P_GPIO3C4_P_SHIFT) /* 0x00000300 */
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#define GRF_GPIO3C_P_GPIO3C5_P_SHIFT (10U)
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#define GRF_GPIO3C_P_GPIO3C5_P_MASK (0x3U << GRF_GPIO3C_P_GPIO3C5_P_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO3C_P_GPIO3C6_P_SHIFT (12U)
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#define GRF_GPIO3C_P_GPIO3C6_P_MASK (0x3U << GRF_GPIO3C_P_GPIO3C6_P_SHIFT) /* 0x00003000 */
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#define GRF_GPIO3C_P_GPIO3C7_P_SHIFT (14U)
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#define GRF_GPIO3C_P_GPIO3C7_P_MASK (0x3U << GRF_GPIO3C_P_GPIO3C7_P_SHIFT) /* 0x0000C000 */
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/* GPIO3D_P */
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#define GRF_GPIO3D_P_OFFSET (0x400ACU)
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#define GRF_GPIO3D_P_GPIO3D0_P_SHIFT (0U)
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#define GRF_GPIO3D_P_GPIO3D0_P_MASK (0x3U << GRF_GPIO3D_P_GPIO3D0_P_SHIFT) /* 0x00000003 */
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#define GRF_GPIO3D_P_GPIO3D1_P_SHIFT (2U)
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#define GRF_GPIO3D_P_GPIO3D1_P_MASK (0x3U << GRF_GPIO3D_P_GPIO3D1_P_SHIFT) /* 0x0000000C */
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#define GRF_GPIO3D_P_GPIO3D2_P_SHIFT (4U)
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#define GRF_GPIO3D_P_GPIO3D2_P_MASK (0x3U << GRF_GPIO3D_P_GPIO3D2_P_SHIFT) /* 0x00000030 */
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#define GRF_GPIO3D_P_GPIO3D3_P_SHIFT (6U)
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#define GRF_GPIO3D_P_GPIO3D3_P_MASK (0x3U << GRF_GPIO3D_P_GPIO3D3_P_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO3D_P_GPIO3D4_P_SHIFT (8U)
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#define GRF_GPIO3D_P_GPIO3D4_P_MASK (0x3U << GRF_GPIO3D_P_GPIO3D4_P_SHIFT) /* 0x00000300 */
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#define GRF_GPIO3D_P_GPIO3D5_P_SHIFT (10U)
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#define GRF_GPIO3D_P_GPIO3D5_P_MASK (0x3U << GRF_GPIO3D_P_GPIO3D5_P_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO3D_P_GPIO3D6_P_SHIFT (12U)
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#define GRF_GPIO3D_P_GPIO3D6_P_MASK (0x3U << GRF_GPIO3D_P_GPIO3D6_P_SHIFT) /* 0x00003000 */
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#define GRF_GPIO3D_P_GPIO3D7_P_SHIFT (14U)
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#define GRF_GPIO3D_P_GPIO3D7_P_MASK (0x3U << GRF_GPIO3D_P_GPIO3D7_P_SHIFT) /* 0x0000C000 */
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/* GPIO4A_P */
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#define GRF_GPIO4A_P_OFFSET (0x400B0U)
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#define GRF_GPIO4A_P_GPIO4A0_P_SHIFT (0U)
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#define GRF_GPIO4A_P_GPIO4A0_P_MASK (0x3U << GRF_GPIO4A_P_GPIO4A0_P_SHIFT) /* 0x00000003 */
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#define GRF_GPIO4A_P_GPIO4A1_P_SHIFT (2U)
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#define GRF_GPIO4A_P_GPIO4A1_P_MASK (0x3U << GRF_GPIO4A_P_GPIO4A1_P_SHIFT) /* 0x0000000C */
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#define GRF_GPIO4A_P_GPIO4A2_P_SHIFT (4U)
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#define GRF_GPIO4A_P_GPIO4A2_P_MASK (0x3U << GRF_GPIO4A_P_GPIO4A2_P_SHIFT) /* 0x00000030 */
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#define GRF_GPIO4A_P_GPIO4A3_P_SHIFT (6U)
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#define GRF_GPIO4A_P_GPIO4A3_P_MASK (0x3U << GRF_GPIO4A_P_GPIO4A3_P_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO4A_P_GPIO4A4_P_SHIFT (8U)
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#define GRF_GPIO4A_P_GPIO4A4_P_MASK (0x3U << GRF_GPIO4A_P_GPIO4A4_P_SHIFT) /* 0x00000300 */
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#define GRF_GPIO4A_P_GPIO4A5_P_SHIFT (10U)
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#define GRF_GPIO4A_P_GPIO4A5_P_MASK (0x3U << GRF_GPIO4A_P_GPIO4A5_P_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO4A_P_GPIO4A6_P_SHIFT (12U)
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#define GRF_GPIO4A_P_GPIO4A6_P_MASK (0x3U << GRF_GPIO4A_P_GPIO4A6_P_SHIFT) /* 0x00003000 */
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#define GRF_GPIO4A_P_GPIO4A7_P_SHIFT (14U)
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#define GRF_GPIO4A_P_GPIO4A7_P_MASK (0x3U << GRF_GPIO4A_P_GPIO4A7_P_SHIFT) /* 0x0000C000 */
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/* GPIO4B_P */
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#define GRF_GPIO4B_P_OFFSET (0x400B4U)
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#define GRF_GPIO4B_P_GPIO4B0_P_SHIFT (0U)
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#define GRF_GPIO4B_P_GPIO4B0_P_MASK (0x3U << GRF_GPIO4B_P_GPIO4B0_P_SHIFT) /* 0x00000003 */
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#define GRF_GPIO4B_P_GPIO4B1_P_SHIFT (2U)
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#define GRF_GPIO4B_P_GPIO4B1_P_MASK (0x3U << GRF_GPIO4B_P_GPIO4B1_P_SHIFT) /* 0x0000000C */
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#define GRF_GPIO4B_P_GPIO4B2_P_SHIFT (4U)
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#define GRF_GPIO4B_P_GPIO4B2_P_MASK (0x3U << GRF_GPIO4B_P_GPIO4B2_P_SHIFT) /* 0x00000030 */
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#define GRF_GPIO4B_P_GPIO4B3_P_SHIFT (6U)
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#define GRF_GPIO4B_P_GPIO4B3_P_MASK (0x3U << GRF_GPIO4B_P_GPIO4B3_P_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO4B_P_GPIO4B4_P_SHIFT (8U)
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#define GRF_GPIO4B_P_GPIO4B4_P_MASK (0x3U << GRF_GPIO4B_P_GPIO4B4_P_SHIFT) /* 0x00000300 */
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#define GRF_GPIO4B_P_GPIO4B5_P_SHIFT (10U)
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#define GRF_GPIO4B_P_GPIO4B5_P_MASK (0x3U << GRF_GPIO4B_P_GPIO4B5_P_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO4B_P_GPIO4B6_P_SHIFT (12U)
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#define GRF_GPIO4B_P_GPIO4B6_P_MASK (0x3U << GRF_GPIO4B_P_GPIO4B6_P_SHIFT) /* 0x00003000 */
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#define GRF_GPIO4B_P_GPIO4B7_P_SHIFT (14U)
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#define GRF_GPIO4B_P_GPIO4B7_P_MASK (0x3U << GRF_GPIO4B_P_GPIO4B7_P_SHIFT) /* 0x0000C000 */
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/* GPIO4C_P */
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#define GRF_GPIO4C_P_OFFSET (0x400B8U)
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#define GRF_GPIO4C_P_GPIO4C0_P_SHIFT (0U)
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#define GRF_GPIO4C_P_GPIO4C0_P_MASK (0x3U << GRF_GPIO4C_P_GPIO4C0_P_SHIFT) /* 0x00000003 */
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#define GRF_GPIO4C_P_GPIO4C1_P_SHIFT (2U)
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#define GRF_GPIO4C_P_GPIO4C1_P_MASK (0x3U << GRF_GPIO4C_P_GPIO4C1_P_SHIFT) /* 0x0000000C */
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#define GRF_GPIO4C_P_GPIO4C2_P_SHIFT (4U)
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#define GRF_GPIO4C_P_GPIO4C2_P_MASK (0x3U << GRF_GPIO4C_P_GPIO4C2_P_SHIFT) /* 0x00000030 */
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#define GRF_GPIO4C_P_GPIO4C3_P_SHIFT (6U)
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#define GRF_GPIO4C_P_GPIO4C3_P_MASK (0x3U << GRF_GPIO4C_P_GPIO4C3_P_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO4C_P_GPIO4C4_P_SHIFT (8U)
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#define GRF_GPIO4C_P_GPIO4C4_P_MASK (0x3U << GRF_GPIO4C_P_GPIO4C4_P_SHIFT) /* 0x00000300 */
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#define GRF_GPIO4C_P_GPIO4C5_P_SHIFT (10U)
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#define GRF_GPIO4C_P_GPIO4C5_P_MASK (0x3U << GRF_GPIO4C_P_GPIO4C5_P_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO4C_P_GPIO4C6_P_SHIFT (12U)
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#define GRF_GPIO4C_P_GPIO4C6_P_MASK (0x3U << GRF_GPIO4C_P_GPIO4C6_P_SHIFT) /* 0x00003000 */
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#define GRF_GPIO4C_P_GPIO4C7_P_SHIFT (14U)
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#define GRF_GPIO4C_P_GPIO4C7_P_MASK (0x3U << GRF_GPIO4C_P_GPIO4C7_P_SHIFT) /* 0x0000C000 */
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/* GPIO4D_P */
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#define GRF_GPIO4D_P_OFFSET (0x400BCU)
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#define GRF_GPIO4D_P_GPIO4D0_P_SHIFT (0U)
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#define GRF_GPIO4D_P_GPIO4D0_P_MASK (0x3U << GRF_GPIO4D_P_GPIO4D0_P_SHIFT) /* 0x00000003 */
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#define GRF_GPIO4D_P_GPIO4D1_P_SHIFT (2U)
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#define GRF_GPIO4D_P_GPIO4D1_P_MASK (0x3U << GRF_GPIO4D_P_GPIO4D1_P_SHIFT) /* 0x0000000C */
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#define GRF_GPIO4D_P_GPIO4D2_P_SHIFT (4U)
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#define GRF_GPIO4D_P_GPIO4D2_P_MASK (0x3U << GRF_GPIO4D_P_GPIO4D2_P_SHIFT) /* 0x00000030 */
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#define GRF_GPIO4D_P_GPIO4D3_P_SHIFT (6U)
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#define GRF_GPIO4D_P_GPIO4D3_P_MASK (0x3U << GRF_GPIO4D_P_GPIO4D3_P_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO4D_P_GPIO4D4_P_SHIFT (8U)
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#define GRF_GPIO4D_P_GPIO4D4_P_MASK (0x3U << GRF_GPIO4D_P_GPIO4D4_P_SHIFT) /* 0x00000300 */
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#define GRF_GPIO4D_P_GPIO4D5_P_SHIFT (10U)
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#define GRF_GPIO4D_P_GPIO4D5_P_MASK (0x3U << GRF_GPIO4D_P_GPIO4D5_P_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO4D_P_GPIO4D6_P_SHIFT (12U)
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#define GRF_GPIO4D_P_GPIO4D6_P_MASK (0x3U << GRF_GPIO4D_P_GPIO4D6_P_SHIFT) /* 0x00003000 */
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#define GRF_GPIO4D_P_GPIO4D7_P_SHIFT (14U)
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#define GRF_GPIO4D_P_GPIO4D7_P_MASK (0x3U << GRF_GPIO4D_P_GPIO4D7_P_SHIFT) /* 0x0000C000 */
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/* GPIO1A_IE */
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#define GRF_GPIO1A_IE_OFFSET (0x400C0U)
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#define GRF_GPIO1A_IE_GPIO1A0_IE_SHIFT (0U)
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#define GRF_GPIO1A_IE_GPIO1A0_IE_MASK (0x3U << GRF_GPIO1A_IE_GPIO1A0_IE_SHIFT) /* 0x00000003 */
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#define GRF_GPIO1A_IE_GPIO1A1_IE_SHIFT (2U)
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#define GRF_GPIO1A_IE_GPIO1A1_IE_MASK (0x3U << GRF_GPIO1A_IE_GPIO1A1_IE_SHIFT) /* 0x0000000C */
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#define GRF_GPIO1A_IE_GPIO1A2_IE_SHIFT (4U)
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#define GRF_GPIO1A_IE_GPIO1A2_IE_MASK (0x3U << GRF_GPIO1A_IE_GPIO1A2_IE_SHIFT) /* 0x00000030 */
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#define GRF_GPIO1A_IE_GPIO1A3_IE_SHIFT (6U)
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#define GRF_GPIO1A_IE_GPIO1A3_IE_MASK (0x3U << GRF_GPIO1A_IE_GPIO1A3_IE_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO1A_IE_GPIO1A4_IE_SHIFT (8U)
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#define GRF_GPIO1A_IE_GPIO1A4_IE_MASK (0x3U << GRF_GPIO1A_IE_GPIO1A4_IE_SHIFT) /* 0x00000300 */
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#define GRF_GPIO1A_IE_GPIO1A5_IE_SHIFT (10U)
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#define GRF_GPIO1A_IE_GPIO1A5_IE_MASK (0x3U << GRF_GPIO1A_IE_GPIO1A5_IE_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO1A_IE_GPIO1A6_IE_SHIFT (12U)
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#define GRF_GPIO1A_IE_GPIO1A6_IE_MASK (0x3U << GRF_GPIO1A_IE_GPIO1A6_IE_SHIFT) /* 0x00003000 */
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#define GRF_GPIO1A_IE_GPIO1A7_IE_SHIFT (14U)
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#define GRF_GPIO1A_IE_GPIO1A7_IE_MASK (0x3U << GRF_GPIO1A_IE_GPIO1A7_IE_SHIFT) /* 0x0000C000 */
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/* GPIO1B_IE */
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#define GRF_GPIO1B_IE_OFFSET (0x400C4U)
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#define GRF_GPIO1B_IE_GPIO1B0_IE_SHIFT (0U)
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#define GRF_GPIO1B_IE_GPIO1B0_IE_MASK (0x3U << GRF_GPIO1B_IE_GPIO1B0_IE_SHIFT) /* 0x00000003 */
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#define GRF_GPIO1B_IE_GPIO1B1_IE_SHIFT (2U)
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#define GRF_GPIO1B_IE_GPIO1B1_IE_MASK (0x3U << GRF_GPIO1B_IE_GPIO1B1_IE_SHIFT) /* 0x0000000C */
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#define GRF_GPIO1B_IE_GPIO1B2_IE_SHIFT (4U)
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#define GRF_GPIO1B_IE_GPIO1B2_IE_MASK (0x3U << GRF_GPIO1B_IE_GPIO1B2_IE_SHIFT) /* 0x00000030 */
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#define GRF_GPIO1B_IE_GPIO1B3_IE_SHIFT (6U)
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#define GRF_GPIO1B_IE_GPIO1B3_IE_MASK (0x3U << GRF_GPIO1B_IE_GPIO1B3_IE_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO1B_IE_GPIO1B4_IE_SHIFT (8U)
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#define GRF_GPIO1B_IE_GPIO1B4_IE_MASK (0x3U << GRF_GPIO1B_IE_GPIO1B4_IE_SHIFT) /* 0x00000300 */
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#define GRF_GPIO1B_IE_GPIO1B5_IE_SHIFT (10U)
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#define GRF_GPIO1B_IE_GPIO1B5_IE_MASK (0x3U << GRF_GPIO1B_IE_GPIO1B5_IE_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO1B_IE_GPIO1B6_IE_SHIFT (12U)
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#define GRF_GPIO1B_IE_GPIO1B6_IE_MASK (0x3U << GRF_GPIO1B_IE_GPIO1B6_IE_SHIFT) /* 0x00003000 */
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#define GRF_GPIO1B_IE_GPIO1B7_IE_SHIFT (14U)
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#define GRF_GPIO1B_IE_GPIO1B7_IE_MASK (0x3U << GRF_GPIO1B_IE_GPIO1B7_IE_SHIFT) /* 0x0000C000 */
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/* GPIO1C_IE */
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#define GRF_GPIO1C_IE_OFFSET (0x400C8U)
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#define GRF_GPIO1C_IE_GPIO1C0_IE_SHIFT (0U)
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#define GRF_GPIO1C_IE_GPIO1C0_IE_MASK (0x3U << GRF_GPIO1C_IE_GPIO1C0_IE_SHIFT) /* 0x00000003 */
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#define GRF_GPIO1C_IE_GPIO1C1_IE_SHIFT (2U)
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#define GRF_GPIO1C_IE_GPIO1C1_IE_MASK (0x3U << GRF_GPIO1C_IE_GPIO1C1_IE_SHIFT) /* 0x0000000C */
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#define GRF_GPIO1C_IE_GPIO1C2_IE_SHIFT (4U)
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#define GRF_GPIO1C_IE_GPIO1C2_IE_MASK (0x3U << GRF_GPIO1C_IE_GPIO1C2_IE_SHIFT) /* 0x00000030 */
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#define GRF_GPIO1C_IE_GPIO1C3_IE_SHIFT (6U)
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#define GRF_GPIO1C_IE_GPIO1C3_IE_MASK (0x3U << GRF_GPIO1C_IE_GPIO1C3_IE_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO1C_IE_GPIO1C4_IE_SHIFT (8U)
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#define GRF_GPIO1C_IE_GPIO1C4_IE_MASK (0x3U << GRF_GPIO1C_IE_GPIO1C4_IE_SHIFT) /* 0x00000300 */
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#define GRF_GPIO1C_IE_GPIO1C5_IE_SHIFT (10U)
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#define GRF_GPIO1C_IE_GPIO1C5_IE_MASK (0x3U << GRF_GPIO1C_IE_GPIO1C5_IE_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO1C_IE_GPIO1C6_IE_SHIFT (12U)
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#define GRF_GPIO1C_IE_GPIO1C6_IE_MASK (0x3U << GRF_GPIO1C_IE_GPIO1C6_IE_SHIFT) /* 0x00003000 */
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#define GRF_GPIO1C_IE_GPIO1C7_IE_SHIFT (14U)
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#define GRF_GPIO1C_IE_GPIO1C7_IE_MASK (0x3U << GRF_GPIO1C_IE_GPIO1C7_IE_SHIFT) /* 0x0000C000 */
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/* GPIO1D_IE */
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#define GRF_GPIO1D_IE_OFFSET (0x400CCU)
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#define GRF_GPIO1D_IE_GPIO1D0_IE_SHIFT (0U)
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#define GRF_GPIO1D_IE_GPIO1D0_IE_MASK (0x3U << GRF_GPIO1D_IE_GPIO1D0_IE_SHIFT) /* 0x00000003 */
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#define GRF_GPIO1D_IE_GPIO1D1_IE_SHIFT (2U)
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#define GRF_GPIO1D_IE_GPIO1D1_IE_MASK (0x3U << GRF_GPIO1D_IE_GPIO1D1_IE_SHIFT) /* 0x0000000C */
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#define GRF_GPIO1D_IE_GPIO1D2_IE_SHIFT (4U)
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#define GRF_GPIO1D_IE_GPIO1D2_IE_MASK (0x3U << GRF_GPIO1D_IE_GPIO1D2_IE_SHIFT) /* 0x00000030 */
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#define GRF_GPIO1D_IE_GPIO1D3_IE_SHIFT (6U)
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#define GRF_GPIO1D_IE_GPIO1D3_IE_MASK (0x3U << GRF_GPIO1D_IE_GPIO1D3_IE_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO1D_IE_GPIO1D4_IE_SHIFT (8U)
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#define GRF_GPIO1D_IE_GPIO1D4_IE_MASK (0x3U << GRF_GPIO1D_IE_GPIO1D4_IE_SHIFT) /* 0x00000300 */
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#define GRF_GPIO1D_IE_GPIO1D5_IE_SHIFT (10U)
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#define GRF_GPIO1D_IE_GPIO1D5_IE_MASK (0x3U << GRF_GPIO1D_IE_GPIO1D5_IE_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO1D_IE_GPIO1D6_IE_SHIFT (12U)
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#define GRF_GPIO1D_IE_GPIO1D6_IE_MASK (0x3U << GRF_GPIO1D_IE_GPIO1D6_IE_SHIFT) /* 0x00003000 */
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#define GRF_GPIO1D_IE_GPIO1D7_IE_SHIFT (14U)
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#define GRF_GPIO1D_IE_GPIO1D7_IE_MASK (0x3U << GRF_GPIO1D_IE_GPIO1D7_IE_SHIFT) /* 0x0000C000 */
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/* GPIO2A_IE */
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#define GRF_GPIO2A_IE_OFFSET (0x400D0U)
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#define GRF_GPIO2A_IE_GPIO2A0_IE_SHIFT (0U)
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#define GRF_GPIO2A_IE_GPIO2A0_IE_MASK (0x3U << GRF_GPIO2A_IE_GPIO2A0_IE_SHIFT) /* 0x00000003 */
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#define GRF_GPIO2A_IE_GPIO2A1_IE_SHIFT (2U)
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#define GRF_GPIO2A_IE_GPIO2A1_IE_MASK (0x3U << GRF_GPIO2A_IE_GPIO2A1_IE_SHIFT) /* 0x0000000C */
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#define GRF_GPIO2A_IE_GPIO2A2_IE_SHIFT (4U)
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#define GRF_GPIO2A_IE_GPIO2A2_IE_MASK (0x3U << GRF_GPIO2A_IE_GPIO2A2_IE_SHIFT) /* 0x00000030 */
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#define GRF_GPIO2A_IE_GPIO2A3_IE_SHIFT (6U)
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#define GRF_GPIO2A_IE_GPIO2A3_IE_MASK (0x3U << GRF_GPIO2A_IE_GPIO2A3_IE_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO2A_IE_GPIO2A4_IE_SHIFT (8U)
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#define GRF_GPIO2A_IE_GPIO2A4_IE_MASK (0x3U << GRF_GPIO2A_IE_GPIO2A4_IE_SHIFT) /* 0x00000300 */
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#define GRF_GPIO2A_IE_GPIO2A5_IE_SHIFT (10U)
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#define GRF_GPIO2A_IE_GPIO2A5_IE_MASK (0x3U << GRF_GPIO2A_IE_GPIO2A5_IE_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO2A_IE_GPIO2A6_IE_SHIFT (12U)
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#define GRF_GPIO2A_IE_GPIO2A6_IE_MASK (0x3U << GRF_GPIO2A_IE_GPIO2A6_IE_SHIFT) /* 0x00003000 */
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#define GRF_GPIO2A_IE_GPIO2A7_IE_SHIFT (14U)
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#define GRF_GPIO2A_IE_GPIO2A7_IE_MASK (0x3U << GRF_GPIO2A_IE_GPIO2A7_IE_SHIFT) /* 0x0000C000 */
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/* GPIO2B_IE */
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#define GRF_GPIO2B_IE_OFFSET (0x400D4U)
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#define GRF_GPIO2B_IE_GPIO2B0_IE_SHIFT (0U)
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#define GRF_GPIO2B_IE_GPIO2B0_IE_MASK (0x3U << GRF_GPIO2B_IE_GPIO2B0_IE_SHIFT) /* 0x00000003 */
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#define GRF_GPIO2B_IE_GPIO2B1_IE_SHIFT (2U)
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#define GRF_GPIO2B_IE_GPIO2B1_IE_MASK (0x3U << GRF_GPIO2B_IE_GPIO2B1_IE_SHIFT) /* 0x0000000C */
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#define GRF_GPIO2B_IE_GPIO2B2_IE_SHIFT (4U)
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#define GRF_GPIO2B_IE_GPIO2B2_IE_MASK (0x3U << GRF_GPIO2B_IE_GPIO2B2_IE_SHIFT) /* 0x00000030 */
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#define GRF_GPIO2B_IE_GPIO2B3_IE_SHIFT (6U)
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#define GRF_GPIO2B_IE_GPIO2B3_IE_MASK (0x3U << GRF_GPIO2B_IE_GPIO2B3_IE_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO2B_IE_GPIO2B4_IE_SHIFT (8U)
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#define GRF_GPIO2B_IE_GPIO2B4_IE_MASK (0x3U << GRF_GPIO2B_IE_GPIO2B4_IE_SHIFT) /* 0x00000300 */
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#define GRF_GPIO2B_IE_GPIO2B5_IE_SHIFT (10U)
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#define GRF_GPIO2B_IE_GPIO2B5_IE_MASK (0x3U << GRF_GPIO2B_IE_GPIO2B5_IE_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO2B_IE_GPIO2B6_IE_SHIFT (12U)
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#define GRF_GPIO2B_IE_GPIO2B6_IE_MASK (0x3U << GRF_GPIO2B_IE_GPIO2B6_IE_SHIFT) /* 0x00003000 */
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#define GRF_GPIO2B_IE_GPIO2B7_IE_SHIFT (14U)
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#define GRF_GPIO2B_IE_GPIO2B7_IE_MASK (0x3U << GRF_GPIO2B_IE_GPIO2B7_IE_SHIFT) /* 0x0000C000 */
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/* GPIO2C_IE */
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#define GRF_GPIO2C_IE_OFFSET (0x400D8U)
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#define GRF_GPIO2C_IE_GPIO2C0_IE_SHIFT (0U)
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#define GRF_GPIO2C_IE_GPIO2C0_IE_MASK (0x3U << GRF_GPIO2C_IE_GPIO2C0_IE_SHIFT) /* 0x00000003 */
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#define GRF_GPIO2C_IE_GPIO2C1_IE_SHIFT (2U)
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#define GRF_GPIO2C_IE_GPIO2C1_IE_MASK (0x3U << GRF_GPIO2C_IE_GPIO2C1_IE_SHIFT) /* 0x0000000C */
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#define GRF_GPIO2C_IE_GPIO2C2_IE_SHIFT (4U)
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#define GRF_GPIO2C_IE_GPIO2C2_IE_MASK (0x3U << GRF_GPIO2C_IE_GPIO2C2_IE_SHIFT) /* 0x00000030 */
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#define GRF_GPIO2C_IE_GPIO2C3_IE_SHIFT (6U)
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#define GRF_GPIO2C_IE_GPIO2C3_IE_MASK (0x3U << GRF_GPIO2C_IE_GPIO2C3_IE_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO2C_IE_GPIO2C4_IE_SHIFT (8U)
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#define GRF_GPIO2C_IE_GPIO2C4_IE_MASK (0x3U << GRF_GPIO2C_IE_GPIO2C4_IE_SHIFT) /* 0x00000300 */
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#define GRF_GPIO2C_IE_GPIO2C5_IE_SHIFT (10U)
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#define GRF_GPIO2C_IE_GPIO2C5_IE_MASK (0x3U << GRF_GPIO2C_IE_GPIO2C5_IE_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO2C_IE_GPIO2C6_IE_SHIFT (12U)
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#define GRF_GPIO2C_IE_GPIO2C6_IE_MASK (0x3U << GRF_GPIO2C_IE_GPIO2C6_IE_SHIFT) /* 0x00003000 */
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#define GRF_GPIO2C_IE_GPIO2C7_IE_SHIFT (14U)
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#define GRF_GPIO2C_IE_GPIO2C7_IE_MASK (0x3U << GRF_GPIO2C_IE_GPIO2C7_IE_SHIFT) /* 0x0000C000 */
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/* GPIO2D_IE */
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#define GRF_GPIO2D_IE_OFFSET (0x400DCU)
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#define GRF_GPIO2D_IE_GPIO2D0_IE_SHIFT (0U)
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#define GRF_GPIO2D_IE_GPIO2D0_IE_MASK (0x3U << GRF_GPIO2D_IE_GPIO2D0_IE_SHIFT) /* 0x00000003 */
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#define GRF_GPIO2D_IE_GPIO2D1_IE_SHIFT (2U)
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#define GRF_GPIO2D_IE_GPIO2D1_IE_MASK (0x3U << GRF_GPIO2D_IE_GPIO2D1_IE_SHIFT) /* 0x0000000C */
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#define GRF_GPIO2D_IE_GPIO2D2_IE_SHIFT (4U)
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#define GRF_GPIO2D_IE_GPIO2D2_IE_MASK (0x3U << GRF_GPIO2D_IE_GPIO2D2_IE_SHIFT) /* 0x00000030 */
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#define GRF_GPIO2D_IE_GPIO2D3_IE_SHIFT (6U)
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#define GRF_GPIO2D_IE_GPIO2D3_IE_MASK (0x3U << GRF_GPIO2D_IE_GPIO2D3_IE_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO2D_IE_GPIO2D4_IE_SHIFT (8U)
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#define GRF_GPIO2D_IE_GPIO2D4_IE_MASK (0x3U << GRF_GPIO2D_IE_GPIO2D4_IE_SHIFT) /* 0x00000300 */
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#define GRF_GPIO2D_IE_GPIO2A5_IE_SHIFT (10U)
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#define GRF_GPIO2D_IE_GPIO2A5_IE_MASK (0x3U << GRF_GPIO2D_IE_GPIO2A5_IE_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO2D_IE_GPIO2A6_IE_SHIFT (12U)
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#define GRF_GPIO2D_IE_GPIO2A6_IE_MASK (0x3U << GRF_GPIO2D_IE_GPIO2A6_IE_SHIFT) /* 0x00003000 */
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#define GRF_GPIO2D_IE_GPIO2D7_IE_SHIFT (14U)
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#define GRF_GPIO2D_IE_GPIO2D7_IE_MASK (0x3U << GRF_GPIO2D_IE_GPIO2D7_IE_SHIFT) /* 0x0000C000 */
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/* GPIO3A_IE */
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#define GRF_GPIO3A_IE_OFFSET (0x400E0U)
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#define GRF_GPIO3A_IE_GPIO3A0_IE_SHIFT (0U)
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#define GRF_GPIO3A_IE_GPIO3A0_IE_MASK (0x3U << GRF_GPIO3A_IE_GPIO3A0_IE_SHIFT) /* 0x00000003 */
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#define GRF_GPIO3A_IE_GPIO3A1_IE_SHIFT (2U)
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#define GRF_GPIO3A_IE_GPIO3A1_IE_MASK (0x3U << GRF_GPIO3A_IE_GPIO3A1_IE_SHIFT) /* 0x0000000C */
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#define GRF_GPIO3A_IE_GPIO3A2_IE_SHIFT (4U)
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#define GRF_GPIO3A_IE_GPIO3A2_IE_MASK (0x3U << GRF_GPIO3A_IE_GPIO3A2_IE_SHIFT) /* 0x00000030 */
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#define GRF_GPIO3A_IE_GPIO3A3_IE_SHIFT (6U)
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#define GRF_GPIO3A_IE_GPIO3A3_IE_MASK (0x3U << GRF_GPIO3A_IE_GPIO3A3_IE_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO3A_IE_GPIO3A4_IE_SHIFT (8U)
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#define GRF_GPIO3A_IE_GPIO3A4_IE_MASK (0x3U << GRF_GPIO3A_IE_GPIO3A4_IE_SHIFT) /* 0x00000300 */
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#define GRF_GPIO3A_IE_GPIO3A5_IE_SHIFT (10U)
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#define GRF_GPIO3A_IE_GPIO3A5_IE_MASK (0x3U << GRF_GPIO3A_IE_GPIO3A5_IE_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO3A_IE_GPIO3A6_IE_SHIFT (12U)
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#define GRF_GPIO3A_IE_GPIO3A6_IE_MASK (0x3U << GRF_GPIO3A_IE_GPIO3A6_IE_SHIFT) /* 0x00003000 */
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#define GRF_GPIO3A_IE_GPIO3A7_IE_SHIFT (14U)
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#define GRF_GPIO3A_IE_GPIO3A7_IE_MASK (0x3U << GRF_GPIO3A_IE_GPIO3A7_IE_SHIFT) /* 0x0000C000 */
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/* GPIO3B_IE */
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#define GRF_GPIO3B_IE_OFFSET (0x400E4U)
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#define GRF_GPIO3B_IE_GPIO3B0_IE_SHIFT (0U)
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#define GRF_GPIO3B_IE_GPIO3B0_IE_MASK (0x3U << GRF_GPIO3B_IE_GPIO3B0_IE_SHIFT) /* 0x00000003 */
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#define GRF_GPIO3B_IE_GPIO3B1_IE_SHIFT (2U)
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#define GRF_GPIO3B_IE_GPIO3B1_IE_MASK (0x3U << GRF_GPIO3B_IE_GPIO3B1_IE_SHIFT) /* 0x0000000C */
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#define GRF_GPIO3B_IE_GPIO3B2_IE_SHIFT (4U)
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#define GRF_GPIO3B_IE_GPIO3B2_IE_MASK (0x3U << GRF_GPIO3B_IE_GPIO3B2_IE_SHIFT) /* 0x00000030 */
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#define GRF_GPIO3B_IE_GPIO3B3_IE_SHIFT (6U)
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#define GRF_GPIO3B_IE_GPIO3B3_IE_MASK (0x3U << GRF_GPIO3B_IE_GPIO3B3_IE_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO3B_IE_GPIO3B4_IE_SHIFT (8U)
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#define GRF_GPIO3B_IE_GPIO3B4_IE_MASK (0x3U << GRF_GPIO3B_IE_GPIO3B4_IE_SHIFT) /* 0x00000300 */
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#define GRF_GPIO3B_IE_GPIO3B5_IE_SHIFT (10U)
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#define GRF_GPIO3B_IE_GPIO3B5_IE_MASK (0x3U << GRF_GPIO3B_IE_GPIO3B5_IE_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO3B_IE_GPIO3B6_IE_SHIFT (12U)
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#define GRF_GPIO3B_IE_GPIO3B6_IE_MASK (0x3U << GRF_GPIO3B_IE_GPIO3B6_IE_SHIFT) /* 0x00003000 */
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#define GRF_GPIO3B_IE_GPIO3B7_IE_SHIFT (14U)
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#define GRF_GPIO3B_IE_GPIO3B7_IE_MASK (0x3U << GRF_GPIO3B_IE_GPIO3B7_IE_SHIFT) /* 0x0000C000 */
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/* GPIO3C_IE */
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#define GRF_GPIO3C_IE_OFFSET (0x400E8U)
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#define GRF_GPIO3C_IE_GPIO3C0_IE_SHIFT (0U)
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#define GRF_GPIO3C_IE_GPIO3C0_IE_MASK (0x3U << GRF_GPIO3C_IE_GPIO3C0_IE_SHIFT) /* 0x00000003 */
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#define GRF_GPIO3C_IE_GPIO3C1_IE_SHIFT (2U)
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#define GRF_GPIO3C_IE_GPIO3C1_IE_MASK (0x3U << GRF_GPIO3C_IE_GPIO3C1_IE_SHIFT) /* 0x0000000C */
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#define GRF_GPIO3C_IE_GPIO3C2_IE_SHIFT (4U)
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#define GRF_GPIO3C_IE_GPIO3C2_IE_MASK (0x3U << GRF_GPIO3C_IE_GPIO3C2_IE_SHIFT) /* 0x00000030 */
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#define GRF_GPIO3C_IE_GPIO3C3_IE_SHIFT (6U)
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#define GRF_GPIO3C_IE_GPIO3C3_IE_MASK (0x3U << GRF_GPIO3C_IE_GPIO3C3_IE_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO3C_IE_GPIO3C4_IE_SHIFT (8U)
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#define GRF_GPIO3C_IE_GPIO3C4_IE_MASK (0x3U << GRF_GPIO3C_IE_GPIO3C4_IE_SHIFT) /* 0x00000300 */
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#define GRF_GPIO3C_IE_GPIO3C5_IE_SHIFT (10U)
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#define GRF_GPIO3C_IE_GPIO3C5_IE_MASK (0x3U << GRF_GPIO3C_IE_GPIO3C5_IE_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO3C_IE_GPIO3C6_IE_SHIFT (12U)
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#define GRF_GPIO3C_IE_GPIO3C6_IE_MASK (0x3U << GRF_GPIO3C_IE_GPIO3C6_IE_SHIFT) /* 0x00003000 */
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#define GRF_GPIO3C_IE_GPIO3C7_IE_SHIFT (14U)
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#define GRF_GPIO3C_IE_GPIO3C7_IE_MASK (0x3U << GRF_GPIO3C_IE_GPIO3C7_IE_SHIFT) /* 0x0000C000 */
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/* GPIO3D_IE */
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#define GRF_GPIO3D_IE_OFFSET (0x400ECU)
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#define GRF_GPIO3D_IE_GPIO3D0_IE_SHIFT (0U)
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#define GRF_GPIO3D_IE_GPIO3D0_IE_MASK (0x3U << GRF_GPIO3D_IE_GPIO3D0_IE_SHIFT) /* 0x00000003 */
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#define GRF_GPIO3D_IE_GPIO3D1_IE_SHIFT (2U)
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#define GRF_GPIO3D_IE_GPIO3D1_IE_MASK (0x3U << GRF_GPIO3D_IE_GPIO3D1_IE_SHIFT) /* 0x0000000C */
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#define GRF_GPIO3D_IE_GPIO3D2_IE_SHIFT (4U)
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#define GRF_GPIO3D_IE_GPIO3D2_IE_MASK (0x3U << GRF_GPIO3D_IE_GPIO3D2_IE_SHIFT) /* 0x00000030 */
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#define GRF_GPIO3D_IE_GPIO3D3_IE_SHIFT (6U)
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#define GRF_GPIO3D_IE_GPIO3D3_IE_MASK (0x3U << GRF_GPIO3D_IE_GPIO3D3_IE_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO3D_IE_GPIO3D4_IE_SHIFT (8U)
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#define GRF_GPIO3D_IE_GPIO3D4_IE_MASK (0x3U << GRF_GPIO3D_IE_GPIO3D4_IE_SHIFT) /* 0x00000300 */
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#define GRF_GPIO3D_IE_GPIO3D5_IE_SHIFT (10U)
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#define GRF_GPIO3D_IE_GPIO3D5_IE_MASK (0x3U << GRF_GPIO3D_IE_GPIO3D5_IE_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO3D_IE_GPIO3D6_IE_SHIFT (12U)
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#define GRF_GPIO3D_IE_GPIO3D6_IE_MASK (0x3U << GRF_GPIO3D_IE_GPIO3D6_IE_SHIFT) /* 0x00003000 */
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#define GRF_GPIO3D_IE_GPIO3D7_IE_SHIFT (14U)
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#define GRF_GPIO3D_IE_GPIO3D7_IE_MASK (0x3U << GRF_GPIO3D_IE_GPIO3D7_IE_SHIFT) /* 0x0000C000 */
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/* GPIO4A_IE */
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#define GRF_GPIO4A_IE_OFFSET (0x400F0U)
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#define GRF_GPIO4A_IE_GPIO4A0_IE_SHIFT (0U)
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#define GRF_GPIO4A_IE_GPIO4A0_IE_MASK (0x3U << GRF_GPIO4A_IE_GPIO4A0_IE_SHIFT) /* 0x00000003 */
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#define GRF_GPIO4A_IE_GPIO4A1_IE_SHIFT (2U)
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#define GRF_GPIO4A_IE_GPIO4A1_IE_MASK (0x3U << GRF_GPIO4A_IE_GPIO4A1_IE_SHIFT) /* 0x0000000C */
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#define GRF_GPIO4A_IE_GPIO4A2_IE_SHIFT (4U)
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#define GRF_GPIO4A_IE_GPIO4A2_IE_MASK (0x3U << GRF_GPIO4A_IE_GPIO4A2_IE_SHIFT) /* 0x00000030 */
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#define GRF_GPIO4A_IE_GPIO4A3_IE_SHIFT (6U)
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#define GRF_GPIO4A_IE_GPIO4A3_IE_MASK (0x3U << GRF_GPIO4A_IE_GPIO4A3_IE_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO4A_IE_GPIO4A4_IE_SHIFT (8U)
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#define GRF_GPIO4A_IE_GPIO4A4_IE_MASK (0x3U << GRF_GPIO4A_IE_GPIO4A4_IE_SHIFT) /* 0x00000300 */
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#define GRF_GPIO4A_IE_GPIO4A5_IE_SHIFT (10U)
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#define GRF_GPIO4A_IE_GPIO4A5_IE_MASK (0x3U << GRF_GPIO4A_IE_GPIO4A5_IE_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO4A_IE_GPIO4A6_IE_SHIFT (12U)
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#define GRF_GPIO4A_IE_GPIO4A6_IE_MASK (0x3U << GRF_GPIO4A_IE_GPIO4A6_IE_SHIFT) /* 0x00003000 */
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#define GRF_GPIO4A_IE_GPIO4A7_IE_SHIFT (14U)
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#define GRF_GPIO4A_IE_GPIO4A7_IE_MASK (0x3U << GRF_GPIO4A_IE_GPIO4A7_IE_SHIFT) /* 0x0000C000 */
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/* GPIO4B_IE */
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#define GRF_GPIO4B_IE_OFFSET (0x400F4U)
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#define GRF_GPIO4B_IE_GPIO4B0_IE_SHIFT (0U)
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#define GRF_GPIO4B_IE_GPIO4B0_IE_MASK (0x3U << GRF_GPIO4B_IE_GPIO4B0_IE_SHIFT) /* 0x00000003 */
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#define GRF_GPIO4B_IE_GPIO4B1_IE_SHIFT (2U)
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#define GRF_GPIO4B_IE_GPIO4B1_IE_MASK (0x3U << GRF_GPIO4B_IE_GPIO4B1_IE_SHIFT) /* 0x0000000C */
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#define GRF_GPIO4B_IE_GPIO4B2_IE_SHIFT (4U)
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#define GRF_GPIO4B_IE_GPIO4B2_IE_MASK (0x3U << GRF_GPIO4B_IE_GPIO4B2_IE_SHIFT) /* 0x00000030 */
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#define GRF_GPIO4B_IE_GPIO4B3_IE_SHIFT (6U)
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#define GRF_GPIO4B_IE_GPIO4B3_IE_MASK (0x3U << GRF_GPIO4B_IE_GPIO4B3_IE_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO4B_IE_GPIO4B4_IE_SHIFT (8U)
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#define GRF_GPIO4B_IE_GPIO4B4_IE_MASK (0x3U << GRF_GPIO4B_IE_GPIO4B4_IE_SHIFT) /* 0x00000300 */
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#define GRF_GPIO4B_IE_GPIO4B5_IE_SHIFT (10U)
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#define GRF_GPIO4B_IE_GPIO4B5_IE_MASK (0x3U << GRF_GPIO4B_IE_GPIO4B5_IE_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO4B_IE_GPIO4B6_IE_SHIFT (12U)
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#define GRF_GPIO4B_IE_GPIO4B6_IE_MASK (0x3U << GRF_GPIO4B_IE_GPIO4B6_IE_SHIFT) /* 0x00003000 */
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#define GRF_GPIO4B_IE_GPIO4B7_IE_SHIFT (14U)
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#define GRF_GPIO4B_IE_GPIO4B7_IE_MASK (0x3U << GRF_GPIO4B_IE_GPIO4B7_IE_SHIFT) /* 0x0000C000 */
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/* GPIO4C_IE */
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#define GRF_GPIO4C_IE_OFFSET (0x400F8U)
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#define GRF_GPIO4C_IE_GPIO4C0_IE_SHIFT (0U)
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#define GRF_GPIO4C_IE_GPIO4C0_IE_MASK (0x3U << GRF_GPIO4C_IE_GPIO4C0_IE_SHIFT) /* 0x00000003 */
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#define GRF_GPIO4C_IE_GPIO4C1_IE_SHIFT (2U)
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#define GRF_GPIO4C_IE_GPIO4C1_IE_MASK (0x3U << GRF_GPIO4C_IE_GPIO4C1_IE_SHIFT) /* 0x0000000C */
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#define GRF_GPIO4C_IE_GPIO4C2_IE_SHIFT (4U)
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#define GRF_GPIO4C_IE_GPIO4C2_IE_MASK (0x3U << GRF_GPIO4C_IE_GPIO4C2_IE_SHIFT) /* 0x00000030 */
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#define GRF_GPIO4C_IE_GPIO4C3_IE_SHIFT (6U)
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#define GRF_GPIO4C_IE_GPIO4C3_IE_MASK (0x3U << GRF_GPIO4C_IE_GPIO4C3_IE_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO4C_IE_GPIO4C4_IE_SHIFT (8U)
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#define GRF_GPIO4C_IE_GPIO4C4_IE_MASK (0x3U << GRF_GPIO4C_IE_GPIO4C4_IE_SHIFT) /* 0x00000300 */
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#define GRF_GPIO4C_IE_GPIO4C5_IE_SHIFT (10U)
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#define GRF_GPIO4C_IE_GPIO4C5_IE_MASK (0x3U << GRF_GPIO4C_IE_GPIO4C5_IE_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO4C_IE_GPIO4C6_IE_SHIFT (12U)
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#define GRF_GPIO4C_IE_GPIO4C6_IE_MASK (0x3U << GRF_GPIO4C_IE_GPIO4C6_IE_SHIFT) /* 0x00003000 */
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#define GRF_GPIO4C_IE_GPIO4C7_IE_SHIFT (14U)
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#define GRF_GPIO4C_IE_GPIO4C7_IE_MASK (0x3U << GRF_GPIO4C_IE_GPIO4C7_IE_SHIFT) /* 0x0000C000 */
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/* GPIO4D_IE */
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#define GRF_GPIO4D_IE_OFFSET (0x400FCU)
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#define GRF_GPIO4D_IE_GPIO4D0_IE_SHIFT (0U)
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#define GRF_GPIO4D_IE_GPIO4D0_IE_MASK (0x3U << GRF_GPIO4D_IE_GPIO4D0_IE_SHIFT) /* 0x00000003 */
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#define GRF_GPIO4D_IE_GPIO4D1_IE_SHIFT (2U)
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#define GRF_GPIO4D_IE_GPIO4D1_IE_MASK (0x3U << GRF_GPIO4D_IE_GPIO4D1_IE_SHIFT) /* 0x0000000C */
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#define GRF_GPIO4D_IE_GPIO4D2_IE_SHIFT (4U)
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#define GRF_GPIO4D_IE_GPIO4D2_IE_MASK (0x3U << GRF_GPIO4D_IE_GPIO4D2_IE_SHIFT) /* 0x00000030 */
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#define GRF_GPIO4D_IE_GPIO4D3_IE_SHIFT (6U)
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#define GRF_GPIO4D_IE_GPIO4D3_IE_MASK (0x3U << GRF_GPIO4D_IE_GPIO4D3_IE_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO4D_IE_GPIO4D4_IE_SHIFT (8U)
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#define GRF_GPIO4D_IE_GPIO4D4_IE_MASK (0x3U << GRF_GPIO4D_IE_GPIO4D4_IE_SHIFT) /* 0x00000300 */
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#define GRF_GPIO4D_IE_GPIO4D5_IE_SHIFT (10U)
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#define GRF_GPIO4D_IE_GPIO4D5_IE_MASK (0x3U << GRF_GPIO4D_IE_GPIO4D5_IE_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO4D_IE_GPIO4D6_IE_SHIFT (12U)
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#define GRF_GPIO4D_IE_GPIO4D6_IE_MASK (0x3U << GRF_GPIO4D_IE_GPIO4D6_IE_SHIFT) /* 0x00003000 */
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#define GRF_GPIO4D_IE_GPIO4D7_IE_SHIFT (14U)
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#define GRF_GPIO4D_IE_GPIO4D7_IE_MASK (0x3U << GRF_GPIO4D_IE_GPIO4D7_IE_SHIFT) /* 0x0000C000 */
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/* GPIO1A_OPD */
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#define GRF_GPIO1A_OPD_OFFSET (0x40100U)
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#define GRF_GPIO1A_OPD_GPIO1A0_OPD_SHIFT (0U)
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#define GRF_GPIO1A_OPD_GPIO1A0_OPD_MASK (0x1U << GRF_GPIO1A_OPD_GPIO1A0_OPD_SHIFT) /* 0x00000001 */
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#define GRF_GPIO1A_OPD_GPIO1A1_OPD_SHIFT (1U)
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#define GRF_GPIO1A_OPD_GPIO1A1_OPD_MASK (0x1U << GRF_GPIO1A_OPD_GPIO1A1_OPD_SHIFT) /* 0x00000002 */
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#define GRF_GPIO1A_OPD_GPIO1A2_OPD_SHIFT (2U)
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#define GRF_GPIO1A_OPD_GPIO1A2_OPD_MASK (0x1U << GRF_GPIO1A_OPD_GPIO1A2_OPD_SHIFT) /* 0x00000004 */
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#define GRF_GPIO1A_OPD_GPIO1A3_OPD_SHIFT (3U)
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#define GRF_GPIO1A_OPD_GPIO1A3_OPD_MASK (0x1U << GRF_GPIO1A_OPD_GPIO1A3_OPD_SHIFT) /* 0x00000008 */
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#define GRF_GPIO1A_OPD_GPIO1A4_OPD_SHIFT (4U)
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#define GRF_GPIO1A_OPD_GPIO1A4_OPD_MASK (0x1U << GRF_GPIO1A_OPD_GPIO1A4_OPD_SHIFT) /* 0x00000010 */
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#define GRF_GPIO1A_OPD_GPIO1A5_OPD_SHIFT (5U)
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#define GRF_GPIO1A_OPD_GPIO1A5_OPD_MASK (0x1U << GRF_GPIO1A_OPD_GPIO1A5_OPD_SHIFT) /* 0x00000020 */
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#define GRF_GPIO1A_OPD_GPIO1A6_OPD_SHIFT (6U)
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#define GRF_GPIO1A_OPD_GPIO1A6_OPD_MASK (0x1U << GRF_GPIO1A_OPD_GPIO1A6_OPD_SHIFT) /* 0x00000040 */
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#define GRF_GPIO1A_OPD_GPIO1A7_OPD_SHIFT (7U)
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#define GRF_GPIO1A_OPD_GPIO1A7_OPD_MASK (0x1U << GRF_GPIO1A_OPD_GPIO1A7_OPD_SHIFT) /* 0x00000080 */
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/* GPIO1B_OPD */
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#define GRF_GPIO1B_OPD_OFFSET (0x40104U)
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#define GRF_GPIO1B_OPD_GPIO1B0_OPD_SHIFT (0U)
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#define GRF_GPIO1B_OPD_GPIO1B0_OPD_MASK (0x1U << GRF_GPIO1B_OPD_GPIO1B0_OPD_SHIFT) /* 0x00000001 */
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#define GRF_GPIO1B_OPD_GPIO1B1_OPD_SHIFT (1U)
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#define GRF_GPIO1B_OPD_GPIO1B1_OPD_MASK (0x1U << GRF_GPIO1B_OPD_GPIO1B1_OPD_SHIFT) /* 0x00000002 */
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#define GRF_GPIO1B_OPD_GPIO1B2_OPD_SHIFT (2U)
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#define GRF_GPIO1B_OPD_GPIO1B2_OPD_MASK (0x1U << GRF_GPIO1B_OPD_GPIO1B2_OPD_SHIFT) /* 0x00000004 */
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#define GRF_GPIO1B_OPD_GPIO1B3_OPD_SHIFT (3U)
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#define GRF_GPIO1B_OPD_GPIO1B3_OPD_MASK (0x1U << GRF_GPIO1B_OPD_GPIO1B3_OPD_SHIFT) /* 0x00000008 */
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#define GRF_GPIO1B_OPD_GPIO1B4_OPD_SHIFT (4U)
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#define GRF_GPIO1B_OPD_GPIO1B4_OPD_MASK (0x1U << GRF_GPIO1B_OPD_GPIO1B4_OPD_SHIFT) /* 0x00000010 */
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#define GRF_GPIO1B_OPD_GPIO1B5_OPD_SHIFT (5U)
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#define GRF_GPIO1B_OPD_GPIO1B5_OPD_MASK (0x1U << GRF_GPIO1B_OPD_GPIO1B5_OPD_SHIFT) /* 0x00000020 */
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#define GRF_GPIO1B_OPD_GPIO1B6_OPD_SHIFT (6U)
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#define GRF_GPIO1B_OPD_GPIO1B6_OPD_MASK (0x1U << GRF_GPIO1B_OPD_GPIO1B6_OPD_SHIFT) /* 0x00000040 */
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#define GRF_GPIO1B_OPD_GPIO1B7_OPD_SHIFT (7U)
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#define GRF_GPIO1B_OPD_GPIO1B7_OPD_MASK (0x1U << GRF_GPIO1B_OPD_GPIO1B7_OPD_SHIFT) /* 0x00000080 */
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/* GPIO1C_OPD */
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#define GRF_GPIO1C_OPD_OFFSET (0x40108U)
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#define GRF_GPIO1C_OPD_GPIO1C0_OPD_SHIFT (0U)
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#define GRF_GPIO1C_OPD_GPIO1C0_OPD_MASK (0x1U << GRF_GPIO1C_OPD_GPIO1C0_OPD_SHIFT) /* 0x00000001 */
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#define GRF_GPIO1C_OPD_GPIO1C1_OPD_SHIFT (1U)
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#define GRF_GPIO1C_OPD_GPIO1C1_OPD_MASK (0x1U << GRF_GPIO1C_OPD_GPIO1C1_OPD_SHIFT) /* 0x00000002 */
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#define GRF_GPIO1C_OPD_GPIO1C2_OPD_SHIFT (2U)
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#define GRF_GPIO1C_OPD_GPIO1C2_OPD_MASK (0x1U << GRF_GPIO1C_OPD_GPIO1C2_OPD_SHIFT) /* 0x00000004 */
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#define GRF_GPIO1C_OPD_GPIO1C3_OPD_SHIFT (3U)
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#define GRF_GPIO1C_OPD_GPIO1C3_OPD_MASK (0x1U << GRF_GPIO1C_OPD_GPIO1C3_OPD_SHIFT) /* 0x00000008 */
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#define GRF_GPIO1C_OPD_GPIO1C4_OPD_SHIFT (4U)
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#define GRF_GPIO1C_OPD_GPIO1C4_OPD_MASK (0x1U << GRF_GPIO1C_OPD_GPIO1C4_OPD_SHIFT) /* 0x00000010 */
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#define GRF_GPIO1C_OPD_GPIO1C5_OPD_SHIFT (5U)
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#define GRF_GPIO1C_OPD_GPIO1C5_OPD_MASK (0x1U << GRF_GPIO1C_OPD_GPIO1C5_OPD_SHIFT) /* 0x00000020 */
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#define GRF_GPIO1C_OPD_GPIO1C6_OPD_SHIFT (6U)
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#define GRF_GPIO1C_OPD_GPIO1C6_OPD_MASK (0x1U << GRF_GPIO1C_OPD_GPIO1C6_OPD_SHIFT) /* 0x00000040 */
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#define GRF_GPIO1C_OPD_GPIO1C7_OPD_SHIFT (7U)
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#define GRF_GPIO1C_OPD_GPIO1C7_OPD_MASK (0x1U << GRF_GPIO1C_OPD_GPIO1C7_OPD_SHIFT) /* 0x00000080 */
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/* GPIO1D_OPD */
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#define GRF_GPIO1D_OPD_OFFSET (0x4010CU)
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#define GRF_GPIO1D_OPD_GPIO1D0_OPD_SHIFT (0U)
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#define GRF_GPIO1D_OPD_GPIO1D0_OPD_MASK (0x1U << GRF_GPIO1D_OPD_GPIO1D0_OPD_SHIFT) /* 0x00000001 */
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#define GRF_GPIO1D_OPD_GPIO1D1_OPD_SHIFT (1U)
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#define GRF_GPIO1D_OPD_GPIO1D1_OPD_MASK (0x1U << GRF_GPIO1D_OPD_GPIO1D1_OPD_SHIFT) /* 0x00000002 */
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#define GRF_GPIO1D_OPD_GPIO1D2_OPD_SHIFT (2U)
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#define GRF_GPIO1D_OPD_GPIO1D2_OPD_MASK (0x1U << GRF_GPIO1D_OPD_GPIO1D2_OPD_SHIFT) /* 0x00000004 */
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#define GRF_GPIO1D_OPD_GPIO1D3_OPD_SHIFT (3U)
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#define GRF_GPIO1D_OPD_GPIO1D3_OPD_MASK (0x1U << GRF_GPIO1D_OPD_GPIO1D3_OPD_SHIFT) /* 0x00000008 */
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#define GRF_GPIO1D_OPD_GPIO1D4_OPD_SHIFT (4U)
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#define GRF_GPIO1D_OPD_GPIO1D4_OPD_MASK (0x1U << GRF_GPIO1D_OPD_GPIO1D4_OPD_SHIFT) /* 0x00000010 */
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#define GRF_GPIO1D_OPD_GPIO1D5_OPD_SHIFT (5U)
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#define GRF_GPIO1D_OPD_GPIO1D5_OPD_MASK (0x1U << GRF_GPIO1D_OPD_GPIO1D5_OPD_SHIFT) /* 0x00000020 */
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#define GRF_GPIO1D_OPD_GPIO1D6_OPD_SHIFT (6U)
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#define GRF_GPIO1D_OPD_GPIO1D6_OPD_MASK (0x1U << GRF_GPIO1D_OPD_GPIO1D6_OPD_SHIFT) /* 0x00000040 */
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#define GRF_GPIO1D_OPD_GPIO1D7_OPD_SHIFT (7U)
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#define GRF_GPIO1D_OPD_GPIO1D7_OPD_MASK (0x1U << GRF_GPIO1D_OPD_GPIO1D7_OPD_SHIFT) /* 0x00000080 */
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/* GPIO2A_OPD */
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#define GRF_GPIO2A_OPD_OFFSET (0x40110U)
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#define GRF_GPIO2A_OPD_GPIO2A0_OPD_SHIFT (0U)
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#define GRF_GPIO2A_OPD_GPIO2A0_OPD_MASK (0x1U << GRF_GPIO2A_OPD_GPIO2A0_OPD_SHIFT) /* 0x00000001 */
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#define GRF_GPIO2A_OPD_GPIO2A1_OPD_SHIFT (1U)
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#define GRF_GPIO2A_OPD_GPIO2A1_OPD_MASK (0x1U << GRF_GPIO2A_OPD_GPIO2A1_OPD_SHIFT) /* 0x00000002 */
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#define GRF_GPIO2A_OPD_GPIO2A2_OPD_SHIFT (2U)
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#define GRF_GPIO2A_OPD_GPIO2A2_OPD_MASK (0x1U << GRF_GPIO2A_OPD_GPIO2A2_OPD_SHIFT) /* 0x00000004 */
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#define GRF_GPIO2A_OPD_GPIO2A3_OPD_SHIFT (3U)
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#define GRF_GPIO2A_OPD_GPIO2A3_OPD_MASK (0x1U << GRF_GPIO2A_OPD_GPIO2A3_OPD_SHIFT) /* 0x00000008 */
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#define GRF_GPIO2A_OPD_GPIO2A4_OPD_SHIFT (4U)
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#define GRF_GPIO2A_OPD_GPIO2A4_OPD_MASK (0x1U << GRF_GPIO2A_OPD_GPIO2A4_OPD_SHIFT) /* 0x00000010 */
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#define GRF_GPIO2A_OPD_GPIO2A5_OPD_SHIFT (5U)
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#define GRF_GPIO2A_OPD_GPIO2A5_OPD_MASK (0x1U << GRF_GPIO2A_OPD_GPIO2A5_OPD_SHIFT) /* 0x00000020 */
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#define GRF_GPIO2A_OPD_GPIO2A6_OPD_SHIFT (6U)
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#define GRF_GPIO2A_OPD_GPIO2A6_OPD_MASK (0x1U << GRF_GPIO2A_OPD_GPIO2A6_OPD_SHIFT) /* 0x00000040 */
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#define GRF_GPIO2A_OPD_GPIO2A7_OPD_SHIFT (7U)
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#define GRF_GPIO2A_OPD_GPIO2A7_OPD_MASK (0x1U << GRF_GPIO2A_OPD_GPIO2A7_OPD_SHIFT) /* 0x00000080 */
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/* GPIO2B_OPD */
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#define GRF_GPIO2B_OPD_OFFSET (0x40114U)
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#define GRF_GPIO2B_OPD_GPIO2B0_OPD_SHIFT (0U)
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#define GRF_GPIO2B_OPD_GPIO2B0_OPD_MASK (0x1U << GRF_GPIO2B_OPD_GPIO2B0_OPD_SHIFT) /* 0x00000001 */
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#define GRF_GPIO2B_OPD_GPIO2B1_OPD_SHIFT (1U)
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#define GRF_GPIO2B_OPD_GPIO2B1_OPD_MASK (0x1U << GRF_GPIO2B_OPD_GPIO2B1_OPD_SHIFT) /* 0x00000002 */
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#define GRF_GPIO2B_OPD_GPIO2B2_OPD_SHIFT (2U)
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#define GRF_GPIO2B_OPD_GPIO2B2_OPD_MASK (0x1U << GRF_GPIO2B_OPD_GPIO2B2_OPD_SHIFT) /* 0x00000004 */
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#define GRF_GPIO2B_OPD_GPIO2B3_OPD_SHIFT (3U)
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#define GRF_GPIO2B_OPD_GPIO2B3_OPD_MASK (0x1U << GRF_GPIO2B_OPD_GPIO2B3_OPD_SHIFT) /* 0x00000008 */
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#define GRF_GPIO2B_OPD_GPIO2B4_OPD_SHIFT (4U)
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#define GRF_GPIO2B_OPD_GPIO2B4_OPD_MASK (0x1U << GRF_GPIO2B_OPD_GPIO2B4_OPD_SHIFT) /* 0x00000010 */
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#define GRF_GPIO2B_OPD_GPIO2B5_OPD_SHIFT (5U)
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#define GRF_GPIO2B_OPD_GPIO2B5_OPD_MASK (0x1U << GRF_GPIO2B_OPD_GPIO2B5_OPD_SHIFT) /* 0x00000020 */
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#define GRF_GPIO2B_OPD_GPIO2B6_OPD_SHIFT (6U)
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#define GRF_GPIO2B_OPD_GPIO2B6_OPD_MASK (0x1U << GRF_GPIO2B_OPD_GPIO2B6_OPD_SHIFT) /* 0x00000040 */
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#define GRF_GPIO2B_OPD_GPIO2B7_OPD_SHIFT (7U)
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#define GRF_GPIO2B_OPD_GPIO2B7_OPD_MASK (0x1U << GRF_GPIO2B_OPD_GPIO2B7_OPD_SHIFT) /* 0x00000080 */
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/* GPIO2C_OPD */
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#define GRF_GPIO2C_OPD_OFFSET (0x40118U)
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#define GRF_GPIO2C_OPD_GPIO2C0_OPD_SHIFT (0U)
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#define GRF_GPIO2C_OPD_GPIO2C0_OPD_MASK (0x1U << GRF_GPIO2C_OPD_GPIO2C0_OPD_SHIFT) /* 0x00000001 */
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#define GRF_GPIO2C_OPD_GPIO2C1_OPD_SHIFT (1U)
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#define GRF_GPIO2C_OPD_GPIO2C1_OPD_MASK (0x1U << GRF_GPIO2C_OPD_GPIO2C1_OPD_SHIFT) /* 0x00000002 */
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#define GRF_GPIO2C_OPD_GPIO2C2_OPD_SHIFT (2U)
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#define GRF_GPIO2C_OPD_GPIO2C2_OPD_MASK (0x1U << GRF_GPIO2C_OPD_GPIO2C2_OPD_SHIFT) /* 0x00000004 */
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#define GRF_GPIO2C_OPD_GPIO2C3_OPD_SHIFT (3U)
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#define GRF_GPIO2C_OPD_GPIO2C3_OPD_MASK (0x1U << GRF_GPIO2C_OPD_GPIO2C3_OPD_SHIFT) /* 0x00000008 */
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#define GRF_GPIO2C_OPD_GPIO2C4_OPD_SHIFT (4U)
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#define GRF_GPIO2C_OPD_GPIO2C4_OPD_MASK (0x1U << GRF_GPIO2C_OPD_GPIO2C4_OPD_SHIFT) /* 0x00000010 */
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#define GRF_GPIO2C_OPD_GPIO2C5_OPD_SHIFT (5U)
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#define GRF_GPIO2C_OPD_GPIO2C5_OPD_MASK (0x1U << GRF_GPIO2C_OPD_GPIO2C5_OPD_SHIFT) /* 0x00000020 */
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#define GRF_GPIO2C_OPD_GPIO2C6_OPD_SHIFT (6U)
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#define GRF_GPIO2C_OPD_GPIO2C6_OPD_MASK (0x1U << GRF_GPIO2C_OPD_GPIO2C6_OPD_SHIFT) /* 0x00000040 */
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#define GRF_GPIO2C_OPD_GPIO2C7_OPD_SHIFT (7U)
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#define GRF_GPIO2C_OPD_GPIO2C7_OPD_MASK (0x1U << GRF_GPIO2C_OPD_GPIO2C7_OPD_SHIFT) /* 0x00000080 */
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/* GPIO2D_OPD */
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#define GRF_GPIO2D_OPD_OFFSET (0x4011CU)
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#define GRF_GPIO2D_OPD_GPIO2D0_OPD_SHIFT (0U)
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#define GRF_GPIO2D_OPD_GPIO2D0_OPD_MASK (0x1U << GRF_GPIO2D_OPD_GPIO2D0_OPD_SHIFT) /* 0x00000001 */
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#define GRF_GPIO2D_OPD_GPIO2D1_OPD_SHIFT (1U)
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#define GRF_GPIO2D_OPD_GPIO2D1_OPD_MASK (0x1U << GRF_GPIO2D_OPD_GPIO2D1_OPD_SHIFT) /* 0x00000002 */
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#define GRF_GPIO2D_OPD_GPIO2D2_OPD_SHIFT (2U)
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#define GRF_GPIO2D_OPD_GPIO2D2_OPD_MASK (0x1U << GRF_GPIO2D_OPD_GPIO2D2_OPD_SHIFT) /* 0x00000004 */
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#define GRF_GPIO2D_OPD_GPIO2D3_OPD_SHIFT (3U)
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#define GRF_GPIO2D_OPD_GPIO2D3_OPD_MASK (0x1U << GRF_GPIO2D_OPD_GPIO2D3_OPD_SHIFT) /* 0x00000008 */
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#define GRF_GPIO2D_OPD_GPIO2D4_OPD_SHIFT (4U)
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#define GRF_GPIO2D_OPD_GPIO2D4_OPD_MASK (0x1U << GRF_GPIO2D_OPD_GPIO2D4_OPD_SHIFT) /* 0x00000010 */
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#define GRF_GPIO2D_OPD_GPIO2D5_OPD_SHIFT (5U)
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#define GRF_GPIO2D_OPD_GPIO2D5_OPD_MASK (0x1U << GRF_GPIO2D_OPD_GPIO2D5_OPD_SHIFT) /* 0x00000020 */
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#define GRF_GPIO2D_OPD_GPIO2D6_OPD_SHIFT (6U)
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#define GRF_GPIO2D_OPD_GPIO2D6_OPD_MASK (0x1U << GRF_GPIO2D_OPD_GPIO2D6_OPD_SHIFT) /* 0x00000040 */
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#define GRF_GPIO2D_OPD_GPIO2D7_OPD_SHIFT (7U)
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#define GRF_GPIO2D_OPD_GPIO2D7_OPD_MASK (0x1U << GRF_GPIO2D_OPD_GPIO2D7_OPD_SHIFT) /* 0x00000080 */
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/* GPIO3A_OPD */
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#define GRF_GPIO3A_OPD_OFFSET (0x40120U)
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#define GRF_GPIO3A_OPD_GPIO3A0_OPD_SHIFT (0U)
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#define GRF_GPIO3A_OPD_GPIO3A0_OPD_MASK (0x1U << GRF_GPIO3A_OPD_GPIO3A0_OPD_SHIFT) /* 0x00000001 */
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#define GRF_GPIO3A_OPD_GPIO3A1_OPD_SHIFT (1U)
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#define GRF_GPIO3A_OPD_GPIO3A1_OPD_MASK (0x1U << GRF_GPIO3A_OPD_GPIO3A1_OPD_SHIFT) /* 0x00000002 */
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#define GRF_GPIO3A_OPD_GPIO3A2_OPD_SHIFT (2U)
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#define GRF_GPIO3A_OPD_GPIO3A2_OPD_MASK (0x1U << GRF_GPIO3A_OPD_GPIO3A2_OPD_SHIFT) /* 0x00000004 */
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#define GRF_GPIO3A_OPD_GPIO3A3_OPD_SHIFT (3U)
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#define GRF_GPIO3A_OPD_GPIO3A3_OPD_MASK (0x1U << GRF_GPIO3A_OPD_GPIO3A3_OPD_SHIFT) /* 0x00000008 */
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#define GRF_GPIO3A_OPD_GPIO3A4_OPD_SHIFT (4U)
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#define GRF_GPIO3A_OPD_GPIO3A4_OPD_MASK (0x1U << GRF_GPIO3A_OPD_GPIO3A4_OPD_SHIFT) /* 0x00000010 */
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#define GRF_GPIO3A_OPD_GPIO3A5_OPD_SHIFT (5U)
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#define GRF_GPIO3A_OPD_GPIO3A5_OPD_MASK (0x1U << GRF_GPIO3A_OPD_GPIO3A5_OPD_SHIFT) /* 0x00000020 */
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#define GRF_GPIO3A_OPD_GPIO3A6_OPD_SHIFT (6U)
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#define GRF_GPIO3A_OPD_GPIO3A6_OPD_MASK (0x1U << GRF_GPIO3A_OPD_GPIO3A6_OPD_SHIFT) /* 0x00000040 */
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#define GRF_GPIO3A_OPD_GPIO3A7_OPD_SHIFT (7U)
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#define GRF_GPIO3A_OPD_GPIO3A7_OPD_MASK (0x1U << GRF_GPIO3A_OPD_GPIO3A7_OPD_SHIFT) /* 0x00000080 */
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/* GPIO3B_OPD */
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#define GRF_GPIO3B_OPD_OFFSET (0x40124U)
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#define GRF_GPIO3B_OPD_GPIO3B0_OPD_SHIFT (0U)
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#define GRF_GPIO3B_OPD_GPIO3B0_OPD_MASK (0x1U << GRF_GPIO3B_OPD_GPIO3B0_OPD_SHIFT) /* 0x00000001 */
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#define GRF_GPIO3B_OPD_GPIO3B1_OPD_SHIFT (1U)
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#define GRF_GPIO3B_OPD_GPIO3B1_OPD_MASK (0x1U << GRF_GPIO3B_OPD_GPIO3B1_OPD_SHIFT) /* 0x00000002 */
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#define GRF_GPIO3B_OPD_GPIO3B2_OPD_SHIFT (2U)
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#define GRF_GPIO3B_OPD_GPIO3B2_OPD_MASK (0x1U << GRF_GPIO3B_OPD_GPIO3B2_OPD_SHIFT) /* 0x00000004 */
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#define GRF_GPIO3B_OPD_GPIO3B3_OPD_SHIFT (3U)
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#define GRF_GPIO3B_OPD_GPIO3B3_OPD_MASK (0x1U << GRF_GPIO3B_OPD_GPIO3B3_OPD_SHIFT) /* 0x00000008 */
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#define GRF_GPIO3B_OPD_GPIO3B4_OPD_SHIFT (4U)
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#define GRF_GPIO3B_OPD_GPIO3B4_OPD_MASK (0x1U << GRF_GPIO3B_OPD_GPIO3B4_OPD_SHIFT) /* 0x00000010 */
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#define GRF_GPIO3B_OPD_GPIO3B5_OPD_SHIFT (5U)
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#define GRF_GPIO3B_OPD_GPIO3B5_OPD_MASK (0x1U << GRF_GPIO3B_OPD_GPIO3B5_OPD_SHIFT) /* 0x00000020 */
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#define GRF_GPIO3B_OPD_GPIO3B6_OPD_SHIFT (6U)
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#define GRF_GPIO3B_OPD_GPIO3B6_OPD_MASK (0x1U << GRF_GPIO3B_OPD_GPIO3B6_OPD_SHIFT) /* 0x00000040 */
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#define GRF_GPIO3B_OPD_GPIO3B7_OPD_SHIFT (7U)
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#define GRF_GPIO3B_OPD_GPIO3B7_OPD_MASK (0x1U << GRF_GPIO3B_OPD_GPIO3B7_OPD_SHIFT) /* 0x00000080 */
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/* GPIO3C_OPD */
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#define GRF_GPIO3C_OPD_OFFSET (0x40128U)
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#define GRF_GPIO3C_OPD_GPIO3C0_OPD_SHIFT (0U)
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#define GRF_GPIO3C_OPD_GPIO3C0_OPD_MASK (0x1U << GRF_GPIO3C_OPD_GPIO3C0_OPD_SHIFT) /* 0x00000001 */
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#define GRF_GPIO3C_OPD_GPIO3C1_OPD_SHIFT (1U)
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#define GRF_GPIO3C_OPD_GPIO3C1_OPD_MASK (0x1U << GRF_GPIO3C_OPD_GPIO3C1_OPD_SHIFT) /* 0x00000002 */
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#define GRF_GPIO3C_OPD_GPIO3C2_OPD_SHIFT (2U)
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#define GRF_GPIO3C_OPD_GPIO3C2_OPD_MASK (0x1U << GRF_GPIO3C_OPD_GPIO3C2_OPD_SHIFT) /* 0x00000004 */
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#define GRF_GPIO3C_OPD_GPIO3C3_OPD_SHIFT (3U)
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#define GRF_GPIO3C_OPD_GPIO3C3_OPD_MASK (0x1U << GRF_GPIO3C_OPD_GPIO3C3_OPD_SHIFT) /* 0x00000008 */
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#define GRF_GPIO3C_OPD_GPIO3C4_OPD_SHIFT (4U)
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#define GRF_GPIO3C_OPD_GPIO3C4_OPD_MASK (0x1U << GRF_GPIO3C_OPD_GPIO3C4_OPD_SHIFT) /* 0x00000010 */
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#define GRF_GPIO3C_OPD_GPIO3C5_OPD_SHIFT (5U)
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#define GRF_GPIO3C_OPD_GPIO3C5_OPD_MASK (0x1U << GRF_GPIO3C_OPD_GPIO3C5_OPD_SHIFT) /* 0x00000020 */
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#define GRF_GPIO3C_OPD_GPIO3C6_OPD_SHIFT (6U)
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#define GRF_GPIO3C_OPD_GPIO3C6_OPD_MASK (0x1U << GRF_GPIO3C_OPD_GPIO3C6_OPD_SHIFT) /* 0x00000040 */
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#define GRF_GPIO3C_OPD_GPIO3C7_OPD_SHIFT (7U)
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#define GRF_GPIO3C_OPD_GPIO3C7_OPD_MASK (0x1U << GRF_GPIO3C_OPD_GPIO3C7_OPD_SHIFT) /* 0x00000080 */
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/* GPIO3D_OPD */
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#define GRF_GPIO3D_OPD_OFFSET (0x4012CU)
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#define GRF_GPIO3D_OPD_GPIO3D0_OPD_SHIFT (0U)
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#define GRF_GPIO3D_OPD_GPIO3D0_OPD_MASK (0x1U << GRF_GPIO3D_OPD_GPIO3D0_OPD_SHIFT) /* 0x00000001 */
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#define GRF_GPIO3D_OPD_GPIO3D1_OPD_SHIFT (1U)
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#define GRF_GPIO3D_OPD_GPIO3D1_OPD_MASK (0x1U << GRF_GPIO3D_OPD_GPIO3D1_OPD_SHIFT) /* 0x00000002 */
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#define GRF_GPIO3D_OPD_GPIO3D2_OPD_SHIFT (2U)
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#define GRF_GPIO3D_OPD_GPIO3D2_OPD_MASK (0x1U << GRF_GPIO3D_OPD_GPIO3D2_OPD_SHIFT) /* 0x00000004 */
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#define GRF_GPIO3D_OPD_GPIO3D3_OPD_SHIFT (3U)
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#define GRF_GPIO3D_OPD_GPIO3D3_OPD_MASK (0x1U << GRF_GPIO3D_OPD_GPIO3D3_OPD_SHIFT) /* 0x00000008 */
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#define GRF_GPIO3D_OPD_GPIO3D4_OPD_SHIFT (4U)
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#define GRF_GPIO3D_OPD_GPIO3D4_OPD_MASK (0x1U << GRF_GPIO3D_OPD_GPIO3D4_OPD_SHIFT) /* 0x00000010 */
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#define GRF_GPIO3D_OPD_GPIO3D5_OPD_SHIFT (5U)
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#define GRF_GPIO3D_OPD_GPIO3D5_OPD_MASK (0x1U << GRF_GPIO3D_OPD_GPIO3D5_OPD_SHIFT) /* 0x00000020 */
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#define GRF_GPIO3D_OPD_GPIO3D6_OPD_SHIFT (6U)
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#define GRF_GPIO3D_OPD_GPIO3D6_OPD_MASK (0x1U << GRF_GPIO3D_OPD_GPIO3D6_OPD_SHIFT) /* 0x00000040 */
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#define GRF_GPIO3D_OPD_GPIO3D7_OPD_SHIFT (7U)
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#define GRF_GPIO3D_OPD_GPIO3D7_OPD_MASK (0x1U << GRF_GPIO3D_OPD_GPIO3D7_OPD_SHIFT) /* 0x00000080 */
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/* GPIO4A_OPD */
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#define GRF_GPIO4A_OPD_OFFSET (0x40130U)
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#define GRF_GPIO4A_OPD_GPIO4A0_OPD_SHIFT (0U)
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#define GRF_GPIO4A_OPD_GPIO4A0_OPD_MASK (0x1U << GRF_GPIO4A_OPD_GPIO4A0_OPD_SHIFT) /* 0x00000001 */
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#define GRF_GPIO4A_OPD_GPIO4A1_OPD_SHIFT (1U)
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#define GRF_GPIO4A_OPD_GPIO4A1_OPD_MASK (0x1U << GRF_GPIO4A_OPD_GPIO4A1_OPD_SHIFT) /* 0x00000002 */
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#define GRF_GPIO4A_OPD_GPIO4A2_OPD_SHIFT (2U)
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#define GRF_GPIO4A_OPD_GPIO4A2_OPD_MASK (0x1U << GRF_GPIO4A_OPD_GPIO4A2_OPD_SHIFT) /* 0x00000004 */
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#define GRF_GPIO4A_OPD_GPIO4A3_OPD_SHIFT (3U)
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#define GRF_GPIO4A_OPD_GPIO4A3_OPD_MASK (0x1U << GRF_GPIO4A_OPD_GPIO4A3_OPD_SHIFT) /* 0x00000008 */
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#define GRF_GPIO4A_OPD_GPIO4A4_OPD_SHIFT (4U)
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#define GRF_GPIO4A_OPD_GPIO4A4_OPD_MASK (0x1U << GRF_GPIO4A_OPD_GPIO4A4_OPD_SHIFT) /* 0x00000010 */
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#define GRF_GPIO4A_OPD_GPIO4A5_OPD_SHIFT (5U)
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#define GRF_GPIO4A_OPD_GPIO4A5_OPD_MASK (0x1U << GRF_GPIO4A_OPD_GPIO4A5_OPD_SHIFT) /* 0x00000020 */
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#define GRF_GPIO4A_OPD_GPIO4A6_OPD_SHIFT (6U)
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#define GRF_GPIO4A_OPD_GPIO4A6_OPD_MASK (0x1U << GRF_GPIO4A_OPD_GPIO4A6_OPD_SHIFT) /* 0x00000040 */
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#define GRF_GPIO4A_OPD_GPIO4A7_OPD_SHIFT (7U)
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#define GRF_GPIO4A_OPD_GPIO4A7_OPD_MASK (0x1U << GRF_GPIO4A_OPD_GPIO4A7_OPD_SHIFT) /* 0x00000080 */
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/* GPIO4B_OPD */
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#define GRF_GPIO4B_OPD_OFFSET (0x40134U)
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#define GRF_GPIO4B_OPD_GPIO4B0_OPD_SHIFT (0U)
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#define GRF_GPIO4B_OPD_GPIO4B0_OPD_MASK (0x1U << GRF_GPIO4B_OPD_GPIO4B0_OPD_SHIFT) /* 0x00000001 */
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#define GRF_GPIO4B_OPD_GPIO4B1_OPD_SHIFT (1U)
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#define GRF_GPIO4B_OPD_GPIO4B1_OPD_MASK (0x1U << GRF_GPIO4B_OPD_GPIO4B1_OPD_SHIFT) /* 0x00000002 */
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#define GRF_GPIO4B_OPD_GPIO4B2_OPD_SHIFT (2U)
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#define GRF_GPIO4B_OPD_GPIO4B2_OPD_MASK (0x1U << GRF_GPIO4B_OPD_GPIO4B2_OPD_SHIFT) /* 0x00000004 */
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#define GRF_GPIO4B_OPD_GPIO4B3_OPD_SHIFT (3U)
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#define GRF_GPIO4B_OPD_GPIO4B3_OPD_MASK (0x1U << GRF_GPIO4B_OPD_GPIO4B3_OPD_SHIFT) /* 0x00000008 */
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#define GRF_GPIO4B_OPD_GPIO4B4_OPD_SHIFT (4U)
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#define GRF_GPIO4B_OPD_GPIO4B4_OPD_MASK (0x1U << GRF_GPIO4B_OPD_GPIO4B4_OPD_SHIFT) /* 0x00000010 */
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#define GRF_GPIO4B_OPD_GPIO4B5_OPD_SHIFT (5U)
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#define GRF_GPIO4B_OPD_GPIO4B5_OPD_MASK (0x1U << GRF_GPIO4B_OPD_GPIO4B5_OPD_SHIFT) /* 0x00000020 */
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#define GRF_GPIO4B_OPD_GPIO4B6_OPD_SHIFT (6U)
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#define GRF_GPIO4B_OPD_GPIO4B6_OPD_MASK (0x1U << GRF_GPIO4B_OPD_GPIO4B6_OPD_SHIFT) /* 0x00000040 */
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#define GRF_GPIO4B_OPD_GPIO4B7_OPD_SHIFT (7U)
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#define GRF_GPIO4B_OPD_GPIO4B7_OPD_MASK (0x1U << GRF_GPIO4B_OPD_GPIO4B7_OPD_SHIFT) /* 0x00000080 */
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/* GPIO4C_OPD */
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#define GRF_GPIO4C_OPD_OFFSET (0x40138U)
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#define GRF_GPIO4C_OPD_GPIO4C0_OPD_SHIFT (0U)
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#define GRF_GPIO4C_OPD_GPIO4C0_OPD_MASK (0x1U << GRF_GPIO4C_OPD_GPIO4C0_OPD_SHIFT) /* 0x00000001 */
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#define GRF_GPIO4C_OPD_GPIO4C1_OPD_SHIFT (1U)
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#define GRF_GPIO4C_OPD_GPIO4C1_OPD_MASK (0x1U << GRF_GPIO4C_OPD_GPIO4C1_OPD_SHIFT) /* 0x00000002 */
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#define GRF_GPIO4C_OPD_GPIO4C2_OPD_SHIFT (2U)
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#define GRF_GPIO4C_OPD_GPIO4C2_OPD_MASK (0x1U << GRF_GPIO4C_OPD_GPIO4C2_OPD_SHIFT) /* 0x00000004 */
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#define GRF_GPIO4C_OPD_GPIO4C3_OPD_SHIFT (3U)
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#define GRF_GPIO4C_OPD_GPIO4C3_OPD_MASK (0x1U << GRF_GPIO4C_OPD_GPIO4C3_OPD_SHIFT) /* 0x00000008 */
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#define GRF_GPIO4C_OPD_GPIO4C4_OPD_SHIFT (4U)
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#define GRF_GPIO4C_OPD_GPIO4C4_OPD_MASK (0x1U << GRF_GPIO4C_OPD_GPIO4C4_OPD_SHIFT) /* 0x00000010 */
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#define GRF_GPIO4C_OPD_GPIO4C5_OPD_SHIFT (5U)
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#define GRF_GPIO4C_OPD_GPIO4C5_OPD_MASK (0x1U << GRF_GPIO4C_OPD_GPIO4C5_OPD_SHIFT) /* 0x00000020 */
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#define GRF_GPIO4C_OPD_GPIO4C6_OPD_SHIFT (6U)
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#define GRF_GPIO4C_OPD_GPIO4C6_OPD_MASK (0x1U << GRF_GPIO4C_OPD_GPIO4C6_OPD_SHIFT) /* 0x00000040 */
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#define GRF_GPIO4C_OPD_GPIO4C7_OPD_SHIFT (7U)
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#define GRF_GPIO4C_OPD_GPIO4C7_OPD_MASK (0x1U << GRF_GPIO4C_OPD_GPIO4C7_OPD_SHIFT) /* 0x00000080 */
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/* GPIO4D_OPD */
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#define GRF_GPIO4D_OPD_OFFSET (0x4013CU)
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#define GRF_GPIO4D_OPD_GPIO4D0_OPD_SHIFT (0U)
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#define GRF_GPIO4D_OPD_GPIO4D0_OPD_MASK (0x1U << GRF_GPIO4D_OPD_GPIO4D0_OPD_SHIFT) /* 0x00000001 */
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#define GRF_GPIO4D_OPD_GPIO4D1_OPD_SHIFT (1U)
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#define GRF_GPIO4D_OPD_GPIO4D1_OPD_MASK (0x1U << GRF_GPIO4D_OPD_GPIO4D1_OPD_SHIFT) /* 0x00000002 */
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#define GRF_GPIO4D_OPD_GPIO4D2_OPD_SHIFT (2U)
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#define GRF_GPIO4D_OPD_GPIO4D2_OPD_MASK (0x1U << GRF_GPIO4D_OPD_GPIO4D2_OPD_SHIFT) /* 0x00000004 */
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#define GRF_GPIO4D_OPD_GPIO4D3_OPD_SHIFT (3U)
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#define GRF_GPIO4D_OPD_GPIO4D3_OPD_MASK (0x1U << GRF_GPIO4D_OPD_GPIO4D3_OPD_SHIFT) /* 0x00000008 */
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#define GRF_GPIO4D_OPD_GPIO4D4_OPD_SHIFT (4U)
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#define GRF_GPIO4D_OPD_GPIO4D4_OPD_MASK (0x1U << GRF_GPIO4D_OPD_GPIO4D4_OPD_SHIFT) /* 0x00000010 */
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#define GRF_GPIO4D_OPD_GPIO4D5_OPD_SHIFT (5U)
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#define GRF_GPIO4D_OPD_GPIO4D5_OPD_MASK (0x1U << GRF_GPIO4D_OPD_GPIO4D5_OPD_SHIFT) /* 0x00000020 */
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#define GRF_GPIO4D_OPD_GPIO4D6_OPD_SHIFT (6U)
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#define GRF_GPIO4D_OPD_GPIO4D6_OPD_MASK (0x1U << GRF_GPIO4D_OPD_GPIO4D6_OPD_SHIFT) /* 0x00000040 */
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#define GRF_GPIO4D_OPD_GPIO4D7_OPD_SHIFT (7U)
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#define GRF_GPIO4D_OPD_GPIO4D7_OPD_MASK (0x1U << GRF_GPIO4D_OPD_GPIO4D7_OPD_SHIFT) /* 0x00000080 */
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/* GPIO1A_SUS */
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#define GRF_GPIO1A_SUS_OFFSET (0x40140U)
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#define GRF_GPIO1A_SUS_GPIO1A0_SUS_SHIFT (0U)
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#define GRF_GPIO1A_SUS_GPIO1A0_SUS_MASK (0x1U << GRF_GPIO1A_SUS_GPIO1A0_SUS_SHIFT) /* 0x00000001 */
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#define GRF_GPIO1A_SUS_GPIO1A1_SUS_SHIFT (1U)
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#define GRF_GPIO1A_SUS_GPIO1A1_SUS_MASK (0x1U << GRF_GPIO1A_SUS_GPIO1A1_SUS_SHIFT) /* 0x00000002 */
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#define GRF_GPIO1A_SUS_GPIO1A2_SUS_SHIFT (2U)
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#define GRF_GPIO1A_SUS_GPIO1A2_SUS_MASK (0x1U << GRF_GPIO1A_SUS_GPIO1A2_SUS_SHIFT) /* 0x00000004 */
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#define GRF_GPIO1A_SUS_GPIO1A3_SUS_SHIFT (3U)
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#define GRF_GPIO1A_SUS_GPIO1A3_SUS_MASK (0x1U << GRF_GPIO1A_SUS_GPIO1A3_SUS_SHIFT) /* 0x00000008 */
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#define GRF_GPIO1A_SUS_GPIO1A4_SUS_SHIFT (4U)
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#define GRF_GPIO1A_SUS_GPIO1A4_SUS_MASK (0x1U << GRF_GPIO1A_SUS_GPIO1A4_SUS_SHIFT) /* 0x00000010 */
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#define GRF_GPIO1A_SUS_GPIO1A5_SUS_SHIFT (5U)
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#define GRF_GPIO1A_SUS_GPIO1A5_SUS_MASK (0x1U << GRF_GPIO1A_SUS_GPIO1A5_SUS_SHIFT) /* 0x00000020 */
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#define GRF_GPIO1A_SUS_GPIO1A6_SUS_SHIFT (6U)
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#define GRF_GPIO1A_SUS_GPIO1A6_SUS_MASK (0x1U << GRF_GPIO1A_SUS_GPIO1A6_SUS_SHIFT) /* 0x00000040 */
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#define GRF_GPIO1A_SUS_GPIO1A7_SUS_SHIFT (7U)
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#define GRF_GPIO1A_SUS_GPIO1A7_SUS_MASK (0x1U << GRF_GPIO1A_SUS_GPIO1A7_SUS_SHIFT) /* 0x00000080 */
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/* GPIO1B_SUS */
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#define GRF_GPIO1B_SUS_OFFSET (0x40144U)
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#define GRF_GPIO1B_SUS_GPIO1B0_SUS_SHIFT (0U)
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#define GRF_GPIO1B_SUS_GPIO1B0_SUS_MASK (0x1U << GRF_GPIO1B_SUS_GPIO1B0_SUS_SHIFT) /* 0x00000001 */
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#define GRF_GPIO1B_SUS_GPIO1B1_SUS_SHIFT (1U)
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#define GRF_GPIO1B_SUS_GPIO1B1_SUS_MASK (0x1U << GRF_GPIO1B_SUS_GPIO1B1_SUS_SHIFT) /* 0x00000002 */
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#define GRF_GPIO1B_SUS_GPIO1B2_SUS_SHIFT (2U)
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#define GRF_GPIO1B_SUS_GPIO1B2_SUS_MASK (0x1U << GRF_GPIO1B_SUS_GPIO1B2_SUS_SHIFT) /* 0x00000004 */
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#define GRF_GPIO1B_SUS_GPIO1B3_SUS_SHIFT (3U)
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#define GRF_GPIO1B_SUS_GPIO1B3_SUS_MASK (0x1U << GRF_GPIO1B_SUS_GPIO1B3_SUS_SHIFT) /* 0x00000008 */
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#define GRF_GPIO1B_SUS_GPIO1B4_SUS_SHIFT (4U)
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#define GRF_GPIO1B_SUS_GPIO1B4_SUS_MASK (0x1U << GRF_GPIO1B_SUS_GPIO1B4_SUS_SHIFT) /* 0x00000010 */
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#define GRF_GPIO1B_SUS_GPIO1B5_SUS_SHIFT (5U)
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#define GRF_GPIO1B_SUS_GPIO1B5_SUS_MASK (0x1U << GRF_GPIO1B_SUS_GPIO1B5_SUS_SHIFT) /* 0x00000020 */
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#define GRF_GPIO1B_SUS_GPIO1B6_SUS_SHIFT (6U)
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#define GRF_GPIO1B_SUS_GPIO1B6_SUS_MASK (0x1U << GRF_GPIO1B_SUS_GPIO1B6_SUS_SHIFT) /* 0x00000040 */
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#define GRF_GPIO1B_SUS_GPIO1B7_SUS_SHIFT (7U)
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#define GRF_GPIO1B_SUS_GPIO1B7_SUS_MASK (0x1U << GRF_GPIO1B_SUS_GPIO1B7_SUS_SHIFT) /* 0x00000080 */
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/* GPIO1C_SUS */
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#define GRF_GPIO1C_SUS_OFFSET (0x40148U)
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#define GRF_GPIO1C_SUS_GPIO1C0_SUS_SHIFT (0U)
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#define GRF_GPIO1C_SUS_GPIO1C0_SUS_MASK (0x1U << GRF_GPIO1C_SUS_GPIO1C0_SUS_SHIFT) /* 0x00000001 */
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#define GRF_GPIO1C_SUS_GPIO1C1_SUS_SHIFT (1U)
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#define GRF_GPIO1C_SUS_GPIO1C1_SUS_MASK (0x1U << GRF_GPIO1C_SUS_GPIO1C1_SUS_SHIFT) /* 0x00000002 */
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#define GRF_GPIO1C_SUS_GPIO1C2_SUS_SHIFT (2U)
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#define GRF_GPIO1C_SUS_GPIO1C2_SUS_MASK (0x1U << GRF_GPIO1C_SUS_GPIO1C2_SUS_SHIFT) /* 0x00000004 */
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#define GRF_GPIO1C_SUS_GPIO1C3_SUS_SHIFT (3U)
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#define GRF_GPIO1C_SUS_GPIO1C3_SUS_MASK (0x1U << GRF_GPIO1C_SUS_GPIO1C3_SUS_SHIFT) /* 0x00000008 */
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#define GRF_GPIO1C_SUS_GPIO1C4_SUS_SHIFT (4U)
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#define GRF_GPIO1C_SUS_GPIO1C4_SUS_MASK (0x1U << GRF_GPIO1C_SUS_GPIO1C4_SUS_SHIFT) /* 0x00000010 */
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#define GRF_GPIO1C_SUS_GPIO1C5_SUS_SHIFT (5U)
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#define GRF_GPIO1C_SUS_GPIO1C5_SUS_MASK (0x1U << GRF_GPIO1C_SUS_GPIO1C5_SUS_SHIFT) /* 0x00000020 */
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#define GRF_GPIO1C_SUS_GPIO1C6_SUS_SHIFT (6U)
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#define GRF_GPIO1C_SUS_GPIO1C6_SUS_MASK (0x1U << GRF_GPIO1C_SUS_GPIO1C6_SUS_SHIFT) /* 0x00000040 */
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#define GRF_GPIO1C_SUS_GPIO1C7_SUS_SHIFT (7U)
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#define GRF_GPIO1C_SUS_GPIO1C7_SUS_MASK (0x1U << GRF_GPIO1C_SUS_GPIO1C7_SUS_SHIFT) /* 0x00000080 */
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/* GPIO1D_SUS */
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#define GRF_GPIO1D_SUS_OFFSET (0x4014CU)
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#define GRF_GPIO1D_SUS_GPIO1D0_SUS_SHIFT (0U)
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#define GRF_GPIO1D_SUS_GPIO1D0_SUS_MASK (0x1U << GRF_GPIO1D_SUS_GPIO1D0_SUS_SHIFT) /* 0x00000001 */
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#define GRF_GPIO1D_SUS_GPIO1D1_SUS_SHIFT (1U)
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#define GRF_GPIO1D_SUS_GPIO1D1_SUS_MASK (0x1U << GRF_GPIO1D_SUS_GPIO1D1_SUS_SHIFT) /* 0x00000002 */
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#define GRF_GPIO1D_SUS_GPIO1D2_SUS_SHIFT (2U)
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#define GRF_GPIO1D_SUS_GPIO1D2_SUS_MASK (0x1U << GRF_GPIO1D_SUS_GPIO1D2_SUS_SHIFT) /* 0x00000004 */
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#define GRF_GPIO1D_SUS_GPIO1D3_SUS_SHIFT (3U)
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#define GRF_GPIO1D_SUS_GPIO1D3_SUS_MASK (0x1U << GRF_GPIO1D_SUS_GPIO1D3_SUS_SHIFT) /* 0x00000008 */
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#define GRF_GPIO1D_SUS_GPIO1D4_SUS_SHIFT (4U)
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#define GRF_GPIO1D_SUS_GPIO1D4_SUS_MASK (0x1U << GRF_GPIO1D_SUS_GPIO1D4_SUS_SHIFT) /* 0x00000010 */
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#define GRF_GPIO1D_SUS_GPIO1D5_SUS_SHIFT (5U)
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#define GRF_GPIO1D_SUS_GPIO1D5_SUS_MASK (0x1U << GRF_GPIO1D_SUS_GPIO1D5_SUS_SHIFT) /* 0x00000020 */
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#define GRF_GPIO1D_SUS_GPIO1D6_SUS_SHIFT (6U)
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#define GRF_GPIO1D_SUS_GPIO1D6_SUS_MASK (0x1U << GRF_GPIO1D_SUS_GPIO1D6_SUS_SHIFT) /* 0x00000040 */
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#define GRF_GPIO1D_SUS_GPIO1D7_SUS_SHIFT (7U)
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#define GRF_GPIO1D_SUS_GPIO1D7_SUS_MASK (0x1U << GRF_GPIO1D_SUS_GPIO1D7_SUS_SHIFT) /* 0x00000080 */
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/* GPIO2A_SUS */
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#define GRF_GPIO2A_SUS_OFFSET (0x40150U)
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#define GRF_GPIO2A_SUS_GPIO2A0_SUS_SHIFT (0U)
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#define GRF_GPIO2A_SUS_GPIO2A0_SUS_MASK (0x1U << GRF_GPIO2A_SUS_GPIO2A0_SUS_SHIFT) /* 0x00000001 */
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#define GRF_GPIO2A_SUS_GPIO2A1_SUS_SHIFT (1U)
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#define GRF_GPIO2A_SUS_GPIO2A1_SUS_MASK (0x1U << GRF_GPIO2A_SUS_GPIO2A1_SUS_SHIFT) /* 0x00000002 */
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#define GRF_GPIO2A_SUS_GPIO2A2_SUS_SHIFT (2U)
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#define GRF_GPIO2A_SUS_GPIO2A2_SUS_MASK (0x1U << GRF_GPIO2A_SUS_GPIO2A2_SUS_SHIFT) /* 0x00000004 */
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#define GRF_GPIO2A_SUS_GPIO2A3_SUS_SHIFT (3U)
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#define GRF_GPIO2A_SUS_GPIO2A3_SUS_MASK (0x1U << GRF_GPIO2A_SUS_GPIO2A3_SUS_SHIFT) /* 0x00000008 */
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#define GRF_GPIO2A_SUS_GPIO2A4_SUS_SHIFT (4U)
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#define GRF_GPIO2A_SUS_GPIO2A4_SUS_MASK (0x1U << GRF_GPIO2A_SUS_GPIO2A4_SUS_SHIFT) /* 0x00000010 */
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#define GRF_GPIO2A_SUS_GPIO2A5_SUS_SHIFT (5U)
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#define GRF_GPIO2A_SUS_GPIO2A5_SUS_MASK (0x1U << GRF_GPIO2A_SUS_GPIO2A5_SUS_SHIFT) /* 0x00000020 */
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#define GRF_GPIO2A_SUS_GPIO2A6_SUS_SHIFT (6U)
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#define GRF_GPIO2A_SUS_GPIO2A6_SUS_MASK (0x1U << GRF_GPIO2A_SUS_GPIO2A6_SUS_SHIFT) /* 0x00000040 */
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#define GRF_GPIO2A_SUS_GPIO2A7_SUS_SHIFT (7U)
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#define GRF_GPIO2A_SUS_GPIO2A7_SUS_MASK (0x1U << GRF_GPIO2A_SUS_GPIO2A7_SUS_SHIFT) /* 0x00000080 */
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/* GPIO2B_SUS */
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#define GRF_GPIO2B_SUS_OFFSET (0x40154U)
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#define GRF_GPIO2B_SUS_GPIO2B0_SUS_SHIFT (0U)
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#define GRF_GPIO2B_SUS_GPIO2B0_SUS_MASK (0x1U << GRF_GPIO2B_SUS_GPIO2B0_SUS_SHIFT) /* 0x00000001 */
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#define GRF_GPIO2B_SUS_GPIO2B1_SUS_SHIFT (1U)
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#define GRF_GPIO2B_SUS_GPIO2B1_SUS_MASK (0x1U << GRF_GPIO2B_SUS_GPIO2B1_SUS_SHIFT) /* 0x00000002 */
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#define GRF_GPIO2B_SUS_GPIO2B2_SUS_SHIFT (2U)
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#define GRF_GPIO2B_SUS_GPIO2B2_SUS_MASK (0x1U << GRF_GPIO2B_SUS_GPIO2B2_SUS_SHIFT) /* 0x00000004 */
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#define GRF_GPIO2B_SUS_GPIO2B3_SUS_SHIFT (3U)
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#define GRF_GPIO2B_SUS_GPIO2B3_SUS_MASK (0x1U << GRF_GPIO2B_SUS_GPIO2B3_SUS_SHIFT) /* 0x00000008 */
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#define GRF_GPIO2B_SUS_GPIO2B4_SUS_SHIFT (4U)
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#define GRF_GPIO2B_SUS_GPIO2B4_SUS_MASK (0x1U << GRF_GPIO2B_SUS_GPIO2B4_SUS_SHIFT) /* 0x00000010 */
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#define GRF_GPIO2B_SUS_GPIO2B5_SUS_SHIFT (5U)
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#define GRF_GPIO2B_SUS_GPIO2B5_SUS_MASK (0x1U << GRF_GPIO2B_SUS_GPIO2B5_SUS_SHIFT) /* 0x00000020 */
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#define GRF_GPIO2B_SUS_GPIO2B6_SUS_SHIFT (6U)
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#define GRF_GPIO2B_SUS_GPIO2B6_SUS_MASK (0x1U << GRF_GPIO2B_SUS_GPIO2B6_SUS_SHIFT) /* 0x00000040 */
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#define GRF_GPIO2B_SUS_GPIO2B7_SUS_SHIFT (7U)
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#define GRF_GPIO2B_SUS_GPIO2B7_SUS_MASK (0x1U << GRF_GPIO2B_SUS_GPIO2B7_SUS_SHIFT) /* 0x00000080 */
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/* GPIO2C_SUS */
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#define GRF_GPIO2C_SUS_OFFSET (0x40158U)
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#define GRF_GPIO2C_SUS_GPIO2C0_SUS_SHIFT (0U)
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#define GRF_GPIO2C_SUS_GPIO2C0_SUS_MASK (0x1U << GRF_GPIO2C_SUS_GPIO2C0_SUS_SHIFT) /* 0x00000001 */
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#define GRF_GPIO2C_SUS_GPIO2C1_SUS_SHIFT (1U)
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#define GRF_GPIO2C_SUS_GPIO2C1_SUS_MASK (0x1U << GRF_GPIO2C_SUS_GPIO2C1_SUS_SHIFT) /* 0x00000002 */
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#define GRF_GPIO2C_SUS_GPIO2C2_SUS_SHIFT (2U)
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#define GRF_GPIO2C_SUS_GPIO2C2_SUS_MASK (0x1U << GRF_GPIO2C_SUS_GPIO2C2_SUS_SHIFT) /* 0x00000004 */
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#define GRF_GPIO2C_SUS_GPIO2C3_SUS_SHIFT (3U)
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#define GRF_GPIO2C_SUS_GPIO2C3_SUS_MASK (0x1U << GRF_GPIO2C_SUS_GPIO2C3_SUS_SHIFT) /* 0x00000008 */
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#define GRF_GPIO2C_SUS_GPIO2C4_SUS_SHIFT (4U)
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#define GRF_GPIO2C_SUS_GPIO2C4_SUS_MASK (0x1U << GRF_GPIO2C_SUS_GPIO2C4_SUS_SHIFT) /* 0x00000010 */
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#define GRF_GPIO2C_SUS_GPIO2C5_SUS_SHIFT (5U)
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#define GRF_GPIO2C_SUS_GPIO2C5_SUS_MASK (0x1U << GRF_GPIO2C_SUS_GPIO2C5_SUS_SHIFT) /* 0x00000020 */
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#define GRF_GPIO2C_SUS_GPIO2C6_SUS_SHIFT (6U)
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#define GRF_GPIO2C_SUS_GPIO2C6_SUS_MASK (0x1U << GRF_GPIO2C_SUS_GPIO2C6_SUS_SHIFT) /* 0x00000040 */
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#define GRF_GPIO2C_SUS_GPIO2C7_SUS_SHIFT (7U)
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#define GRF_GPIO2C_SUS_GPIO2C7_SUS_MASK (0x1U << GRF_GPIO2C_SUS_GPIO2C7_SUS_SHIFT) /* 0x00000080 */
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/* GPIO2D_SUS */
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#define GRF_GPIO2D_SUS_OFFSET (0x4015CU)
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#define GRF_GPIO2D_SUS_GPIO2D0_SUS_SHIFT (0U)
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#define GRF_GPIO2D_SUS_GPIO2D0_SUS_MASK (0x1U << GRF_GPIO2D_SUS_GPIO2D0_SUS_SHIFT) /* 0x00000001 */
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#define GRF_GPIO2D_SUS_GPIO2D1_SUS_SHIFT (1U)
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#define GRF_GPIO2D_SUS_GPIO2D1_SUS_MASK (0x1U << GRF_GPIO2D_SUS_GPIO2D1_SUS_SHIFT) /* 0x00000002 */
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#define GRF_GPIO2D_SUS_GPIO2D2_SUS_SHIFT (2U)
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#define GRF_GPIO2D_SUS_GPIO2D2_SUS_MASK (0x1U << GRF_GPIO2D_SUS_GPIO2D2_SUS_SHIFT) /* 0x00000004 */
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#define GRF_GPIO2D_SUS_GPIO2D3_SUS_SHIFT (3U)
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#define GRF_GPIO2D_SUS_GPIO2D3_SUS_MASK (0x1U << GRF_GPIO2D_SUS_GPIO2D3_SUS_SHIFT) /* 0x00000008 */
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#define GRF_GPIO2D_SUS_GPIO2D4_SUS_SHIFT (4U)
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#define GRF_GPIO2D_SUS_GPIO2D4_SUS_MASK (0x1U << GRF_GPIO2D_SUS_GPIO2D4_SUS_SHIFT) /* 0x00000010 */
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#define GRF_GPIO2D_SUS_GPIO2D5_SUS_SHIFT (5U)
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#define GRF_GPIO2D_SUS_GPIO2D5_SUS_MASK (0x1U << GRF_GPIO2D_SUS_GPIO2D5_SUS_SHIFT) /* 0x00000020 */
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#define GRF_GPIO2D_SUS_GPIO2D6_SUS_SHIFT (6U)
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#define GRF_GPIO2D_SUS_GPIO2D6_SUS_MASK (0x1U << GRF_GPIO2D_SUS_GPIO2D6_SUS_SHIFT) /* 0x00000040 */
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#define GRF_GPIO2D_SUS_GPIO2D7_SUS_SHIFT (7U)
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#define GRF_GPIO2D_SUS_GPIO2D7_SUS_MASK (0x1U << GRF_GPIO2D_SUS_GPIO2D7_SUS_SHIFT) /* 0x00000080 */
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/* GPIO3A_SUS */
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#define GRF_GPIO3A_SUS_OFFSET (0x40160U)
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#define GRF_GPIO3A_SUS_GPIO3A0_SUS_SHIFT (0U)
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#define GRF_GPIO3A_SUS_GPIO3A0_SUS_MASK (0x1U << GRF_GPIO3A_SUS_GPIO3A0_SUS_SHIFT) /* 0x00000001 */
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#define GRF_GPIO3A_SUS_GPIO3A1_SUS_SHIFT (1U)
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#define GRF_GPIO3A_SUS_GPIO3A1_SUS_MASK (0x1U << GRF_GPIO3A_SUS_GPIO3A1_SUS_SHIFT) /* 0x00000002 */
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#define GRF_GPIO3A_SUS_GPIO3A2_SUS_SHIFT (2U)
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#define GRF_GPIO3A_SUS_GPIO3A2_SUS_MASK (0x1U << GRF_GPIO3A_SUS_GPIO3A2_SUS_SHIFT) /* 0x00000004 */
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#define GRF_GPIO3A_SUS_GPIO3A3_SUS_SHIFT (3U)
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#define GRF_GPIO3A_SUS_GPIO3A3_SUS_MASK (0x1U << GRF_GPIO3A_SUS_GPIO3A3_SUS_SHIFT) /* 0x00000008 */
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#define GRF_GPIO3A_SUS_GPIO3A4_SUS_SHIFT (4U)
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#define GRF_GPIO3A_SUS_GPIO3A4_SUS_MASK (0x1U << GRF_GPIO3A_SUS_GPIO3A4_SUS_SHIFT) /* 0x00000010 */
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#define GRF_GPIO3A_SUS_GPIO3A5_SUS_SHIFT (5U)
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#define GRF_GPIO3A_SUS_GPIO3A5_SUS_MASK (0x1U << GRF_GPIO3A_SUS_GPIO3A5_SUS_SHIFT) /* 0x00000020 */
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#define GRF_GPIO3A_SUS_GPIO3A6_SUS_SHIFT (6U)
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#define GRF_GPIO3A_SUS_GPIO3A6_SUS_MASK (0x1U << GRF_GPIO3A_SUS_GPIO3A6_SUS_SHIFT) /* 0x00000040 */
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#define GRF_GPIO3A_SUS_GPIO3A7_SUS_SHIFT (7U)
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#define GRF_GPIO3A_SUS_GPIO3A7_SUS_MASK (0x1U << GRF_GPIO3A_SUS_GPIO3A7_SUS_SHIFT) /* 0x00000080 */
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/* GPIO3B_SUS */
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#define GRF_GPIO3B_SUS_OFFSET (0x40164U)
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#define GRF_GPIO3B_SUS_GPIO3B0_SUS_SHIFT (0U)
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#define GRF_GPIO3B_SUS_GPIO3B0_SUS_MASK (0x1U << GRF_GPIO3B_SUS_GPIO3B0_SUS_SHIFT) /* 0x00000001 */
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#define GRF_GPIO3B_SUS_GPIO3B1_SUS_SHIFT (1U)
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#define GRF_GPIO3B_SUS_GPIO3B1_SUS_MASK (0x1U << GRF_GPIO3B_SUS_GPIO3B1_SUS_SHIFT) /* 0x00000002 */
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#define GRF_GPIO3B_SUS_GPIO3B2_SUS_SHIFT (2U)
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#define GRF_GPIO3B_SUS_GPIO3B2_SUS_MASK (0x1U << GRF_GPIO3B_SUS_GPIO3B2_SUS_SHIFT) /* 0x00000004 */
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#define GRF_GPIO3B_SUS_GPIO3B3_SUS_SHIFT (3U)
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#define GRF_GPIO3B_SUS_GPIO3B3_SUS_MASK (0x1U << GRF_GPIO3B_SUS_GPIO3B3_SUS_SHIFT) /* 0x00000008 */
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#define GRF_GPIO3B_SUS_GPIO3B4_SUS_SHIFT (4U)
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#define GRF_GPIO3B_SUS_GPIO3B4_SUS_MASK (0x1U << GRF_GPIO3B_SUS_GPIO3B4_SUS_SHIFT) /* 0x00000010 */
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#define GRF_GPIO3B_SUS_GPIO3B5_SUS_SHIFT (5U)
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#define GRF_GPIO3B_SUS_GPIO3B5_SUS_MASK (0x1U << GRF_GPIO3B_SUS_GPIO3B5_SUS_SHIFT) /* 0x00000020 */
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#define GRF_GPIO3B_SUS_GPIO3B6_SUS_SHIFT (6U)
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#define GRF_GPIO3B_SUS_GPIO3B6_SUS_MASK (0x1U << GRF_GPIO3B_SUS_GPIO3B6_SUS_SHIFT) /* 0x00000040 */
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#define GRF_GPIO3B_SUS_GPIO3B7_SUS_SHIFT (7U)
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#define GRF_GPIO3B_SUS_GPIO3B7_SUS_MASK (0x1U << GRF_GPIO3B_SUS_GPIO3B7_SUS_SHIFT) /* 0x00000080 */
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/* GPIO3C_SUS */
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#define GRF_GPIO3C_SUS_OFFSET (0x40168U)
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#define GRF_GPIO3C_SUS_GPIO3C0_SUS_SHIFT (0U)
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#define GRF_GPIO3C_SUS_GPIO3C0_SUS_MASK (0x1U << GRF_GPIO3C_SUS_GPIO3C0_SUS_SHIFT) /* 0x00000001 */
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#define GRF_GPIO3C_SUS_GPIO3C1_SUS_SHIFT (1U)
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#define GRF_GPIO3C_SUS_GPIO3C1_SUS_MASK (0x1U << GRF_GPIO3C_SUS_GPIO3C1_SUS_SHIFT) /* 0x00000002 */
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#define GRF_GPIO3C_SUS_GPIO3C2_SUS_SHIFT (2U)
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#define GRF_GPIO3C_SUS_GPIO3C2_SUS_MASK (0x1U << GRF_GPIO3C_SUS_GPIO3C2_SUS_SHIFT) /* 0x00000004 */
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#define GRF_GPIO3C_SUS_GPIO3C3_SUS_SHIFT (3U)
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#define GRF_GPIO3C_SUS_GPIO3C3_SUS_MASK (0x1U << GRF_GPIO3C_SUS_GPIO3C3_SUS_SHIFT) /* 0x00000008 */
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#define GRF_GPIO3C_SUS_GPIO3C4_SUS_SHIFT (4U)
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#define GRF_GPIO3C_SUS_GPIO3C4_SUS_MASK (0x1U << GRF_GPIO3C_SUS_GPIO3C4_SUS_SHIFT) /* 0x00000010 */
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#define GRF_GPIO3C_SUS_GPIO3C5_SUS_SHIFT (5U)
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#define GRF_GPIO3C_SUS_GPIO3C5_SUS_MASK (0x1U << GRF_GPIO3C_SUS_GPIO3C5_SUS_SHIFT) /* 0x00000020 */
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#define GRF_GPIO3C_SUS_GPIO3C6_SUS_SHIFT (6U)
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#define GRF_GPIO3C_SUS_GPIO3C6_SUS_MASK (0x1U << GRF_GPIO3C_SUS_GPIO3C6_SUS_SHIFT) /* 0x00000040 */
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#define GRF_GPIO3C_SUS_GPIO3C7_SUS_SHIFT (7U)
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#define GRF_GPIO3C_SUS_GPIO3C7_SUS_MASK (0x1U << GRF_GPIO3C_SUS_GPIO3C7_SUS_SHIFT) /* 0x00000080 */
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/* GPIO3D_SUS */
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#define GRF_GPIO3D_SUS_OFFSET (0x4016CU)
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#define GRF_GPIO3D_SUS_GPIO3D0_SUS_SHIFT (0U)
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#define GRF_GPIO3D_SUS_GPIO3D0_SUS_MASK (0x1U << GRF_GPIO3D_SUS_GPIO3D0_SUS_SHIFT) /* 0x00000001 */
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#define GRF_GPIO3D_SUS_GPIO3D1_SUS_SHIFT (1U)
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#define GRF_GPIO3D_SUS_GPIO3D1_SUS_MASK (0x1U << GRF_GPIO3D_SUS_GPIO3D1_SUS_SHIFT) /* 0x00000002 */
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#define GRF_GPIO3D_SUS_GPIO3D2_SUS_SHIFT (2U)
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#define GRF_GPIO3D_SUS_GPIO3D2_SUS_MASK (0x1U << GRF_GPIO3D_SUS_GPIO3D2_SUS_SHIFT) /* 0x00000004 */
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#define GRF_GPIO3D_SUS_GPIO3D3_SUS_SHIFT (3U)
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#define GRF_GPIO3D_SUS_GPIO3D3_SUS_MASK (0x1U << GRF_GPIO3D_SUS_GPIO3D3_SUS_SHIFT) /* 0x00000008 */
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#define GRF_GPIO3D_SUS_GPIO3D4_SUS_SHIFT (4U)
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#define GRF_GPIO3D_SUS_GPIO3D4_SUS_MASK (0x1U << GRF_GPIO3D_SUS_GPIO3D4_SUS_SHIFT) /* 0x00000010 */
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#define GRF_GPIO3D_SUS_GPIO3D5_SUS_SHIFT (5U)
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#define GRF_GPIO3D_SUS_GPIO3D5_SUS_MASK (0x1U << GRF_GPIO3D_SUS_GPIO3D5_SUS_SHIFT) /* 0x00000020 */
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#define GRF_GPIO3D_SUS_GPIO3D6_SUS_SHIFT (6U)
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#define GRF_GPIO3D_SUS_GPIO3D6_SUS_MASK (0x1U << GRF_GPIO3D_SUS_GPIO3D6_SUS_SHIFT) /* 0x00000040 */
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#define GRF_GPIO3D_SUS_GPIO3D7_SUS_SHIFT (7U)
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#define GRF_GPIO3D_SUS_GPIO3D7_SUS_MASK (0x1U << GRF_GPIO3D_SUS_GPIO3D7_SUS_SHIFT) /* 0x00000080 */
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/* GPIO4A_SUS */
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#define GRF_GPIO4A_SUS_OFFSET (0x40170U)
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#define GRF_GPIO4A_SUS_GPIO4A0_SUS_SHIFT (0U)
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#define GRF_GPIO4A_SUS_GPIO4A0_SUS_MASK (0x1U << GRF_GPIO4A_SUS_GPIO4A0_SUS_SHIFT) /* 0x00000001 */
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#define GRF_GPIO4A_SUS_GPIO4A1_SUS_SHIFT (1U)
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#define GRF_GPIO4A_SUS_GPIO4A1_SUS_MASK (0x1U << GRF_GPIO4A_SUS_GPIO4A1_SUS_SHIFT) /* 0x00000002 */
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#define GRF_GPIO4A_SUS_GPIO4A2_SUS_SHIFT (2U)
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#define GRF_GPIO4A_SUS_GPIO4A2_SUS_MASK (0x1U << GRF_GPIO4A_SUS_GPIO4A2_SUS_SHIFT) /* 0x00000004 */
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#define GRF_GPIO4A_SUS_GPIO4A3_SUS_SHIFT (3U)
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#define GRF_GPIO4A_SUS_GPIO4A3_SUS_MASK (0x1U << GRF_GPIO4A_SUS_GPIO4A3_SUS_SHIFT) /* 0x00000008 */
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#define GRF_GPIO4A_SUS_GPIO4A4_SUS_SHIFT (4U)
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#define GRF_GPIO4A_SUS_GPIO4A4_SUS_MASK (0x1U << GRF_GPIO4A_SUS_GPIO4A4_SUS_SHIFT) /* 0x00000010 */
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#define GRF_GPIO4A_SUS_GPIO4A5_SUS_SHIFT (5U)
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#define GRF_GPIO4A_SUS_GPIO4A5_SUS_MASK (0x1U << GRF_GPIO4A_SUS_GPIO4A5_SUS_SHIFT) /* 0x00000020 */
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#define GRF_GPIO4A_SUS_GPIO4A6_SUS_SHIFT (6U)
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#define GRF_GPIO4A_SUS_GPIO4A6_SUS_MASK (0x1U << GRF_GPIO4A_SUS_GPIO4A6_SUS_SHIFT) /* 0x00000040 */
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#define GRF_GPIO4A_SUS_GPIO4A7_SUS_SHIFT (7U)
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#define GRF_GPIO4A_SUS_GPIO4A7_SUS_MASK (0x1U << GRF_GPIO4A_SUS_GPIO4A7_SUS_SHIFT) /* 0x00000080 */
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/* GPIO4B_SUS */
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#define GRF_GPIO4B_SUS_OFFSET (0x40174U)
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#define GRF_GPIO4B_SUS_GPIO4B0_SUS_SHIFT (0U)
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#define GRF_GPIO4B_SUS_GPIO4B0_SUS_MASK (0x1U << GRF_GPIO4B_SUS_GPIO4B0_SUS_SHIFT) /* 0x00000001 */
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#define GRF_GPIO4B_SUS_GPIO4B1_SUS_SHIFT (1U)
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#define GRF_GPIO4B_SUS_GPIO4B1_SUS_MASK (0x1U << GRF_GPIO4B_SUS_GPIO4B1_SUS_SHIFT) /* 0x00000002 */
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#define GRF_GPIO4B_SUS_GPIO4B2_SUS_SHIFT (2U)
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#define GRF_GPIO4B_SUS_GPIO4B2_SUS_MASK (0x1U << GRF_GPIO4B_SUS_GPIO4B2_SUS_SHIFT) /* 0x00000004 */
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#define GRF_GPIO4B_SUS_GPIO4B3_SUS_SHIFT (3U)
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#define GRF_GPIO4B_SUS_GPIO4B3_SUS_MASK (0x1U << GRF_GPIO4B_SUS_GPIO4B3_SUS_SHIFT) /* 0x00000008 */
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#define GRF_GPIO4B_SUS_GPIO4B4_SUS_SHIFT (4U)
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#define GRF_GPIO4B_SUS_GPIO4B4_SUS_MASK (0x1U << GRF_GPIO4B_SUS_GPIO4B4_SUS_SHIFT) /* 0x00000010 */
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#define GRF_GPIO4B_SUS_GPIO4B5_SUS_SHIFT (5U)
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#define GRF_GPIO4B_SUS_GPIO4B5_SUS_MASK (0x1U << GRF_GPIO4B_SUS_GPIO4B5_SUS_SHIFT) /* 0x00000020 */
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#define GRF_GPIO4B_SUS_GPIO4B6_SUS_SHIFT (6U)
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#define GRF_GPIO4B_SUS_GPIO4B6_SUS_MASK (0x1U << GRF_GPIO4B_SUS_GPIO4B6_SUS_SHIFT) /* 0x00000040 */
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#define GRF_GPIO4B_SUS_GPIO4B7_SUS_SHIFT (7U)
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#define GRF_GPIO4B_SUS_GPIO4B7_SUS_MASK (0x1U << GRF_GPIO4B_SUS_GPIO4B7_SUS_SHIFT) /* 0x00000080 */
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/* GPIO4C_SUS */
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#define GRF_GPIO4C_SUS_OFFSET (0x40178U)
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#define GRF_GPIO4C_SUS_GPIO4C0_SUS_SHIFT (0U)
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#define GRF_GPIO4C_SUS_GPIO4C0_SUS_MASK (0x1U << GRF_GPIO4C_SUS_GPIO4C0_SUS_SHIFT) /* 0x00000001 */
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#define GRF_GPIO4C_SUS_GPIO4C1_SUS_SHIFT (1U)
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#define GRF_GPIO4C_SUS_GPIO4C1_SUS_MASK (0x1U << GRF_GPIO4C_SUS_GPIO4C1_SUS_SHIFT) /* 0x00000002 */
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#define GRF_GPIO4C_SUS_GPIO4C2_SUS_SHIFT (2U)
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#define GRF_GPIO4C_SUS_GPIO4C2_SUS_MASK (0x1U << GRF_GPIO4C_SUS_GPIO4C2_SUS_SHIFT) /* 0x00000004 */
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#define GRF_GPIO4C_SUS_GPIO4C3_SUS_SHIFT (3U)
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#define GRF_GPIO4C_SUS_GPIO4C3_SUS_MASK (0x1U << GRF_GPIO4C_SUS_GPIO4C3_SUS_SHIFT) /* 0x00000008 */
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#define GRF_GPIO4C_SUS_GPIO4C4_SUS_SHIFT (4U)
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#define GRF_GPIO4C_SUS_GPIO4C4_SUS_MASK (0x1U << GRF_GPIO4C_SUS_GPIO4C4_SUS_SHIFT) /* 0x00000010 */
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#define GRF_GPIO4C_SUS_GPIO4C5_SUS_SHIFT (5U)
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#define GRF_GPIO4C_SUS_GPIO4C5_SUS_MASK (0x1U << GRF_GPIO4C_SUS_GPIO4C5_SUS_SHIFT) /* 0x00000020 */
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#define GRF_GPIO4C_SUS_GPIO4C6_SUS_SHIFT (6U)
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#define GRF_GPIO4C_SUS_GPIO4C6_SUS_MASK (0x1U << GRF_GPIO4C_SUS_GPIO4C6_SUS_SHIFT) /* 0x00000040 */
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#define GRF_GPIO4C_SUS_GPIO4C7_SUS_SHIFT (7U)
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#define GRF_GPIO4C_SUS_GPIO4C7_SUS_MASK (0x1U << GRF_GPIO4C_SUS_GPIO4C7_SUS_SHIFT) /* 0x00000080 */
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/* GPIO4D_SUS */
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#define GRF_GPIO4D_SUS_OFFSET (0x4017CU)
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#define GRF_GPIO4D_SUS_GPIO4D0_SUS_SHIFT (0U)
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#define GRF_GPIO4D_SUS_GPIO4D0_SUS_MASK (0x1U << GRF_GPIO4D_SUS_GPIO4D0_SUS_SHIFT) /* 0x00000001 */
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#define GRF_GPIO4D_SUS_GPIO4D1_SUS_SHIFT (1U)
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#define GRF_GPIO4D_SUS_GPIO4D1_SUS_MASK (0x1U << GRF_GPIO4D_SUS_GPIO4D1_SUS_SHIFT) /* 0x00000002 */
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#define GRF_GPIO4D_SUS_GPIO4D2_SUS_SHIFT (2U)
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#define GRF_GPIO4D_SUS_GPIO4D2_SUS_MASK (0x1U << GRF_GPIO4D_SUS_GPIO4D2_SUS_SHIFT) /* 0x00000004 */
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#define GRF_GPIO4D_SUS_GPIO4D3_SUS_SHIFT (3U)
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#define GRF_GPIO4D_SUS_GPIO4D3_SUS_MASK (0x1U << GRF_GPIO4D_SUS_GPIO4D3_SUS_SHIFT) /* 0x00000008 */
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#define GRF_GPIO4D_SUS_GPIO4D4_SUS_SHIFT (4U)
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#define GRF_GPIO4D_SUS_GPIO4D4_SUS_MASK (0x1U << GRF_GPIO4D_SUS_GPIO4D4_SUS_SHIFT) /* 0x00000010 */
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#define GRF_GPIO4D_SUS_GPIO4D5_SUS_SHIFT (5U)
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#define GRF_GPIO4D_SUS_GPIO4D5_SUS_MASK (0x1U << GRF_GPIO4D_SUS_GPIO4D5_SUS_SHIFT) /* 0x00000020 */
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#define GRF_GPIO4D_SUS_GPIO4D6_SUS_SHIFT (6U)
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#define GRF_GPIO4D_SUS_GPIO4D6_SUS_MASK (0x1U << GRF_GPIO4D_SUS_GPIO4D6_SUS_SHIFT) /* 0x00000040 */
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#define GRF_GPIO4D_SUS_GPIO4D7_SUS_SHIFT (7U)
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#define GRF_GPIO4D_SUS_GPIO4D7_SUS_MASK (0x1U << GRF_GPIO4D_SUS_GPIO4D7_SUS_SHIFT) /* 0x00000080 */
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/* GPIO1A_SL */
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#define GRF_GPIO1A_SL_OFFSET (0x40180U)
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#define GRF_GPIO1A_SL_GPIO1A0_SL_SHIFT (0U)
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#define GRF_GPIO1A_SL_GPIO1A0_SL_MASK (0x3U << GRF_GPIO1A_SL_GPIO1A0_SL_SHIFT) /* 0x00000003 */
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#define GRF_GPIO1A_SL_GPIO1A1_SL_SHIFT (2U)
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#define GRF_GPIO1A_SL_GPIO1A1_SL_MASK (0x3U << GRF_GPIO1A_SL_GPIO1A1_SL_SHIFT) /* 0x0000000C */
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#define GRF_GPIO1A_SL_GPIO1A2_SL_SHIFT (4U)
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#define GRF_GPIO1A_SL_GPIO1A2_SL_MASK (0x3U << GRF_GPIO1A_SL_GPIO1A2_SL_SHIFT) /* 0x00000030 */
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#define GRF_GPIO1A_SL_GPIO1A3_SL_SHIFT (6U)
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#define GRF_GPIO1A_SL_GPIO1A3_SL_MASK (0x3U << GRF_GPIO1A_SL_GPIO1A3_SL_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO1A_SL_GPIO1A4_SL_SHIFT (8U)
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#define GRF_GPIO1A_SL_GPIO1A4_SL_MASK (0x3U << GRF_GPIO1A_SL_GPIO1A4_SL_SHIFT) /* 0x00000300 */
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#define GRF_GPIO1A_SL_GPIO1A5_SL_SHIFT (10U)
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#define GRF_GPIO1A_SL_GPIO1A5_SL_MASK (0x3U << GRF_GPIO1A_SL_GPIO1A5_SL_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO1A_SL_GPIO1A6_SL_SHIFT (12U)
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#define GRF_GPIO1A_SL_GPIO1A6_SL_MASK (0x3U << GRF_GPIO1A_SL_GPIO1A6_SL_SHIFT) /* 0x00003000 */
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#define GRF_GPIO1A_SL_GPIO1A7_SL_SHIFT (14U)
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#define GRF_GPIO1A_SL_GPIO1A7_SL_MASK (0x3U << GRF_GPIO1A_SL_GPIO1A7_SL_SHIFT) /* 0x0000C000 */
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/* GPIO1B_SL */
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#define GRF_GPIO1B_SL_OFFSET (0x40184U)
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#define GRF_GPIO1B_SL_GPIO1B0_SL_SHIFT (0U)
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#define GRF_GPIO1B_SL_GPIO1B0_SL_MASK (0x3U << GRF_GPIO1B_SL_GPIO1B0_SL_SHIFT) /* 0x00000003 */
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#define GRF_GPIO1B_SL_GPIO1B1_SL_SHIFT (2U)
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#define GRF_GPIO1B_SL_GPIO1B1_SL_MASK (0x3U << GRF_GPIO1B_SL_GPIO1B1_SL_SHIFT) /* 0x0000000C */
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#define GRF_GPIO1B_SL_GPIO1B2_SL_SHIFT (4U)
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#define GRF_GPIO1B_SL_GPIO1B2_SL_MASK (0x3U << GRF_GPIO1B_SL_GPIO1B2_SL_SHIFT) /* 0x00000030 */
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#define GRF_GPIO1B_SL_GPIO1B3_SL_SHIFT (6U)
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#define GRF_GPIO1B_SL_GPIO1B3_SL_MASK (0x3U << GRF_GPIO1B_SL_GPIO1B3_SL_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO1B_SL_GPIO1B4_SL_SHIFT (8U)
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#define GRF_GPIO1B_SL_GPIO1B4_SL_MASK (0x3U << GRF_GPIO1B_SL_GPIO1B4_SL_SHIFT) /* 0x00000300 */
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#define GRF_GPIO1B_SL_GPIO1B5_SL_SHIFT (10U)
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#define GRF_GPIO1B_SL_GPIO1B5_SL_MASK (0x3U << GRF_GPIO1B_SL_GPIO1B5_SL_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO1B_SL_GPIO1B6_SL_SHIFT (12U)
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#define GRF_GPIO1B_SL_GPIO1B6_SL_MASK (0x3U << GRF_GPIO1B_SL_GPIO1B6_SL_SHIFT) /* 0x00003000 */
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#define GRF_GPIO1B_SL_GPIO1B7_SL_SHIFT (14U)
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#define GRF_GPIO1B_SL_GPIO1B7_SL_MASK (0x3U << GRF_GPIO1B_SL_GPIO1B7_SL_SHIFT) /* 0x0000C000 */
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/* GPIO1C_SL */
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#define GRF_GPIO1C_SL_OFFSET (0x40188U)
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#define GRF_GPIO1C_SL_GPIO1C0_SL_SHIFT (0U)
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#define GRF_GPIO1C_SL_GPIO1C0_SL_MASK (0x3U << GRF_GPIO1C_SL_GPIO1C0_SL_SHIFT) /* 0x00000003 */
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#define GRF_GPIO1C_SL_GPIO1C1_SL_SHIFT (2U)
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#define GRF_GPIO1C_SL_GPIO1C1_SL_MASK (0x3U << GRF_GPIO1C_SL_GPIO1C1_SL_SHIFT) /* 0x0000000C */
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#define GRF_GPIO1C_SL_GPIO1C2_SL_SHIFT (4U)
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#define GRF_GPIO1C_SL_GPIO1C2_SL_MASK (0x3U << GRF_GPIO1C_SL_GPIO1C2_SL_SHIFT) /* 0x00000030 */
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#define GRF_GPIO1C_SL_GPIO1C3_SL_SHIFT (6U)
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#define GRF_GPIO1C_SL_GPIO1C3_SL_MASK (0x3U << GRF_GPIO1C_SL_GPIO1C3_SL_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO1C_SL_GPIO1C4_SL_SHIFT (8U)
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#define GRF_GPIO1C_SL_GPIO1C4_SL_MASK (0x3U << GRF_GPIO1C_SL_GPIO1C4_SL_SHIFT) /* 0x00000300 */
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#define GRF_GPIO1C_SL_GPIO1C5_SL_SHIFT (10U)
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#define GRF_GPIO1C_SL_GPIO1C5_SL_MASK (0x3U << GRF_GPIO1C_SL_GPIO1C5_SL_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO1C_SL_GPIO1C6_SL_SHIFT (12U)
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#define GRF_GPIO1C_SL_GPIO1C6_SL_MASK (0x3U << GRF_GPIO1C_SL_GPIO1C6_SL_SHIFT) /* 0x00003000 */
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#define GRF_GPIO1C_SL_GPIO1C7_SL_SHIFT (14U)
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#define GRF_GPIO1C_SL_GPIO1C7_SL_MASK (0x3U << GRF_GPIO1C_SL_GPIO1C7_SL_SHIFT) /* 0x0000C000 */
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/* GPIO1D_SL */
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#define GRF_GPIO1D_SL_OFFSET (0x4018CU)
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#define GRF_GPIO1D_SL_GPIO1D0_SL_SHIFT (0U)
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#define GRF_GPIO1D_SL_GPIO1D0_SL_MASK (0x3U << GRF_GPIO1D_SL_GPIO1D0_SL_SHIFT) /* 0x00000003 */
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#define GRF_GPIO1D_SL_GPIO1D1_SL_SHIFT (2U)
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#define GRF_GPIO1D_SL_GPIO1D1_SL_MASK (0x3U << GRF_GPIO1D_SL_GPIO1D1_SL_SHIFT) /* 0x0000000C */
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#define GRF_GPIO1D_SL_GPIO1D2_SL_SHIFT (4U)
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#define GRF_GPIO1D_SL_GPIO1D2_SL_MASK (0x3U << GRF_GPIO1D_SL_GPIO1D2_SL_SHIFT) /* 0x00000030 */
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#define GRF_GPIO1D_SL_GPIO1D3_SL_SHIFT (6U)
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#define GRF_GPIO1D_SL_GPIO1D3_SL_MASK (0x3U << GRF_GPIO1D_SL_GPIO1D3_SL_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO1D_SL_GPIO1D4_SL_SHIFT (8U)
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#define GRF_GPIO1D_SL_GPIO1D4_SL_MASK (0x3U << GRF_GPIO1D_SL_GPIO1D4_SL_SHIFT) /* 0x00000300 */
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#define GRF_GPIO1D_SL_GPIO1D5_SL_SHIFT (10U)
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#define GRF_GPIO1D_SL_GPIO1D5_SL_MASK (0x3U << GRF_GPIO1D_SL_GPIO1D5_SL_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO1D_SL_GPIO1D6_SL_SHIFT (12U)
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#define GRF_GPIO1D_SL_GPIO1D6_SL_MASK (0x3U << GRF_GPIO1D_SL_GPIO1D6_SL_SHIFT) /* 0x00003000 */
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#define GRF_GPIO1D_SL_GPIO1D7_SL_SHIFT (14U)
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#define GRF_GPIO1D_SL_GPIO1D7_SL_MASK (0x3U << GRF_GPIO1D_SL_GPIO1D7_SL_SHIFT) /* 0x0000C000 */
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/* GPIO2A_SL */
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#define GRF_GPIO2A_SL_OFFSET (0x40190U)
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#define GRF_GPIO2A_SL_GPIO2A0_SL_SHIFT (0U)
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#define GRF_GPIO2A_SL_GPIO2A0_SL_MASK (0x3U << GRF_GPIO2A_SL_GPIO2A0_SL_SHIFT) /* 0x00000003 */
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#define GRF_GPIO2A_SL_GPIO2A1_SL_SHIFT (2U)
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#define GRF_GPIO2A_SL_GPIO2A1_SL_MASK (0x3U << GRF_GPIO2A_SL_GPIO2A1_SL_SHIFT) /* 0x0000000C */
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#define GRF_GPIO2A_SL_GPIO2A2_SL_SHIFT (4U)
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#define GRF_GPIO2A_SL_GPIO2A2_SL_MASK (0x3U << GRF_GPIO2A_SL_GPIO2A2_SL_SHIFT) /* 0x00000030 */
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#define GRF_GPIO2A_SL_GPIO2A3_SL_SHIFT (6U)
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#define GRF_GPIO2A_SL_GPIO2A3_SL_MASK (0x3U << GRF_GPIO2A_SL_GPIO2A3_SL_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO2A_SL_GPIO2A4_SL_SHIFT (8U)
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#define GRF_GPIO2A_SL_GPIO2A4_SL_MASK (0x3U << GRF_GPIO2A_SL_GPIO2A4_SL_SHIFT) /* 0x00000300 */
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#define GRF_GPIO2A_SL_GPIO2A5_SL_SHIFT (10U)
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#define GRF_GPIO2A_SL_GPIO2A5_SL_MASK (0x3U << GRF_GPIO2A_SL_GPIO2A5_SL_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO2A_SL_GPIO2A6_SL_SHIFT (12U)
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#define GRF_GPIO2A_SL_GPIO2A6_SL_MASK (0x3U << GRF_GPIO2A_SL_GPIO2A6_SL_SHIFT) /* 0x00003000 */
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#define GRF_GPIO2A_SL_GPIO2A7_SL_SHIFT (14U)
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#define GRF_GPIO2A_SL_GPIO2A7_SL_MASK (0x3U << GRF_GPIO2A_SL_GPIO2A7_SL_SHIFT) /* 0x0000C000 */
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/* GPIO2B_SL */
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#define GRF_GPIO2B_SL_OFFSET (0x40194U)
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#define GRF_GPIO2B_SL_GPIO2B0_SL_SHIFT (0U)
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#define GRF_GPIO2B_SL_GPIO2B0_SL_MASK (0x3U << GRF_GPIO2B_SL_GPIO2B0_SL_SHIFT) /* 0x00000003 */
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#define GRF_GPIO2B_SL_GPIO2B1_SL_SHIFT (2U)
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#define GRF_GPIO2B_SL_GPIO2B1_SL_MASK (0x3U << GRF_GPIO2B_SL_GPIO2B1_SL_SHIFT) /* 0x0000000C */
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#define GRF_GPIO2B_SL_GPIO2B2_SL_SHIFT (4U)
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#define GRF_GPIO2B_SL_GPIO2B2_SL_MASK (0x3U << GRF_GPIO2B_SL_GPIO2B2_SL_SHIFT) /* 0x00000030 */
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#define GRF_GPIO2B_SL_GPIO2B3_SL_SHIFT (6U)
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#define GRF_GPIO2B_SL_GPIO2B3_SL_MASK (0x3U << GRF_GPIO2B_SL_GPIO2B3_SL_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO2B_SL_GPIO2B4_SL_SHIFT (8U)
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#define GRF_GPIO2B_SL_GPIO2B4_SL_MASK (0x3U << GRF_GPIO2B_SL_GPIO2B4_SL_SHIFT) /* 0x00000300 */
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#define GRF_GPIO2B_SL_GPIO2B5_SL_SHIFT (10U)
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#define GRF_GPIO2B_SL_GPIO2B5_SL_MASK (0x3U << GRF_GPIO2B_SL_GPIO2B5_SL_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO2B_SL_GPIO2B6_SL_SHIFT (12U)
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#define GRF_GPIO2B_SL_GPIO2B6_SL_MASK (0x3U << GRF_GPIO2B_SL_GPIO2B6_SL_SHIFT) /* 0x00003000 */
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#define GRF_GPIO2B_SL_GPIO2B7_SL_SHIFT (14U)
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#define GRF_GPIO2B_SL_GPIO2B7_SL_MASK (0x3U << GRF_GPIO2B_SL_GPIO2B7_SL_SHIFT) /* 0x0000C000 */
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/* GPIO2C_SL */
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#define GRF_GPIO2C_SL_OFFSET (0x40198U)
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#define GRF_GPIO2C_SL_GPIO2C0_SL_SHIFT (0U)
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#define GRF_GPIO2C_SL_GPIO2C0_SL_MASK (0x3U << GRF_GPIO2C_SL_GPIO2C0_SL_SHIFT) /* 0x00000003 */
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#define GRF_GPIO2C_SL_GPIO2C1_SL_SHIFT (2U)
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#define GRF_GPIO2C_SL_GPIO2C1_SL_MASK (0x3U << GRF_GPIO2C_SL_GPIO2C1_SL_SHIFT) /* 0x0000000C */
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#define GRF_GPIO2C_SL_GPIO2C2_SL_SHIFT (4U)
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#define GRF_GPIO2C_SL_GPIO2C2_SL_MASK (0x3U << GRF_GPIO2C_SL_GPIO2C2_SL_SHIFT) /* 0x00000030 */
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#define GRF_GPIO2C_SL_GPIO2C3_SL_SHIFT (6U)
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#define GRF_GPIO2C_SL_GPIO2C3_SL_MASK (0x3U << GRF_GPIO2C_SL_GPIO2C3_SL_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO2C_SL_GPIO2C4_SL_SHIFT (8U)
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#define GRF_GPIO2C_SL_GPIO2C4_SL_MASK (0x3U << GRF_GPIO2C_SL_GPIO2C4_SL_SHIFT) /* 0x00000300 */
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#define GRF_GPIO2C_SL_GPIO2C5_SL_SHIFT (10U)
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#define GRF_GPIO2C_SL_GPIO2C5_SL_MASK (0x3U << GRF_GPIO2C_SL_GPIO2C5_SL_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO2C_SL_GPIO2C6_SL_SHIFT (12U)
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#define GRF_GPIO2C_SL_GPIO2C6_SL_MASK (0x3U << GRF_GPIO2C_SL_GPIO2C6_SL_SHIFT) /* 0x00003000 */
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#define GRF_GPIO2C_SL_GPIO2C7_SL_SHIFT (14U)
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#define GRF_GPIO2C_SL_GPIO2C7_SL_MASK (0x3U << GRF_GPIO2C_SL_GPIO2C7_SL_SHIFT) /* 0x0000C000 */
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/* GPIO2D_SL */
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#define GRF_GPIO2D_SL_OFFSET (0x4019CU)
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#define GRF_GPIO2D_SL_GPIO2D0_SL_SHIFT (0U)
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#define GRF_GPIO2D_SL_GPIO2D0_SL_MASK (0x3U << GRF_GPIO2D_SL_GPIO2D0_SL_SHIFT) /* 0x00000003 */
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#define GRF_GPIO2D_SL_GPIO2D1_SL_SHIFT (2U)
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#define GRF_GPIO2D_SL_GPIO2D1_SL_MASK (0x3U << GRF_GPIO2D_SL_GPIO2D1_SL_SHIFT) /* 0x0000000C */
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#define GRF_GPIO2D_SL_GPIO2D2_SL_SHIFT (4U)
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#define GRF_GPIO2D_SL_GPIO2D2_SL_MASK (0x3U << GRF_GPIO2D_SL_GPIO2D2_SL_SHIFT) /* 0x00000030 */
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#define GRF_GPIO2D_SL_GPIO2D3_SL_SHIFT (6U)
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#define GRF_GPIO2D_SL_GPIO2D3_SL_MASK (0x3U << GRF_GPIO2D_SL_GPIO2D3_SL_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO2D_SL_GPIO2D4_SL_SHIFT (8U)
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#define GRF_GPIO2D_SL_GPIO2D4_SL_MASK (0x3U << GRF_GPIO2D_SL_GPIO2D4_SL_SHIFT) /* 0x00000300 */
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#define GRF_GPIO2D_SL_GPIO2D5_SL_SHIFT (10U)
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#define GRF_GPIO2D_SL_GPIO2D5_SL_MASK (0x3U << GRF_GPIO2D_SL_GPIO2D5_SL_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO2D_SL_GPIO2D6_SL_SHIFT (12U)
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#define GRF_GPIO2D_SL_GPIO2D6_SL_MASK (0x3U << GRF_GPIO2D_SL_GPIO2D6_SL_SHIFT) /* 0x00003000 */
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#define GRF_GPIO2D_SL_GPIO2D7_SL_SHIFT (14U)
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#define GRF_GPIO2D_SL_GPIO2D7_SL_MASK (0x3U << GRF_GPIO2D_SL_GPIO2D7_SL_SHIFT) /* 0x0000C000 */
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/* GPIO3A_SL */
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#define GRF_GPIO3A_SL_OFFSET (0x401A0U)
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#define GRF_GPIO3A_SL_GPIO3A0_SL_SHIFT (0U)
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#define GRF_GPIO3A_SL_GPIO3A0_SL_MASK (0x3U << GRF_GPIO3A_SL_GPIO3A0_SL_SHIFT) /* 0x00000003 */
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#define GRF_GPIO3A_SL_GPIO3A1_SL_SHIFT (2U)
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#define GRF_GPIO3A_SL_GPIO3A1_SL_MASK (0x3U << GRF_GPIO3A_SL_GPIO3A1_SL_SHIFT) /* 0x0000000C */
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#define GRF_GPIO3A_SL_GPIO3A2_SL_SHIFT (4U)
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#define GRF_GPIO3A_SL_GPIO3A2_SL_MASK (0x3U << GRF_GPIO3A_SL_GPIO3A2_SL_SHIFT) /* 0x00000030 */
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#define GRF_GPIO3A_SL_GPIO3A3_SL_SHIFT (6U)
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#define GRF_GPIO3A_SL_GPIO3A3_SL_MASK (0x3U << GRF_GPIO3A_SL_GPIO3A3_SL_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO3A_SL_GPIO3A4_SL_SHIFT (8U)
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#define GRF_GPIO3A_SL_GPIO3A4_SL_MASK (0x3U << GRF_GPIO3A_SL_GPIO3A4_SL_SHIFT) /* 0x00000300 */
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#define GRF_GPIO3A_SL_GPIO3A5_SL_SHIFT (10U)
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#define GRF_GPIO3A_SL_GPIO3A5_SL_MASK (0x3U << GRF_GPIO3A_SL_GPIO3A5_SL_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO3A_SL_GPIO3A6_SL_SHIFT (12U)
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#define GRF_GPIO3A_SL_GPIO3A6_SL_MASK (0x3U << GRF_GPIO3A_SL_GPIO3A6_SL_SHIFT) /* 0x00003000 */
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#define GRF_GPIO3A_SL_GPIO3A7_SL_SHIFT (14U)
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#define GRF_GPIO3A_SL_GPIO3A7_SL_MASK (0x3U << GRF_GPIO3A_SL_GPIO3A7_SL_SHIFT) /* 0x0000C000 */
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/* GPIO3B_SL */
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#define GRF_GPIO3B_SL_OFFSET (0x401A4U)
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#define GRF_GPIO3B_SL_GPIO3B0_SL_SHIFT (0U)
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#define GRF_GPIO3B_SL_GPIO3B0_SL_MASK (0x3U << GRF_GPIO3B_SL_GPIO3B0_SL_SHIFT) /* 0x00000003 */
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#define GRF_GPIO3B_SL_GPIO3B1_SL_SHIFT (2U)
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#define GRF_GPIO3B_SL_GPIO3B1_SL_MASK (0x3U << GRF_GPIO3B_SL_GPIO3B1_SL_SHIFT) /* 0x0000000C */
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#define GRF_GPIO3B_SL_GPIO3B2_SL_SHIFT (4U)
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#define GRF_GPIO3B_SL_GPIO3B2_SL_MASK (0x3U << GRF_GPIO3B_SL_GPIO3B2_SL_SHIFT) /* 0x00000030 */
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#define GRF_GPIO3B_SL_GPIO3B3_SL_SHIFT (6U)
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#define GRF_GPIO3B_SL_GPIO3B3_SL_MASK (0x3U << GRF_GPIO3B_SL_GPIO3B3_SL_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO3B_SL_GPIO3B4_SL_SHIFT (8U)
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#define GRF_GPIO3B_SL_GPIO3B4_SL_MASK (0x3U << GRF_GPIO3B_SL_GPIO3B4_SL_SHIFT) /* 0x00000300 */
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#define GRF_GPIO3B_SL_GPIO3B5_SL_SHIFT (10U)
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#define GRF_GPIO3B_SL_GPIO3B5_SL_MASK (0x3U << GRF_GPIO3B_SL_GPIO3B5_SL_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO3B_SL_GPIO3B6_SL_SHIFT (12U)
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#define GRF_GPIO3B_SL_GPIO3B6_SL_MASK (0x3U << GRF_GPIO3B_SL_GPIO3B6_SL_SHIFT) /* 0x00003000 */
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#define GRF_GPIO3B_SL_GPIO3B7_SL_SHIFT (14U)
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#define GRF_GPIO3B_SL_GPIO3B7_SL_MASK (0x3U << GRF_GPIO3B_SL_GPIO3B7_SL_SHIFT) /* 0x0000C000 */
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/* GPIO3C_SL */
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#define GRF_GPIO3C_SL_OFFSET (0x401A8U)
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#define GRF_GPIO3C_SL_GPIO3C0_SL_SHIFT (0U)
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#define GRF_GPIO3C_SL_GPIO3C0_SL_MASK (0x3U << GRF_GPIO3C_SL_GPIO3C0_SL_SHIFT) /* 0x00000003 */
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#define GRF_GPIO3C_SL_GPIO3C1_SL_SHIFT (2U)
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#define GRF_GPIO3C_SL_GPIO3C1_SL_MASK (0x3U << GRF_GPIO3C_SL_GPIO3C1_SL_SHIFT) /* 0x0000000C */
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#define GRF_GPIO3C_SL_GPIO3C2_SL_SHIFT (4U)
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#define GRF_GPIO3C_SL_GPIO3C2_SL_MASK (0x3U << GRF_GPIO3C_SL_GPIO3C2_SL_SHIFT) /* 0x00000030 */
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#define GRF_GPIO3C_SL_GPIO3C3_SL_SHIFT (6U)
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#define GRF_GPIO3C_SL_GPIO3C3_SL_MASK (0x3U << GRF_GPIO3C_SL_GPIO3C3_SL_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO3C_SL_GPIO3C4_SL_SHIFT (8U)
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#define GRF_GPIO3C_SL_GPIO3C4_SL_MASK (0x3U << GRF_GPIO3C_SL_GPIO3C4_SL_SHIFT) /* 0x00000300 */
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#define GRF_GPIO3C_SL_GPIO3C5_SL_SHIFT (10U)
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#define GRF_GPIO3C_SL_GPIO3C5_SL_MASK (0x3U << GRF_GPIO3C_SL_GPIO3C5_SL_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO3C_SL_GPIO3C6_SL_SHIFT (12U)
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#define GRF_GPIO3C_SL_GPIO3C6_SL_MASK (0x3U << GRF_GPIO3C_SL_GPIO3C6_SL_SHIFT) /* 0x00003000 */
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#define GRF_GPIO3C_SL_GPIO3C7_SL_SHIFT (14U)
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#define GRF_GPIO3C_SL_GPIO3C7_SL_MASK (0x3U << GRF_GPIO3C_SL_GPIO3C7_SL_SHIFT) /* 0x0000C000 */
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/* GPIO3D_SL */
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#define GRF_GPIO3D_SL_OFFSET (0x401ACU)
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#define GRF_GPIO3D_SL_GPIO3D0_SL_SHIFT (0U)
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#define GRF_GPIO3D_SL_GPIO3D0_SL_MASK (0x3U << GRF_GPIO3D_SL_GPIO3D0_SL_SHIFT) /* 0x00000003 */
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#define GRF_GPIO3D_SL_GPIO3D1_SL_SHIFT (2U)
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#define GRF_GPIO3D_SL_GPIO3D1_SL_MASK (0x3U << GRF_GPIO3D_SL_GPIO3D1_SL_SHIFT) /* 0x0000000C */
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#define GRF_GPIO3D_SL_GPIO3D2_SL_SHIFT (4U)
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#define GRF_GPIO3D_SL_GPIO3D2_SL_MASK (0x3U << GRF_GPIO3D_SL_GPIO3D2_SL_SHIFT) /* 0x00000030 */
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#define GRF_GPIO3D_SL_GPIO3D3_SL_SHIFT (6U)
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#define GRF_GPIO3D_SL_GPIO3D3_SL_MASK (0x3U << GRF_GPIO3D_SL_GPIO3D3_SL_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO3D_SL_GPIO3D4_SL_SHIFT (8U)
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#define GRF_GPIO3D_SL_GPIO3D4_SL_MASK (0x3U << GRF_GPIO3D_SL_GPIO3D4_SL_SHIFT) /* 0x00000300 */
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#define GRF_GPIO3D_SL_GPIO3D5_SL_SHIFT (10U)
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#define GRF_GPIO3D_SL_GPIO3D5_SL_MASK (0x3U << GRF_GPIO3D_SL_GPIO3D5_SL_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO3D_SL_GPIO3D6_SL_SHIFT (12U)
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#define GRF_GPIO3D_SL_GPIO3D6_SL_MASK (0x3U << GRF_GPIO3D_SL_GPIO3D6_SL_SHIFT) /* 0x00003000 */
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#define GRF_GPIO3D_SL_GPIO3D7_SL_SHIFT (14U)
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#define GRF_GPIO3D_SL_GPIO3D7_SL_MASK (0x3U << GRF_GPIO3D_SL_GPIO3D7_SL_SHIFT) /* 0x0000C000 */
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/* GPIO4A_SL */
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#define GRF_GPIO4A_SL_OFFSET (0x401B0U)
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#define GRF_GPIO4A_SL_GPIO4A0_SL_SHIFT (0U)
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#define GRF_GPIO4A_SL_GPIO4A0_SL_MASK (0x3U << GRF_GPIO4A_SL_GPIO4A0_SL_SHIFT) /* 0x00000003 */
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#define GRF_GPIO4A_SL_GPIO4A1_SL_SHIFT (2U)
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#define GRF_GPIO4A_SL_GPIO4A1_SL_MASK (0x3U << GRF_GPIO4A_SL_GPIO4A1_SL_SHIFT) /* 0x0000000C */
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#define GRF_GPIO4A_SL_GPIO4A2_SL_SHIFT (4U)
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#define GRF_GPIO4A_SL_GPIO4A2_SL_MASK (0x3U << GRF_GPIO4A_SL_GPIO4A2_SL_SHIFT) /* 0x00000030 */
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#define GRF_GPIO4A_SL_GPIO4A3_SL_SHIFT (6U)
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#define GRF_GPIO4A_SL_GPIO4A3_SL_MASK (0x3U << GRF_GPIO4A_SL_GPIO4A3_SL_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO4A_SL_GPIO4A4_SL_SHIFT (8U)
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#define GRF_GPIO4A_SL_GPIO4A4_SL_MASK (0x3U << GRF_GPIO4A_SL_GPIO4A4_SL_SHIFT) /* 0x00000300 */
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#define GRF_GPIO4A_SL_GPIO4A5_SL_SHIFT (10U)
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#define GRF_GPIO4A_SL_GPIO4A5_SL_MASK (0x3U << GRF_GPIO4A_SL_GPIO4A5_SL_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO4A_SL_GPIO4A6_SL_SHIFT (12U)
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#define GRF_GPIO4A_SL_GPIO4A6_SL_MASK (0x3U << GRF_GPIO4A_SL_GPIO4A6_SL_SHIFT) /* 0x00003000 */
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#define GRF_GPIO4A_SL_GPIO4A7_SL_SHIFT (14U)
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#define GRF_GPIO4A_SL_GPIO4A7_SL_MASK (0x3U << GRF_GPIO4A_SL_GPIO4A7_SL_SHIFT) /* 0x0000C000 */
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/* GPIO4B_SL */
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#define GRF_GPIO4B_SL_OFFSET (0x401B4U)
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#define GRF_GPIO4B_SL_GPIO4B0_SL_SHIFT (0U)
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#define GRF_GPIO4B_SL_GPIO4B0_SL_MASK (0x3U << GRF_GPIO4B_SL_GPIO4B0_SL_SHIFT) /* 0x00000003 */
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#define GRF_GPIO4B_SL_GPIO4B1_SL_SHIFT (2U)
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#define GRF_GPIO4B_SL_GPIO4B1_SL_MASK (0x3U << GRF_GPIO4B_SL_GPIO4B1_SL_SHIFT) /* 0x0000000C */
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#define GRF_GPIO4B_SL_GPIO4B2_SL_SHIFT (4U)
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#define GRF_GPIO4B_SL_GPIO4B2_SL_MASK (0x3U << GRF_GPIO4B_SL_GPIO4B2_SL_SHIFT) /* 0x00000030 */
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#define GRF_GPIO4B_SL_GPIO4B3_SL_SHIFT (6U)
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#define GRF_GPIO4B_SL_GPIO4B3_SL_MASK (0x3U << GRF_GPIO4B_SL_GPIO4B3_SL_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO4B_SL_GPIO4B4_SL_SHIFT (8U)
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#define GRF_GPIO4B_SL_GPIO4B4_SL_MASK (0x3U << GRF_GPIO4B_SL_GPIO4B4_SL_SHIFT) /* 0x00000300 */
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#define GRF_GPIO4B_SL_GPIO4B5_SL_SHIFT (10U)
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#define GRF_GPIO4B_SL_GPIO4B5_SL_MASK (0x3U << GRF_GPIO4B_SL_GPIO4B5_SL_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO4B_SL_GPIO4B6_SL_SHIFT (12U)
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#define GRF_GPIO4B_SL_GPIO4B6_SL_MASK (0x3U << GRF_GPIO4B_SL_GPIO4B6_SL_SHIFT) /* 0x00003000 */
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#define GRF_GPIO4B_SL_GPIO4B7_SL_SHIFT (14U)
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#define GRF_GPIO4B_SL_GPIO4B7_SL_MASK (0x3U << GRF_GPIO4B_SL_GPIO4B7_SL_SHIFT) /* 0x0000C000 */
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/* GPIO4C_SL */
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#define GRF_GPIO4C_SL_OFFSET (0x401B8U)
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#define GRF_GPIO4C_SL_GPIO4C0_SL_SHIFT (0U)
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#define GRF_GPIO4C_SL_GPIO4C0_SL_MASK (0x3U << GRF_GPIO4C_SL_GPIO4C0_SL_SHIFT) /* 0x00000003 */
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#define GRF_GPIO4C_SL_GPIO4C1_SL_SHIFT (2U)
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#define GRF_GPIO4C_SL_GPIO4C1_SL_MASK (0x3U << GRF_GPIO4C_SL_GPIO4C1_SL_SHIFT) /* 0x0000000C */
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#define GRF_GPIO4C_SL_GPIO4C2_SL_SHIFT (4U)
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#define GRF_GPIO4C_SL_GPIO4C2_SL_MASK (0x3U << GRF_GPIO4C_SL_GPIO4C2_SL_SHIFT) /* 0x00000030 */
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#define GRF_GPIO4C_SL_GPIO4C3_SL_SHIFT (6U)
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#define GRF_GPIO4C_SL_GPIO4C3_SL_MASK (0x3U << GRF_GPIO4C_SL_GPIO4C3_SL_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO4C_SL_GPIO4C4_SL_SHIFT (8U)
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#define GRF_GPIO4C_SL_GPIO4C4_SL_MASK (0x3U << GRF_GPIO4C_SL_GPIO4C4_SL_SHIFT) /* 0x00000300 */
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#define GRF_GPIO4C_SL_GPIO4C5_SL_SHIFT (10U)
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#define GRF_GPIO4C_SL_GPIO4C5_SL_MASK (0x3U << GRF_GPIO4C_SL_GPIO4C5_SL_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO4C_SL_GPIO4C6_SL_SHIFT (12U)
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#define GRF_GPIO4C_SL_GPIO4C6_SL_MASK (0x3U << GRF_GPIO4C_SL_GPIO4C6_SL_SHIFT) /* 0x00003000 */
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#define GRF_GPIO4C_SL_GPIO4C7_SL_SHIFT (14U)
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#define GRF_GPIO4C_SL_GPIO4C7_SL_MASK (0x3U << GRF_GPIO4C_SL_GPIO4C7_SL_SHIFT) /* 0x0000C000 */
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/* GPIO4D_SL */
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#define GRF_GPIO4D_SL_OFFSET (0x401BCU)
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#define GRF_GPIO4D_SL_GPIO4D0_SL_SHIFT (0U)
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#define GRF_GPIO4D_SL_GPIO4D0_SL_MASK (0x3U << GRF_GPIO4D_SL_GPIO4D0_SL_SHIFT) /* 0x00000003 */
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#define GRF_GPIO4D_SL_GPIO4D1_SL_SHIFT (2U)
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#define GRF_GPIO4D_SL_GPIO4D1_SL_MASK (0x3U << GRF_GPIO4D_SL_GPIO4D1_SL_SHIFT) /* 0x0000000C */
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#define GRF_GPIO4D_SL_GPIO4D2_SL_SHIFT (4U)
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#define GRF_GPIO4D_SL_GPIO4D2_SL_MASK (0x3U << GRF_GPIO4D_SL_GPIO4D2_SL_SHIFT) /* 0x00000030 */
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#define GRF_GPIO4D_SL_GPIO4D3_SL_SHIFT (6U)
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#define GRF_GPIO4D_SL_GPIO4D3_SL_MASK (0x3U << GRF_GPIO4D_SL_GPIO4D3_SL_SHIFT) /* 0x000000C0 */
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#define GRF_GPIO4D_SL_GPIO4D4_SL_SHIFT (8U)
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#define GRF_GPIO4D_SL_GPIO4D4_SL_MASK (0x3U << GRF_GPIO4D_SL_GPIO4D4_SL_SHIFT) /* 0x00000300 */
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#define GRF_GPIO4D_SL_GPIO4D5_SL_SHIFT (10U)
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#define GRF_GPIO4D_SL_GPIO4D5_SL_MASK (0x3U << GRF_GPIO4D_SL_GPIO4D5_SL_SHIFT) /* 0x00000C00 */
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#define GRF_GPIO4D_SL_GPIO4D6_SL_SHIFT (12U)
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#define GRF_GPIO4D_SL_GPIO4D6_SL_MASK (0x3U << GRF_GPIO4D_SL_GPIO4D6_SL_SHIFT) /* 0x00003000 */
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#define GRF_GPIO4D_SL_GPIO4D7_SL_SHIFT (14U)
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#define GRF_GPIO4D_SL_GPIO4D7_SL_MASK (0x3U << GRF_GPIO4D_SL_GPIO4D7_SL_SHIFT) /* 0x0000C000 */
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/* GPIO1A_DS_0 */
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#define GRF_GPIO1A_DS_0_OFFSET (0x40200U)
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#define GRF_GPIO1A_DS_0_GPIO1A0_DS_SHIFT (0U)
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#define GRF_GPIO1A_DS_0_GPIO1A0_DS_MASK (0x3FU << GRF_GPIO1A_DS_0_GPIO1A0_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO1A_DS_0_GPIO1A1_DS_SHIFT (8U)
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#define GRF_GPIO1A_DS_0_GPIO1A1_DS_MASK (0x3FU << GRF_GPIO1A_DS_0_GPIO1A1_DS_SHIFT) /* 0x00003F00 */
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/* GPIO1A_DS_1 */
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#define GRF_GPIO1A_DS_1_OFFSET (0x40204U)
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#define GRF_GPIO1A_DS_1_GPIO1A2_DS_SHIFT (0U)
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#define GRF_GPIO1A_DS_1_GPIO1A2_DS_MASK (0x3FU << GRF_GPIO1A_DS_1_GPIO1A2_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO1A_DS_1_GPIO1A3_DS_SHIFT (8U)
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#define GRF_GPIO1A_DS_1_GPIO1A3_DS_MASK (0x3FU << GRF_GPIO1A_DS_1_GPIO1A3_DS_SHIFT) /* 0x00003F00 */
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/* GPIO1A_DS_2 */
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#define GRF_GPIO1A_DS_2_OFFSET (0x40208U)
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#define GRF_GPIO1A_DS_2_GPIO1A4_DS_SHIFT (0U)
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#define GRF_GPIO1A_DS_2_GPIO1A4_DS_MASK (0x3FU << GRF_GPIO1A_DS_2_GPIO1A4_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO1A_DS_2_GPIO1A5_DS_SHIFT (8U)
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#define GRF_GPIO1A_DS_2_GPIO1A5_DS_MASK (0x3FU << GRF_GPIO1A_DS_2_GPIO1A5_DS_SHIFT) /* 0x00003F00 */
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/* GPIO1A_DS_3 */
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#define GRF_GPIO1A_DS_3_OFFSET (0x4020CU)
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#define GRF_GPIO1A_DS_3_GPIO1A6_DS_SHIFT (0U)
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#define GRF_GPIO1A_DS_3_GPIO1A6_DS_MASK (0x3FU << GRF_GPIO1A_DS_3_GPIO1A6_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO1A_DS_3_GPIO1A7_DS_SHIFT (8U)
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#define GRF_GPIO1A_DS_3_GPIO1A7_DS_MASK (0x3FU << GRF_GPIO1A_DS_3_GPIO1A7_DS_SHIFT) /* 0x00003F00 */
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/* GPIO1B_DS_0 */
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#define GRF_GPIO1B_DS_0_OFFSET (0x40210U)
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#define GRF_GPIO1B_DS_0_GPIO1B0_DS_SHIFT (0U)
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#define GRF_GPIO1B_DS_0_GPIO1B0_DS_MASK (0x3FU << GRF_GPIO1B_DS_0_GPIO1B0_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO1B_DS_0_GPIO1B1_DS_SHIFT (8U)
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#define GRF_GPIO1B_DS_0_GPIO1B1_DS_MASK (0x3FU << GRF_GPIO1B_DS_0_GPIO1B1_DS_SHIFT) /* 0x00003F00 */
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/* GPIO1B_DS_1 */
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#define GRF_GPIO1B_DS_1_OFFSET (0x40214U)
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#define GRF_GPIO1B_DS_1_GPIO1B2_DS_SHIFT (0U)
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#define GRF_GPIO1B_DS_1_GPIO1B2_DS_MASK (0x3FU << GRF_GPIO1B_DS_1_GPIO1B2_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO1B_DS_1_GPIO1B3_DS_SHIFT (8U)
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#define GRF_GPIO1B_DS_1_GPIO1B3_DS_MASK (0x3FU << GRF_GPIO1B_DS_1_GPIO1B3_DS_SHIFT) /* 0x00003F00 */
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/* GPIO1B_DS_2 */
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#define GRF_GPIO1B_DS_2_OFFSET (0x40218U)
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#define GRF_GPIO1B_DS_2_GPIO1B4_DS_SHIFT (0U)
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#define GRF_GPIO1B_DS_2_GPIO1B4_DS_MASK (0x3FU << GRF_GPIO1B_DS_2_GPIO1B4_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO1B_DS_2_GPIO1B5_DS_SHIFT (8U)
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#define GRF_GPIO1B_DS_2_GPIO1B5_DS_MASK (0x3FU << GRF_GPIO1B_DS_2_GPIO1B5_DS_SHIFT) /* 0x00003F00 */
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/* GPIO1B_DS_3 */
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#define GRF_GPIO1B_DS_3_OFFSET (0x4021CU)
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#define GRF_GPIO1B_DS_3_GPIO1B6_DS_SHIFT (0U)
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#define GRF_GPIO1B_DS_3_GPIO1B6_DS_MASK (0x3FU << GRF_GPIO1B_DS_3_GPIO1B6_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO1B_DS_3_GPIO1B7_DS_SHIFT (8U)
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#define GRF_GPIO1B_DS_3_GPIO1B7_DS_MASK (0x3FU << GRF_GPIO1B_DS_3_GPIO1B7_DS_SHIFT) /* 0x00003F00 */
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/* GPIO1C_DS_0 */
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#define GRF_GPIO1C_DS_0_OFFSET (0x40220U)
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#define GRF_GPIO1C_DS_0_GPIO1C0_DS_SHIFT (0U)
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#define GRF_GPIO1C_DS_0_GPIO1C0_DS_MASK (0x3FU << GRF_GPIO1C_DS_0_GPIO1C0_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO1C_DS_0_GPIO1C1_DS_SHIFT (8U)
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#define GRF_GPIO1C_DS_0_GPIO1C1_DS_MASK (0x3FU << GRF_GPIO1C_DS_0_GPIO1C1_DS_SHIFT) /* 0x00003F00 */
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/* GPIO1C_DS_1 */
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#define GRF_GPIO1C_DS_1_OFFSET (0x40224U)
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#define GRF_GPIO1C_DS_1_GPIO1C2_DS_SHIFT (0U)
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#define GRF_GPIO1C_DS_1_GPIO1C2_DS_MASK (0x3FU << GRF_GPIO1C_DS_1_GPIO1C2_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO1C_DS_1_GPIO1C3_DS_SHIFT (8U)
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#define GRF_GPIO1C_DS_1_GPIO1C3_DS_MASK (0x3FU << GRF_GPIO1C_DS_1_GPIO1C3_DS_SHIFT) /* 0x00003F00 */
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/* GPIO1C_DS_2 */
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#define GRF_GPIO1C_DS_2_OFFSET (0x40228U)
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#define GRF_GPIO1C_DS_2_GPIO1C4_DS_SHIFT (0U)
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#define GRF_GPIO1C_DS_2_GPIO1C4_DS_MASK (0x3FU << GRF_GPIO1C_DS_2_GPIO1C4_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO1C_DS_2_GPIO1C5_DS_SHIFT (8U)
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#define GRF_GPIO1C_DS_2_GPIO1C5_DS_MASK (0x3FU << GRF_GPIO1C_DS_2_GPIO1C5_DS_SHIFT) /* 0x00003F00 */
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/* GPIO1C_DS_3 */
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#define GRF_GPIO1C_DS_3_OFFSET (0x4022CU)
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#define GRF_GPIO1C_DS_3_GPIO1C6_DS_SHIFT (0U)
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#define GRF_GPIO1C_DS_3_GPIO1C6_DS_MASK (0x3FU << GRF_GPIO1C_DS_3_GPIO1C6_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO1C_DS_3_GPIO1C7_DS_SHIFT (8U)
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#define GRF_GPIO1C_DS_3_GPIO1C7_DS_MASK (0x3FU << GRF_GPIO1C_DS_3_GPIO1C7_DS_SHIFT) /* 0x00003F00 */
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/* GPIO1D_DS_0 */
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#define GRF_GPIO1D_DS_0_OFFSET (0x40230U)
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#define GRF_GPIO1D_DS_0_GPIO1D0_DS_SHIFT (0U)
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#define GRF_GPIO1D_DS_0_GPIO1D0_DS_MASK (0x3FU << GRF_GPIO1D_DS_0_GPIO1D0_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO1D_DS_0_GPIO1D1_DS_SHIFT (8U)
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#define GRF_GPIO1D_DS_0_GPIO1D1_DS_MASK (0x3FU << GRF_GPIO1D_DS_0_GPIO1D1_DS_SHIFT) /* 0x00003F00 */
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/* GPIO1D_DS_1 */
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#define GRF_GPIO1D_DS_1_OFFSET (0x40234U)
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#define GRF_GPIO1D_DS_1_GPIO1D2_DS_SHIFT (0U)
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#define GRF_GPIO1D_DS_1_GPIO1D2_DS_MASK (0x3FU << GRF_GPIO1D_DS_1_GPIO1D2_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO1D_DS_1_GPIO1D3_DS_SHIFT (8U)
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#define GRF_GPIO1D_DS_1_GPIO1D3_DS_MASK (0x3FU << GRF_GPIO1D_DS_1_GPIO1D3_DS_SHIFT) /* 0x00003F00 */
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/* GPIO1D_DS_2 */
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#define GRF_GPIO1D_DS_2_OFFSET (0x40238U)
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#define GRF_GPIO1D_DS_2_GPIO1D4_DS_SHIFT (0U)
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#define GRF_GPIO1D_DS_2_GPIO1D4_DS_MASK (0x3FU << GRF_GPIO1D_DS_2_GPIO1D4_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO1D_DS_2_GPIO1D5_DS_SHIFT (8U)
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#define GRF_GPIO1D_DS_2_GPIO1D5_DS_MASK (0x3FU << GRF_GPIO1D_DS_2_GPIO1D5_DS_SHIFT) /* 0x00003F00 */
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/* GPIO1D_DS_3 */
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#define GRF_GPIO1D_DS_3_OFFSET (0x4023CU)
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#define GRF_GPIO1D_DS_3_GPIO1D6_DS_SHIFT (0U)
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#define GRF_GPIO1D_DS_3_GPIO1D6_DS_MASK (0x3FU << GRF_GPIO1D_DS_3_GPIO1D6_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO1D_DS_3_GPIO1D7_DS_SHIFT (8U)
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#define GRF_GPIO1D_DS_3_GPIO1D7_DS_MASK (0x3FU << GRF_GPIO1D_DS_3_GPIO1D7_DS_SHIFT) /* 0x00003F00 */
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/* GPIO2A_DS_0 */
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#define GRF_GPIO2A_DS_0_OFFSET (0x40240U)
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#define GRF_GPIO2A_DS_0_GPIO2A0_DS_SHIFT (0U)
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#define GRF_GPIO2A_DS_0_GPIO2A0_DS_MASK (0x3FU << GRF_GPIO2A_DS_0_GPIO2A0_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO2A_DS_0_GPIO2A1_DS_SHIFT (8U)
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#define GRF_GPIO2A_DS_0_GPIO2A1_DS_MASK (0x3FU << GRF_GPIO2A_DS_0_GPIO2A1_DS_SHIFT) /* 0x00003F00 */
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/* GPIO2A_DS_1 */
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#define GRF_GPIO2A_DS_1_OFFSET (0x40244U)
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#define GRF_GPIO2A_DS_1_GPIO2A2_DS_SHIFT (0U)
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#define GRF_GPIO2A_DS_1_GPIO2A2_DS_MASK (0x3FU << GRF_GPIO2A_DS_1_GPIO2A2_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO2A_DS_1_GPIO2A3_DS_SHIFT (8U)
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#define GRF_GPIO2A_DS_1_GPIO2A3_DS_MASK (0x3FU << GRF_GPIO2A_DS_1_GPIO2A3_DS_SHIFT) /* 0x00003F00 */
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/* GPIO2A_DS_2 */
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#define GRF_GPIO2A_DS_2_OFFSET (0x40248U)
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#define GRF_GPIO2A_DS_2_GPIO2A4_DS_SHIFT (0U)
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#define GRF_GPIO2A_DS_2_GPIO2A4_DS_MASK (0x3FU << GRF_GPIO2A_DS_2_GPIO2A4_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO2A_DS_2_GPIO2A5_DS_SHIFT (8U)
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#define GRF_GPIO2A_DS_2_GPIO2A5_DS_MASK (0x3FU << GRF_GPIO2A_DS_2_GPIO2A5_DS_SHIFT) /* 0x00003F00 */
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/* GPIO2A_DS_3 */
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#define GRF_GPIO2A_DS_3_OFFSET (0x4024CU)
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#define GRF_GPIO2A_DS_3_GPIO2A6_DS_SHIFT (0U)
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#define GRF_GPIO2A_DS_3_GPIO2A6_DS_MASK (0x3FU << GRF_GPIO2A_DS_3_GPIO2A6_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO2A_DS_3_GPIO2A7_DS_SHIFT (8U)
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#define GRF_GPIO2A_DS_3_GPIO2A7_DS_MASK (0x3FU << GRF_GPIO2A_DS_3_GPIO2A7_DS_SHIFT) /* 0x00003F00 */
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/* GPIO2B_DS_0 */
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#define GRF_GPIO2B_DS_0_OFFSET (0x40250U)
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#define GRF_GPIO2B_DS_0_GPIO2B0_DS_SHIFT (0U)
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#define GRF_GPIO2B_DS_0_GPIO2B0_DS_MASK (0x3FU << GRF_GPIO2B_DS_0_GPIO2B0_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO2B_DS_0_GPIO2B1_DS_SHIFT (8U)
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#define GRF_GPIO2B_DS_0_GPIO2B1_DS_MASK (0x3FU << GRF_GPIO2B_DS_0_GPIO2B1_DS_SHIFT) /* 0x00003F00 */
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/* GPIO2B_DS_1 */
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#define GRF_GPIO2B_DS_1_OFFSET (0x40254U)
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#define GRF_GPIO2B_DS_1_GPIO2B2_DS_SHIFT (0U)
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#define GRF_GPIO2B_DS_1_GPIO2B2_DS_MASK (0x3FU << GRF_GPIO2B_DS_1_GPIO2B2_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO2B_DS_1_GPIO2B3_DS_SHIFT (8U)
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#define GRF_GPIO2B_DS_1_GPIO2B3_DS_MASK (0x3FU << GRF_GPIO2B_DS_1_GPIO2B3_DS_SHIFT) /* 0x00003F00 */
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/* GPIO2B_DS_2 */
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#define GRF_GPIO2B_DS_2_OFFSET (0x40258U)
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#define GRF_GPIO2B_DS_2_GPIO2B4_DS_SHIFT (0U)
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#define GRF_GPIO2B_DS_2_GPIO2B4_DS_MASK (0x3FU << GRF_GPIO2B_DS_2_GPIO2B4_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO2B_DS_2_GPIO2B5_DS_SHIFT (8U)
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#define GRF_GPIO2B_DS_2_GPIO2B5_DS_MASK (0x3FU << GRF_GPIO2B_DS_2_GPIO2B5_DS_SHIFT) /* 0x00003F00 */
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/* GPIO2B_DS_3 */
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#define GRF_GPIO2B_DS_3_OFFSET (0x4025CU)
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#define GRF_GPIO2B_DS_3_GPIO2B6_DS_SHIFT (0U)
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#define GRF_GPIO2B_DS_3_GPIO2B6_DS_MASK (0x3FU << GRF_GPIO2B_DS_3_GPIO2B6_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO2B_DS_3_GPIO2B7_DS_SHIFT (8U)
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#define GRF_GPIO2B_DS_3_GPIO2B7_DS_MASK (0x3FU << GRF_GPIO2B_DS_3_GPIO2B7_DS_SHIFT) /* 0x00003F00 */
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/* GPIO2C_DS_0 */
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#define GRF_GPIO2C_DS_0_OFFSET (0x40260U)
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#define GRF_GPIO2C_DS_0_GPIO2C0_DS_SHIFT (0U)
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#define GRF_GPIO2C_DS_0_GPIO2C0_DS_MASK (0x3FU << GRF_GPIO2C_DS_0_GPIO2C0_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO2C_DS_0_GPIO2C1_DS_SHIFT (8U)
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#define GRF_GPIO2C_DS_0_GPIO2C1_DS_MASK (0x3FU << GRF_GPIO2C_DS_0_GPIO2C1_DS_SHIFT) /* 0x00003F00 */
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/* GPIO2C_DS_1 */
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#define GRF_GPIO2C_DS_1_OFFSET (0x40264U)
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#define GRF_GPIO2C_DS_1_GPIO2C2_DS_SHIFT (0U)
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#define GRF_GPIO2C_DS_1_GPIO2C2_DS_MASK (0x3FU << GRF_GPIO2C_DS_1_GPIO2C2_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO2C_DS_1_GPIO2C3_DS_SHIFT (8U)
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#define GRF_GPIO2C_DS_1_GPIO2C3_DS_MASK (0x3FU << GRF_GPIO2C_DS_1_GPIO2C3_DS_SHIFT) /* 0x00003F00 */
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/* GPIO2C_DS_2 */
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#define GRF_GPIO2C_DS_2_OFFSET (0x40268U)
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#define GRF_GPIO2C_DS_2_GPIO2C4_DS_SHIFT (0U)
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#define GRF_GPIO2C_DS_2_GPIO2C4_DS_MASK (0x3FU << GRF_GPIO2C_DS_2_GPIO2C4_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO2C_DS_2_GPIO2C5_DS_SHIFT (8U)
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#define GRF_GPIO2C_DS_2_GPIO2C5_DS_MASK (0x3FU << GRF_GPIO2C_DS_2_GPIO2C5_DS_SHIFT) /* 0x00003F00 */
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/* GPIO2C_DS_3 */
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#define GRF_GPIO2C_DS_3_OFFSET (0x4026CU)
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#define GRF_GPIO2C_DS_3_GPIO2C6_DS_SHIFT (0U)
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#define GRF_GPIO2C_DS_3_GPIO2C6_DS_MASK (0x3FU << GRF_GPIO2C_DS_3_GPIO2C6_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO2C_DS_3_GPIO2C7_DS_SHIFT (8U)
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#define GRF_GPIO2C_DS_3_GPIO2C7_DS_MASK (0x3FU << GRF_GPIO2C_DS_3_GPIO2C7_DS_SHIFT) /* 0x00003F00 */
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/* GPIO2D_DS_0 */
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#define GRF_GPIO2D_DS_0_OFFSET (0x40270U)
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#define GRF_GPIO2D_DS_0_GPIO2D0_DS_SHIFT (0U)
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#define GRF_GPIO2D_DS_0_GPIO2D0_DS_MASK (0x3FU << GRF_GPIO2D_DS_0_GPIO2D0_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO2D_DS_0_GPIO2D1_DS_SHIFT (8U)
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#define GRF_GPIO2D_DS_0_GPIO2D1_DS_MASK (0x3FU << GRF_GPIO2D_DS_0_GPIO2D1_DS_SHIFT) /* 0x00003F00 */
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/* GPIO2D_DS_1 */
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#define GRF_GPIO2D_DS_1_OFFSET (0x40274U)
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#define GRF_GPIO2D_DS_1_GPIO2D2_DS_SHIFT (0U)
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#define GRF_GPIO2D_DS_1_GPIO2D2_DS_MASK (0x3FU << GRF_GPIO2D_DS_1_GPIO2D2_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO2D_DS_1_GPIO2D3_DS_SHIFT (8U)
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#define GRF_GPIO2D_DS_1_GPIO2D3_DS_MASK (0x3FU << GRF_GPIO2D_DS_1_GPIO2D3_DS_SHIFT) /* 0x00003F00 */
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/* GPIO2D_DS_2 */
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#define GRF_GPIO2D_DS_2_OFFSET (0x40278U)
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#define GRF_GPIO2D_DS_2_GPIO2D4_DS_SHIFT (0U)
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#define GRF_GPIO2D_DS_2_GPIO2D4_DS_MASK (0x3FU << GRF_GPIO2D_DS_2_GPIO2D4_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO2D_DS_2_GPIO2D5_DS_SHIFT (8U)
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#define GRF_GPIO2D_DS_2_GPIO2D5_DS_MASK (0x3FU << GRF_GPIO2D_DS_2_GPIO2D5_DS_SHIFT) /* 0x00003F00 */
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/* GPIO2D_DS_3 */
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#define GRF_GPIO2D_DS_3_OFFSET (0x4027CU)
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#define GRF_GPIO2D_DS_3_GPIO2D6_DS_SHIFT (0U)
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#define GRF_GPIO2D_DS_3_GPIO2D6_DS_MASK (0x3FU << GRF_GPIO2D_DS_3_GPIO2D6_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO2D_DS_3_GPIO2D7_DS_SHIFT (8U)
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#define GRF_GPIO2D_DS_3_GPIO2D7_DS_MASK (0x3FU << GRF_GPIO2D_DS_3_GPIO2D7_DS_SHIFT) /* 0x00003F00 */
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/* GPIO3A_DS_0 */
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#define GRF_GPIO3A_DS_0_OFFSET (0x40280U)
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#define GRF_GPIO3A_DS_0_GPIO3A0_DS_SHIFT (0U)
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#define GRF_GPIO3A_DS_0_GPIO3A0_DS_MASK (0x3FU << GRF_GPIO3A_DS_0_GPIO3A0_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO3A_DS_0_GPIO3A1_DS_SHIFT (8U)
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#define GRF_GPIO3A_DS_0_GPIO3A1_DS_MASK (0x3FU << GRF_GPIO3A_DS_0_GPIO3A1_DS_SHIFT) /* 0x00003F00 */
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/* GPIO3A_DS_1 */
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#define GRF_GPIO3A_DS_1_OFFSET (0x40284U)
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#define GRF_GPIO3A_DS_1_GPIO3A2_DS_SHIFT (0U)
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#define GRF_GPIO3A_DS_1_GPIO3A2_DS_MASK (0x3FU << GRF_GPIO3A_DS_1_GPIO3A2_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO3A_DS_1_GPIO3A3_DS_SHIFT (8U)
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#define GRF_GPIO3A_DS_1_GPIO3A3_DS_MASK (0x3FU << GRF_GPIO3A_DS_1_GPIO3A3_DS_SHIFT) /* 0x00003F00 */
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/* GPIO3A_DS_2 */
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#define GRF_GPIO3A_DS_2_OFFSET (0x40288U)
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#define GRF_GPIO3A_DS_2_GPIO3A4_DS_SHIFT (0U)
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#define GRF_GPIO3A_DS_2_GPIO3A4_DS_MASK (0x3FU << GRF_GPIO3A_DS_2_GPIO3A4_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO3A_DS_2_GPIO3A5_DS_SHIFT (8U)
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#define GRF_GPIO3A_DS_2_GPIO3A5_DS_MASK (0x3FU << GRF_GPIO3A_DS_2_GPIO3A5_DS_SHIFT) /* 0x00003F00 */
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/* GPIO3A_DS_3 */
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#define GRF_GPIO3A_DS_3_OFFSET (0x4028CU)
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#define GRF_GPIO3A_DS_3_GPIO3A6_DS_SHIFT (0U)
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#define GRF_GPIO3A_DS_3_GPIO3A6_DS_MASK (0x3FU << GRF_GPIO3A_DS_3_GPIO3A6_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO3A_DS_3_GPIO3A7_DS_SHIFT (8U)
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#define GRF_GPIO3A_DS_3_GPIO3A7_DS_MASK (0x3FU << GRF_GPIO3A_DS_3_GPIO3A7_DS_SHIFT) /* 0x00003F00 */
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/* GPIO3B_DS_0 */
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#define GRF_GPIO3B_DS_0_OFFSET (0x40290U)
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#define GRF_GPIO3B_DS_0_GPIO3B0_DS_SHIFT (0U)
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#define GRF_GPIO3B_DS_0_GPIO3B0_DS_MASK (0x3FU << GRF_GPIO3B_DS_0_GPIO3B0_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO3B_DS_0_GPIO3B1_DS_SHIFT (8U)
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#define GRF_GPIO3B_DS_0_GPIO3B1_DS_MASK (0x3FU << GRF_GPIO3B_DS_0_GPIO3B1_DS_SHIFT) /* 0x00003F00 */
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/* GPIO3B_DS_1 */
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#define GRF_GPIO3B_DS_1_OFFSET (0x40294U)
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#define GRF_GPIO3B_DS_1_GPIO3B2_DS_SHIFT (0U)
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#define GRF_GPIO3B_DS_1_GPIO3B2_DS_MASK (0x3FU << GRF_GPIO3B_DS_1_GPIO3B2_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO3B_DS_1_GPIO3B3_DS_SHIFT (8U)
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#define GRF_GPIO3B_DS_1_GPIO3B3_DS_MASK (0x3FU << GRF_GPIO3B_DS_1_GPIO3B3_DS_SHIFT) /* 0x00003F00 */
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/* GPIO3B_DS_2 */
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#define GRF_GPIO3B_DS_2_OFFSET (0x40298U)
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#define GRF_GPIO3B_DS_2_GPIO3B4_DS_SHIFT (0U)
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#define GRF_GPIO3B_DS_2_GPIO3B4_DS_MASK (0x3FU << GRF_GPIO3B_DS_2_GPIO3B4_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO3B_DS_2_GPIO3B5_DS_SHIFT (8U)
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#define GRF_GPIO3B_DS_2_GPIO3B5_DS_MASK (0x3FU << GRF_GPIO3B_DS_2_GPIO3B5_DS_SHIFT) /* 0x00003F00 */
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/* GPIO3B_DS_3 */
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#define GRF_GPIO3B_DS_3_OFFSET (0x4029CU)
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#define GRF_GPIO3B_DS_3_GPIO3B6_DS_SHIFT (0U)
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#define GRF_GPIO3B_DS_3_GPIO3B6_DS_MASK (0x3FU << GRF_GPIO3B_DS_3_GPIO3B6_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO3B_DS_3_GPIO3B7_DS_SHIFT (8U)
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#define GRF_GPIO3B_DS_3_GPIO3B7_DS_MASK (0x3FU << GRF_GPIO3B_DS_3_GPIO3B7_DS_SHIFT) /* 0x00003F00 */
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/* GPIO3C_DS_0 */
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#define GRF_GPIO3C_DS_0_OFFSET (0x402A0U)
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#define GRF_GPIO3C_DS_0_GPIO3C0_DS_SHIFT (0U)
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#define GRF_GPIO3C_DS_0_GPIO3C0_DS_MASK (0x3FU << GRF_GPIO3C_DS_0_GPIO3C0_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO3C_DS_0_GPIO3C1_DS_SHIFT (8U)
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#define GRF_GPIO3C_DS_0_GPIO3C1_DS_MASK (0x3FU << GRF_GPIO3C_DS_0_GPIO3C1_DS_SHIFT) /* 0x00003F00 */
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/* GPIO3C_DS_1 */
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#define GRF_GPIO3C_DS_1_OFFSET (0x402A4U)
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#define GRF_GPIO3C_DS_1_GPIO3C2_DS_SHIFT (0U)
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#define GRF_GPIO3C_DS_1_GPIO3C2_DS_MASK (0x3FU << GRF_GPIO3C_DS_1_GPIO3C2_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO3C_DS_1_GPIO3C3_DS_SHIFT (8U)
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#define GRF_GPIO3C_DS_1_GPIO3C3_DS_MASK (0x3FU << GRF_GPIO3C_DS_1_GPIO3C3_DS_SHIFT) /* 0x00003F00 */
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/* GPIO3C_DS_2 */
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#define GRF_GPIO3C_DS_2_OFFSET (0x402A8U)
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#define GRF_GPIO3C_DS_2_GPIO3C4_DS_SHIFT (0U)
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#define GRF_GPIO3C_DS_2_GPIO3C4_DS_MASK (0x3FU << GRF_GPIO3C_DS_2_GPIO3C4_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO3C_DS_2_GPIO3C5_DS_SHIFT (8U)
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#define GRF_GPIO3C_DS_2_GPIO3C5_DS_MASK (0x3FU << GRF_GPIO3C_DS_2_GPIO3C5_DS_SHIFT) /* 0x00003F00 */
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/* GPIO3C_DS_3 */
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#define GRF_GPIO3C_DS_3_OFFSET (0x402ACU)
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#define GRF_GPIO3C_DS_3_GPIO3C6_DS_SHIFT (0U)
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#define GRF_GPIO3C_DS_3_GPIO3C6_DS_MASK (0x3FU << GRF_GPIO3C_DS_3_GPIO3C6_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO3C_DS_3_GPIO3C7_DS_SHIFT (8U)
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#define GRF_GPIO3C_DS_3_GPIO3C7_DS_MASK (0x3FU << GRF_GPIO3C_DS_3_GPIO3C7_DS_SHIFT) /* 0x00003F00 */
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/* GPIO3D_DS_0 */
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#define GRF_GPIO3D_DS_0_OFFSET (0x402B0U)
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#define GRF_GPIO3D_DS_0_GPIO3D0_DS_SHIFT (0U)
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#define GRF_GPIO3D_DS_0_GPIO3D0_DS_MASK (0x3FU << GRF_GPIO3D_DS_0_GPIO3D0_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO3D_DS_0_GPIO3D1_DS_SHIFT (8U)
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#define GRF_GPIO3D_DS_0_GPIO3D1_DS_MASK (0x3FU << GRF_GPIO3D_DS_0_GPIO3D1_DS_SHIFT) /* 0x00003F00 */
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/* GPIO3D_DS_1 */
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#define GRF_GPIO3D_DS_1_OFFSET (0x402B4U)
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#define GRF_GPIO3D_DS_1_GPIO3D2_DS_SHIFT (0U)
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#define GRF_GPIO3D_DS_1_GPIO3D2_DS_MASK (0x3FU << GRF_GPIO3D_DS_1_GPIO3D2_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO3D_DS_1_GPIO3D3_DS_SHIFT (8U)
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#define GRF_GPIO3D_DS_1_GPIO3D3_DS_MASK (0x3FU << GRF_GPIO3D_DS_1_GPIO3D3_DS_SHIFT) /* 0x00003F00 */
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/* GPIO3D_DS_2 */
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#define GRF_GPIO3D_DS_2_OFFSET (0x402B8U)
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#define GRF_GPIO3D_DS_2_GPIO3D4_DS_SHIFT (0U)
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#define GRF_GPIO3D_DS_2_GPIO3D4_DS_MASK (0x3FU << GRF_GPIO3D_DS_2_GPIO3D4_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO3D_DS_2_GPIO3D5_DS_SHIFT (8U)
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#define GRF_GPIO3D_DS_2_GPIO3D5_DS_MASK (0x3FU << GRF_GPIO3D_DS_2_GPIO3D5_DS_SHIFT) /* 0x00003F00 */
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/* GPIO3D_DS_3 */
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#define GRF_GPIO3D_DS_3_OFFSET (0x402BCU)
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#define GRF_GPIO3D_DS_3_GPIO3D6_DS_SHIFT (0U)
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#define GRF_GPIO3D_DS_3_GPIO3D6_DS_MASK (0x3FU << GRF_GPIO3D_DS_3_GPIO3D6_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO3D_DS_3_GPIO3D7_DS_SHIFT (8U)
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#define GRF_GPIO3D_DS_3_GPIO3D7_DS_MASK (0x3FU << GRF_GPIO3D_DS_3_GPIO3D7_DS_SHIFT) /* 0x00003F00 */
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/* GPIO4A_DS_0 */
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#define GRF_GPIO4A_DS_0_OFFSET (0x402C0U)
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#define GRF_GPIO4A_DS_0_GPIO4A0_DS_SHIFT (0U)
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#define GRF_GPIO4A_DS_0_GPIO4A0_DS_MASK (0x3FU << GRF_GPIO4A_DS_0_GPIO4A0_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO4A_DS_0_GPIO4A1_DS_SHIFT (8U)
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#define GRF_GPIO4A_DS_0_GPIO4A1_DS_MASK (0x3FU << GRF_GPIO4A_DS_0_GPIO4A1_DS_SHIFT) /* 0x00003F00 */
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/* GPIO4A_DS_1 */
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#define GRF_GPIO4A_DS_1_OFFSET (0x402C4U)
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#define GRF_GPIO4A_DS_1_GPIO4A2_DS_SHIFT (0U)
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#define GRF_GPIO4A_DS_1_GPIO4A2_DS_MASK (0x3FU << GRF_GPIO4A_DS_1_GPIO4A2_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO4A_DS_1_GPIO4A3_DS_SHIFT (8U)
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#define GRF_GPIO4A_DS_1_GPIO4A3_DS_MASK (0x3FU << GRF_GPIO4A_DS_1_GPIO4A3_DS_SHIFT) /* 0x00003F00 */
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/* GPIO4A_DS_2 */
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#define GRF_GPIO4A_DS_2_OFFSET (0x402C8U)
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#define GRF_GPIO4A_DS_2_GPIO4A4_DS_SHIFT (0U)
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#define GRF_GPIO4A_DS_2_GPIO4A4_DS_MASK (0x3FU << GRF_GPIO4A_DS_2_GPIO4A4_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO4A_DS_2_GPIO4A5_DS_SHIFT (8U)
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#define GRF_GPIO4A_DS_2_GPIO4A5_DS_MASK (0x3FU << GRF_GPIO4A_DS_2_GPIO4A5_DS_SHIFT) /* 0x00003F00 */
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/* GPIO4A_DS_3 */
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#define GRF_GPIO4A_DS_3_OFFSET (0x402CCU)
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#define GRF_GPIO4A_DS_3_GPIO4A6_DS_SHIFT (0U)
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#define GRF_GPIO4A_DS_3_GPIO4A6_DS_MASK (0x3FU << GRF_GPIO4A_DS_3_GPIO4A6_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO4A_DS_3_GPIO4A7_DS_SHIFT (8U)
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#define GRF_GPIO4A_DS_3_GPIO4A7_DS_MASK (0x3FU << GRF_GPIO4A_DS_3_GPIO4A7_DS_SHIFT) /* 0x00003F00 */
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/* GPIO4B_DS_0 */
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#define GRF_GPIO4B_DS_0_OFFSET (0x402D0U)
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#define GRF_GPIO4B_DS_0_GPIO4B0_DS_SHIFT (0U)
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#define GRF_GPIO4B_DS_0_GPIO4B0_DS_MASK (0x3FU << GRF_GPIO4B_DS_0_GPIO4B0_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO4B_DS_0_GPIO4B1_DS_SHIFT (8U)
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#define GRF_GPIO4B_DS_0_GPIO4B1_DS_MASK (0x3FU << GRF_GPIO4B_DS_0_GPIO4B1_DS_SHIFT) /* 0x00003F00 */
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/* GPIO4B_DS_1 */
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#define GRF_GPIO4B_DS_1_OFFSET (0x402D4U)
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#define GRF_GPIO4B_DS_1_GPIO4B2_DS_SHIFT (0U)
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#define GRF_GPIO4B_DS_1_GPIO4B2_DS_MASK (0x3FU << GRF_GPIO4B_DS_1_GPIO4B2_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO4B_DS_1_GPIO4B3_DS_SHIFT (8U)
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#define GRF_GPIO4B_DS_1_GPIO4B3_DS_MASK (0x3FU << GRF_GPIO4B_DS_1_GPIO4B3_DS_SHIFT) /* 0x00003F00 */
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/* GPIO4B_DS_2 */
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#define GRF_GPIO4B_DS_2_OFFSET (0x402D8U)
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#define GRF_GPIO4B_DS_2_GPIO4B4_DS_SHIFT (0U)
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#define GRF_GPIO4B_DS_2_GPIO4B4_DS_MASK (0x3FU << GRF_GPIO4B_DS_2_GPIO4B4_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO4B_DS_2_GPIO4B5_DS_SHIFT (8U)
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#define GRF_GPIO4B_DS_2_GPIO4B5_DS_MASK (0x3FU << GRF_GPIO4B_DS_2_GPIO4B5_DS_SHIFT) /* 0x00003F00 */
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/* GPIO4B_DS_3 */
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#define GRF_GPIO4B_DS_3_OFFSET (0x402DCU)
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#define GRF_GPIO4B_DS_3_GPIO4B6_DS_SHIFT (0U)
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#define GRF_GPIO4B_DS_3_GPIO4B6_DS_MASK (0x3FU << GRF_GPIO4B_DS_3_GPIO4B6_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO4B_DS_3_GPIO4B7_DS_SHIFT (8U)
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#define GRF_GPIO4B_DS_3_GPIO4B7_DS_MASK (0x3FU << GRF_GPIO4B_DS_3_GPIO4B7_DS_SHIFT) /* 0x00003F00 */
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/* GPIO4C_DS_0 */
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#define GRF_GPIO4C_DS_0_OFFSET (0x402E0U)
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#define GRF_GPIO4C_DS_0_GPIO4C0_DS_SHIFT (0U)
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#define GRF_GPIO4C_DS_0_GPIO4C0_DS_MASK (0x3FU << GRF_GPIO4C_DS_0_GPIO4C0_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO4C_DS_0_GPIO4C1_DS_SHIFT (8U)
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#define GRF_GPIO4C_DS_0_GPIO4C1_DS_MASK (0x3FU << GRF_GPIO4C_DS_0_GPIO4C1_DS_SHIFT) /* 0x00003F00 */
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/* GPIO4C_DS_1 */
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#define GRF_GPIO4C_DS_1_OFFSET (0x402E4U)
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#define GRF_GPIO4C_DS_1_GPIO4C2_DS_SHIFT (0U)
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#define GRF_GPIO4C_DS_1_GPIO4C2_DS_MASK (0x3FU << GRF_GPIO4C_DS_1_GPIO4C2_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO4C_DS_1_GPIO4C3_DS_SHIFT (8U)
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#define GRF_GPIO4C_DS_1_GPIO4C3_DS_MASK (0x3FU << GRF_GPIO4C_DS_1_GPIO4C3_DS_SHIFT) /* 0x00003F00 */
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/* GPIO4C_DS_2 */
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#define GRF_GPIO4C_DS_2_OFFSET (0x402E8U)
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#define GRF_GPIO4C_DS_2_GPIO4C4_DS_SHIFT (0U)
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#define GRF_GPIO4C_DS_2_GPIO4C4_DS_MASK (0x3FU << GRF_GPIO4C_DS_2_GPIO4C4_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO4C_DS_2_GPIO4C5_DS_SHIFT (8U)
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#define GRF_GPIO4C_DS_2_GPIO4C5_DS_MASK (0x3FU << GRF_GPIO4C_DS_2_GPIO4C5_DS_SHIFT) /* 0x00003F00 */
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/* GPIO4C_DS_3 */
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#define GRF_GPIO4C_DS_3_OFFSET (0x402ECU)
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#define GRF_GPIO4C_DS_3_GPIO4C6_DS_SHIFT (0U)
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#define GRF_GPIO4C_DS_3_GPIO4C6_DS_MASK (0x3FU << GRF_GPIO4C_DS_3_GPIO4C6_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO4C_DS_3_GPIO4C7_DS_SHIFT (8U)
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#define GRF_GPIO4C_DS_3_GPIO4C7_DS_MASK (0x3FU << GRF_GPIO4C_DS_3_GPIO4C7_DS_SHIFT) /* 0x00003F00 */
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/* GPIO4D_DS_0 */
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#define GRF_GPIO4D_DS_0_OFFSET (0x402F0U)
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#define GRF_GPIO4D_DS_0_GPIO4D0_DS_SHIFT (0U)
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#define GRF_GPIO4D_DS_0_GPIO4D0_DS_MASK (0x3FU << GRF_GPIO4D_DS_0_GPIO4D0_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO4D_DS_0_GPIO4D1_DS_SHIFT (8U)
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#define GRF_GPIO4D_DS_0_GPIO4D1_DS_MASK (0x3FU << GRF_GPIO4D_DS_0_GPIO4D1_DS_SHIFT) /* 0x00003F00 */
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/* GPIO4D_DS_1 */
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#define GRF_GPIO4D_DS_1_OFFSET (0x402F4U)
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#define GRF_GPIO4D_DS_1_GPIO4D2_DS_SHIFT (0U)
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#define GRF_GPIO4D_DS_1_GPIO4D2_DS_MASK (0x3FU << GRF_GPIO4D_DS_1_GPIO4D2_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO4D_DS_1_GPIO4D3_DS_SHIFT (8U)
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#define GRF_GPIO4D_DS_1_GPIO4D3_DS_MASK (0x3FU << GRF_GPIO4D_DS_1_GPIO4D3_DS_SHIFT) /* 0x00003F00 */
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/* GPIO4D_DS_2 */
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#define GRF_GPIO4D_DS_2_OFFSET (0x402F8U)
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#define GRF_GPIO4D_DS_2_GPIO4D4_DS_SHIFT (0U)
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#define GRF_GPIO4D_DS_2_GPIO4D4_DS_MASK (0x3FU << GRF_GPIO4D_DS_2_GPIO4D4_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO4D_DS_2_GPIO4D5_DS_SHIFT (8U)
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#define GRF_GPIO4D_DS_2_GPIO4D5_DS_MASK (0x3FU << GRF_GPIO4D_DS_2_GPIO4D5_DS_SHIFT) /* 0x00003F00 */
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/* GPIO4D_DS_3 */
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#define GRF_GPIO4D_DS_3_OFFSET (0x402FCU)
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#define GRF_GPIO4D_DS_3_GPIO4D6_DS_SHIFT (0U)
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#define GRF_GPIO4D_DS_3_GPIO4D6_DS_MASK (0x3FU << GRF_GPIO4D_DS_3_GPIO4D6_DS_SHIFT) /* 0x0000003F */
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#define GRF_GPIO4D_DS_3_GPIO4D7_DS_SHIFT (8U)
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#define GRF_GPIO4D_DS_3_GPIO4D7_DS_MASK (0x3FU << GRF_GPIO4D_DS_3_GPIO4D7_DS_SHIFT) /* 0x00003F00 */
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/* IOFUNC_SEL0 */
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#define GRF_IOFUNC_SEL0_OFFSET (0x40300U)
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#define GRF_IOFUNC_SEL0_CAN0_IOMUX_SEL_SHIFT (0U)
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#define GRF_IOFUNC_SEL0_CAN0_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL0_CAN0_IOMUX_SEL_SHIFT) /* 0x00000001 */
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#define GRF_IOFUNC_SEL0_CAN1_IOMUX_SEL_SHIFT (2U)
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#define GRF_IOFUNC_SEL0_CAN1_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL0_CAN1_IOMUX_SEL_SHIFT) /* 0x00000004 */
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#define GRF_IOFUNC_SEL0_CAN2_IOMUX_SEL_SHIFT (4U)
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#define GRF_IOFUNC_SEL0_CAN2_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL0_CAN2_IOMUX_SEL_SHIFT) /* 0x00000010 */
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#define GRF_IOFUNC_SEL0_EDP_HPD_IOMUX_SEL_SHIFT (6U)
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#define GRF_IOFUNC_SEL0_EDP_HPD_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL0_EDP_HPD_IOMUX_SEL_SHIFT) /* 0x00000040 */
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#define GRF_IOFUNC_SEL0_GMAC1_IOMUX_SEL_SHIFT (8U)
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#define GRF_IOFUNC_SEL0_GMAC1_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL0_GMAC1_IOMUX_SEL_SHIFT) /* 0x00000100 */
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#define GRF_IOFUNC_SEL0_HDMITX_IOMUX_SEL_SHIFT (10U)
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#define GRF_IOFUNC_SEL0_HDMITX_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL0_HDMITX_IOMUX_SEL_SHIFT) /* 0x00000400 */
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#define GRF_IOFUNC_SEL0_I2C2_IOMUX_SEL_SHIFT (14U)
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#define GRF_IOFUNC_SEL0_I2C2_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL0_I2C2_IOMUX_SEL_SHIFT) /* 0x00004000 */
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/* IOFUNC_SEL1 */
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#define GRF_IOFUNC_SEL1_OFFSET (0x40304U)
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#define GRF_IOFUNC_SEL1_I2C3_IOMUX_SEL_SHIFT (0U)
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#define GRF_IOFUNC_SEL1_I2C3_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL1_I2C3_IOMUX_SEL_SHIFT) /* 0x00000001 */
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#define GRF_IOFUNC_SEL1_I2C4_IOMUX_SEL_SHIFT (2U)
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#define GRF_IOFUNC_SEL1_I2C4_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL1_I2C4_IOMUX_SEL_SHIFT) /* 0x00000004 */
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#define GRF_IOFUNC_SEL1_I2C5_IOMUX_SEL_SHIFT (4U)
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#define GRF_IOFUNC_SEL1_I2C5_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL1_I2C5_IOMUX_SEL_SHIFT) /* 0x00000010 */
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#define GRF_IOFUNC_SEL1_PWM8_IOMUX_SEL_SHIFT (14U)
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#define GRF_IOFUNC_SEL1_PWM8_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL1_PWM8_IOMUX_SEL_SHIFT) /* 0x00004000 */
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/* IOFUNC_SEL2 */
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#define GRF_IOFUNC_SEL2_OFFSET (0x40308U)
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#define GRF_IOFUNC_SEL2_PWM9_IOMUX_SEL_SHIFT (0U)
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#define GRF_IOFUNC_SEL2_PWM9_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL2_PWM9_IOMUX_SEL_SHIFT) /* 0x00000001 */
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#define GRF_IOFUNC_SEL2_PWM10_IOMUX_SEL_SHIFT (2U)
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#define GRF_IOFUNC_SEL2_PWM10_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL2_PWM10_IOMUX_SEL_SHIFT) /* 0x00000004 */
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#define GRF_IOFUNC_SEL2_PWM11_IOMUX_SEL_SHIFT (4U)
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#define GRF_IOFUNC_SEL2_PWM11_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL2_PWM11_IOMUX_SEL_SHIFT) /* 0x00000010 */
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#define GRF_IOFUNC_SEL2_PWM12_IOMUX_SEL_SHIFT (6U)
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#define GRF_IOFUNC_SEL2_PWM12_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL2_PWM12_IOMUX_SEL_SHIFT) /* 0x00000040 */
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#define GRF_IOFUNC_SEL2_PWM13_IOMUX_SEL_SHIFT (8U)
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#define GRF_IOFUNC_SEL2_PWM13_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL2_PWM13_IOMUX_SEL_SHIFT) /* 0x00000100 */
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#define GRF_IOFUNC_SEL2_PWM14_IOMUX_SEL_SHIFT (10U)
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#define GRF_IOFUNC_SEL2_PWM14_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL2_PWM14_IOMUX_SEL_SHIFT) /* 0x00000400 */
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#define GRF_IOFUNC_SEL2_PWM15_IOMUX_SEL_SHIFT (12U)
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#define GRF_IOFUNC_SEL2_PWM15_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL2_PWM15_IOMUX_SEL_SHIFT) /* 0x00001000 */
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#define GRF_IOFUNC_SEL2_SDMMC2_IOMUX_SEL_SHIFT (14U)
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#define GRF_IOFUNC_SEL2_SDMMC2_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL2_SDMMC2_IOMUX_SEL_SHIFT) /* 0x00004000 */
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/* IOFUNC_SEL3 */
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#define GRF_IOFUNC_SEL3_OFFSET (0x4030CU)
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#define GRF_IOFUNC_SEL3_SPI0_IOMUX_SEL_SHIFT (0U)
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#define GRF_IOFUNC_SEL3_SPI0_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL3_SPI0_IOMUX_SEL_SHIFT) /* 0x00000001 */
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#define GRF_IOFUNC_SEL3_SPI1_IOMUX_SEL_SHIFT (2U)
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#define GRF_IOFUNC_SEL3_SPI1_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL3_SPI1_IOMUX_SEL_SHIFT) /* 0x00000004 */
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#define GRF_IOFUNC_SEL3_SPI2_IOMUX_SEL_SHIFT (4U)
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#define GRF_IOFUNC_SEL3_SPI2_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL3_SPI2_IOMUX_SEL_SHIFT) /* 0x00000010 */
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#define GRF_IOFUNC_SEL3_SPI3_IOMUX_SEL_SHIFT (6U)
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#define GRF_IOFUNC_SEL3_SPI3_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL3_SPI3_IOMUX_SEL_SHIFT) /* 0x00000040 */
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#define GRF_IOFUNC_SEL3_UART1_IOMUX_SEL_SHIFT (8U)
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#define GRF_IOFUNC_SEL3_UART1_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL3_UART1_IOMUX_SEL_SHIFT) /* 0x00000100 */
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#define GRF_IOFUNC_SEL3_UART2_IOMUX_SEL_SHIFT (10U)
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#define GRF_IOFUNC_SEL3_UART2_IOMUX_SEL_MASK (0x3U << GRF_IOFUNC_SEL3_UART2_IOMUX_SEL_SHIFT) /* 0x00000C00 */
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#define GRF_IOFUNC_SEL3_UART3_IOMUX_SEL_SHIFT (12U)
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#define GRF_IOFUNC_SEL3_UART3_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL3_UART3_IOMUX_SEL_SHIFT) /* 0x00001000 */
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#define GRF_IOFUNC_SEL3_UART4_IOMUX_SEL_SHIFT (14U)
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#define GRF_IOFUNC_SEL3_UART4_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL3_UART4_IOMUX_SEL_SHIFT) /* 0x00004000 */
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/* IOFUNC_SEL4 */
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#define GRF_IOFUNC_SEL4_OFFSET (0x40310U)
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#define GRF_IOFUNC_SEL4_UART5_IOMUX_SEL_SHIFT (0U)
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#define GRF_IOFUNC_SEL4_UART5_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL4_UART5_IOMUX_SEL_SHIFT) /* 0x00000001 */
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#define GRF_IOFUNC_SEL4_UART6_IOMUX_SEL_SHIFT (2U)
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#define GRF_IOFUNC_SEL4_UART6_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL4_UART6_IOMUX_SEL_SHIFT) /* 0x00000004 */
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#define GRF_IOFUNC_SEL4_UART7_IOMUX_SEL_SHIFT (4U)
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#define GRF_IOFUNC_SEL4_UART7_IOMUX_SEL_MASK (0x3U << GRF_IOFUNC_SEL4_UART7_IOMUX_SEL_SHIFT) /* 0x00000030 */
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#define GRF_IOFUNC_SEL4_UART8_IOMUX_SEL_SHIFT (6U)
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#define GRF_IOFUNC_SEL4_UART8_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL4_UART8_IOMUX_SEL_SHIFT) /* 0x00000040 */
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#define GRF_IOFUNC_SEL4_UART9_IOMUX_SEL_SHIFT (8U)
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#define GRF_IOFUNC_SEL4_UART9_IOMUX_SEL_MASK (0x3U << GRF_IOFUNC_SEL4_UART9_IOMUX_SEL_SHIFT) /* 0x00000300 */
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#define GRF_IOFUNC_SEL4_I2S1_IOMUX_SEL_SHIFT (10U)
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#define GRF_IOFUNC_SEL4_I2S1_IOMUX_SEL_MASK (0x3U << GRF_IOFUNC_SEL4_I2S1_IOMUX_SEL_SHIFT) /* 0x00000C00 */
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#define GRF_IOFUNC_SEL4_I2S2_IOMUX_SEL_SHIFT (12U)
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#define GRF_IOFUNC_SEL4_I2S2_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL4_I2S2_IOMUX_SEL_SHIFT) /* 0x00001000 */
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#define GRF_IOFUNC_SEL4_I2S3_IOMUX_SEL_SHIFT (14U)
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#define GRF_IOFUNC_SEL4_I2S3_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL4_I2S3_IOMUX_SEL_SHIFT) /* 0x00004000 */
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/* IOFUNC_SEL5 */
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#define GRF_IOFUNC_SEL5_OFFSET (0x40314U)
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#define GRF_IOFUNC_SEL5_PDM_IOMUX_SEL_SHIFT (0U)
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#define GRF_IOFUNC_SEL5_PDM_IOMUX_SEL_MASK (0x3U << GRF_IOFUNC_SEL5_PDM_IOMUX_SEL_SHIFT) /* 0x00000003 */
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#define GRF_IOFUNC_SEL5_PCIE20_IOMUX_SEL_SHIFT (2U)
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#define GRF_IOFUNC_SEL5_PCIE20_IOMUX_SEL_MASK (0x3U << GRF_IOFUNC_SEL5_PCIE20_IOMUX_SEL_SHIFT) /* 0x0000000C */
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#define GRF_IOFUNC_SEL5_PCIE30X1_IOMUX_SEL_SHIFT (4U)
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#define GRF_IOFUNC_SEL5_PCIE30X1_IOMUX_SEL_MASK (0x3U << GRF_IOFUNC_SEL5_PCIE30X1_IOMUX_SEL_SHIFT) /* 0x00000030 */
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#define GRF_IOFUNC_SEL5_PCIE30X2_IOMUX_SEL_SHIFT (6U)
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#define GRF_IOFUNC_SEL5_PCIE30X2_IOMUX_SEL_MASK (0x3U << GRF_IOFUNC_SEL5_PCIE30X2_IOMUX_SEL_SHIFT) /* 0x000000C0 */
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#define GRF_IOFUNC_SEL5_SATA_CP_POD_SEL_SHIFT (8U)
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#define GRF_IOFUNC_SEL5_SATA_CP_POD_SEL_MASK (0x3U << GRF_IOFUNC_SEL5_SATA_CP_POD_SEL_SHIFT) /* 0x00000300 */
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#define GRF_IOFUNC_SEL5_SATA0_MP_SWITCH_SEL_SHIFT (10U)
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#define GRF_IOFUNC_SEL5_SATA0_MP_SWITCH_SEL_MASK (0x1U << GRF_IOFUNC_SEL5_SATA0_MP_SWITCH_SEL_SHIFT) /* 0x00000400 */
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#define GRF_IOFUNC_SEL5_SATA1_MP_SWITCH_SEL_SHIFT (11U)
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#define GRF_IOFUNC_SEL5_SATA1_MP_SWITCH_SEL_MASK (0x1U << GRF_IOFUNC_SEL5_SATA1_MP_SWITCH_SEL_SHIFT) /* 0x00000800 */
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#define GRF_IOFUNC_SEL5_SATA2_MP_SWITCH_SEL_SHIFT (12U)
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#define GRF_IOFUNC_SEL5_SATA2_MP_SWITCH_SEL_MASK (0x1U << GRF_IOFUNC_SEL5_SATA2_MP_SWITCH_SEL_SHIFT) /* 0x00001000 */
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#define GRF_IOFUNC_SEL5_SATA0_CP_DEL_SEL_SHIFT (13U)
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#define GRF_IOFUNC_SEL5_SATA0_CP_DEL_SEL_MASK (0x1U << GRF_IOFUNC_SEL5_SATA0_CP_DEL_SEL_SHIFT) /* 0x00002000 */
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#define GRF_IOFUNC_SEL5_SATA1_CP_DEL_SEL_SHIFT (14U)
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#define GRF_IOFUNC_SEL5_SATA1_CP_DEL_SEL_MASK (0x1U << GRF_IOFUNC_SEL5_SATA1_CP_DEL_SEL_SHIFT) /* 0x00004000 */
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#define GRF_IOFUNC_SEL5_SATA2_CP_DEL_SEL_SHIFT (15U)
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#define GRF_IOFUNC_SEL5_SATA2_CP_DEL_SEL_MASK (0x1U << GRF_IOFUNC_SEL5_SATA2_CP_DEL_SEL_SHIFT) /* 0x00008000 */
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/* VI_CON0 */
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#define GRF_VI_CON0_OFFSET (0x40340U)
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#define GRF_VI_CON0_CSIPHY_FORCERXMODE_0_SHIFT (0U)
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#define GRF_VI_CON0_CSIPHY_FORCERXMODE_0_MASK (0x1U << GRF_VI_CON0_CSIPHY_FORCERXMODE_0_SHIFT) /* 0x00000001 */
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#define GRF_VI_CON0_CSIPHY_FORCERXMODE_1_SHIFT (1U)
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#define GRF_VI_CON0_CSIPHY_FORCERXMODE_1_MASK (0x1U << GRF_VI_CON0_CSIPHY_FORCERXMODE_1_SHIFT) /* 0x00000002 */
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#define GRF_VI_CON0_CSIPHY_FORCERXMODE_2_SHIFT (2U)
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#define GRF_VI_CON0_CSIPHY_FORCERXMODE_2_MASK (0x1U << GRF_VI_CON0_CSIPHY_FORCERXMODE_2_SHIFT) /* 0x00000004 */
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#define GRF_VI_CON0_CSIPHY_FORCERXMODE_3_SHIFT (3U)
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#define GRF_VI_CON0_CSIPHY_FORCERXMODE_3_MASK (0x1U << GRF_VI_CON0_CSIPHY_FORCERXMODE_3_SHIFT) /* 0x00000008 */
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#define GRF_VI_CON0_CSIPHY_DATALANE_EN_0_SHIFT (4U)
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#define GRF_VI_CON0_CSIPHY_DATALANE_EN_0_MASK (0x1U << GRF_VI_CON0_CSIPHY_DATALANE_EN_0_SHIFT) /* 0x00000010 */
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#define GRF_VI_CON0_CSIPHY_DATALANE_EN_1_SHIFT (5U)
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#define GRF_VI_CON0_CSIPHY_DATALANE_EN_1_MASK (0x1U << GRF_VI_CON0_CSIPHY_DATALANE_EN_1_SHIFT) /* 0x00000020 */
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#define GRF_VI_CON0_CSIPHY_DATALANE_EN_2_SHIFT (6U)
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#define GRF_VI_CON0_CSIPHY_DATALANE_EN_2_MASK (0x1U << GRF_VI_CON0_CSIPHY_DATALANE_EN_2_SHIFT) /* 0x00000040 */
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#define GRF_VI_CON0_CSIPHY_DATALANE_EN_3_SHIFT (7U)
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#define GRF_VI_CON0_CSIPHY_DATALANE_EN_3_MASK (0x1U << GRF_VI_CON0_CSIPHY_DATALANE_EN_3_SHIFT) /* 0x00000080 */
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#define GRF_VI_CON0_CSIPHY_CLKLANE0_EN_SHIFT (8U)
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#define GRF_VI_CON0_CSIPHY_CLKLANE0_EN_MASK (0x1U << GRF_VI_CON0_CSIPHY_CLKLANE0_EN_SHIFT) /* 0x00000100 */
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#define GRF_VI_CON0_CSIPHY_CLK0_INV_SELECTION_SHIFT (9U)
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#define GRF_VI_CON0_CSIPHY_CLK0_INV_SELECTION_MASK (0x1U << GRF_VI_CON0_CSIPHY_CLK0_INV_SELECTION_SHIFT) /* 0x00000200 */
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#define GRF_VI_CON0_CSIPHY_CLKLANE1_EN_SHIFT (10U)
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#define GRF_VI_CON0_CSIPHY_CLKLANE1_EN_MASK (0x1U << GRF_VI_CON0_CSIPHY_CLKLANE1_EN_SHIFT) /* 0x00000400 */
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#define GRF_VI_CON0_CSIPHY_CLK1_INV_SELECTION_SHIFT (11U)
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#define GRF_VI_CON0_CSIPHY_CLK1_INV_SELECTION_MASK (0x1U << GRF_VI_CON0_CSIPHY_CLK1_INV_SELECTION_SHIFT) /* 0x00000800 */
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#define GRF_VI_CON0_DVP_CLK_INV_SEL_SHIFT (12U)
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#define GRF_VI_CON0_DVP_CLK_INV_SEL_MASK (0x1U << GRF_VI_CON0_DVP_CLK_INV_SEL_SHIFT) /* 0x00001000 */
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/* VI_CON1 */
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#define GRF_VI_CON1_OFFSET (0x40344U)
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#define GRF_VI_CON1_CIF_CLK_DELAYNUM_SHIFT (0U)
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#define GRF_VI_CON1_CIF_CLK_DELAYNUM_MASK (0x7FU << GRF_VI_CON1_CIF_CLK_DELAYNUM_SHIFT) /* 0x0000007F */
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#define GRF_VI_CON1_CSIPHY_MODE_SEL_SHIFT (7U)
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#define GRF_VI_CON1_CSIPHY_MODE_SEL_MASK (0x1U << GRF_VI_CON1_CSIPHY_MODE_SEL_SHIFT) /* 0x00000080 */
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#define GRF_VI_CON1_CIF_DATAPATH_SHIFT (9U)
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#define GRF_VI_CON1_CIF_DATAPATH_MASK (0x1U << GRF_VI_CON1_CIF_DATAPATH_SHIFT) /* 0x00000200 */
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#define GRF_VI_CON1_VICAP_CSIPHY_SEL_SHIFT (11U)
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#define GRF_VI_CON1_VICAP_CSIPHY_SEL_MASK (0x1U << GRF_VI_CON1_VICAP_CSIPHY_SEL_SHIFT) /* 0x00000800 */
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#define GRF_VI_CON1_ISP_CSIPHY_SEL_SHIFT (12U)
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#define GRF_VI_CON1_ISP_CSIPHY_SEL_MASK (0x1U << GRF_VI_CON1_ISP_CSIPHY_SEL_SHIFT) /* 0x00001000 */
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#define GRF_VI_CON1_ISP_SHUTTER_TRIG_SHIFT (13U)
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#define GRF_VI_CON1_ISP_SHUTTER_TRIG_MASK (0x1U << GRF_VI_CON1_ISP_SHUTTER_TRIG_SHIFT) /* 0x00002000 */
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#define GRF_VI_CON1_ISP_WIDTH_SHIFT (14U)
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#define GRF_VI_CON1_ISP_WIDTH_MASK (0x3U << GRF_VI_CON1_ISP_WIDTH_SHIFT) /* 0x0000C000 */
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/* VI_STATUS0 */
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#define GRF_VI_STATUS0_OFFSET (0x40348U)
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#define GRF_VI_STATUS0_CSIPHY_ULPSACTIVENOT_0_SHIFT (0U)
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#define GRF_VI_STATUS0_CSIPHY_ULPSACTIVENOT_0_MASK (0x1U << GRF_VI_STATUS0_CSIPHY_ULPSACTIVENOT_0_SHIFT) /* 0x00000001 */
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#define GRF_VI_STATUS0_CSIPHY_ULPSACTIVENOT_1_SHIFT (1U)
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#define GRF_VI_STATUS0_CSIPHY_ULPSACTIVENOT_1_MASK (0x1U << GRF_VI_STATUS0_CSIPHY_ULPSACTIVENOT_1_SHIFT) /* 0x00000002 */
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#define GRF_VI_STATUS0_CSIPHY_ULPSACTIVENOT_2_SHIFT (2U)
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#define GRF_VI_STATUS0_CSIPHY_ULPSACTIVENOT_2_MASK (0x1U << GRF_VI_STATUS0_CSIPHY_ULPSACTIVENOT_2_SHIFT) /* 0x00000004 */
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#define GRF_VI_STATUS0_CSIPHY_ULPSACTIVENOT_3_SHIFT (3U)
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#define GRF_VI_STATUS0_CSIPHY_ULPSACTIVENOT_3_MASK (0x1U << GRF_VI_STATUS0_CSIPHY_ULPSACTIVENOT_3_SHIFT) /* 0x00000008 */
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#define GRF_VI_STATUS0_CSIPHY_DIRECTION_SHIFT (4U)
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#define GRF_VI_STATUS0_CSIPHY_DIRECTION_MASK (0x1U << GRF_VI_STATUS0_CSIPHY_DIRECTION_SHIFT) /* 0x00000010 */
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#define GRF_VI_STATUS0_CSIPHY_RXSKEWCALHS_0_SHIFT (5U)
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#define GRF_VI_STATUS0_CSIPHY_RXSKEWCALHS_0_MASK (0x1U << GRF_VI_STATUS0_CSIPHY_RXSKEWCALHS_0_SHIFT) /* 0x00000020 */
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#define GRF_VI_STATUS0_CSIPHY_RXSKEWCALHS_1_SHIFT (6U)
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#define GRF_VI_STATUS0_CSIPHY_RXSKEWCALHS_1_MASK (0x1U << GRF_VI_STATUS0_CSIPHY_RXSKEWCALHS_1_SHIFT) /* 0x00000040 */
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#define GRF_VI_STATUS0_CSIPHY_RXSKEWCALHS_2_SHIFT (7U)
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#define GRF_VI_STATUS0_CSIPHY_RXSKEWCALHS_2_MASK (0x1U << GRF_VI_STATUS0_CSIPHY_RXSKEWCALHS_2_SHIFT) /* 0x00000080 */
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#define GRF_VI_STATUS0_CSIPHY_RXSKEWCALHS_3_SHIFT (8U)
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#define GRF_VI_STATUS0_CSIPHY_RXSKEWCALHS_3_MASK (0x1U << GRF_VI_STATUS0_CSIPHY_RXSKEWCALHS_3_SHIFT) /* 0x00000100 */
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#define GRF_VI_STATUS0_CSIPHY_ERRCONTENTIONLP0_0_SHIFT (9U)
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#define GRF_VI_STATUS0_CSIPHY_ERRCONTENTIONLP0_0_MASK (0x1U << GRF_VI_STATUS0_CSIPHY_ERRCONTENTIONLP0_0_SHIFT) /* 0x00000200 */
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#define GRF_VI_STATUS0_CSIPHY_ERRCONTENTIONLP1_0_SHIFT (10U)
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#define GRF_VI_STATUS0_CSIPHY_ERRCONTENTIONLP1_0_MASK (0x1U << GRF_VI_STATUS0_CSIPHY_ERRCONTENTIONLP1_0_SHIFT) /* 0x00000400 */
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/* VO_CON0 */
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#define GRF_VO_CON0_OFFSET (0x40360U)
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#define GRF_VO_CON0_DSI0_DPISHUTDN_SHIFT (0U)
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#define GRF_VO_CON0_DSI0_DPISHUTDN_MASK (0x1U << GRF_VO_CON0_DSI0_DPISHUTDN_SHIFT) /* 0x00000001 */
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#define GRF_VO_CON0_DSI0_DPICOLORM_SHIFT (1U)
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#define GRF_VO_CON0_DSI0_DPICOLORM_MASK (0x1U << GRF_VO_CON0_DSI0_DPICOLORM_SHIFT) /* 0x00000002 */
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#define GRF_VO_CON0_DSI0_DPIUPDATECFG_SHIFT (2U)
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#define GRF_VO_CON0_DSI0_DPIUPDATECFG_MASK (0x1U << GRF_VO_CON0_DSI0_DPIUPDATECFG_SHIFT) /* 0x00000004 */
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#define GRF_VO_CON0_LVDSFORMAT_LVDS0_MSBSEL_SHIFT (3U)
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#define GRF_VO_CON0_LVDSFORMAT_LVDS0_MSBSEL_MASK (0x1U << GRF_VO_CON0_LVDSFORMAT_LVDS0_MSBSEL_SHIFT) /* 0x00000008 */
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#define GRF_VO_CON0_LVDSFORMAT_LVDS0_SELECT_SHIFT (4U)
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#define GRF_VO_CON0_LVDSFORMAT_LVDS0_SELECT_MASK (0x3U << GRF_VO_CON0_LVDSFORMAT_LVDS0_SELECT_SHIFT) /* 0x00000030 */
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#define GRF_VO_CON0_DSI1_DPISHUTDN_SHIFT (8U)
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#define GRF_VO_CON0_DSI1_DPISHUTDN_MASK (0x1U << GRF_VO_CON0_DSI1_DPISHUTDN_SHIFT) /* 0x00000100 */
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#define GRF_VO_CON0_DSI1_DPICOLORM_SHIFT (9U)
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#define GRF_VO_CON0_DSI1_DPICOLORM_MASK (0x1U << GRF_VO_CON0_DSI1_DPICOLORM_SHIFT) /* 0x00000200 */
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#define GRF_VO_CON0_DSI1_DPIUPDATECFG_SHIFT (10U)
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#define GRF_VO_CON0_DSI1_DPIUPDATECFG_MASK (0x1U << GRF_VO_CON0_DSI1_DPIUPDATECFG_SHIFT) /* 0x00000400 */
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#define GRF_VO_CON0_HDMIPHY_I2C_JTAGZ_SHIFT (15U)
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#define GRF_VO_CON0_HDMIPHY_I2C_JTAGZ_MASK (0x1U << GRF_VO_CON0_HDMIPHY_I2C_JTAGZ_SHIFT) /* 0x00008000 */
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/* VO_CON1 */
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#define GRF_VO_CON1_OFFSET (0x40364U)
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#define GRF_VO_CON1_EBC_CLK_INV_SEL_SHIFT (0U)
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#define GRF_VO_CON1_EBC_CLK_INV_SEL_MASK (0x1U << GRF_VO_CON1_EBC_CLK_INV_SEL_SHIFT) /* 0x00000001 */
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#define GRF_VO_CON1_BT656_CLK_INV_SEL_SHIFT (1U)
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#define GRF_VO_CON1_BT656_CLK_INV_SEL_MASK (0x1U << GRF_VO_CON1_BT656_CLK_INV_SEL_SHIFT) /* 0x00000002 */
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#define GRF_VO_CON1_BT1120_CLK_INV_SEL_SHIFT (2U)
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#define GRF_VO_CON1_BT1120_CLK_INV_SEL_MASK (0x1U << GRF_VO_CON1_BT1120_CLK_INV_SEL_SHIFT) /* 0x00000004 */
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#define GRF_VO_CON1_RGB_DCLK_INV_SEL_SHIFT (3U)
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#define GRF_VO_CON1_RGB_DCLK_INV_SEL_MASK (0x1U << GRF_VO_CON1_RGB_DCLK_INV_SEL_SHIFT) /* 0x00000008 */
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#define GRF_VO_CON1_BT656_BYPASS_SHIFT (4U)
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#define GRF_VO_CON1_BT656_BYPASS_MASK (0x1U << GRF_VO_CON1_BT656_BYPASS_SHIFT) /* 0x00000010 */
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#define GRF_VO_CON1_BT1120_BYPASS_SHIFT (5U)
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#define GRF_VO_CON1_BT1120_BYPASS_MASK (0x1U << GRF_VO_CON1_BT1120_BYPASS_SHIFT) /* 0x00000020 */
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#define GRF_VO_CON1_RGB_BYPASS_SHIFT (6U)
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#define GRF_VO_CON1_RGB_BYPASS_MASK (0x1U << GRF_VO_CON1_RGB_BYPASS_SHIFT) /* 0x00000040 */
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#define GRF_VO_CON1_HDMI_CECIN_MSK_SHIFT (13U)
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#define GRF_VO_CON1_HDMI_CECIN_MSK_MASK (0x1U << GRF_VO_CON1_HDMI_CECIN_MSK_SHIFT) /* 0x00002000 */
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#define GRF_VO_CON1_HDMI_SCLIN_MSK_SHIFT (14U)
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#define GRF_VO_CON1_HDMI_SCLIN_MSK_MASK (0x1U << GRF_VO_CON1_HDMI_SCLIN_MSK_SHIFT) /* 0x00004000 */
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#define GRF_VO_CON1_HDMI_SDAIN_MSK_SHIFT (15U)
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#define GRF_VO_CON1_HDMI_SDAIN_MSK_MASK (0x1U << GRF_VO_CON1_HDMI_SDAIN_MSK_SHIFT) /* 0x00008000 */
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/* VO_CON2 */
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#define GRF_VO_CON2_OFFSET (0x40368U)
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#define GRF_VO_CON2_DSIPHY0_FORCERXMODE_SHIFT (0U)
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#define GRF_VO_CON2_DSIPHY0_FORCERXMODE_MASK (0x1U << GRF_VO_CON2_DSIPHY0_FORCERXMODE_SHIFT) /* 0x00000001 */
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#define GRF_VO_CON2_DSIPHY0_LVDS_MODE_SHIFT (1U)
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#define GRF_VO_CON2_DSIPHY0_LVDS_MODE_MASK (0x1U << GRF_VO_CON2_DSIPHY0_LVDS_MODE_SHIFT) /* 0x00000002 */
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#define GRF_VO_CON2_DSIPHY0_LANE0_TURNDISABLE_SHIFT (2U)
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#define GRF_VO_CON2_DSIPHY0_LANE0_TURNDISABLE_MASK (0x1U << GRF_VO_CON2_DSIPHY0_LANE0_TURNDISABLE_SHIFT) /* 0x00000004 */
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#define GRF_VO_CON2_DSIPHY0_LANE0_FRCTXSTPM_SHIFT (4U)
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#define GRF_VO_CON2_DSIPHY0_LANE0_FRCTXSTPM_MASK (0x1U << GRF_VO_CON2_DSIPHY0_LANE0_FRCTXSTPM_SHIFT) /* 0x00000010 */
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#define GRF_VO_CON2_DSIPHY0_LANE1_FRCTXSTPM_SHIFT (5U)
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#define GRF_VO_CON2_DSIPHY0_LANE1_FRCTXSTPM_MASK (0x1U << GRF_VO_CON2_DSIPHY0_LANE1_FRCTXSTPM_SHIFT) /* 0x00000020 */
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#define GRF_VO_CON2_DSIPHY0_LANE2_FRCTXSTPM_SHIFT (6U)
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#define GRF_VO_CON2_DSIPHY0_LANE2_FRCTXSTPM_MASK (0x1U << GRF_VO_CON2_DSIPHY0_LANE2_FRCTXSTPM_SHIFT) /* 0x00000040 */
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#define GRF_VO_CON2_DSIPHY0_LANE3_FRCTXSTPM_SHIFT (7U)
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#define GRF_VO_CON2_DSIPHY0_LANE3_FRCTXSTPM_MASK (0x1U << GRF_VO_CON2_DSIPHY0_LANE3_FRCTXSTPM_SHIFT) /* 0x00000080 */
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#define GRF_VO_CON2_LVDS0_DCLK_DIV2_SEL_SHIFT (8U)
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#define GRF_VO_CON2_LVDS0_DCLK_DIV2_SEL_MASK (0x1U << GRF_VO_CON2_LVDS0_DCLK_DIV2_SEL_SHIFT) /* 0x00000100 */
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#define GRF_VO_CON2_LVDS0_DCLK_INV_SEL_SHIFT (9U)
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#define GRF_VO_CON2_LVDS0_DCLK_INV_SEL_MASK (0x1U << GRF_VO_CON2_LVDS0_DCLK_INV_SEL_SHIFT) /* 0x00000200 */
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#define GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_CK_SHIFT (11U)
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#define GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_CK_MASK (0x1U << GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_CK_SHIFT) /* 0x00000800 */
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#define GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_0_SHIFT (12U)
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#define GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_0_MASK (0x1U << GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_0_SHIFT) /* 0x00001000 */
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#define GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_1_SHIFT (13U)
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#define GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_1_MASK (0x1U << GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_1_SHIFT) /* 0x00002000 */
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#define GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_2_SHIFT (14U)
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#define GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_2_MASK (0x1U << GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_2_SHIFT) /* 0x00004000 */
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#define GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_3_SHIFT (15U)
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#define GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_3_MASK (0x1U << GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_3_SHIFT) /* 0x00008000 */
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/* MAC0_CON0 */
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#define GRF_MAC0_CON0_OFFSET (0x40380U)
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#define GRF_MAC0_CON0_GMAC0_CLK_TX_DL_CFG_SHIFT (0U)
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#define GRF_MAC0_CON0_GMAC0_CLK_TX_DL_CFG_MASK (0xFFU << GRF_MAC0_CON0_GMAC0_CLK_TX_DL_CFG_SHIFT) /* 0x000000FF */
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#define GRF_MAC0_CON0_GMAC0_CLK_RX_DL_CFG_SHIFT (8U)
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#define GRF_MAC0_CON0_GMAC0_CLK_RX_DL_CFG_MASK (0xFFU << GRF_MAC0_CON0_GMAC0_CLK_RX_DL_CFG_SHIFT) /* 0x0000FF00 */
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/* MAC0_CON1 */
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#define GRF_MAC0_CON1_OFFSET (0x40384U)
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#define GRF_MAC0_CON1_GMAC0_TXCLK_DLY_ENA_SHIFT (0U)
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#define GRF_MAC0_CON1_GMAC0_TXCLK_DLY_ENA_MASK (0x1U << GRF_MAC0_CON1_GMAC0_TXCLK_DLY_ENA_SHIFT) /* 0x00000001 */
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#define GRF_MAC0_CON1_GMAC0_RXCLK_DLY_ENA_SHIFT (1U)
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#define GRF_MAC0_CON1_GMAC0_RXCLK_DLY_ENA_MASK (0x1U << GRF_MAC0_CON1_GMAC0_RXCLK_DLY_ENA_SHIFT) /* 0x00000002 */
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#define GRF_MAC0_CON1_GMAC0_MAC_SPEED_SHIFT (2U)
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#define GRF_MAC0_CON1_GMAC0_MAC_SPEED_MASK (0x1U << GRF_MAC0_CON1_GMAC0_MAC_SPEED_SHIFT) /* 0x00000004 */
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#define GRF_MAC0_CON1_GMAC0_FLOWCTRL_SHIFT (3U)
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#define GRF_MAC0_CON1_GMAC0_FLOWCTRL_MASK (0x1U << GRF_MAC0_CON1_GMAC0_FLOWCTRL_SHIFT) /* 0x00000008 */
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#define GRF_MAC0_CON1_GMAC0_PHY_INTF_SEL_SHIFT (4U)
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#define GRF_MAC0_CON1_GMAC0_PHY_INTF_SEL_MASK (0x7U << GRF_MAC0_CON1_GMAC0_PHY_INTF_SEL_SHIFT) /* 0x00000070 */
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#define GRF_MAC0_CON1_GMAC0_QSGMII_MODE_SHIFT (7U)
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#define GRF_MAC0_CON1_GMAC0_QSGMII_MODE_MASK (0x1U << GRF_MAC0_CON1_GMAC0_QSGMII_MODE_SHIFT) /* 0x00000080 */
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/* MAC1_CON0 */
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#define GRF_MAC1_CON0_OFFSET (0x40388U)
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#define GRF_MAC1_CON0_GMAC1_CLK_TX_DL_CFG_SHIFT (0U)
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#define GRF_MAC1_CON0_GMAC1_CLK_TX_DL_CFG_MASK (0xFFU << GRF_MAC1_CON0_GMAC1_CLK_TX_DL_CFG_SHIFT) /* 0x000000FF */
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#define GRF_MAC1_CON0_GMAC1_CLK_RX_DL_CFG_SHIFT (8U)
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#define GRF_MAC1_CON0_GMAC1_CLK_RX_DL_CFG_MASK (0xFFU << GRF_MAC1_CON0_GMAC1_CLK_RX_DL_CFG_SHIFT) /* 0x0000FF00 */
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/* MAC1_CON1 */
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#define GRF_MAC1_CON1_OFFSET (0x4038CU)
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#define GRF_MAC1_CON1_GMAC1_TXCLK_DLY_ENA_SHIFT (0U)
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#define GRF_MAC1_CON1_GMAC1_TXCLK_DLY_ENA_MASK (0x1U << GRF_MAC1_CON1_GMAC1_TXCLK_DLY_ENA_SHIFT) /* 0x00000001 */
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#define GRF_MAC1_CON1_GMAC1_RXCLK_DLY_ENA_SHIFT (1U)
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#define GRF_MAC1_CON1_GMAC1_RXCLK_DLY_ENA_MASK (0x1U << GRF_MAC1_CON1_GMAC1_RXCLK_DLY_ENA_SHIFT) /* 0x00000002 */
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#define GRF_MAC1_CON1_GMAC1_MAC_SPEED_SHIFT (2U)
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#define GRF_MAC1_CON1_GMAC1_MAC_SPEED_MASK (0x1U << GRF_MAC1_CON1_GMAC1_MAC_SPEED_SHIFT) /* 0x00000004 */
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#define GRF_MAC1_CON1_GMAC1_FLOWCTRL_SHIFT (3U)
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#define GRF_MAC1_CON1_GMAC1_FLOWCTRL_MASK (0x1U << GRF_MAC1_CON1_GMAC1_FLOWCTRL_SHIFT) /* 0x00000008 */
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#define GRF_MAC1_CON1_GMAC1_PHY_INTF_SEL_SHIFT (4U)
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#define GRF_MAC1_CON1_GMAC1_PHY_INTF_SEL_MASK (0x7U << GRF_MAC1_CON1_GMAC1_PHY_INTF_SEL_SHIFT) /* 0x00000070 */
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#define GRF_MAC1_CON1_GMAC1_QSGMII_MODE_SHIFT (7U)
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#define GRF_MAC1_CON1_GMAC1_QSGMII_MODE_MASK (0x1U << GRF_MAC1_CON1_GMAC1_QSGMII_MODE_SHIFT) /* 0x00000080 */
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/* BIU_CON0 */
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#define GRF_BIU_CON0_OFFSET (0x403A0U)
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#define GRF_BIU_CON0_BUS_FWD_TOP_STALL_SHIFT (0U)
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#define GRF_BIU_CON0_BUS_FWD_TOP_STALL_MASK (0x1U << GRF_BIU_CON0_BUS_FWD_TOP_STALL_SHIFT) /* 0x00000001 */
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#define GRF_BIU_CON0_CPU_FWD_MSCH_STALL_SHIFT (1U)
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#define GRF_BIU_CON0_CPU_FWD_MSCH_STALL_MASK (0x1U << GRF_BIU_CON0_CPU_FWD_MSCH_STALL_SHIFT) /* 0x00000002 */
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#define GRF_BIU_CON0_CPU_FWD_TOP_STALL_SHIFT (2U)
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#define GRF_BIU_CON0_CPU_FWD_TOP_STALL_MASK (0x1U << GRF_BIU_CON0_CPU_FWD_TOP_STALL_SHIFT) /* 0x00000004 */
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#define GRF_BIU_CON0_GIC_FWD_PERI_STALL_SHIFT (3U)
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#define GRF_BIU_CON0_GIC_FWD_PERI_STALL_MASK (0x1U << GRF_BIU_CON0_GIC_FWD_PERI_STALL_SHIFT) /* 0x00000008 */
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#define GRF_BIU_CON0_GPU_FWD_MSCH_STALL_SHIFT (4U)
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#define GRF_BIU_CON0_GPU_FWD_MSCH_STALL_MASK (0x1U << GRF_BIU_CON0_GPU_FWD_MSCH_STALL_SHIFT) /* 0x00000010 */
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#define GRF_BIU_CON0_NPU_FWD_TOP_STALL_SHIFT (5U)
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#define GRF_BIU_CON0_NPU_FWD_TOP_STALL_MASK (0x1U << GRF_BIU_CON0_NPU_FWD_TOP_STALL_SHIFT) /* 0x00000020 */
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#define GRF_BIU_CON0_PERI_FWD_TOP_STALL_SHIFT (6U)
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#define GRF_BIU_CON0_PERI_FWD_TOP_STALL_MASK (0x1U << GRF_BIU_CON0_PERI_FWD_TOP_STALL_SHIFT) /* 0x00000040 */
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#define GRF_BIU_CON0_PERI_REQ_GA_STALL_SHIFT (7U)
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#define GRF_BIU_CON0_PERI_REQ_GA_STALL_MASK (0x1U << GRF_BIU_CON0_PERI_REQ_GA_STALL_SHIFT) /* 0x00000080 */
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#define GRF_BIU_CON0_PERI_FWD_PHP_STALL_SHIFT (8U)
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#define GRF_BIU_CON0_PERI_FWD_PHP_STALL_MASK (0x1U << GRF_BIU_CON0_PERI_FWD_PHP_STALL_SHIFT) /* 0x00000100 */
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#define GRF_BIU_CON0_PERI_FWD_SF_STALL_SHIFT (9U)
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#define GRF_BIU_CON0_PERI_FWD_SF_STALL_MASK (0x1U << GRF_BIU_CON0_PERI_FWD_SF_STALL_SHIFT) /* 0x00000200 */
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#define GRF_BIU_CON0_PHP_REQ_PERI_STALL_SHIFT (10U)
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#define GRF_BIU_CON0_PHP_REQ_PERI_STALL_MASK (0x1U << GRF_BIU_CON0_PHP_REQ_PERI_STALL_SHIFT) /* 0x00000400 */
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#define GRF_BIU_CON0_PIPE_FWD_TOP_STALL_SHIFT (11U)
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#define GRF_BIU_CON0_PIPE_FWD_TOP_STALL_MASK (0x1U << GRF_BIU_CON0_PIPE_FWD_TOP_STALL_SHIFT) /* 0x00000800 */
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#define GRF_BIU_CON0_RGA_FWD_MSCH_STALL_SHIFT (12U)
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#define GRF_BIU_CON0_RGA_FWD_MSCH_STALL_MASK (0x1U << GRF_BIU_CON0_RGA_FWD_MSCH_STALL_SHIFT) /* 0x00001000 */
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#define GRF_BIU_CON0_SF_REQ_PERI_STALL_SHIFT (13U)
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#define GRF_BIU_CON0_SF_REQ_PERI_STALL_MASK (0x1U << GRF_BIU_CON0_SF_REQ_PERI_STALL_SHIFT) /* 0x00002000 */
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#define GRF_BIU_CON0_TOP_FWD_DDRC_STALL_SHIFT (14U)
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#define GRF_BIU_CON0_TOP_FWD_DDRC_STALL_MASK (0x1U << GRF_BIU_CON0_TOP_FWD_DDRC_STALL_SHIFT) /* 0x00004000 */
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#define GRF_BIU_CON0_TOP_FWD_MSCH_STALL_SHIFT (15U)
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#define GRF_BIU_CON0_TOP_FWD_MSCH_STALL_MASK (0x1U << GRF_BIU_CON0_TOP_FWD_MSCH_STALL_SHIFT) /* 0x00008000 */
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/* BIU_CON1 */
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#define GRF_BIU_CON1_OFFSET (0x403A4U)
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#define GRF_BIU_CON1_TOP_FWD_PMU_STALL_SHIFT (0U)
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#define GRF_BIU_CON1_TOP_FWD_PMU_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_PMU_STALL_SHIFT) /* 0x00000001 */
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#define GRF_BIU_CON1_TOP_FWD_RGA_STALL_SHIFT (1U)
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#define GRF_BIU_CON1_TOP_FWD_RGA_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_RGA_STALL_SHIFT) /* 0x00000002 */
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#define GRF_BIU_CON1_TOP_FWD_VPU_STALL_SHIFT (2U)
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#define GRF_BIU_CON1_TOP_FWD_VPU_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_VPU_STALL_SHIFT) /* 0x00000004 */
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#define GRF_BIU_CON1_TOPAHPU_FWD_MSCH_STALL_SHIFT (3U)
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#define GRF_BIU_CON1_TOPAHPU_FWD_MSCH_STALL_MASK (0x1U << GRF_BIU_CON1_TOPAHPU_FWD_MSCH_STALL_SHIFT) /* 0x00000008 */
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#define GRF_BIU_CON1_TOPAHVO_FWD_MSCH_STALL_SHIFT (4U)
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#define GRF_BIU_CON1_TOPAHVO_FWD_MSCH_STALL_MASK (0x1U << GRF_BIU_CON1_TOPAHVO_FWD_MSCH_STALL_SHIFT) /* 0x00000010 */
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#define GRF_BIU_CON1_TOPAL_FWD_MSCH_STALL_SHIFT (5U)
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#define GRF_BIU_CON1_TOPAL_FWD_MSCH_STALL_MASK (0x1U << GRF_BIU_CON1_TOPAL_FWD_MSCH_STALL_SHIFT) /* 0x00000020 */
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#define GRF_BIU_CON1_TOP_FWD_USB_STALL_SHIFT (6U)
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#define GRF_BIU_CON1_TOP_FWD_USB_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_USB_STALL_SHIFT) /* 0x00000040 */
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#define GRF_BIU_CON1_TOP_FWD_VI_STALL_SHIFT (7U)
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#define GRF_BIU_CON1_TOP_FWD_VI_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_VI_STALL_SHIFT) /* 0x00000080 */
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#define GRF_BIU_CON1_TOP_FWD_VO_STALL_SHIFT (8U)
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#define GRF_BIU_CON1_TOP_FWD_VO_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_VO_STALL_SHIFT) /* 0x00000100 */
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#define GRF_BIU_CON1_TOP_FWD_GPU_STALL_SHIFT (9U)
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#define GRF_BIU_CON1_TOP_FWD_GPU_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_GPU_STALL_SHIFT) /* 0x00000200 */
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#define GRF_BIU_CON1_TOP_FWD_VDEC_STALL_SHIFT (10U)
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#define GRF_BIU_CON1_TOP_FWD_VDEC_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_VDEC_STALL_SHIFT) /* 0x00000400 */
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#define GRF_BIU_CON1_TOP_FWD_VENC_STALL_SHIFT (11U)
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#define GRF_BIU_CON1_TOP_FWD_VENC_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_VENC_STALL_SHIFT) /* 0x00000800 */
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#define GRF_BIU_CON1_TOP_FWD_BUS_STALL_SHIFT (12U)
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#define GRF_BIU_CON1_TOP_FWD_BUS_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_BUS_STALL_SHIFT) /* 0x00001000 */
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#define GRF_BIU_CON1_TOP_FWD_NPU_STALL_SHIFT (13U)
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#define GRF_BIU_CON1_TOP_FWD_NPU_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_NPU_STALL_SHIFT) /* 0x00002000 */
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#define GRF_BIU_CON1_TOP_FWD_PERI_STALL_SHIFT (14U)
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#define GRF_BIU_CON1_TOP_FWD_PERI_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_PERI_STALL_SHIFT) /* 0x00004000 */
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#define GRF_BIU_CON1_TOP_FWD_PIPE_STALL_SHIFT (15U)
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#define GRF_BIU_CON1_TOP_FWD_PIPE_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_PIPE_STALL_SHIFT) /* 0x00008000 */
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/* BIU_CON2 */
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#define GRF_BIU_CON2_OFFSET (0x403A8U)
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#define GRF_BIU_CON2_USB_FWD_MSCH_STALL_SHIFT (0U)
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#define GRF_BIU_CON2_USB_FWD_MSCH_STALL_MASK (0x1U << GRF_BIU_CON2_USB_FWD_MSCH_STALL_SHIFT) /* 0x00000001 */
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#define GRF_BIU_CON2_VDEC_FWD_MSCH_STALL_SHIFT (1U)
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#define GRF_BIU_CON2_VDEC_FWD_MSCH_STALL_MASK (0x1U << GRF_BIU_CON2_VDEC_FWD_MSCH_STALL_SHIFT) /* 0x00000002 */
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#define GRF_BIU_CON2_VDEC_FWD_TOP_STALL_SHIFT (2U)
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#define GRF_BIU_CON2_VDEC_FWD_TOP_STALL_MASK (0x1U << GRF_BIU_CON2_VDEC_FWD_TOP_STALL_SHIFT) /* 0x00000004 */
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#define GRF_BIU_CON2_VENC_FWD_MSCH_STALL_SHIFT (3U)
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#define GRF_BIU_CON2_VENC_FWD_MSCH_STALL_MASK (0x1U << GRF_BIU_CON2_VENC_FWD_MSCH_STALL_SHIFT) /* 0x00000008 */
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#define GRF_BIU_CON2_VI_FWD_TOP_STALL_SHIFT (4U)
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#define GRF_BIU_CON2_VI_FWD_TOP_STALL_MASK (0x1U << GRF_BIU_CON2_VI_FWD_TOP_STALL_SHIFT) /* 0x00000010 */
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#define GRF_BIU_CON2_VO_FWD_TOP_STALL_SHIFT (5U)
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#define GRF_BIU_CON2_VO_FWD_TOP_STALL_MASK (0x1U << GRF_BIU_CON2_VO_FWD_TOP_STALL_SHIFT) /* 0x00000020 */
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#define GRF_BIU_CON2_VPU_FWD_MSCH_STALL_SHIFT (6U)
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#define GRF_BIU_CON2_VPU_FWD_MSCH_STALL_MASK (0x1U << GRF_BIU_CON2_VPU_FWD_MSCH_STALL_SHIFT) /* 0x00000040 */
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/* GIC_CON0 */
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#define GRF_GIC_CON0_OFFSET (0x403C0U)
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#define GRF_GIC_CON0_GICD_PAGE_OFFSET_SHIFT (0U)
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#define GRF_GIC_CON0_GICD_PAGE_OFFSET_MASK (0xFFFFU << GRF_GIC_CON0_GICD_PAGE_OFFSET_SHIFT) /* 0x0000FFFF */
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/* GIC_CON1 */
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#define GRF_GIC_CON1_OFFSET (0x403C4U)
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#define GRF_GIC_CON1_ITS_TRANSR_PAGE_OFFSET_SHIFT (0U)
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#define GRF_GIC_CON1_ITS_TRANSR_PAGE_OFFSET_MASK (0xFFFFU << GRF_GIC_CON1_ITS_TRANSR_PAGE_OFFSET_SHIFT) /* 0x0000FFFF */
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/* GIC_CON2 */
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#define GRF_GIC_CON2_OFFSET (0x403C8U)
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#define GRF_GIC_CON2_CPU_ACTIVE_SHIFT (0U)
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#define GRF_GIC_CON2_CPU_ACTIVE_MASK (0xFU << GRF_GIC_CON2_CPU_ACTIVE_SHIFT) /* 0x0000000F */
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#define GRF_GIC_CON2_SAMPLE_REQ_SHIFT (4U)
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#define GRF_GIC_CON2_SAMPLE_REQ_MASK (0x1U << GRF_GIC_CON2_SAMPLE_REQ_SHIFT) /* 0x00000010 */
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#define GRF_GIC_CON2_GIC2CORE_PWRQ_PERMIT_DENY_SAR_SHIFT (5U)
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#define GRF_GIC_CON2_GIC2CORE_PWRQ_PERMIT_DENY_SAR_MASK (0x1U << GRF_GIC_CON2_GIC2CORE_PWRQ_PERMIT_DENY_SAR_SHIFT) /* 0x00000020 */
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/* GPU_CON0 */
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#define GRF_GPU_CON0_OFFSET (0x403F0U)
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#define GRF_GPU_CON0_DBGEN_SHIFT (0U)
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#define GRF_GPU_CON0_DBGEN_MASK (0x1U << GRF_GPU_CON0_DBGEN_SHIFT) /* 0x00000001 */
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#define GRF_GPU_CON0_NIDEN_SHIFT (1U)
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#define GRF_GPU_CON0_NIDEN_MASK (0x1U << GRF_GPU_CON0_NIDEN_SHIFT) /* 0x00000002 */
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#define GRF_GPU_CON0_STRIPPING_GRANULE_SHIFT (2U)
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#define GRF_GPU_CON0_STRIPPING_GRANULE_MASK (0x7U << GRF_GPU_CON0_STRIPPING_GRANULE_SHIFT) /* 0x0000001C */
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/* GPU_CON1 */
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#define GRF_GPU_CON1_OFFSET (0x403F4U)
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#define GRF_GPU_CON1_GPU_TEXFMTENABLE_SHIFT (0U)
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#define GRF_GPU_CON1_GPU_TEXFMTENABLE_MASK (0xFFFFFFFFU << GRF_GPU_CON1_GPU_TEXFMTENABLE_SHIFT) /* 0xFFFFFFFF */
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/* CPU_CON0 */
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#define GRF_CPU_CON0_OFFSET (0x40400U)
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#define GRF_CPU_CON0_CFGEND_SHIFT (0U)
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#define GRF_CPU_CON0_CFGEND_MASK (0xFU << GRF_CPU_CON0_CFGEND_SHIFT) /* 0x0000000F */
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#define GRF_CPU_CON0_CFGTE_SHIFT (4U)
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#define GRF_CPU_CON0_CFGTE_MASK (0xFU << GRF_CPU_CON0_CFGTE_SHIFT) /* 0x000000F0 */
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#define GRF_CPU_CON0_PMUSNAPSHOTREQ_SHIFT (8U)
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#define GRF_CPU_CON0_PMUSNAPSHOTREQ_MASK (0x1U << GRF_CPU_CON0_PMUSNAPSHOTREQ_SHIFT) /* 0x00000100 */
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#define GRF_CPU_CON0_DBGCONNECTED_SHIFT (9U)
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#define GRF_CPU_CON0_DBGCONNECTED_MASK (0x1U << GRF_CPU_CON0_DBGCONNECTED_SHIFT) /* 0x00000200 */
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#define GRF_CPU_CON0_EVENTOACK_SHIFT (10U)
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#define GRF_CPU_CON0_EVENTOACK_MASK (0x1U << GRF_CPU_CON0_EVENTOACK_SHIFT) /* 0x00000400 */
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#define GRF_CPU_CON0_EVENCTIREQ_SHIFT (11U)
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#define GRF_CPU_CON0_EVENCTIREQ_MASK (0x1U << GRF_CPU_CON0_EVENCTIREQ_SHIFT) /* 0x00000800 */
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#define GRF_CPU_CON0_ADB400_PWRQ_PERMIT_DENY_SHIFT (13U)
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#define GRF_CPU_CON0_ADB400_PWRQ_PERMIT_DENY_MASK (0x1U << GRF_CPU_CON0_ADB400_PWRQ_PERMIT_DENY_SHIFT) /* 0x00002000 */
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/* CPU_STATUS0 */
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#define GRF_CPU_STATUS0_OFFSET (0x40420U)
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#define GRF_CPU_STATUS0_COREINSTRUN_SHIFT (0U)
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#define GRF_CPU_STATUS0_COREINSTRUN_MASK (0xFU << GRF_CPU_STATUS0_COREINSTRUN_SHIFT) /* 0x0000000F */
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#define GRF_CPU_STATUS0_COREINSTRRET_SHIFT (4U)
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#define GRF_CPU_STATUS0_COREINSTRRET_MASK (0xFU << GRF_CPU_STATUS0_COREINSTRRET_SHIFT) /* 0x000000F0 */
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#define GRF_CPU_STATUS0_PMUSNAPSHOTACK_SHIFT (8U)
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#define GRF_CPU_STATUS0_PMUSNAPSHOTACK_MASK (0x1U << GRF_CPU_STATUS0_PMUSNAPSHOTACK_SHIFT) /* 0x00000100 */
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#define GRF_CPU_STATUS0_EVENTIACK_SHIFT (10U)
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#define GRF_CPU_STATUS0_EVENTIACK_MASK (0x1U << GRF_CPU_STATUS0_EVENTIACK_SHIFT) /* 0x00000400 */
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#define GRF_CPU_STATUS0_EVENTOREQ_SHIFT (11U)
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#define GRF_CPU_STATUS0_EVENTOREQ_MASK (0x1U << GRF_CPU_STATUS0_EVENTOREQ_SHIFT) /* 0x00000800 */
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#define GRF_CPU_STATUS0_SWACTIVE_SHIFT (12U)
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#define GRF_CPU_STATUS0_SWACTIVE_MASK (0x1U << GRF_CPU_STATUS0_SWACTIVE_SHIFT) /* 0x00001000 */
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#define GRF_CPU_STATUS0_JTAGACTIVE_SHIFT (13U)
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#define GRF_CPU_STATUS0_JTAGACTIVE_MASK (0x1U << GRF_CPU_STATUS0_JTAGACTIVE_SHIFT) /* 0x00002000 */
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#define GRF_CPU_STATUS0_JTAGIR_SHIFT (14U)
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#define GRF_CPU_STATUS0_JTAGIR_MASK (0xFU << GRF_CPU_STATUS0_JTAGIR_SHIFT) /* 0x0003C000 */
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#define GRF_CPU_STATUS0_JTAGSTATE_SHIFT (18U)
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#define GRF_CPU_STATUS0_JTAGSTATE_MASK (0xFU << GRF_CPU_STATUS0_JTAGSTATE_SHIFT) /* 0x003C0000 */
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#define GRF_CPU_STATUS0_DORMANTSTATE_SHIFT (22U)
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#define GRF_CPU_STATUS0_DORMANTSTATE_MASK (0x1U << GRF_CPU_STATUS0_DORMANTSTATE_SHIFT) /* 0x00400000 */
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/* SOC_CON10 */
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#define GRF_SOC_CON10_OFFSET (0x40500U)
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#define GRF_SOC_CON10_UART1_CTS_INV_SHIFT (0U)
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#define GRF_SOC_CON10_UART1_CTS_INV_MASK (0x1U << GRF_SOC_CON10_UART1_CTS_INV_SHIFT) /* 0x00000001 */
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#define GRF_SOC_CON10_UART1_RTS_INV_SHIFT (1U)
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#define GRF_SOC_CON10_UART1_RTS_INV_MASK (0x1U << GRF_SOC_CON10_UART1_RTS_INV_SHIFT) /* 0x00000002 */
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#define GRF_SOC_CON10_UART2_CTS_INV_SHIFT (2U)
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#define GRF_SOC_CON10_UART2_CTS_INV_MASK (0x1U << GRF_SOC_CON10_UART2_CTS_INV_SHIFT) /* 0x00000004 */
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#define GRF_SOC_CON10_UART2_RTS_INV_SHIFT (3U)
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#define GRF_SOC_CON10_UART2_RTS_INV_MASK (0x1U << GRF_SOC_CON10_UART2_RTS_INV_SHIFT) /* 0x00000008 */
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#define GRF_SOC_CON10_UART3_CTS_INV_SHIFT (4U)
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#define GRF_SOC_CON10_UART3_CTS_INV_MASK (0x1U << GRF_SOC_CON10_UART3_CTS_INV_SHIFT) /* 0x00000010 */
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#define GRF_SOC_CON10_UART3_RTS_INV_SHIFT (5U)
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#define GRF_SOC_CON10_UART3_RTS_INV_MASK (0x1U << GRF_SOC_CON10_UART3_RTS_INV_SHIFT) /* 0x00000020 */
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#define GRF_SOC_CON10_UART4_CTS_INV_SHIFT (6U)
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#define GRF_SOC_CON10_UART4_CTS_INV_MASK (0x1U << GRF_SOC_CON10_UART4_CTS_INV_SHIFT) /* 0x00000040 */
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#define GRF_SOC_CON10_UART4_RTS_INV_SHIFT (7U)
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#define GRF_SOC_CON10_UART4_RTS_INV_MASK (0x1U << GRF_SOC_CON10_UART4_RTS_INV_SHIFT) /* 0x00000080 */
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#define GRF_SOC_CON10_UART5_CTS_INV_SHIFT (8U)
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#define GRF_SOC_CON10_UART5_CTS_INV_MASK (0x1U << GRF_SOC_CON10_UART5_CTS_INV_SHIFT) /* 0x00000100 */
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#define GRF_SOC_CON10_UART5_RTS_INV_SHIFT (9U)
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#define GRF_SOC_CON10_UART5_RTS_INV_MASK (0x1U << GRF_SOC_CON10_UART5_RTS_INV_SHIFT) /* 0x00000200 */
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#define GRF_SOC_CON10_UART6_CTS_INV_SHIFT (10U)
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#define GRF_SOC_CON10_UART6_CTS_INV_MASK (0x1U << GRF_SOC_CON10_UART6_CTS_INV_SHIFT) /* 0x00000400 */
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#define GRF_SOC_CON10_UART6_RTS_INV_SHIFT (11U)
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#define GRF_SOC_CON10_UART6_RTS_INV_MASK (0x1U << GRF_SOC_CON10_UART6_RTS_INV_SHIFT) /* 0x00000800 */
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#define GRF_SOC_CON10_UART7_CTS_INV_SHIFT (12U)
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#define GRF_SOC_CON10_UART7_CTS_INV_MASK (0x1U << GRF_SOC_CON10_UART7_CTS_INV_SHIFT) /* 0x00001000 */
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#define GRF_SOC_CON10_UART7_RTS_INV_SHIFT (13U)
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#define GRF_SOC_CON10_UART7_RTS_INV_MASK (0x1U << GRF_SOC_CON10_UART7_RTS_INV_SHIFT) /* 0x00002000 */
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#define GRF_SOC_CON10_UART8_CTS_INV_SHIFT (14U)
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#define GRF_SOC_CON10_UART8_CTS_INV_MASK (0x1U << GRF_SOC_CON10_UART8_CTS_INV_SHIFT) /* 0x00004000 */
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#define GRF_SOC_CON10_UART8_RTS_INV_SHIFT (15U)
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#define GRF_SOC_CON10_UART8_RTS_INV_MASK (0x1U << GRF_SOC_CON10_UART8_RTS_INV_SHIFT) /* 0x00008000 */
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/* SOC_CON11 */
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#define GRF_SOC_CON11_OFFSET (0x40504U)
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#define GRF_SOC_CON11_UART9_CTS_INV_SHIFT (0U)
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#define GRF_SOC_CON11_UART9_CTS_INV_MASK (0x1U << GRF_SOC_CON11_UART9_CTS_INV_SHIFT) /* 0x00000001 */
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#define GRF_SOC_CON11_UART9_RTS_INV_SHIFT (1U)
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#define GRF_SOC_CON11_UART9_RTS_INV_MASK (0x1U << GRF_SOC_CON11_UART9_RTS_INV_SHIFT) /* 0x00000002 */
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#define GRF_SOC_CON11_EMMC_CLKBYPASS_SHIFT (2U)
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#define GRF_SOC_CON11_EMMC_CLKBYPASS_MASK (0x1U << GRF_SOC_CON11_EMMC_CLKBYPASS_SHIFT) /* 0x00000004 */
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#define GRF_SOC_CON11_EMMC_CLKSTABLE_SHIFT (3U)
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#define GRF_SOC_CON11_EMMC_CLKSTABLE_MASK (0x1U << GRF_SOC_CON11_EMMC_CLKSTABLE_SHIFT) /* 0x00000008 */
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#define GRF_SOC_CON11_WDT_NS_PAUSE_EN_SHIFT (4U)
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#define GRF_SOC_CON11_WDT_NS_PAUSE_EN_MASK (0x1U << GRF_SOC_CON11_WDT_NS_PAUSE_EN_SHIFT) /* 0x00000010 */
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#define GRF_SOC_CON11_I2S1_MCLK_SEL_SHIFT (5U)
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#define GRF_SOC_CON11_I2S1_MCLK_SEL_MASK (0x1U << GRF_SOC_CON11_I2S1_MCLK_SEL_SHIFT) /* 0x00000020 */
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#define GRF_SOC_CON11_I2S3_LRCK_SEL_SHIFT (6U)
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#define GRF_SOC_CON11_I2S3_LRCK_SEL_MASK (0x1U << GRF_SOC_CON11_I2S3_LRCK_SEL_SHIFT) /* 0x00000040 */
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#define GRF_SOC_CON11_I2S3_SCLK_SEL_SHIFT (7U)
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#define GRF_SOC_CON11_I2S3_SCLK_SEL_MASK (0x1U << GRF_SOC_CON11_I2S3_SCLK_SEL_SHIFT) /* 0x00000080 */
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#define GRF_SOC_CON11_PCIE_ADDR_EXTEND_SHIFT (8U)
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#define GRF_SOC_CON11_PCIE_ADDR_EXTEND_MASK (0x1U << GRF_SOC_CON11_PCIE_ADDR_EXTEND_SHIFT) /* 0x00000100 */
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#define GRF_SOC_CON11_SDMMC0_BUFFER_EN_SHIFT (9U)
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#define GRF_SOC_CON11_SDMMC0_BUFFER_EN_MASK (0x1U << GRF_SOC_CON11_SDMMC0_BUFFER_EN_SHIFT) /* 0x00000200 */
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#define GRF_SOC_CON11_SDMMC1_BUFFER_EN_SHIFT (10U)
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#define GRF_SOC_CON11_SDMMC1_BUFFER_EN_MASK (0x1U << GRF_SOC_CON11_SDMMC1_BUFFER_EN_SHIFT) /* 0x00000400 */
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#define GRF_SOC_CON11_SDMMC2_BUFFER_EN_SHIFT (11U)
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#define GRF_SOC_CON11_SDMMC2_BUFFER_EN_MASK (0x1U << GRF_SOC_CON11_SDMMC2_BUFFER_EN_SHIFT) /* 0x00000800 */
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#define GRF_SOC_CON11_OTPCS_LOCK_SHIFT (12U)
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#define GRF_SOC_CON11_OTPCS_LOCK_MASK (0x1U << GRF_SOC_CON11_OTPCS_LOCK_SHIFT) /* 0x00001000 */
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#define GRF_SOC_CON11_OPTCNS_LOCK_SHIFT (13U)
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#define GRF_SOC_CON11_OPTCNS_LOCK_MASK (0x1U << GRF_SOC_CON11_OPTCNS_LOCK_SHIFT) /* 0x00002000 */
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/* SOC_CON12 */
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#define GRF_SOC_CON12_OFFSET (0x40508U)
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#define GRF_SOC_CON12_I2S1_MCLK_RX_OE_SHIFT (0U)
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#define GRF_SOC_CON12_I2S1_MCLK_RX_OE_MASK (0x1U << GRF_SOC_CON12_I2S1_MCLK_RX_OE_SHIFT) /* 0x00000001 */
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#define GRF_SOC_CON12_I2S1_MCLK_TX_OE_SHIFT (1U)
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#define GRF_SOC_CON12_I2S1_MCLK_TX_OE_MASK (0x1U << GRF_SOC_CON12_I2S1_MCLK_TX_OE_SHIFT) /* 0x00000002 */
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#define GRF_SOC_CON12_I2S2_MCLK_OE_SHIFT (2U)
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#define GRF_SOC_CON12_I2S2_MCLK_OE_MASK (0x1U << GRF_SOC_CON12_I2S2_MCLK_OE_SHIFT) /* 0x00000004 */
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#define GRF_SOC_CON12_I2S3_MCLK_OE_SHIFT (3U)
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#define GRF_SOC_CON12_I2S3_MCLK_OE_MASK (0x1U << GRF_SOC_CON12_I2S3_MCLK_OE_SHIFT) /* 0x00000008 */
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#define GRF_SOC_CON12_WDTNS_GLB_RESET_EN_SHIFT (4U)
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#define GRF_SOC_CON12_WDTNS_GLB_RESET_EN_MASK (0x1U << GRF_SOC_CON12_WDTNS_GLB_RESET_EN_SHIFT) /* 0x00000010 */
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#define GRF_SOC_CON12_SCR_DET_INV_SEL_SHIFT (5U)
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#define GRF_SOC_CON12_SCR_DET_INV_SEL_MASK (0x1U << GRF_SOC_CON12_SCR_DET_INV_SEL_SHIFT) /* 0x00000020 */
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#define GRF_SOC_CON12_PMU_PWR_IDLE_REQ_SHIFT (10U)
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#define GRF_SOC_CON12_PMU_PWR_IDLE_REQ_MASK (0x1U << GRF_SOC_CON12_PMU_PWR_IDLE_REQ_SHIFT) /* 0x00000400 */
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#define GRF_SOC_CON12_BUS_PWR_IDLE_REQ_SHIFT (11U)
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#define GRF_SOC_CON12_BUS_PWR_IDLE_REQ_MASK (0x1U << GRF_SOC_CON12_BUS_PWR_IDLE_REQ_SHIFT) /* 0x00000800 */
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#define GRF_SOC_CON12_ACDCDIG_I2S_ACTIVE_SHIFT (13U)
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#define GRF_SOC_CON12_ACDCDIG_I2S_ACTIVE_MASK (0x1U << GRF_SOC_CON12_ACDCDIG_I2S_ACTIVE_SHIFT) /* 0x00002000 */
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#define GRF_SOC_CON12_ACDCDIG_I2C_TRAN_REQ_SHIFT (14U)
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#define GRF_SOC_CON12_ACDCDIG_I2C_TRAN_REQ_MASK (0x1U << GRF_SOC_CON12_ACDCDIG_I2C_TRAN_REQ_SHIFT) /* 0x00004000 */
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#define GRF_SOC_CON12_I2S3_MCLK_SEL_SHIFT (15U)
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#define GRF_SOC_CON12_I2S3_MCLK_SEL_MASK (0x1U << GRF_SOC_CON12_I2S3_MCLK_SEL_SHIFT) /* 0x00008000 */
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/* SOC_CON13 */
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#define GRF_SOC_CON13_OFFSET (0x4050CU)
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#define GRF_SOC_CON13_SDMMC_BUFFER_WR_THRESH_SHIFT (0U)
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#define GRF_SOC_CON13_SDMMC_BUFFER_WR_THRESH_MASK (0x1FU << GRF_SOC_CON13_SDMMC_BUFFER_WR_THRESH_SHIFT) /* 0x0000001F */
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#define GRF_SOC_CON13_SDMMC_BUFFER_EN_SHIFT (6U)
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#define GRF_SOC_CON13_SDMMC_BUFFER_EN_MASK (0x1U << GRF_SOC_CON13_SDMMC_BUFFER_EN_SHIFT) /* 0x00000040 */
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#define GRF_SOC_CON13_SDMMC_BUF_CLK_INV_SEL_SHIFT (7U)
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#define GRF_SOC_CON13_SDMMC_BUF_CLK_INV_SEL_MASK (0x1U << GRF_SOC_CON13_SDMMC_BUF_CLK_INV_SEL_SHIFT) /* 0x00000080 */
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#define GRF_SOC_CON13_HDCP_UART_EN_SHIFT (8U)
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#define GRF_SOC_CON13_HDCP_UART_EN_MASK (0x1U << GRF_SOC_CON13_HDCP_UART_EN_SHIFT) /* 0x00000100 */
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#define GRF_SOC_CON13_MCU_SOFT_IRQ_SHIFT (12U)
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#define GRF_SOC_CON13_MCU_SOFT_IRQ_MASK (0x1U << GRF_SOC_CON13_MCU_SOFT_IRQ_SHIFT) /* 0x00001000 */
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#define GRF_SOC_CON13_MCU_SEL_AXI_SHIFT (13U)
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#define GRF_SOC_CON13_MCU_SEL_AXI_MASK (0x1U << GRF_SOC_CON13_MCU_SEL_AXI_SHIFT) /* 0x00002000 */
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#define GRF_SOC_CON13_MCU_AHB2AXI_I_BUF_FLUSH_SHIFT (14U)
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#define GRF_SOC_CON13_MCU_AHB2AXI_I_BUF_FLUSH_MASK (0x1U << GRF_SOC_CON13_MCU_AHB2AXI_I_BUF_FLUSH_SHIFT) /* 0x00004000 */
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#define GRF_SOC_CON13_MCU_AHB2AXI_D_BUF_FLUSH_SHIFT (15U)
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#define GRF_SOC_CON13_MCU_AHB2AXI_D_BUF_FLUSH_MASK (0x1U << GRF_SOC_CON13_MCU_AHB2AXI_D_BUF_FLUSH_SHIFT) /* 0x00008000 */
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/* SOC_CON14 */
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#define GRF_SOC_CON14_OFFSET (0x40510U)
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#define GRF_SOC_CON14_MCU_BOOT_ADDR_SHIFT (0U)
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#define GRF_SOC_CON14_MCU_BOOT_ADDR_MASK (0xFFFFU << GRF_SOC_CON14_MCU_BOOT_ADDR_SHIFT) /* 0x0000FFFF */
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/* SOC_CON15 */
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#define GRF_SOC_CON15_OFFSET (0x40514U)
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#define GRF_SOC_CON15_SDCARD_DECTN_DLY_SHIFT (0U)
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#define GRF_SOC_CON15_SDCARD_DECTN_DLY_MASK (0xFFFFFFFFU << GRF_SOC_CON15_SDCARD_DECTN_DLY_SHIFT) /* 0xFFFFFFFF */
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/* SOC_CON16 */
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#define GRF_SOC_CON16_OFFSET (0x40518U)
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#define GRF_SOC_CON16_AHB2AXI_D_TIMEOUT_SHIFT (0U)
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#define GRF_SOC_CON16_AHB2AXI_D_TIMEOUT_MASK (0xFFU << GRF_SOC_CON16_AHB2AXI_D_TIMEOUT_SHIFT) /* 0x000000FF */
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#define GRF_SOC_CON16_AHB2AXI_I_RD_CLEAN_SHIFT (8U)
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#define GRF_SOC_CON16_AHB2AXI_I_RD_CLEAN_MASK (0x1U << GRF_SOC_CON16_AHB2AXI_I_RD_CLEAN_SHIFT) /* 0x00000100 */
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#define GRF_SOC_CON16_AHB2AXI_D_RD_CLEAN_SHIFT (9U)
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#define GRF_SOC_CON16_AHB2AXI_D_RD_CLEAN_MASK (0x1U << GRF_SOC_CON16_AHB2AXI_D_RD_CLEAN_SHIFT) /* 0x00000200 */
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#define GRF_SOC_CON16_PCIE30PHY_PRB_IO_EN_SHIFT (10U)
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#define GRF_SOC_CON16_PCIE30PHY_PRB_IO_EN_MASK (0x1U << GRF_SOC_CON16_PCIE30PHY_PRB_IO_EN_SHIFT) /* 0x00000400 */
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#define GRF_SOC_CON16_HPLL_CLK_SEL_SHIFT (11U)
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#define GRF_SOC_CON16_HPLL_CLK_SEL_MASK (0x1U << GRF_SOC_CON16_HPLL_CLK_SEL_SHIFT) /* 0x00000800 */
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#define GRF_SOC_CON16_PPLL_CLK_SEL_SHIFT (12U)
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#define GRF_SOC_CON16_PPLL_CLK_SEL_MASK (0x1U << GRF_SOC_CON16_PPLL_CLK_SEL_SHIFT) /* 0x00001000 */
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#define GRF_SOC_CON16_GMAC0_TXCLK_INV_EN_SHIFT (13U)
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#define GRF_SOC_CON16_GMAC0_TXCLK_INV_EN_MASK (0x1U << GRF_SOC_CON16_GMAC0_TXCLK_INV_EN_SHIFT) /* 0x00002000 */
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#define GRF_SOC_CON16_GMAC1_TXCLKM0_INV_EN_SHIFT (14U)
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#define GRF_SOC_CON16_GMAC1_TXCLKM0_INV_EN_MASK (0x1U << GRF_SOC_CON16_GMAC1_TXCLKM0_INV_EN_SHIFT) /* 0x00004000 */
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#define GRF_SOC_CON16_GMAC1_TXCLKM1_INV_EN_SHIFT (15U)
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#define GRF_SOC_CON16_GMAC1_TXCLKM1_INV_EN_MASK (0x1U << GRF_SOC_CON16_GMAC1_TXCLKM1_INV_EN_SHIFT) /* 0x00008000 */
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/* SOC_STATUS0 */
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#define GRF_SOC_STATUS0_OFFSET (0x40580U)
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#define GRF_SOC_STATUS0_APLL_LOCK_SHIFT (0U)
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#define GRF_SOC_STATUS0_APLL_LOCK_MASK (0x1U << GRF_SOC_STATUS0_APLL_LOCK_SHIFT) /* 0x00000001 */
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#define GRF_SOC_STATUS0_DPLL_LOCK_SHIFT (1U)
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#define GRF_SOC_STATUS0_DPLL_LOCK_MASK (0x1U << GRF_SOC_STATUS0_DPLL_LOCK_SHIFT) /* 0x00000002 */
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#define GRF_SOC_STATUS0_CPLL_LOCK_SHIFT (2U)
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#define GRF_SOC_STATUS0_CPLL_LOCK_MASK (0x1U << GRF_SOC_STATUS0_CPLL_LOCK_SHIFT) /* 0x00000004 */
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#define GRF_SOC_STATUS0_GPLL_LOCK_SHIFT (3U)
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#define GRF_SOC_STATUS0_GPLL_LOCK_MASK (0x1U << GRF_SOC_STATUS0_GPLL_LOCK_SHIFT) /* 0x00000008 */
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#define GRF_SOC_STATUS0_PPLL_LOCK_SHIFT (4U)
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#define GRF_SOC_STATUS0_PPLL_LOCK_MASK (0x1U << GRF_SOC_STATUS0_PPLL_LOCK_SHIFT) /* 0x00000010 */
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#define GRF_SOC_STATUS0_NPLL_LOCK_SHIFT (5U)
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#define GRF_SOC_STATUS0_NPLL_LOCK_MASK (0x1U << GRF_SOC_STATUS0_NPLL_LOCK_SHIFT) /* 0x00000020 */
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#define GRF_SOC_STATUS0_VPLL_LOCK_SHIFT (6U)
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#define GRF_SOC_STATUS0_VPLL_LOCK_MASK (0x1U << GRF_SOC_STATUS0_VPLL_LOCK_SHIFT) /* 0x00000040 */
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#define GRF_SOC_STATUS0_HPLL_LOCK_SHIFT (7U)
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#define GRF_SOC_STATUS0_HPLL_LOCK_MASK (0x1U << GRF_SOC_STATUS0_HPLL_LOCK_SHIFT) /* 0x00000080 */
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#define GRF_SOC_STATUS0_MPLL_LOCK_SHIFT (8U)
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#define GRF_SOC_STATUS0_MPLL_LOCK_MASK (0x1U << GRF_SOC_STATUS0_MPLL_LOCK_SHIFT) /* 0x00000100 */
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#define GRF_SOC_STATUS0_ACDCDIG_I2C_TRAN_ACK_SHIFT (9U)
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#define GRF_SOC_STATUS0_ACDCDIG_I2C_TRAN_ACK_MASK (0x1U << GRF_SOC_STATUS0_ACDCDIG_I2C_TRAN_ACK_SHIFT) /* 0x00000200 */
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#define GRF_SOC_STATUS0_DDR_CMD_PLL_LOCK_SHIFT (10U)
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#define GRF_SOC_STATUS0_DDR_CMD_PLL_LOCK_MASK (0x1U << GRF_SOC_STATUS0_DDR_CMD_PLL_LOCK_SHIFT) /* 0x00000400 */
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#define GRF_SOC_STATUS0_TIMER_EN_STATUS0_SHIFT (11U)
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#define GRF_SOC_STATUS0_TIMER_EN_STATUS0_MASK (0x1U << GRF_SOC_STATUS0_TIMER_EN_STATUS0_SHIFT) /* 0x00000800 */
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#define GRF_SOC_STATUS0_TIMER_EN_STATUS1_SHIFT (12U)
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#define GRF_SOC_STATUS0_TIMER_EN_STATUS1_MASK (0x1U << GRF_SOC_STATUS0_TIMER_EN_STATUS1_SHIFT) /* 0x00001000 */
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#define GRF_SOC_STATUS0_TIMER_EN_STATUS2_SHIFT (13U)
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#define GRF_SOC_STATUS0_TIMER_EN_STATUS2_MASK (0x1U << GRF_SOC_STATUS0_TIMER_EN_STATUS2_SHIFT) /* 0x00002000 */
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#define GRF_SOC_STATUS0_TIMER_EN_STATUS3_SHIFT (14U)
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#define GRF_SOC_STATUS0_TIMER_EN_STATUS3_MASK (0x1U << GRF_SOC_STATUS0_TIMER_EN_STATUS3_SHIFT) /* 0x00004000 */
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#define GRF_SOC_STATUS0_TIMER_EN_STATUS4_SHIFT (15U)
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#define GRF_SOC_STATUS0_TIMER_EN_STATUS4_MASK (0x1U << GRF_SOC_STATUS0_TIMER_EN_STATUS4_SHIFT) /* 0x00008000 */
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#define GRF_SOC_STATUS0_TIMER_EN_STATUS5_SHIFT (16U)
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#define GRF_SOC_STATUS0_TIMER_EN_STATUS5_MASK (0x1U << GRF_SOC_STATUS0_TIMER_EN_STATUS5_SHIFT) /* 0x00010000 */
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#define GRF_SOC_STATUS0_VOP_DMA_FINISH_SHIFT (17U)
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#define GRF_SOC_STATUS0_VOP_DMA_FINISH_MASK (0x1U << GRF_SOC_STATUS0_VOP_DMA_FINISH_SHIFT) /* 0x00020000 */
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#define GRF_SOC_STATUS0_SCRAMBLE_SHIFT_READY_SHIFT (18U)
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#define GRF_SOC_STATUS0_SCRAMBLE_SHIFT_READY_MASK (0x1U << GRF_SOC_STATUS0_SCRAMBLE_SHIFT_READY_SHIFT) /* 0x00040000 */
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#define GRF_SOC_STATUS0_BUF_FLUSH_ACK_I_SHIFT (19U)
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#define GRF_SOC_STATUS0_BUF_FLUSH_ACK_I_MASK (0x1U << GRF_SOC_STATUS0_BUF_FLUSH_ACK_I_SHIFT) /* 0x00080000 */
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#define GRF_SOC_STATUS0_BUF_FLUSH_ACK_D_SHIFT (20U)
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#define GRF_SOC_STATUS0_BUF_FLUSH_ACK_D_MASK (0x1U << GRF_SOC_STATUS0_BUF_FLUSH_ACK_D_SHIFT) /* 0x00100000 */
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#define GRF_SOC_STATUS0_PMU_PWR_IDLE_SHIFT (21U)
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#define GRF_SOC_STATUS0_PMU_PWR_IDLE_MASK (0x1U << GRF_SOC_STATUS0_PMU_PWR_IDLE_SHIFT) /* 0x00200000 */
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#define GRF_SOC_STATUS0_PMU_PWR_IDLE_ACK_SHIFT (22U)
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#define GRF_SOC_STATUS0_PMU_PWR_IDLE_ACK_MASK (0x1U << GRF_SOC_STATUS0_PMU_PWR_IDLE_ACK_SHIFT) /* 0x00400000 */
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#define GRF_SOC_STATUS0_OTPCNS_SBPI_BUSY_SHIFT (23U)
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#define GRF_SOC_STATUS0_OTPCNS_SBPI_BUSY_MASK (0x1U << GRF_SOC_STATUS0_OTPCNS_SBPI_BUSY_SHIFT) /* 0x00800000 */
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#define GRF_SOC_STATUS0_OTPCNS_USER_BUSY_SHIFT (24U)
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#define GRF_SOC_STATUS0_OTPCNS_USER_BUSY_MASK (0x1U << GRF_SOC_STATUS0_OTPCNS_USER_BUSY_SHIFT) /* 0x01000000 */
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#define GRF_SOC_STATUS0_OTP_S_SBPI_BUSY_SHIFT (25U)
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#define GRF_SOC_STATUS0_OTP_S_SBPI_BUSY_MASK (0x1U << GRF_SOC_STATUS0_OTP_S_SBPI_BUSY_SHIFT) /* 0x02000000 */
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#define GRF_SOC_STATUS0_OTP_S_USER_BUSY_SHIFT (26U)
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#define GRF_SOC_STATUS0_OTP_S_USER_BUSY_MASK (0x1U << GRF_SOC_STATUS0_OTP_S_USER_BUSY_SHIFT) /* 0x04000000 */
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#define GRF_SOC_STATUS0_WFI_HALTED_SHIFT (27U)
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#define GRF_SOC_STATUS0_WFI_HALTED_MASK (0x1U << GRF_SOC_STATUS0_WFI_HALTED_SHIFT) /* 0x08000000 */
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/* RAM_CON */
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#define GRF_RAM_CON_OFFSET (0x405C0U)
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#define GRF_RAM_CON_SPRA_RTSEL_SHIFT (0U)
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#define GRF_RAM_CON_SPRA_RTSEL_MASK (0x3U << GRF_RAM_CON_SPRA_RTSEL_SHIFT) /* 0x00000003 */
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#define GRF_RAM_CON_SPRA_WTSEL_SHIFT (2U)
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#define GRF_RAM_CON_SPRA_WTSEL_MASK (0x3U << GRF_RAM_CON_SPRA_WTSEL_SHIFT) /* 0x0000000C */
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#define GRF_RAM_CON_DPRA_PTSEL_SHIFT (4U)
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#define GRF_RAM_CON_DPRA_PTSEL_MASK (0x3U << GRF_RAM_CON_DPRA_PTSEL_SHIFT) /* 0x00000030 */
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#define GRF_RAM_CON_DPRA_RTSEL_SHIFT (6U)
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#define GRF_RAM_CON_DPRA_RTSEL_MASK (0x3U << GRF_RAM_CON_DPRA_RTSEL_SHIFT) /* 0x000000C0 */
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#define GRF_RAM_CON_DPRA_WTSEL_SHIFT (8U)
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#define GRF_RAM_CON_DPRA_WTSEL_MASK (0x3U << GRF_RAM_CON_DPRA_WTSEL_SHIFT) /* 0x00000300 */
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#define GRF_RAM_CON_ROM_PTSEL_SHIFT (10U)
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#define GRF_RAM_CON_ROM_PTSEL_MASK (0x3U << GRF_RAM_CON_ROM_PTSEL_SHIFT) /* 0x00000C00 */
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#define GRF_RAM_CON_ROM_RTSEL_SHIFT (12U)
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#define GRF_RAM_CON_ROM_RTSEL_MASK (0x3U << GRF_RAM_CON_ROM_RTSEL_SHIFT) /* 0x00003000 */
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#define GRF_RAM_CON_ROM_TRB_SHIFT (14U)
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#define GRF_RAM_CON_ROM_TRB_MASK (0x3U << GRF_RAM_CON_ROM_TRB_SHIFT) /* 0x0000C000 */
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/* CORE_RAM_CON */
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#define GRF_CORE_RAM_CON_OFFSET (0x405C4U)
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#define GRF_CORE_RAM_CON_WTSEL_CPU_SHIFT (0U)
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#define GRF_CORE_RAM_CON_WTSEL_CPU_MASK (0x3U << GRF_CORE_RAM_CON_WTSEL_CPU_SHIFT) /* 0x00000003 */
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#define GRF_CORE_RAM_CON_RTSEL_CPU_SHIFT (2U)
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#define GRF_CORE_RAM_CON_RTSEL_CPU_MASK (0x3U << GRF_CORE_RAM_CON_RTSEL_CPU_SHIFT) /* 0x0000000C */
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#define GRF_CORE_RAM_CON_WTSEL_CPU_DSU_SHIFT (4U)
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#define GRF_CORE_RAM_CON_WTSEL_CPU_DSU_MASK (0x3U << GRF_CORE_RAM_CON_WTSEL_CPU_DSU_SHIFT) /* 0x00000030 */
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#define GRF_CORE_RAM_CON_RTSEL_CPU_DSU_SHIFT (6U)
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#define GRF_CORE_RAM_CON_RTSEL_CPU_DSU_MASK (0x3U << GRF_CORE_RAM_CON_RTSEL_CPU_DSU_SHIFT) /* 0x000000C0 */
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#define GRF_CORE_RAM_CON_SPRA_SLP_SHIFT (15U)
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#define GRF_CORE_RAM_CON_SPRA_SLP_MASK (0x1U << GRF_CORE_RAM_CON_SPRA_SLP_SHIFT) /* 0x00008000 */
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/* TSADC_CON */
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#define GRF_TSADC_CON_OFFSET (0x40600U)
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#define GRF_TSADC_CON_TSADC_ANA_REG0_SHIFT (0U)
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#define GRF_TSADC_CON_TSADC_ANA_REG0_MASK (0x1U << GRF_TSADC_CON_TSADC_ANA_REG0_SHIFT) /* 0x00000001 */
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#define GRF_TSADC_CON_TSADC_ANA_REG1_SHIFT (1U)
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#define GRF_TSADC_CON_TSADC_ANA_REG1_MASK (0x1U << GRF_TSADC_CON_TSADC_ANA_REG1_SHIFT) /* 0x00000002 */
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#define GRF_TSADC_CON_TSADC_ANA_REG2_SHIFT (2U)
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#define GRF_TSADC_CON_TSADC_ANA_REG2_MASK (0x1U << GRF_TSADC_CON_TSADC_ANA_REG2_SHIFT) /* 0x00000004 */
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#define GRF_TSADC_CON_TSADC_ANA_REG3_SHIFT (3U)
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#define GRF_TSADC_CON_TSADC_ANA_REG3_MASK (0x1U << GRF_TSADC_CON_TSADC_ANA_REG3_SHIFT) /* 0x00000008 */
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#define GRF_TSADC_CON_TSADC_ANA_REG4_SHIFT (4U)
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#define GRF_TSADC_CON_TSADC_ANA_REG4_MASK (0x1U << GRF_TSADC_CON_TSADC_ANA_REG4_SHIFT) /* 0x00000010 */
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#define GRF_TSADC_CON_TSADC_ANA_REG5_SHIFT (5U)
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#define GRF_TSADC_CON_TSADC_ANA_REG5_MASK (0x1U << GRF_TSADC_CON_TSADC_ANA_REG5_SHIFT) /* 0x00000020 */
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#define GRF_TSADC_CON_TSADC_ANA_REG6_SHIFT (6U)
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#define GRF_TSADC_CON_TSADC_ANA_REG6_MASK (0x1U << GRF_TSADC_CON_TSADC_ANA_REG6_SHIFT) /* 0x00000040 */
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#define GRF_TSADC_CON_TSADC_TSEN_SHIFT (8U)
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#define GRF_TSADC_CON_TSADC_TSEN_MASK (0x1U << GRF_TSADC_CON_TSADC_TSEN_SHIFT) /* 0x00000100 */
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/* SARADC_CON */
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#define GRF_SARADC_CON_OFFSET (0x40610U)
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#define GRF_SARADC_CON_SARADC_ANA_REG_SHIFT (0U)
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#define GRF_SARADC_CON_SARADC_ANA_REG_MASK (0xFFFFU << GRF_SARADC_CON_SARADC_ANA_REG_SHIFT) /* 0x0000FFFF */
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/* GPUPVTPLL_CON0 */
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#define GRF_GPUPVTPLL_CON0_OFFSET (0x40700U)
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#define GRF_GPUPVTPLL_CON0_GPUPVTPLL_START_SHIFT (0U)
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#define GRF_GPUPVTPLL_CON0_GPUPVTPLL_START_MASK (0x1U << GRF_GPUPVTPLL_CON0_GPUPVTPLL_START_SHIFT) /* 0x00000001 */
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#define GRF_GPUPVTPLL_CON0_GPUPVTPLL_OSC_EN_SHIFT (1U)
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#define GRF_GPUPVTPLL_CON0_GPUPVTPLL_OSC_EN_MASK (0x1U << GRF_GPUPVTPLL_CON0_GPUPVTPLL_OSC_EN_SHIFT) /* 0x00000002 */
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#define GRF_GPUPVTPLL_CON0_GPUPVTPLL_OUT_POLAR_SHIFT (2U)
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#define GRF_GPUPVTPLL_CON0_GPUPVTPLL_OUT_POLAR_MASK (0x1U << GRF_GPUPVTPLL_CON0_GPUPVTPLL_OUT_POLAR_SHIFT) /* 0x00000004 */
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#define GRF_GPUPVTPLL_CON0_GPU_PVTPLL_RING_LENGTH_SEL_SHIFT (3U)
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#define GRF_GPUPVTPLL_CON0_GPU_PVTPLL_RING_LENGTH_SEL_MASK (0x1FU << GRF_GPUPVTPLL_CON0_GPU_PVTPLL_RING_LENGTH_SEL_SHIFT) /* 0x000000F8 */
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#define GRF_GPUPVTPLL_CON0_GPU_PVTPLL_OSC_SEL_SHIFT (8U)
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#define GRF_GPUPVTPLL_CON0_GPU_PVTPLL_OSC_SEL_MASK (0x7U << GRF_GPUPVTPLL_CON0_GPU_PVTPLL_OSC_SEL_SHIFT) /* 0x00000700 */
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#define GRF_GPUPVTPLL_CON0_GPU_PVTPLL_CLK_DIV_CNT_SHIFT (11U)
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#define GRF_GPUPVTPLL_CON0_GPU_PVTPLL_CLK_DIV_CNT_MASK (0xFU << GRF_GPUPVTPLL_CON0_GPU_PVTPLL_CLK_DIV_CNT_SHIFT) /* 0x00007800 */
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/* GPUPVTPLL_CON1 */
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#define GRF_GPUPVTPLL_CON1_OFFSET (0x40704U)
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#define GRF_GPUPVTPLL_CON1_PVTPLL_CAL_CNT_SHIFT (0U)
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#define GRF_GPUPVTPLL_CON1_PVTPLL_CAL_CNT_MASK (0xFFFFFFFFU << GRF_GPUPVTPLL_CON1_PVTPLL_CAL_CNT_SHIFT) /* 0xFFFFFFFF */
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/* GPUPVTPLL_CON2 */
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#define GRF_GPUPVTPLL_CON2_OFFSET (0x40708U)
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#define GRF_GPUPVTPLL_CON2_GPU_PVTPLL_THRESHOLD_SHIFT (0U)
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#define GRF_GPUPVTPLL_CON2_GPU_PVTPLL_THRESHOLD_MASK (0xFFFFFFFFU << GRF_GPUPVTPLL_CON2_GPU_PVTPLL_THRESHOLD_SHIFT) /* 0xFFFFFFFF */
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/* GPUPVTPLL_CON3 */
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#define GRF_GPUPVTPLL_CON3_OFFSET (0x4070CU)
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#define GRF_GPUPVTPLL_CON3_GPU_PVTPLL_REF_CNT_SHIFT (0U)
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#define GRF_GPUPVTPLL_CON3_GPU_PVTPLL_REF_CNT_MASK (0xFFFFFFFFU << GRF_GPUPVTPLL_CON3_GPU_PVTPLL_REF_CNT_SHIFT) /* 0xFFFFFFFF */
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/* NPUPVTPLL_CON0 */
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#define GRF_NPUPVTPLL_CON0_OFFSET (0x40740U)
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#define GRF_NPUPVTPLL_CON0_GPUPVTPLL_START_SHIFT (0U)
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#define GRF_NPUPVTPLL_CON0_GPUPVTPLL_START_MASK (0x1U << GRF_NPUPVTPLL_CON0_GPUPVTPLL_START_SHIFT) /* 0x00000001 */
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#define GRF_NPUPVTPLL_CON0_GPUPVTPLL_OSC_EN_SHIFT (1U)
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#define GRF_NPUPVTPLL_CON0_GPUPVTPLL_OSC_EN_MASK (0x1U << GRF_NPUPVTPLL_CON0_GPUPVTPLL_OSC_EN_SHIFT) /* 0x00000002 */
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#define GRF_NPUPVTPLL_CON0_GPUPVTPLL_OUT_POLAR_SHIFT (2U)
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#define GRF_NPUPVTPLL_CON0_GPUPVTPLL_OUT_POLAR_MASK (0x1U << GRF_NPUPVTPLL_CON0_GPUPVTPLL_OUT_POLAR_SHIFT) /* 0x00000004 */
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#define GRF_NPUPVTPLL_CON0_GPU_PVTPLL_RING_LENGTH_SEL_SHIFT (3U)
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#define GRF_NPUPVTPLL_CON0_GPU_PVTPLL_RING_LENGTH_SEL_MASK (0x1FU << GRF_NPUPVTPLL_CON0_GPU_PVTPLL_RING_LENGTH_SEL_SHIFT) /* 0x000000F8 */
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#define GRF_NPUPVTPLL_CON0_GPU_PVTPLL_OSC_SEL_SHIFT (8U)
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#define GRF_NPUPVTPLL_CON0_GPU_PVTPLL_OSC_SEL_MASK (0x7U << GRF_NPUPVTPLL_CON0_GPU_PVTPLL_OSC_SEL_SHIFT) /* 0x00000700 */
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#define GRF_NPUPVTPLL_CON0_GPU_PVTPLL_CLK_DIV_CNT_SHIFT (11U)
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#define GRF_NPUPVTPLL_CON0_GPU_PVTPLL_CLK_DIV_CNT_MASK (0xFU << GRF_NPUPVTPLL_CON0_GPU_PVTPLL_CLK_DIV_CNT_SHIFT) /* 0x00007800 */
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/* NPUPVTPLL_CON1 */
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#define GRF_NPUPVTPLL_CON1_OFFSET (0x40744U)
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#define GRF_NPUPVTPLL_CON1_PVTPLL_CAL_CNT_SHIFT (0U)
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#define GRF_NPUPVTPLL_CON1_PVTPLL_CAL_CNT_MASK (0xFFFFFFFFU << GRF_NPUPVTPLL_CON1_PVTPLL_CAL_CNT_SHIFT) /* 0xFFFFFFFF */
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/* NPUPVTPLL_CON2 */
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#define GRF_NPUPVTPLL_CON2_OFFSET (0x40748U)
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#define GRF_NPUPVTPLL_CON2_GPU_PVTPLL_THRESHOLD_SHIFT (0U)
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#define GRF_NPUPVTPLL_CON2_GPU_PVTPLL_THRESHOLD_MASK (0xFFFFFFFFU << GRF_NPUPVTPLL_CON2_GPU_PVTPLL_THRESHOLD_SHIFT) /* 0xFFFFFFFF */
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/* NPUPVTPLL_CON3 */
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#define GRF_NPUPVTPLL_CON3_OFFSET (0x4074CU)
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#define GRF_NPUPVTPLL_CON3_GPU_PVTPLL_REF_CNT_SHIFT (0U)
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#define GRF_NPUPVTPLL_CON3_GPU_PVTPLL_REF_CNT_MASK (0xFFFFFFFFU << GRF_NPUPVTPLL_CON3_GPU_PVTPLL_REF_CNT_SHIFT) /* 0xFFFFFFFF */
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/* CHIP_ID */
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#define GRF_CHIP_ID_OFFSET (0x40800U)
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#define GRF_CHIP_ID_CHIP_ID_SHIFT (0U)
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#define GRF_CHIP_ID_CHIP_ID_MASK (0xFFFFFFFFU << GRF_CHIP_ID_CHIP_ID_SHIFT) /* 0xFFFFFFFF */
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/* GPIO1C5_DS */
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#define GRF_GPIO1C5_DS_OFFSET (0x40840U)
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#define GRF_GPIO1C5_DS_GPIO1C5_DS_SHIFT (0U)
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#define GRF_GPIO1C5_DS_GPIO1C5_DS_MASK (0x3FU << GRF_GPIO1C5_DS_GPIO1C5_DS_SHIFT) /* 0x0000003F */
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/* GPIO2A2_DS */
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#define GRF_GPIO2A2_DS_OFFSET (0x40844U)
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#define GRF_GPIO2A2_DS_GPIO2A2_DS_SHIFT (0U)
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#define GRF_GPIO2A2_DS_GPIO2A2_DS_MASK (0x3FU << GRF_GPIO2A2_DS_GPIO2A2_DS_SHIFT) /* 0x0000003F */
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/* GPIO2B0_DS */
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#define GRF_GPIO2B0_DS_OFFSET (0x40848U)
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#define GRF_GPIO2B0_DS_GPIO2B0_DS_SHIFT (0U)
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#define GRF_GPIO2B0_DS_GPIO2B0_DS_MASK (0x3FU << GRF_GPIO2B0_DS_GPIO2B0_DS_SHIFT) /* 0x0000003F */
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/* GPIO3A0_DS */
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#define GRF_GPIO3A0_DS_OFFSET (0x4084CU)
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#define GRF_GPIO3A0_DS_GPIO3A0_DS_SHIFT (0U)
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#define GRF_GPIO3A0_DS_GPIO3A0_DS_MASK (0x3FU << GRF_GPIO3A0_DS_GPIO3A0_DS_SHIFT) /* 0x0000003F */
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/* GPIO3A6_DS */
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#define GRF_GPIO3A6_DS_OFFSET (0x40850U)
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#define GRF_GPIO3A6_DS_GPIO3A6_DS_SHIFT (0U)
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#define GRF_GPIO3A6_DS_GPIO3A6_DS_MASK (0x3FU << GRF_GPIO3A6_DS_GPIO3A6_DS_SHIFT) /* 0x0000003F */
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/* GPIO4A0_DS */
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#define GRF_GPIO4A0_DS_OFFSET (0x40854U)
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#define GRF_GPIO4A0_DS_GPIO4A0_DS_SHIFT (0U)
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#define GRF_GPIO4A0_DS_GPIO4A0_DS_MASK (0x3FU << GRF_GPIO4A0_DS_GPIO4A0_DS_SHIFT) /* 0x0000003F */
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/* DMAC0_CON0 */
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#define GRF_DMAC0_CON0_OFFSET (0x40900U)
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#define GRF_DMAC0_CON0_DMA0_IRQ_BOOT_NONSEC_SHIFT (0U)
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#define GRF_DMAC0_CON0_DMA0_IRQ_BOOT_NONSEC_MASK (0xFFFFU << GRF_DMAC0_CON0_DMA0_IRQ_BOOT_NONSEC_SHIFT) /* 0x0000FFFF */
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/* DMAC0_CON1 */
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#define GRF_DMAC0_CON1_OFFSET (0x40904U)
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#define GRF_DMAC0_CON1_DMA0_PERI_CH_NONSEC_15_0_SHIFT (0U)
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#define GRF_DMAC0_CON1_DMA0_PERI_CH_NONSEC_15_0_MASK (0xFFFFU << GRF_DMAC0_CON1_DMA0_PERI_CH_NONSEC_15_0_SHIFT) /* 0x0000FFFF */
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/* DMAC0_CON2 */
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#define GRF_DMAC0_CON2_OFFSET (0x40908U)
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#define GRF_DMAC0_CON2_DMA0_PERI_CH_NONSEC_31_16_SHIFT (0U)
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#define GRF_DMAC0_CON2_DMA0_PERI_CH_NONSEC_31_16_MASK (0xFFFFU << GRF_DMAC0_CON2_DMA0_PERI_CH_NONSEC_31_16_SHIFT) /* 0x0000FFFF */
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/* DMAC0_CON3 */
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#define GRF_DMAC0_CON3_OFFSET (0x4090CU)
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#define GRF_DMAC0_CON3_DMA0_MANAGER_BOOT_NONSEC_SHIFT (0U)
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#define GRF_DMAC0_CON3_DMA0_MANAGER_BOOT_NONSEC_MASK (0x1U << GRF_DMAC0_CON3_DMA0_MANAGER_BOOT_NONSEC_SHIFT) /* 0x00000001 */
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/* DMAC0_CON4 */
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#define GRF_DMAC0_CON4_OFFSET (0x40910U)
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#define GRF_DMAC0_CON4_GRF_TYPE_UART_0_TX_SHIFT (0U)
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#define GRF_DMAC0_CON4_GRF_TYPE_UART_0_TX_MASK (0x3U << GRF_DMAC0_CON4_GRF_TYPE_UART_0_TX_SHIFT) /* 0x00000003 */
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#define GRF_DMAC0_CON4_GRF_TYPE_UART_0_RX_SHIFT (2U)
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#define GRF_DMAC0_CON4_GRF_TYPE_UART_0_RX_MASK (0x3U << GRF_DMAC0_CON4_GRF_TYPE_UART_0_RX_SHIFT) /* 0x0000000C */
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#define GRF_DMAC0_CON4_GRF_TYPE_UART_1_TX_SHIFT (4U)
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#define GRF_DMAC0_CON4_GRF_TYPE_UART_1_TX_MASK (0x3U << GRF_DMAC0_CON4_GRF_TYPE_UART_1_TX_SHIFT) /* 0x00000030 */
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#define GRF_DMAC0_CON4_GRF_TYPE_UART_1_RX_SHIFT (6U)
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#define GRF_DMAC0_CON4_GRF_TYPE_UART_1_RX_MASK (0x3U << GRF_DMAC0_CON4_GRF_TYPE_UART_1_RX_SHIFT) /* 0x000000C0 */
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#define GRF_DMAC0_CON4_GRF_TYPE_UART_2_TX_SHIFT (8U)
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#define GRF_DMAC0_CON4_GRF_TYPE_UART_2_TX_MASK (0x3U << GRF_DMAC0_CON4_GRF_TYPE_UART_2_TX_SHIFT) /* 0x00000300 */
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#define GRF_DMAC0_CON4_GRF_TYPE_UART_2_RX_SHIFT (10U)
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#define GRF_DMAC0_CON4_GRF_TYPE_UART_2_RX_MASK (0x3U << GRF_DMAC0_CON4_GRF_TYPE_UART_2_RX_SHIFT) /* 0x00000C00 */
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#define GRF_DMAC0_CON4_GRF_TYPE_UART_3_TX_SHIFT (12U)
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#define GRF_DMAC0_CON4_GRF_TYPE_UART_3_TX_MASK (0x3U << GRF_DMAC0_CON4_GRF_TYPE_UART_3_TX_SHIFT) /* 0x00003000 */
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#define GRF_DMAC0_CON4_GRF_TYPE_UART_3_RX_SHIFT (14U)
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#define GRF_DMAC0_CON4_GRF_TYPE_UART_3_RX_MASK (0x3U << GRF_DMAC0_CON4_GRF_TYPE_UART_3_RX_SHIFT) /* 0x0000C000 */
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/* DMAC0_CON5 */
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#define GRF_DMAC0_CON5_OFFSET (0x40914U)
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#define GRF_DMAC0_CON5_GRF_TYPE_UART_4_TX_SHIFT (0U)
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#define GRF_DMAC0_CON5_GRF_TYPE_UART_4_TX_MASK (0x3U << GRF_DMAC0_CON5_GRF_TYPE_UART_4_TX_SHIFT) /* 0x00000003 */
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#define GRF_DMAC0_CON5_GRF_TYPE_UART_4_RX_SHIFT (2U)
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#define GRF_DMAC0_CON5_GRF_TYPE_UART_4_RX_MASK (0x3U << GRF_DMAC0_CON5_GRF_TYPE_UART_4_RX_SHIFT) /* 0x0000000C */
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#define GRF_DMAC0_CON5_GRF_TYPE_UART_5_TX_SHIFT (4U)
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#define GRF_DMAC0_CON5_GRF_TYPE_UART_5_TX_MASK (0x3U << GRF_DMAC0_CON5_GRF_TYPE_UART_5_TX_SHIFT) /* 0x00000030 */
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#define GRF_DMAC0_CON5_GRF_TYPE_UART_5_RX_SHIFT (6U)
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#define GRF_DMAC0_CON5_GRF_TYPE_UART_5_RX_MASK (0x3U << GRF_DMAC0_CON5_GRF_TYPE_UART_5_RX_SHIFT) /* 0x000000C0 */
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#define GRF_DMAC0_CON5_GRF_TYPE_UART_6_TX_SHIFT (8U)
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#define GRF_DMAC0_CON5_GRF_TYPE_UART_6_TX_MASK (0x3U << GRF_DMAC0_CON5_GRF_TYPE_UART_6_TX_SHIFT) /* 0x00000300 */
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#define GRF_DMAC0_CON5_GRF_TYPE_UART_6_RX_SHIFT (10U)
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#define GRF_DMAC0_CON5_GRF_TYPE_UART_6_RX_MASK (0x3U << GRF_DMAC0_CON5_GRF_TYPE_UART_6_RX_SHIFT) /* 0x00000C00 */
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#define GRF_DMAC0_CON5_GRF_TYPE_UART_7_TX_SHIFT (12U)
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#define GRF_DMAC0_CON5_GRF_TYPE_UART_7_TX_MASK (0x3U << GRF_DMAC0_CON5_GRF_TYPE_UART_7_TX_SHIFT) /* 0x00003000 */
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#define GRF_DMAC0_CON5_GRF_TYPE_UART_7_RX_SHIFT (14U)
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#define GRF_DMAC0_CON5_GRF_TYPE_UART_7_RX_MASK (0x3U << GRF_DMAC0_CON5_GRF_TYPE_UART_7_RX_SHIFT) /* 0x0000C000 */
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/* DMAC0_CON6 */
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#define GRF_DMAC0_CON6_OFFSET (0x40918U)
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#define GRF_DMAC0_CON6_GRF_TYPE_UART_8_TX_SHIFT (0U)
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#define GRF_DMAC0_CON6_GRF_TYPE_UART_8_TX_MASK (0x3U << GRF_DMAC0_CON6_GRF_TYPE_UART_8_TX_SHIFT) /* 0x00000003 */
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#define GRF_DMAC0_CON6_GRF_TYPE_UART_8_RX_SHIFT (2U)
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#define GRF_DMAC0_CON6_GRF_TYPE_UART_8_RX_MASK (0x3U << GRF_DMAC0_CON6_GRF_TYPE_UART_8_RX_SHIFT) /* 0x0000000C */
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#define GRF_DMAC0_CON6_GRF_TYPE_UART_9_TX_SHIFT (4U)
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#define GRF_DMAC0_CON6_GRF_TYPE_UART_9_TX_MASK (0x3U << GRF_DMAC0_CON6_GRF_TYPE_UART_9_TX_SHIFT) /* 0x00000030 */
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#define GRF_DMAC0_CON6_GRF_TYPE_UART_9_RX_SHIFT (6U)
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#define GRF_DMAC0_CON6_GRF_TYPE_UART_9_RX_MASK (0x3U << GRF_DMAC0_CON6_GRF_TYPE_UART_9_RX_SHIFT) /* 0x000000C0 */
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#define GRF_DMAC0_CON6_GRF_TYPE_SPI0_TX_SHIFT (8U)
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#define GRF_DMAC0_CON6_GRF_TYPE_SPI0_TX_MASK (0x3U << GRF_DMAC0_CON6_GRF_TYPE_SPI0_TX_SHIFT) /* 0x00000300 */
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#define GRF_DMAC0_CON6_GRF_TYPE_SPI0_RX_SHIFT (10U)
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#define GRF_DMAC0_CON6_GRF_TYPE_SPI0_RX_MASK (0x3U << GRF_DMAC0_CON6_GRF_TYPE_SPI0_RX_SHIFT) /* 0x00000C00 */
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#define GRF_DMAC0_CON6_GRF_TYPE_SPI1_TX_SHIFT (12U)
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#define GRF_DMAC0_CON6_GRF_TYPE_SPI1_TX_MASK (0x3U << GRF_DMAC0_CON6_GRF_TYPE_SPI1_TX_SHIFT) /* 0x00003000 */
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#define GRF_DMAC0_CON6_GRF_TYPE_SPI1_RX_SHIFT (14U)
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#define GRF_DMAC0_CON6_GRF_TYPE_SPI1_RX_MASK (0x3U << GRF_DMAC0_CON6_GRF_TYPE_SPI1_RX_SHIFT) /* 0x0000C000 */
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/* DMAC0_CON7 */
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#define GRF_DMAC0_CON7_OFFSET (0x4091CU)
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#define GRF_DMAC0_CON7_GRF_TYPE_SPI2_TX_SHIFT (0U)
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#define GRF_DMAC0_CON7_GRF_TYPE_SPI2_TX_MASK (0x3U << GRF_DMAC0_CON7_GRF_TYPE_SPI2_TX_SHIFT) /* 0x00000003 */
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#define GRF_DMAC0_CON7_GRF_TYPE_SPI2_RX_SHIFT (2U)
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#define GRF_DMAC0_CON7_GRF_TYPE_SPI2_RX_MASK (0x3U << GRF_DMAC0_CON7_GRF_TYPE_SPI2_RX_SHIFT) /* 0x0000000C */
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#define GRF_DMAC0_CON7_GRF_TYPE_SPI3_TX_SHIFT (4U)
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#define GRF_DMAC0_CON7_GRF_TYPE_SPI3_TX_MASK (0x3U << GRF_DMAC0_CON7_GRF_TYPE_SPI3_TX_SHIFT) /* 0x00000030 */
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#define GRF_DMAC0_CON7_GRF_TYPE_SPI3_RX_SHIFT (6U)
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#define GRF_DMAC0_CON7_GRF_TYPE_SPI3_RX_MASK (0x3U << GRF_DMAC0_CON7_GRF_TYPE_SPI3_RX_SHIFT) /* 0x000000C0 */
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#define GRF_DMAC0_CON7_GRF_TYPE_PWM0_TX_SHIFT (8U)
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#define GRF_DMAC0_CON7_GRF_TYPE_PWM0_TX_MASK (0x3U << GRF_DMAC0_CON7_GRF_TYPE_PWM0_TX_SHIFT) /* 0x00000300 */
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#define GRF_DMAC0_CON7_GRF_TYPE_PWM1_TX_SHIFT (10U)
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#define GRF_DMAC0_CON7_GRF_TYPE_PWM1_TX_MASK (0x3U << GRF_DMAC0_CON7_GRF_TYPE_PWM1_TX_SHIFT) /* 0x00000C00 */
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#define GRF_DMAC0_CON7_GRF_TYPE_PWM2_TX_SHIFT (12U)
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#define GRF_DMAC0_CON7_GRF_TYPE_PWM2_TX_MASK (0x3U << GRF_DMAC0_CON7_GRF_TYPE_PWM2_TX_SHIFT) /* 0x00003000 */
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#define GRF_DMAC0_CON7_GRF_TYPE_PWM3_TX_SHIFT (14U)
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#define GRF_DMAC0_CON7_GRF_TYPE_PWM3_TX_MASK (0x3U << GRF_DMAC0_CON7_GRF_TYPE_PWM3_TX_SHIFT) /* 0x0000C000 */
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/* DMAC0_CON8 */
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#define GRF_DMAC0_CON8_OFFSET (0x40920U)
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#define GRF_DMAC0_CON8_GRF_DMA0_REQ_MODIFY_DIS_SHIFT (0U)
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#define GRF_DMAC0_CON8_GRF_DMA0_REQ_MODIFY_DIS_MASK (0xFFFFU << GRF_DMAC0_CON8_GRF_DMA0_REQ_MODIFY_DIS_SHIFT) /* 0x0000FFFF */
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/* DMAC0_CON9 */
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#define GRF_DMAC0_CON9_OFFSET (0x40924U)
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#define GRF_DMAC0_CON9_GRF_DMA0_REQ_MODIFY_DIS_SHIFT (0U)
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#define GRF_DMAC0_CON9_GRF_DMA0_REQ_MODIFY_DIS_MASK (0xFFFFU << GRF_DMAC0_CON9_GRF_DMA0_REQ_MODIFY_DIS_SHIFT) /* 0x0000FFFF */
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/* DMAC1_CON0 */
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#define GRF_DMAC1_CON0_OFFSET (0x40940U)
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#define GRF_DMAC1_CON0_DMA1_IRQ_BOOT_NONSEC_SHIFT (0U)
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#define GRF_DMAC1_CON0_DMA1_IRQ_BOOT_NONSEC_MASK (0xFFFFU << GRF_DMAC1_CON0_DMA1_IRQ_BOOT_NONSEC_SHIFT) /* 0x0000FFFF */
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/* DMAC1_CON1 */
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#define GRF_DMAC1_CON1_OFFSET (0x40944U)
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#define GRF_DMAC1_CON1_DMA1_PERI_CH_NONSEC_15_0_SHIFT (0U)
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#define GRF_DMAC1_CON1_DMA1_PERI_CH_NONSEC_15_0_MASK (0xFFFFU << GRF_DMAC1_CON1_DMA1_PERI_CH_NONSEC_15_0_SHIFT) /* 0x0000FFFF */
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/* DMAC1_CON2 */
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#define GRF_DMAC1_CON2_OFFSET (0x40948U)
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#define GRF_DMAC1_CON2_DMA1_PERI_CH_NONSEC_31_16_SHIFT (0U)
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#define GRF_DMAC1_CON2_DMA1_PERI_CH_NONSEC_31_16_MASK (0xFFFFU << GRF_DMAC1_CON2_DMA1_PERI_CH_NONSEC_31_16_SHIFT) /* 0x0000FFFF */
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/* DMAC1_CON3 */
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#define GRF_DMAC1_CON3_OFFSET (0x4094CU)
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#define GRF_DMAC1_CON3_DMA1_MANAGER_BOOT_NONSEC_SHIFT (0U)
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#define GRF_DMAC1_CON3_DMA1_MANAGER_BOOT_NONSEC_MASK (0x1U << GRF_DMAC1_CON3_DMA1_MANAGER_BOOT_NONSEC_SHIFT) /* 0x00000001 */
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/* DMAC1_CON4 */
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#define GRF_DMAC1_CON4_OFFSET (0x40950U)
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#define GRF_DMAC1_CON4_GRF_TYPE_I2S0_RX_SHIFT (0U)
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#define GRF_DMAC1_CON4_GRF_TYPE_I2S0_RX_MASK (0x3U << GRF_DMAC1_CON4_GRF_TYPE_I2S0_RX_SHIFT) /* 0x00000003 */
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#define GRF_DMAC1_CON4_GRF_TYPE_SPDIF_SHIFT (2U)
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#define GRF_DMAC1_CON4_GRF_TYPE_SPDIF_MASK (0x3U << GRF_DMAC1_CON4_GRF_TYPE_SPDIF_SHIFT) /* 0x0000000C */
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#define GRF_DMAC1_CON4_GRF_TYPE_I2S1_TX_SHIFT (4U)
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#define GRF_DMAC1_CON4_GRF_TYPE_I2S1_TX_MASK (0x3U << GRF_DMAC1_CON4_GRF_TYPE_I2S1_TX_SHIFT) /* 0x00000030 */
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#define GRF_DMAC1_CON4_GRF_TYPE_I2S1_RX_SHIFT (6U)
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#define GRF_DMAC1_CON4_GRF_TYPE_I2S1_RX_MASK (0x3U << GRF_DMAC1_CON4_GRF_TYPE_I2S1_RX_SHIFT) /* 0x000000C0 */
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#define GRF_DMAC1_CON4_GRF_TYPE_I2S2_TX_SHIFT (8U)
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#define GRF_DMAC1_CON4_GRF_TYPE_I2S2_TX_MASK (0x3U << GRF_DMAC1_CON4_GRF_TYPE_I2S2_TX_SHIFT) /* 0x00000300 */
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#define GRF_DMAC1_CON4_GRF_TYPE_I2S2_RX_SHIFT (10U)
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#define GRF_DMAC1_CON4_GRF_TYPE_I2S2_RX_MASK (0x3U << GRF_DMAC1_CON4_GRF_TYPE_I2S2_RX_SHIFT) /* 0x00000C00 */
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#define GRF_DMAC1_CON4_GRF_TYPE_I2S3_TX_SHIFT (12U)
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#define GRF_DMAC1_CON4_GRF_TYPE_I2S3_TX_MASK (0x3U << GRF_DMAC1_CON4_GRF_TYPE_I2S3_TX_SHIFT) /* 0x00003000 */
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#define GRF_DMAC1_CON4_GRF_TYPE_I2S3_RX_SHIFT (14U)
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#define GRF_DMAC1_CON4_GRF_TYPE_I2S3_RX_MASK (0x3U << GRF_DMAC1_CON4_GRF_TYPE_I2S3_RX_SHIFT) /* 0x0000C000 */
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/* DMAC1_CON5 */
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#define GRF_DMAC1_CON5_OFFSET (0x40954U)
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#define GRF_DMAC1_CON5_GRF_TYPE_CAN1_RX_SHIFT (0U)
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#define GRF_DMAC1_CON5_GRF_TYPE_CAN1_RX_MASK (0x3U << GRF_DMAC1_CON5_GRF_TYPE_CAN1_RX_SHIFT) /* 0x00000003 */
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/* DMAC1_CON6 */
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#define GRF_DMAC1_CON6_OFFSET (0x40958U)
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#define GRF_DMAC1_CON6_GRF_TYPE_AUDPWM_SHIFT (0U)
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#define GRF_DMAC1_CON6_GRF_TYPE_AUDPWM_MASK (0x3U << GRF_DMAC1_CON6_GRF_TYPE_AUDPWM_SHIFT) /* 0x00000003 */
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#define GRF_DMAC1_CON6_GRF_TYPE_PDM_SHIFT (2U)
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#define GRF_DMAC1_CON6_GRF_TYPE_PDM_MASK (0x3U << GRF_DMAC1_CON6_GRF_TYPE_PDM_SHIFT) /* 0x0000000C */
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#define GRF_DMAC1_CON6_GRF_TYPE_SDMMC_BUFFER_SHIFT (4U)
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#define GRF_DMAC1_CON6_GRF_TYPE_SDMMC_BUFFER_MASK (0x3U << GRF_DMAC1_CON6_GRF_TYPE_SDMMC_BUFFER_SHIFT) /* 0x00000030 */
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#define GRF_DMAC1_CON6_GRF_TYPE_CAN0_TX_SHIFT (6U)
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#define GRF_DMAC1_CON6_GRF_TYPE_CAN0_TX_MASK (0x3U << GRF_DMAC1_CON6_GRF_TYPE_CAN0_TX_SHIFT) /* 0x000000C0 */
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#define GRF_DMAC1_CON6_GRF_TYPE_CAN0_RX_SHIFT (8U)
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#define GRF_DMAC1_CON6_GRF_TYPE_CAN0_RX_MASK (0x3U << GRF_DMAC1_CON6_GRF_TYPE_CAN0_RX_SHIFT) /* 0x00000300 */
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#define GRF_DMAC1_CON6_GRF_TYPE_CAN1_TX_SHIFT (10U)
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#define GRF_DMAC1_CON6_GRF_TYPE_CAN1_TX_MASK (0x3U << GRF_DMAC1_CON6_GRF_TYPE_CAN1_TX_SHIFT) /* 0x00000C00 */
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#define GRF_DMAC1_CON6_GRF_TYPE_CAN1_RX_SHIFT (12U)
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#define GRF_DMAC1_CON6_GRF_TYPE_CAN1_RX_MASK (0x3U << GRF_DMAC1_CON6_GRF_TYPE_CAN1_RX_SHIFT) /* 0x00003000 */
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#define GRF_DMAC1_CON6_GRF_TYPE_CAN2_TX_SHIFT (14U)
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#define GRF_DMAC1_CON6_GRF_TYPE_CAN2_TX_MASK (0x3U << GRF_DMAC1_CON6_GRF_TYPE_CAN2_TX_SHIFT) /* 0x0000C000 */
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/* DMAC1_CON7 */
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#define GRF_DMAC1_CON7_OFFSET (0x4095CU)
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#define GRF_DMAC1_CON7_GRF_TYPE_CAN2_RX_SHIFT (0U)
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#define GRF_DMAC1_CON7_GRF_TYPE_CAN2_RX_MASK (0x3U << GRF_DMAC1_CON7_GRF_TYPE_CAN2_RX_SHIFT) /* 0x00000003 */
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/* DMAC1_CON8 */
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#define GRF_DMAC1_CON8_OFFSET (0x40960U)
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#define GRF_DMAC1_CON8_GRF_DMA1_REQ_MODIFY_DIS_SHIFT (0U)
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#define GRF_DMAC1_CON8_GRF_DMA1_REQ_MODIFY_DIS_MASK (0xFFFFU << GRF_DMAC1_CON8_GRF_DMA1_REQ_MODIFY_DIS_SHIFT) /* 0x0000FFFF */
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/* DMAC1_CON9 */
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#define GRF_DMAC1_CON9_OFFSET (0x40964U)
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#define GRF_DMAC1_CON9_GRF_DMA1_REQ_MODIFY_DIS_SHIFT (0U)
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#define GRF_DMAC1_CON9_GRF_DMA1_REQ_MODIFY_DIS_MASK (0xFFFFU << GRF_DMAC1_CON9_GRF_DMA1_REQ_MODIFY_DIS_SHIFT) /* 0x0000FFFF */
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/*****************************************PMUCRU*****************************************/
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/* PPLL_CON0 */
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#define PMUCRU_PPLL_CON0_OFFSET (0x0U)
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#define PMUCRU_PPLL_CON0_FBDIV_SHIFT (0U)
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#define PMUCRU_PPLL_CON0_FBDIV_MASK (0xFFFU << PMUCRU_PPLL_CON0_FBDIV_SHIFT) /* 0x00000FFF */
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#define PMUCRU_PPLL_CON0_POSTDIV1_SHIFT (12U)
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#define PMUCRU_PPLL_CON0_POSTDIV1_MASK (0x7U << PMUCRU_PPLL_CON0_POSTDIV1_SHIFT) /* 0x00007000 */
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#define PMUCRU_PPLL_CON0_BYPASS_SHIFT (15U)
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#define PMUCRU_PPLL_CON0_BYPASS_MASK (0x1U << PMUCRU_PPLL_CON0_BYPASS_SHIFT) /* 0x00008000 */
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/* PPLL_CON1 */
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#define PMUCRU_PPLL_CON1_OFFSET (0x4U)
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#define PMUCRU_PPLL_CON1_REFDIV_SHIFT (0U)
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#define PMUCRU_PPLL_CON1_REFDIV_MASK (0x3FU << PMUCRU_PPLL_CON1_REFDIV_SHIFT) /* 0x0000003F */
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#define PMUCRU_PPLL_CON1_POSTDIV2_SHIFT (6U)
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#define PMUCRU_PPLL_CON1_POSTDIV2_MASK (0x7U << PMUCRU_PPLL_CON1_POSTDIV2_SHIFT) /* 0x000001C0 */
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#define PMUCRU_PPLL_CON1_PLL_LOCK_SHIFT (10U)
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#define PMUCRU_PPLL_CON1_PLL_LOCK_MASK (0x1U << PMUCRU_PPLL_CON1_PLL_LOCK_SHIFT) /* 0x00000400 */
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#define PMUCRU_PPLL_CON1_DSMPD_SHIFT (12U)
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#define PMUCRU_PPLL_CON1_DSMPD_MASK (0x1U << PMUCRU_PPLL_CON1_DSMPD_SHIFT) /* 0x00001000 */
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#define PMUCRU_PPLL_CON1_PLLPD0_SHIFT (13U)
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#define PMUCRU_PPLL_CON1_PLLPD0_MASK (0x1U << PMUCRU_PPLL_CON1_PLLPD0_SHIFT) /* 0x00002000 */
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#define PMUCRU_PPLL_CON1_PLLPD1_SHIFT (14U)
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#define PMUCRU_PPLL_CON1_PLLPD1_MASK (0x1U << PMUCRU_PPLL_CON1_PLLPD1_SHIFT) /* 0x00004000 */
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#define PMUCRU_PPLL_CON1_PLLPDSEL_SHIFT (15U)
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#define PMUCRU_PPLL_CON1_PLLPDSEL_MASK (0x1U << PMUCRU_PPLL_CON1_PLLPDSEL_SHIFT) /* 0x00008000 */
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/* PPLL_CON2 */
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#define PMUCRU_PPLL_CON2_OFFSET (0x8U)
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#define PMUCRU_PPLL_CON2_FRACDIV_SHIFT (0U)
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#define PMUCRU_PPLL_CON2_FRACDIV_MASK (0xFFFFFFU << PMUCRU_PPLL_CON2_FRACDIV_SHIFT) /* 0x00FFFFFF */
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#define PMUCRU_PPLL_CON2_DACPD_SHIFT (24U)
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#define PMUCRU_PPLL_CON2_DACPD_MASK (0x1U << PMUCRU_PPLL_CON2_DACPD_SHIFT) /* 0x01000000 */
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#define PMUCRU_PPLL_CON2_FOUTPOSTDIVPD_SHIFT (25U)
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#define PMUCRU_PPLL_CON2_FOUTPOSTDIVPD_MASK (0x1U << PMUCRU_PPLL_CON2_FOUTPOSTDIVPD_SHIFT) /* 0x02000000 */
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#define PMUCRU_PPLL_CON2_FOUTVCOPD_SHIFT (26U)
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#define PMUCRU_PPLL_CON2_FOUTVCOPD_MASK (0x1U << PMUCRU_PPLL_CON2_FOUTVCOPD_SHIFT) /* 0x04000000 */
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#define PMUCRU_PPLL_CON2_FOUT4PHASEPD_SHIFT (27U)
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#define PMUCRU_PPLL_CON2_FOUT4PHASEPD_MASK (0x1U << PMUCRU_PPLL_CON2_FOUT4PHASEPD_SHIFT) /* 0x08000000 */
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/* PPLL_CON3 */
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#define PMUCRU_PPLL_CON3_OFFSET (0xCU)
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#define PMUCRU_PPLL_CON3_SSMOD_BP_SHIFT (0U)
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#define PMUCRU_PPLL_CON3_SSMOD_BP_MASK (0x1U << PMUCRU_PPLL_CON3_SSMOD_BP_SHIFT) /* 0x00000001 */
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#define PMUCRU_PPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT (1U)
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#define PMUCRU_PPLL_CON3_SSMOD_DISABLE_SSCG_MASK (0x1U << PMUCRU_PPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT) /* 0x00000002 */
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#define PMUCRU_PPLL_CON3_SSMOD_RESET_SHIFT (2U)
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#define PMUCRU_PPLL_CON3_SSMOD_RESET_MASK (0x1U << PMUCRU_PPLL_CON3_SSMOD_RESET_SHIFT) /* 0x00000004 */
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#define PMUCRU_PPLL_CON3_SSMOD_DOWNSPREAD_SHIFT (3U)
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#define PMUCRU_PPLL_CON3_SSMOD_DOWNSPREAD_MASK (0x1U << PMUCRU_PPLL_CON3_SSMOD_DOWNSPREAD_SHIFT) /* 0x00000008 */
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#define PMUCRU_PPLL_CON3_SSMOD_DIVVAL_SHIFT (4U)
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#define PMUCRU_PPLL_CON3_SSMOD_DIVVAL_MASK (0xFU << PMUCRU_PPLL_CON3_SSMOD_DIVVAL_SHIFT) /* 0x000000F0 */
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#define PMUCRU_PPLL_CON3_SSMOD_SPREAD_SHIFT (8U)
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#define PMUCRU_PPLL_CON3_SSMOD_SPREAD_MASK (0x1FU << PMUCRU_PPLL_CON3_SSMOD_SPREAD_SHIFT) /* 0x00001F00 */
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/* PPLL_CON4 */
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#define PMUCRU_PPLL_CON4_OFFSET (0x10U)
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#define PMUCRU_PPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT (0U)
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#define PMUCRU_PPLL_CON4_SSMOD_SEL_EXT_WAVE_MASK (0x1U << PMUCRU_PPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT) /* 0x00000001 */
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#define PMUCRU_PPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT (8U)
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#define PMUCRU_PPLL_CON4_SSMOD_EXT_MAXADDR_MASK (0xFFU << PMUCRU_PPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT) /* 0x0000FF00 */
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/* HPLL_CON0 */
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#define PMUCRU_HPLL_CON0_OFFSET (0x40U)
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#define PMUCRU_HPLL_CON0_FBDIV_SHIFT (0U)
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#define PMUCRU_HPLL_CON0_FBDIV_MASK (0xFFFU << PMUCRU_HPLL_CON0_FBDIV_SHIFT) /* 0x00000FFF */
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#define PMUCRU_HPLL_CON0_POSTDIV1_SHIFT (12U)
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#define PMUCRU_HPLL_CON0_POSTDIV1_MASK (0x7U << PMUCRU_HPLL_CON0_POSTDIV1_SHIFT) /* 0x00007000 */
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#define PMUCRU_HPLL_CON0_BYPASS_SHIFT (15U)
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#define PMUCRU_HPLL_CON0_BYPASS_MASK (0x1U << PMUCRU_HPLL_CON0_BYPASS_SHIFT) /* 0x00008000 */
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/* HPLL_CON1 */
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#define PMUCRU_HPLL_CON1_OFFSET (0x44U)
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#define PMUCRU_HPLL_CON1_REFDIV_SHIFT (0U)
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#define PMUCRU_HPLL_CON1_REFDIV_MASK (0x3FU << PMUCRU_HPLL_CON1_REFDIV_SHIFT) /* 0x0000003F */
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#define PMUCRU_HPLL_CON1_POSTDIV2_SHIFT (6U)
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#define PMUCRU_HPLL_CON1_POSTDIV2_MASK (0x7U << PMUCRU_HPLL_CON1_POSTDIV2_SHIFT) /* 0x000001C0 */
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#define PMUCRU_HPLL_CON1_PLL_LOCK_SHIFT (10U)
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#define PMUCRU_HPLL_CON1_PLL_LOCK_MASK (0x1U << PMUCRU_HPLL_CON1_PLL_LOCK_SHIFT) /* 0x00000400 */
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#define PMUCRU_HPLL_CON1_DSMPD_SHIFT (12U)
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#define PMUCRU_HPLL_CON1_DSMPD_MASK (0x1U << PMUCRU_HPLL_CON1_DSMPD_SHIFT) /* 0x00001000 */
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#define PMUCRU_HPLL_CON1_PLLPD0_SHIFT (13U)
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#define PMUCRU_HPLL_CON1_PLLPD0_MASK (0x1U << PMUCRU_HPLL_CON1_PLLPD0_SHIFT) /* 0x00002000 */
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#define PMUCRU_HPLL_CON1_PLLPD1_SHIFT (14U)
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#define PMUCRU_HPLL_CON1_PLLPD1_MASK (0x1U << PMUCRU_HPLL_CON1_PLLPD1_SHIFT) /* 0x00004000 */
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#define PMUCRU_HPLL_CON1_PLLPDSEL_SHIFT (15U)
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#define PMUCRU_HPLL_CON1_PLLPDSEL_MASK (0x1U << PMUCRU_HPLL_CON1_PLLPDSEL_SHIFT) /* 0x00008000 */
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/* HPLL_CON2 */
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#define PMUCRU_HPLL_CON2_OFFSET (0x48U)
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#define PMUCRU_HPLL_CON2_FRACDIV_SHIFT (0U)
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#define PMUCRU_HPLL_CON2_FRACDIV_MASK (0xFFFFFFU << PMUCRU_HPLL_CON2_FRACDIV_SHIFT) /* 0x00FFFFFF */
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#define PMUCRU_HPLL_CON2_DACPD_SHIFT (24U)
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#define PMUCRU_HPLL_CON2_DACPD_MASK (0x1U << PMUCRU_HPLL_CON2_DACPD_SHIFT) /* 0x01000000 */
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#define PMUCRU_HPLL_CON2_FOUTPOSTDIVPD_SHIFT (25U)
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#define PMUCRU_HPLL_CON2_FOUTPOSTDIVPD_MASK (0x1U << PMUCRU_HPLL_CON2_FOUTPOSTDIVPD_SHIFT) /* 0x02000000 */
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#define PMUCRU_HPLL_CON2_FOUTVCOPD_SHIFT (26U)
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#define PMUCRU_HPLL_CON2_FOUTVCOPD_MASK (0x1U << PMUCRU_HPLL_CON2_FOUTVCOPD_SHIFT) /* 0x04000000 */
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#define PMUCRU_HPLL_CON2_FOUT4PHASEPD_SHIFT (27U)
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#define PMUCRU_HPLL_CON2_FOUT4PHASEPD_MASK (0x1U << PMUCRU_HPLL_CON2_FOUT4PHASEPD_SHIFT) /* 0x08000000 */
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/* HPLL_CON3 */
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#define PMUCRU_HPLL_CON3_OFFSET (0x4CU)
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#define PMUCRU_HPLL_CON3_SSMOD_BP_SHIFT (0U)
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#define PMUCRU_HPLL_CON3_SSMOD_BP_MASK (0x1U << PMUCRU_HPLL_CON3_SSMOD_BP_SHIFT) /* 0x00000001 */
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#define PMUCRU_HPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT (1U)
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#define PMUCRU_HPLL_CON3_SSMOD_DISABLE_SSCG_MASK (0x1U << PMUCRU_HPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT) /* 0x00000002 */
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#define PMUCRU_HPLL_CON3_SSMOD_RESET_SHIFT (2U)
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#define PMUCRU_HPLL_CON3_SSMOD_RESET_MASK (0x1U << PMUCRU_HPLL_CON3_SSMOD_RESET_SHIFT) /* 0x00000004 */
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#define PMUCRU_HPLL_CON3_SSMOD_DOWNSPREAD_SHIFT (3U)
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#define PMUCRU_HPLL_CON3_SSMOD_DOWNSPREAD_MASK (0x1U << PMUCRU_HPLL_CON3_SSMOD_DOWNSPREAD_SHIFT) /* 0x00000008 */
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#define PMUCRU_HPLL_CON3_SSMOD_DIVVAL_SHIFT (4U)
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#define PMUCRU_HPLL_CON3_SSMOD_DIVVAL_MASK (0xFU << PMUCRU_HPLL_CON3_SSMOD_DIVVAL_SHIFT) /* 0x000000F0 */
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#define PMUCRU_HPLL_CON3_SSMOD_SPREAD_SHIFT (8U)
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#define PMUCRU_HPLL_CON3_SSMOD_SPREAD_MASK (0x1FU << PMUCRU_HPLL_CON3_SSMOD_SPREAD_SHIFT) /* 0x00001F00 */
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/* HPLL_CON4 */
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#define PMUCRU_HPLL_CON4_OFFSET (0x50U)
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#define PMUCRU_HPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT (0U)
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#define PMUCRU_HPLL_CON4_SSMOD_SEL_EXT_WAVE_MASK (0x1U << PMUCRU_HPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT) /* 0x00000001 */
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#define PMUCRU_HPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT (8U)
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#define PMUCRU_HPLL_CON4_SSMOD_EXT_MAXADDR_MASK (0xFFU << PMUCRU_HPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT) /* 0x0000FF00 */
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/* MODE_CON00 */
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#define PMUCRU_MODE_CON00_OFFSET (0x80U)
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#define PMUCRU_MODE_CON00_CLK_PPLL_MODE_SHIFT (0U)
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#define PMUCRU_MODE_CON00_CLK_PPLL_MODE_MASK (0x3U << PMUCRU_MODE_CON00_CLK_PPLL_MODE_SHIFT) /* 0x00000003 */
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#define PMUCRU_MODE_CON00_CLK_HPLL_MODE_SHIFT (2U)
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#define PMUCRU_MODE_CON00_CLK_HPLL_MODE_MASK (0x3U << PMUCRU_MODE_CON00_CLK_HPLL_MODE_SHIFT) /* 0x0000000C */
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/* PMUCLKSEL_CON00 */
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#define PMUCRU_PMUCLKSEL_CON00_OFFSET (0x100U)
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#define PMUCRU_PMUCLKSEL_CON00_XIN_OSC0_DIV_DIV_SHIFT (0U)
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#define PMUCRU_PMUCLKSEL_CON00_XIN_OSC0_DIV_DIV_MASK (0x1FU << PMUCRU_PMUCLKSEL_CON00_XIN_OSC0_DIV_DIV_SHIFT) /* 0x0000001F */
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#define PMUCRU_PMUCLKSEL_CON00_CLK_RTC_32K_SEL_SHIFT (6U)
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#define PMUCRU_PMUCLKSEL_CON00_CLK_RTC_32K_SEL_MASK (0x3U << PMUCRU_PMUCLKSEL_CON00_CLK_RTC_32K_SEL_SHIFT) /* 0x000000C0 */
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/* PMUCLKSEL_CON01 */
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#define PMUCRU_PMUCLKSEL_CON01_OFFSET (0x104U)
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#define PMUCRU_PMUCLKSEL_CON01_CLK_OSC0_DIV32K_DIV_SHIFT (0U)
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#define PMUCRU_PMUCLKSEL_CON01_CLK_OSC0_DIV32K_DIV_MASK (0xFFFFFFFFU << PMUCRU_PMUCLKSEL_CON01_CLK_OSC0_DIV32K_DIV_SHIFT) /* 0xFFFFFFFF */
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/* PMUCLKSEL_CON02 */
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#define PMUCRU_PMUCLKSEL_CON02_OFFSET (0x108U)
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#define PMUCRU_PMUCLKSEL_CON02_PCLK_PDPMU_PRE_DIV_SHIFT (0U)
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#define PMUCRU_PMUCLKSEL_CON02_PCLK_PDPMU_PRE_DIV_MASK (0x1FU << PMUCRU_PMUCLKSEL_CON02_PCLK_PDPMU_PRE_DIV_SHIFT) /* 0x0000001F */
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#define PMUCRU_PMUCLKSEL_CON02_CLK_PDPMU_MUX_SEL_SHIFT (15U)
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#define PMUCRU_PMUCLKSEL_CON02_CLK_PDPMU_MUX_SEL_MASK (0x1U << PMUCRU_PMUCLKSEL_CON02_CLK_PDPMU_MUX_SEL_SHIFT) /* 0x00008000 */
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/* PMUCLKSEL_CON03 */
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#define PMUCRU_PMUCLKSEL_CON03_OFFSET (0x10CU)
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#define PMUCRU_PMUCLKSEL_CON03_CLK_I2C0_DIV_SHIFT (0U)
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#define PMUCRU_PMUCLKSEL_CON03_CLK_I2C0_DIV_MASK (0x7FU << PMUCRU_PMUCLKSEL_CON03_CLK_I2C0_DIV_SHIFT) /* 0x0000007F */
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/* PMUCLKSEL_CON04 */
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#define PMUCRU_PMUCLKSEL_CON04_OFFSET (0x110U)
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#define PMUCRU_PMUCLKSEL_CON04_SCLK_UART0_DIV_DIV_SHIFT (0U)
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#define PMUCRU_PMUCLKSEL_CON04_SCLK_UART0_DIV_DIV_MASK (0x7FU << PMUCRU_PMUCLKSEL_CON04_SCLK_UART0_DIV_DIV_SHIFT) /* 0x0000007F */
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#define PMUCRU_PMUCLKSEL_CON04_SCLK_UART0_DIV_SEL_SHIFT (8U)
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#define PMUCRU_PMUCLKSEL_CON04_SCLK_UART0_DIV_SEL_MASK (0x3U << PMUCRU_PMUCLKSEL_CON04_SCLK_UART0_DIV_SEL_SHIFT) /* 0x00000300 */
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#define PMUCRU_PMUCLKSEL_CON04_SCLK_UART0_SEL_SHIFT (10U)
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#define PMUCRU_PMUCLKSEL_CON04_SCLK_UART0_SEL_MASK (0x3U << PMUCRU_PMUCLKSEL_CON04_SCLK_UART0_SEL_SHIFT) /* 0x00000C00 */
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/* PMUCLKSEL_CON05 */
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#define PMUCRU_PMUCLKSEL_CON05_OFFSET (0x114U)
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#define PMUCRU_PMUCLKSEL_CON05_SCLK_UART0_FRACDIV_DIV_SHIFT (0U)
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#define PMUCRU_PMUCLKSEL_CON05_SCLK_UART0_FRACDIV_DIV_MASK (0xFFFFFFFFU << PMUCRU_PMUCLKSEL_CON05_SCLK_UART0_FRACDIV_DIV_SHIFT) /* 0xFFFFFFFF */
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/* PMUCLKSEL_CON06 */
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#define PMUCRU_PMUCLKSEL_CON06_OFFSET (0x118U)
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#define PMUCRU_PMUCLKSEL_CON06_CLK_PWM0_DIV_SHIFT (0U)
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#define PMUCRU_PMUCLKSEL_CON06_CLK_PWM0_DIV_MASK (0x7FU << PMUCRU_PMUCLKSEL_CON06_CLK_PWM0_DIV_SHIFT) /* 0x0000007F */
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#define PMUCRU_PMUCLKSEL_CON06_CLK_PWM0_SEL_SHIFT (7U)
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#define PMUCRU_PMUCLKSEL_CON06_CLK_PWM0_SEL_MASK (0x1U << PMUCRU_PMUCLKSEL_CON06_CLK_PWM0_SEL_SHIFT) /* 0x00000080 */
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#define PMUCRU_PMUCLKSEL_CON06_DBCLK_GPIO0_SEL_SHIFT (15U)
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#define PMUCRU_PMUCLKSEL_CON06_DBCLK_GPIO0_SEL_MASK (0x1U << PMUCRU_PMUCLKSEL_CON06_DBCLK_GPIO0_SEL_SHIFT) /* 0x00008000 */
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/* PMUCLKSEL_CON07 */
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#define PMUCRU_PMUCLKSEL_CON07_OFFSET (0x11CU)
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#define PMUCRU_PMUCLKSEL_CON07_CLK_REF24M_DIV_SHIFT (0U)
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#define PMUCRU_PMUCLKSEL_CON07_CLK_REF24M_DIV_MASK (0x3FU << PMUCRU_PMUCLKSEL_CON07_CLK_REF24M_DIV_SHIFT) /* 0x0000003F */
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/* PMUCLKSEL_CON08 */
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#define PMUCRU_PMUCLKSEL_CON08_OFFSET (0x120U)
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#define PMUCRU_PMUCLKSEL_CON08_CLK_USBPHY0_REF_SEL_SHIFT (0U)
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#define PMUCRU_PMUCLKSEL_CON08_CLK_USBPHY0_REF_SEL_MASK (0x1U << PMUCRU_PMUCLKSEL_CON08_CLK_USBPHY0_REF_SEL_SHIFT) /* 0x00000001 */
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#define PMUCRU_PMUCLKSEL_CON08_CLK_USBPHY1_REF_SEL_SHIFT (1U)
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#define PMUCRU_PMUCLKSEL_CON08_CLK_USBPHY1_REF_SEL_MASK (0x1U << PMUCRU_PMUCLKSEL_CON08_CLK_USBPHY1_REF_SEL_SHIFT) /* 0x00000002 */
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#define PMUCRU_PMUCLKSEL_CON08_CLK_MIPIDSIPHY0_REF_SEL_SHIFT (2U)
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#define PMUCRU_PMUCLKSEL_CON08_CLK_MIPIDSIPHY0_REF_SEL_MASK (0x1U << PMUCRU_PMUCLKSEL_CON08_CLK_MIPIDSIPHY0_REF_SEL_SHIFT) /* 0x00000004 */
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#define PMUCRU_PMUCLKSEL_CON08_CLK_MIPIDSIPHY1_REF_SEL_SHIFT (3U)
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#define PMUCRU_PMUCLKSEL_CON08_CLK_MIPIDSIPHY1_REF_SEL_MASK (0x1U << PMUCRU_PMUCLKSEL_CON08_CLK_MIPIDSIPHY1_REF_SEL_SHIFT) /* 0x00000008 */
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#define PMUCRU_PMUCLKSEL_CON08_CLK_HDMIPHY_REF_SEL_SHIFT (7U)
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#define PMUCRU_PMUCLKSEL_CON08_CLK_HDMIPHY_REF_SEL_MASK (0x1U << PMUCRU_PMUCLKSEL_CON08_CLK_HDMIPHY_REF_SEL_SHIFT) /* 0x00000080 */
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#define PMUCRU_PMUCLKSEL_CON08_CLK_WIFI_DIV_DIV_SHIFT (8U)
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#define PMUCRU_PMUCLKSEL_CON08_CLK_WIFI_DIV_DIV_MASK (0x3FU << PMUCRU_PMUCLKSEL_CON08_CLK_WIFI_DIV_DIV_SHIFT) /* 0x00003F00 */
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#define PMUCRU_PMUCLKSEL_CON08_CLK_WIFI_SEL_SHIFT (15U)
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#define PMUCRU_PMUCLKSEL_CON08_CLK_WIFI_SEL_MASK (0x1U << PMUCRU_PMUCLKSEL_CON08_CLK_WIFI_SEL_SHIFT) /* 0x00008000 */
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/* PMUCLKSEL_CON09 */
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#define PMUCRU_PMUCLKSEL_CON09_OFFSET (0x124U)
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#define PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY0_DIV_DIV_SHIFT (0U)
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#define PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY0_DIV_DIV_MASK (0x7U << PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY0_DIV_DIV_SHIFT) /* 0x00000007 */
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#define PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY0_REF_SEL_SHIFT (3U)
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#define PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY0_REF_SEL_MASK (0x1U << PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY0_REF_SEL_SHIFT) /* 0x00000008 */
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#define PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY1_DIV_DIV_SHIFT (4U)
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#define PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY1_DIV_DIV_MASK (0x7U << PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY1_DIV_DIV_SHIFT) /* 0x00000070 */
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#define PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY1_REF_SEL_SHIFT (7U)
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#define PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY1_REF_SEL_MASK (0x1U << PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY1_REF_SEL_SHIFT) /* 0x00000080 */
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#define PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY2_DIV_DIV_SHIFT (8U)
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#define PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY2_DIV_DIV_MASK (0x7U << PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY2_DIV_DIV_SHIFT) /* 0x00000700 */
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#define PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY2_REF_SEL_SHIFT (11U)
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#define PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY2_REF_SEL_MASK (0x1U << PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY2_REF_SEL_SHIFT) /* 0x00000800 */
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/* PMUGATE_CON00 */
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#define PMUCRU_PMUGATE_CON00_OFFSET (0x180U)
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#define PMUCRU_PMUGATE_CON00_XIN_OSC0_DIV_EN_SHIFT (0U)
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#define PMUCRU_PMUGATE_CON00_XIN_OSC0_DIV_EN_MASK (0x1U << PMUCRU_PMUGATE_CON00_XIN_OSC0_DIV_EN_SHIFT) /* 0x00000001 */
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#define PMUCRU_PMUGATE_CON00_CLK_OSC0_DIV32K_EN_SHIFT (1U)
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#define PMUCRU_PMUGATE_CON00_CLK_OSC0_DIV32K_EN_MASK (0x1U << PMUCRU_PMUGATE_CON00_CLK_OSC0_DIV32K_EN_SHIFT) /* 0x00000002 */
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#define PMUCRU_PMUGATE_CON00_PCLK_PDPMU_EN_SHIFT (2U)
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#define PMUCRU_PMUGATE_CON00_PCLK_PDPMU_EN_MASK (0x1U << PMUCRU_PMUGATE_CON00_PCLK_PDPMU_EN_SHIFT) /* 0x00000004 */
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#define PMUCRU_PMUGATE_CON00_PCLK_PDPMU_NIU_EN_SHIFT (3U)
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#define PMUCRU_PMUGATE_CON00_PCLK_PDPMU_NIU_EN_MASK (0x1U << PMUCRU_PMUGATE_CON00_PCLK_PDPMU_NIU_EN_SHIFT) /* 0x00000008 */
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#define PMUCRU_PMUGATE_CON00_PCLK_PMUCRU_EN_SHIFT (4U)
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#define PMUCRU_PMUGATE_CON00_PCLK_PMUCRU_EN_MASK (0x1U << PMUCRU_PMUGATE_CON00_PCLK_PMUCRU_EN_SHIFT) /* 0x00000010 */
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#define PMUCRU_PMUGATE_CON00_PCLK_PMUGRF_EN_SHIFT (5U)
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#define PMUCRU_PMUGATE_CON00_PCLK_PMUGRF_EN_MASK (0x1U << PMUCRU_PMUGATE_CON00_PCLK_PMUGRF_EN_SHIFT) /* 0x00000020 */
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#define PMUCRU_PMUGATE_CON00_PCLK_PMU_EN_SHIFT (6U)
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#define PMUCRU_PMUGATE_CON00_PCLK_PMU_EN_MASK (0x1U << PMUCRU_PMUGATE_CON00_PCLK_PMU_EN_SHIFT) /* 0x00000040 */
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#define PMUCRU_PMUGATE_CON00_CLK_PMU_EN_SHIFT (7U)
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#define PMUCRU_PMUGATE_CON00_CLK_PMU_EN_MASK (0x1U << PMUCRU_PMUGATE_CON00_CLK_PMU_EN_SHIFT) /* 0x00000080 */
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/* PMUGATE_CON01 */
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#define PMUCRU_PMUGATE_CON01_OFFSET (0x184U)
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#define PMUCRU_PMUGATE_CON01_PCLK_I2C0_EN_SHIFT (0U)
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#define PMUCRU_PMUGATE_CON01_PCLK_I2C0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_PCLK_I2C0_EN_SHIFT) /* 0x00000001 */
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#define PMUCRU_PMUGATE_CON01_CLK_I2C0_EN_SHIFT (1U)
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#define PMUCRU_PMUGATE_CON01_CLK_I2C0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_CLK_I2C0_EN_SHIFT) /* 0x00000002 */
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#define PMUCRU_PMUGATE_CON01_PCLK_UART0_EN_SHIFT (2U)
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#define PMUCRU_PMUGATE_CON01_PCLK_UART0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_PCLK_UART0_EN_SHIFT) /* 0x00000004 */
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#define PMUCRU_PMUGATE_CON01_SCLK_UART0_DIV_EN_SHIFT (3U)
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#define PMUCRU_PMUGATE_CON01_SCLK_UART0_DIV_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_SCLK_UART0_DIV_EN_SHIFT) /* 0x00000008 */
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#define PMUCRU_PMUGATE_CON01_SCLK_UART0_FRACDIV_EN_SHIFT (4U)
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#define PMUCRU_PMUGATE_CON01_SCLK_UART0_FRACDIV_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_SCLK_UART0_FRACDIV_EN_SHIFT) /* 0x00000010 */
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#define PMUCRU_PMUGATE_CON01_SCLK_UART0_EN_SHIFT (5U)
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#define PMUCRU_PMUGATE_CON01_SCLK_UART0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_SCLK_UART0_EN_SHIFT) /* 0x00000020 */
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#define PMUCRU_PMUGATE_CON01_PCLK_PWM0_EN_SHIFT (6U)
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#define PMUCRU_PMUGATE_CON01_PCLK_PWM0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_PCLK_PWM0_EN_SHIFT) /* 0x00000040 */
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#define PMUCRU_PMUGATE_CON01_CLK_PWM0_EN_SHIFT (7U)
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#define PMUCRU_PMUGATE_CON01_CLK_PWM0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_CLK_PWM0_EN_SHIFT) /* 0x00000080 */
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#define PMUCRU_PMUGATE_CON01_CLK_CAPTURE_PWM0_EN_SHIFT (8U)
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#define PMUCRU_PMUGATE_CON01_CLK_CAPTURE_PWM0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_CLK_CAPTURE_PWM0_EN_SHIFT) /* 0x00000100 */
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#define PMUCRU_PMUGATE_CON01_PCLK_GPIO0_EN_SHIFT (9U)
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#define PMUCRU_PMUGATE_CON01_PCLK_GPIO0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_PCLK_GPIO0_EN_SHIFT) /* 0x00000200 */
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#define PMUCRU_PMUGATE_CON01_DBCLK_GPIO0_EN_SHIFT (10U)
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#define PMUCRU_PMUGATE_CON01_DBCLK_GPIO0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_DBCLK_GPIO0_EN_SHIFT) /* 0x00000400 */
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#define PMUCRU_PMUGATE_CON01_PCLK_PMUPVTM_EN_SHIFT (11U)
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#define PMUCRU_PMUGATE_CON01_PCLK_PMUPVTM_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_PCLK_PMUPVTM_EN_SHIFT) /* 0x00000800 */
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#define PMUCRU_PMUGATE_CON01_CLK_PMUPVTM_EN_SHIFT (12U)
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#define PMUCRU_PMUGATE_CON01_CLK_PMUPVTM_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_CLK_PMUPVTM_EN_SHIFT) /* 0x00001000 */
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#define PMUCRU_PMUGATE_CON01_CLK_CORE_PMUPVTM_EN_SHIFT (13U)
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#define PMUCRU_PMUGATE_CON01_CLK_CORE_PMUPVTM_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_CLK_CORE_PMUPVTM_EN_SHIFT) /* 0x00002000 */
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/* PMUGATE_CON02 */
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#define PMUCRU_PMUGATE_CON02_OFFSET (0x188U)
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#define PMUCRU_PMUGATE_CON02_CLK_REF24M_EN_SHIFT (0U)
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#define PMUCRU_PMUGATE_CON02_CLK_REF24M_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_CLK_REF24M_EN_SHIFT) /* 0x00000001 */
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#define PMUCRU_PMUGATE_CON02_XIN_OSC0_USBPHY0_EN_SHIFT (1U)
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#define PMUCRU_PMUGATE_CON02_XIN_OSC0_USBPHY0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_XIN_OSC0_USBPHY0_EN_SHIFT) /* 0x00000002 */
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#define PMUCRU_PMUGATE_CON02_XIN_OSC0_USBPHY1_EN_SHIFT (2U)
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#define PMUCRU_PMUGATE_CON02_XIN_OSC0_USBPHY1_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_XIN_OSC0_USBPHY1_EN_SHIFT) /* 0x00000004 */
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#define PMUCRU_PMUGATE_CON02_XIN_OSC0_MIPIDSIPHY0_EN_SHIFT (3U)
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#define PMUCRU_PMUGATE_CON02_XIN_OSC0_MIPIDSIPHY0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_XIN_OSC0_MIPIDSIPHY0_EN_SHIFT) /* 0x00000008 */
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#define PMUCRU_PMUGATE_CON02_XIN_OSC0_MIPIDSIPHY1_EN_SHIFT (4U)
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#define PMUCRU_PMUGATE_CON02_XIN_OSC0_MIPIDSIPHY1_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_XIN_OSC0_MIPIDSIPHY1_EN_SHIFT) /* 0x00000010 */
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#define PMUCRU_PMUGATE_CON02_CLK_WIFI_DIV_EN_SHIFT (5U)
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#define PMUCRU_PMUGATE_CON02_CLK_WIFI_DIV_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_CLK_WIFI_DIV_EN_SHIFT) /* 0x00000020 */
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#define PMUCRU_PMUGATE_CON02_CLK_WIFI_OSC0_EN_SHIFT (6U)
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#define PMUCRU_PMUGATE_CON02_CLK_WIFI_OSC0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_CLK_WIFI_OSC0_EN_SHIFT) /* 0x00000040 */
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#define PMUCRU_PMUGATE_CON02_CLK_PCIEPHY0_DIV_EN_SHIFT (7U)
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#define PMUCRU_PMUGATE_CON02_CLK_PCIEPHY0_DIV_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_CLK_PCIEPHY0_DIV_EN_SHIFT) /* 0x00000080 */
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#define PMUCRU_PMUGATE_CON02_CLK_PCIEPHY0_OSC0_EN_SHIFT (8U)
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#define PMUCRU_PMUGATE_CON02_CLK_PCIEPHY0_OSC0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_CLK_PCIEPHY0_OSC0_EN_SHIFT) /* 0x00000100 */
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#define PMUCRU_PMUGATE_CON02_CLK_PCIEPHY1_DIV_EN_SHIFT (9U)
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#define PMUCRU_PMUGATE_CON02_CLK_PCIEPHY1_DIV_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_CLK_PCIEPHY1_DIV_EN_SHIFT) /* 0x00000200 */
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#define PMUCRU_PMUGATE_CON02_CLK_PCIEPHY1_OSC0_EN_SHIFT (10U)
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#define PMUCRU_PMUGATE_CON02_CLK_PCIEPHY1_OSC0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_CLK_PCIEPHY1_OSC0_EN_SHIFT) /* 0x00000400 */
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#define PMUCRU_PMUGATE_CON02_CLK_PCIEPHY2_DIV_EN_SHIFT (11U)
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#define PMUCRU_PMUGATE_CON02_CLK_PCIEPHY2_DIV_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_CLK_PCIEPHY2_DIV_EN_SHIFT) /* 0x00000800 */
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#define PMUCRU_PMUGATE_CON02_CLK_PCIEPHY2_OSC0_EN_SHIFT (12U)
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#define PMUCRU_PMUGATE_CON02_CLK_PCIEPHY2_OSC0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_CLK_PCIEPHY2_OSC0_EN_SHIFT) /* 0x00001000 */
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#define PMUCRU_PMUGATE_CON02_CLK_PCIE30PHY_REF_M_EN_SHIFT (13U)
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#define PMUCRU_PMUGATE_CON02_CLK_PCIE30PHY_REF_M_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_CLK_PCIE30PHY_REF_M_EN_SHIFT) /* 0x00002000 */
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#define PMUCRU_PMUGATE_CON02_CLK_PCIE30PHY_REF_N_EN_SHIFT (14U)
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#define PMUCRU_PMUGATE_CON02_CLK_PCIE30PHY_REF_N_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_CLK_PCIE30PHY_REF_N_EN_SHIFT) /* 0x00004000 */
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#define PMUCRU_PMUGATE_CON02_XIN_OSC0_EDPPHY_EN_SHIFT (15U)
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#define PMUCRU_PMUGATE_CON02_XIN_OSC0_EDPPHY_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_XIN_OSC0_EDPPHY_EN_SHIFT) /* 0x00008000 */
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/* PMUSOFTRST_CON00 */
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#define PMUCRU_PMUSOFTRST_CON00_OFFSET (0x200U)
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#define PMUCRU_PMUSOFTRST_CON00_PRESETN_PDPMU_NIU_SHIFT (0U)
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#define PMUCRU_PMUSOFTRST_CON00_PRESETN_PDPMU_NIU_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_PRESETN_PDPMU_NIU_SHIFT) /* 0x00000001 */
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#define PMUCRU_PMUSOFTRST_CON00_PRESETN_PMUCRU_SHIFT (1U)
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#define PMUCRU_PMUSOFTRST_CON00_PRESETN_PMUCRU_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_PRESETN_PMUCRU_SHIFT) /* 0x00000002 */
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#define PMUCRU_PMUSOFTRST_CON00_PRESETN_PMUGRF_SHIFT (2U)
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#define PMUCRU_PMUSOFTRST_CON00_PRESETN_PMUGRF_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_PRESETN_PMUGRF_SHIFT) /* 0x00000004 */
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#define PMUCRU_PMUSOFTRST_CON00_PRESETN_I2C0_SHIFT (3U)
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#define PMUCRU_PMUSOFTRST_CON00_PRESETN_I2C0_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_PRESETN_I2C0_SHIFT) /* 0x00000008 */
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#define PMUCRU_PMUSOFTRST_CON00_RESETN_I2C0_SHIFT (4U)
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#define PMUCRU_PMUSOFTRST_CON00_RESETN_I2C0_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_RESETN_I2C0_SHIFT) /* 0x00000010 */
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#define PMUCRU_PMUSOFTRST_CON00_PRESETN_UART0_SHIFT (5U)
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#define PMUCRU_PMUSOFTRST_CON00_PRESETN_UART0_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_PRESETN_UART0_SHIFT) /* 0x00000020 */
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#define PMUCRU_PMUSOFTRST_CON00_SRESETN_UART0_SHIFT (6U)
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#define PMUCRU_PMUSOFTRST_CON00_SRESETN_UART0_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_SRESETN_UART0_SHIFT) /* 0x00000040 */
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#define PMUCRU_PMUSOFTRST_CON00_PRESETN_PWM0_SHIFT (7U)
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#define PMUCRU_PMUSOFTRST_CON00_PRESETN_PWM0_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_PRESETN_PWM0_SHIFT) /* 0x00000080 */
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#define PMUCRU_PMUSOFTRST_CON00_RESETN_PWM0_SHIFT (8U)
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#define PMUCRU_PMUSOFTRST_CON00_RESETN_PWM0_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_RESETN_PWM0_SHIFT) /* 0x00000100 */
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#define PMUCRU_PMUSOFTRST_CON00_PRESETN_GPIO0_SHIFT (9U)
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#define PMUCRU_PMUSOFTRST_CON00_PRESETN_GPIO0_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_PRESETN_GPIO0_SHIFT) /* 0x00000200 */
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#define PMUCRU_PMUSOFTRST_CON00_DBRESETN_GPIO0_SHIFT (10U)
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#define PMUCRU_PMUSOFTRST_CON00_DBRESETN_GPIO0_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_DBRESETN_GPIO0_SHIFT) /* 0x00000400 */
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#define PMUCRU_PMUSOFTRST_CON00_PRESETN_PMUPVTM_SHIFT (11U)
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#define PMUCRU_PMUSOFTRST_CON00_PRESETN_PMUPVTM_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_PRESETN_PMUPVTM_SHIFT) /* 0x00000800 */
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#define PMUCRU_PMUSOFTRST_CON00_RESETN_PMUPVTM_SHIFT (12U)
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#define PMUCRU_PMUSOFTRST_CON00_RESETN_PMUPVTM_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_RESETN_PMUPVTM_SHIFT) /* 0x00001000 */
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/*****************************************TIMER******************************************/
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/* LOAD_COUNT0 */
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#define TIMER_LOAD_COUNT0_OFFSET (0x0U)
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#define TIMER_LOAD_COUNT0_COUNT0_SHIFT (0U)
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#define TIMER_LOAD_COUNT0_COUNT0_MASK (0xFFFFFFFFU << TIMER_LOAD_COUNT0_COUNT0_SHIFT) /* 0xFFFFFFFF */
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/* LOAD_COUNT1 */
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#define TIMER_LOAD_COUNT1_OFFSET (0x4U)
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#define TIMER_LOAD_COUNT1_COUNT1_SHIFT (0U)
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#define TIMER_LOAD_COUNT1_COUNT1_MASK (0xFFFFFFFFU << TIMER_LOAD_COUNT1_COUNT1_SHIFT) /* 0xFFFFFFFF */
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/* CURRENT_VALUE0 */
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#define TIMER_CURRENT_VALUE0_OFFSET (0x8U)
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#define TIMER_CURRENT_VALUE0 (0x0U)
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#define TIMER_CURRENT_VALUE0_CURRENT_VALUE0_SHIFT (0U)
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#define TIMER_CURRENT_VALUE0_CURRENT_VALUE0_MASK (0xFFFFFFFFU << TIMER_CURRENT_VALUE0_CURRENT_VALUE0_SHIFT) /* 0xFFFFFFFF */
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/* CURRENT_VALUE1 */
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#define TIMER_CURRENT_VALUE1_OFFSET (0xCU)
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#define TIMER_CURRENT_VALUE1 (0x0U)
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#define TIMER_CURRENT_VALUE1_CURRENT_VALUE1_SHIFT (0U)
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#define TIMER_CURRENT_VALUE1_CURRENT_VALUE1_MASK (0xFFFFFFFFU << TIMER_CURRENT_VALUE1_CURRENT_VALUE1_SHIFT) /* 0xFFFFFFFF */
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/* CONTROLREG */
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#define TIMER_CONTROLREG_OFFSET (0x10U)
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#define TIMER_CONTROLREG_TIMER_ENABLE_SHIFT (0U)
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#define TIMER_CONTROLREG_TIMER_ENABLE_MASK (0x1U << TIMER_CONTROLREG_TIMER_ENABLE_SHIFT) /* 0x00000001 */
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#define TIMER_CONTROLREG_TIMER_MODE_SHIFT (1U)
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#define TIMER_CONTROLREG_TIMER_MODE_MASK (0x1U << TIMER_CONTROLREG_TIMER_MODE_SHIFT) /* 0x00000002 */
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#define TIMER_CONTROLREG_TIMER_INT_MASK_SHIFT (2U)
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#define TIMER_CONTROLREG_TIMER_INT_MASK_MASK (0x1U << TIMER_CONTROLREG_TIMER_INT_MASK_SHIFT) /* 0x00000004 */
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/* INTSTATUS */
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#define TIMER_INTSTATUS_OFFSET (0x18U)
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#define TIMER_INTSTATUS_INT_PD_SHIFT (0U)
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#define TIMER_INTSTATUS_INT_PD_MASK (0x1U << TIMER_INTSTATUS_INT_PD_SHIFT) /* 0x00000001 */
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/******************************************CRU*******************************************/
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/* APLL_CON0 */
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#define CRU_APLL_CON0_OFFSET (0x0U)
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#define CRU_APLL_CON0_FBDIV_SHIFT (0U)
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#define CRU_APLL_CON0_FBDIV_MASK (0xFFFU << CRU_APLL_CON0_FBDIV_SHIFT) /* 0x00000FFF */
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#define CRU_APLL_CON0_POSTDIV1_SHIFT (12U)
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#define CRU_APLL_CON0_POSTDIV1_MASK (0x7U << CRU_APLL_CON0_POSTDIV1_SHIFT) /* 0x00007000 */
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#define CRU_APLL_CON0_BYPASS_SHIFT (15U)
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#define CRU_APLL_CON0_BYPASS_MASK (0x1U << CRU_APLL_CON0_BYPASS_SHIFT) /* 0x00008000 */
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/* APLL_CON1 */
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#define CRU_APLL_CON1_OFFSET (0x4U)
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#define CRU_APLL_CON1_REFDIV_SHIFT (0U)
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#define CRU_APLL_CON1_REFDIV_MASK (0x3FU << CRU_APLL_CON1_REFDIV_SHIFT) /* 0x0000003F */
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#define CRU_APLL_CON1_POSTDIV2_SHIFT (6U)
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#define CRU_APLL_CON1_POSTDIV2_MASK (0x7U << CRU_APLL_CON1_POSTDIV2_SHIFT) /* 0x000001C0 */
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#define CRU_APLL_CON1_PLL_LOCK_SHIFT (10U)
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#define CRU_APLL_CON1_PLL_LOCK_MASK (0x1U << CRU_APLL_CON1_PLL_LOCK_SHIFT) /* 0x00000400 */
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#define CRU_APLL_CON1_DSMPD_SHIFT (12U)
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#define CRU_APLL_CON1_DSMPD_MASK (0x1U << CRU_APLL_CON1_DSMPD_SHIFT) /* 0x00001000 */
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#define CRU_APLL_CON1_PLLPD0_SHIFT (13U)
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#define CRU_APLL_CON1_PLLPD0_MASK (0x1U << CRU_APLL_CON1_PLLPD0_SHIFT) /* 0x00002000 */
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#define CRU_APLL_CON1_PLLPD1_SHIFT (14U)
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#define CRU_APLL_CON1_PLLPD1_MASK (0x1U << CRU_APLL_CON1_PLLPD1_SHIFT) /* 0x00004000 */
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#define CRU_APLL_CON1_PLLPDSEL_SHIFT (15U)
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#define CRU_APLL_CON1_PLLPDSEL_MASK (0x1U << CRU_APLL_CON1_PLLPDSEL_SHIFT) /* 0x00008000 */
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/* APLL_CON2 */
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#define CRU_APLL_CON2_OFFSET (0x8U)
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#define CRU_APLL_CON2_FRACDIV_SHIFT (0U)
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#define CRU_APLL_CON2_FRACDIV_MASK (0xFFFFFFU << CRU_APLL_CON2_FRACDIV_SHIFT) /* 0x00FFFFFF */
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#define CRU_APLL_CON2_DACPD_SHIFT (24U)
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#define CRU_APLL_CON2_DACPD_MASK (0x1U << CRU_APLL_CON2_DACPD_SHIFT) /* 0x01000000 */
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#define CRU_APLL_CON2_FOUTPOSTDIVPD_SHIFT (25U)
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#define CRU_APLL_CON2_FOUTPOSTDIVPD_MASK (0x1U << CRU_APLL_CON2_FOUTPOSTDIVPD_SHIFT) /* 0x02000000 */
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#define CRU_APLL_CON2_FOUTVCOPD_SHIFT (26U)
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#define CRU_APLL_CON2_FOUTVCOPD_MASK (0x1U << CRU_APLL_CON2_FOUTVCOPD_SHIFT) /* 0x04000000 */
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#define CRU_APLL_CON2_FOUT4PHASEPD_SHIFT (27U)
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#define CRU_APLL_CON2_FOUT4PHASEPD_MASK (0x1U << CRU_APLL_CON2_FOUT4PHASEPD_SHIFT) /* 0x08000000 */
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/* APLL_CON3 */
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#define CRU_APLL_CON3_OFFSET (0xCU)
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#define CRU_APLL_CON3_SSMOD_BP_SHIFT (0U)
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#define CRU_APLL_CON3_SSMOD_BP_MASK (0x1U << CRU_APLL_CON3_SSMOD_BP_SHIFT) /* 0x00000001 */
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#define CRU_APLL_CON3_SSMOD_DISABLE_SSCG_SHIFT (1U)
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#define CRU_APLL_CON3_SSMOD_DISABLE_SSCG_MASK (0x1U << CRU_APLL_CON3_SSMOD_DISABLE_SSCG_SHIFT) /* 0x00000002 */
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#define CRU_APLL_CON3_SSMOD_RESET_SHIFT (2U)
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#define CRU_APLL_CON3_SSMOD_RESET_MASK (0x1U << CRU_APLL_CON3_SSMOD_RESET_SHIFT) /* 0x00000004 */
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#define CRU_APLL_CON3_SSMOD_DOWNSPREAD_SHIFT (3U)
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#define CRU_APLL_CON3_SSMOD_DOWNSPREAD_MASK (0x1U << CRU_APLL_CON3_SSMOD_DOWNSPREAD_SHIFT) /* 0x00000008 */
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#define CRU_APLL_CON3_SSMOD_DIVVAL_SHIFT (4U)
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#define CRU_APLL_CON3_SSMOD_DIVVAL_MASK (0xFU << CRU_APLL_CON3_SSMOD_DIVVAL_SHIFT) /* 0x000000F0 */
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#define CRU_APLL_CON3_SSMOD_SPREAD_SHIFT (8U)
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#define CRU_APLL_CON3_SSMOD_SPREAD_MASK (0x1FU << CRU_APLL_CON3_SSMOD_SPREAD_SHIFT) /* 0x00001F00 */
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/* APLL_CON4 */
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#define CRU_APLL_CON4_OFFSET (0x10U)
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#define CRU_APLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT (0U)
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#define CRU_APLL_CON4_SSMOD_SEL_EXT_WAVE_MASK (0x1U << CRU_APLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT) /* 0x00000001 */
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#define CRU_APLL_CON4_SSMOD_EXT_MAXADDR_SHIFT (8U)
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#define CRU_APLL_CON4_SSMOD_EXT_MAXADDR_MASK (0xFFU << CRU_APLL_CON4_SSMOD_EXT_MAXADDR_SHIFT) /* 0x0000FF00 */
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/* DPLL_CON0 */
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#define CRU_DPLL_CON0_OFFSET (0x20U)
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#define CRU_DPLL_CON0_FBDIV_SHIFT (0U)
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#define CRU_DPLL_CON0_FBDIV_MASK (0xFFFU << CRU_DPLL_CON0_FBDIV_SHIFT) /* 0x00000FFF */
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#define CRU_DPLL_CON0_POSTDIV1_SHIFT (12U)
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#define CRU_DPLL_CON0_POSTDIV1_MASK (0x7U << CRU_DPLL_CON0_POSTDIV1_SHIFT) /* 0x00007000 */
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#define CRU_DPLL_CON0_BYPASS_SHIFT (15U)
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#define CRU_DPLL_CON0_BYPASS_MASK (0x1U << CRU_DPLL_CON0_BYPASS_SHIFT) /* 0x00008000 */
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/* DPLL_CON1 */
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#define CRU_DPLL_CON1_OFFSET (0x24U)
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#define CRU_DPLL_CON1_REFDIV_SHIFT (0U)
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#define CRU_DPLL_CON1_REFDIV_MASK (0x3FU << CRU_DPLL_CON1_REFDIV_SHIFT) /* 0x0000003F */
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#define CRU_DPLL_CON1_POSTDIV2_SHIFT (6U)
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#define CRU_DPLL_CON1_POSTDIV2_MASK (0x7U << CRU_DPLL_CON1_POSTDIV2_SHIFT) /* 0x000001C0 */
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#define CRU_DPLL_CON1_PLL_LOCK_SHIFT (10U)
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#define CRU_DPLL_CON1_PLL_LOCK_MASK (0x1U << CRU_DPLL_CON1_PLL_LOCK_SHIFT) /* 0x00000400 */
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#define CRU_DPLL_CON1_DSMPD_SHIFT (12U)
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#define CRU_DPLL_CON1_DSMPD_MASK (0x1U << CRU_DPLL_CON1_DSMPD_SHIFT) /* 0x00001000 */
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#define CRU_DPLL_CON1_PLLPD0_SHIFT (13U)
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#define CRU_DPLL_CON1_PLLPD0_MASK (0x1U << CRU_DPLL_CON1_PLLPD0_SHIFT) /* 0x00002000 */
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#define CRU_DPLL_CON1_PLLPD1_SHIFT (14U)
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#define CRU_DPLL_CON1_PLLPD1_MASK (0x1U << CRU_DPLL_CON1_PLLPD1_SHIFT) /* 0x00004000 */
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#define CRU_DPLL_CON1_PLLPDSEL_SHIFT (15U)
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#define CRU_DPLL_CON1_PLLPDSEL_MASK (0x1U << CRU_DPLL_CON1_PLLPDSEL_SHIFT) /* 0x00008000 */
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/* DPLL_CON2 */
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#define CRU_DPLL_CON2_OFFSET (0x28U)
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#define CRU_DPLL_CON2_FRACDIV_SHIFT (0U)
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#define CRU_DPLL_CON2_FRACDIV_MASK (0xFFFFFFU << CRU_DPLL_CON2_FRACDIV_SHIFT) /* 0x00FFFFFF */
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#define CRU_DPLL_CON2_DACPD_SHIFT (24U)
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#define CRU_DPLL_CON2_DACPD_MASK (0x1U << CRU_DPLL_CON2_DACPD_SHIFT) /* 0x01000000 */
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#define CRU_DPLL_CON2_FOUTPOSTDIVPD_SHIFT (25U)
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#define CRU_DPLL_CON2_FOUTPOSTDIVPD_MASK (0x1U << CRU_DPLL_CON2_FOUTPOSTDIVPD_SHIFT) /* 0x02000000 */
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#define CRU_DPLL_CON2_FOUTVCOPD_SHIFT (26U)
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#define CRU_DPLL_CON2_FOUTVCOPD_MASK (0x1U << CRU_DPLL_CON2_FOUTVCOPD_SHIFT) /* 0x04000000 */
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#define CRU_DPLL_CON2_FOUT4PHASEPD_SHIFT (27U)
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#define CRU_DPLL_CON2_FOUT4PHASEPD_MASK (0x1U << CRU_DPLL_CON2_FOUT4PHASEPD_SHIFT) /* 0x08000000 */
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/* DPLL_CON3 */
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#define CRU_DPLL_CON3_OFFSET (0x2CU)
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#define CRU_DPLL_CON3_SSMOD_BP_SHIFT (0U)
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#define CRU_DPLL_CON3_SSMOD_BP_MASK (0x1U << CRU_DPLL_CON3_SSMOD_BP_SHIFT) /* 0x00000001 */
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#define CRU_DPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT (1U)
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#define CRU_DPLL_CON3_SSMOD_DISABLE_SSCG_MASK (0x1U << CRU_DPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT) /* 0x00000002 */
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#define CRU_DPLL_CON3_SSMOD_RESET_SHIFT (2U)
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#define CRU_DPLL_CON3_SSMOD_RESET_MASK (0x1U << CRU_DPLL_CON3_SSMOD_RESET_SHIFT) /* 0x00000004 */
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#define CRU_DPLL_CON3_SSMOD_DOWNSPREAD_SHIFT (3U)
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#define CRU_DPLL_CON3_SSMOD_DOWNSPREAD_MASK (0x1U << CRU_DPLL_CON3_SSMOD_DOWNSPREAD_SHIFT) /* 0x00000008 */
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#define CRU_DPLL_CON3_SSMOD_DIVVAL_SHIFT (4U)
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#define CRU_DPLL_CON3_SSMOD_DIVVAL_MASK (0xFU << CRU_DPLL_CON3_SSMOD_DIVVAL_SHIFT) /* 0x000000F0 */
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#define CRU_DPLL_CON3_SSMOD_SPREAD_SHIFT (8U)
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#define CRU_DPLL_CON3_SSMOD_SPREAD_MASK (0x1FU << CRU_DPLL_CON3_SSMOD_SPREAD_SHIFT) /* 0x00001F00 */
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/* DPLL_CON4 */
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#define CRU_DPLL_CON4_OFFSET (0x30U)
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#define CRU_DPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT (0U)
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#define CRU_DPLL_CON4_SSMOD_SEL_EXT_WAVE_MASK (0x1U << CRU_DPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT) /* 0x00000001 */
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#define CRU_DPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT (8U)
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#define CRU_DPLL_CON4_SSMOD_EXT_MAXADDR_MASK (0xFFU << CRU_DPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT) /* 0x0000FF00 */
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/* GPLL_CON0 */
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#define CRU_GPLL_CON0_OFFSET (0x40U)
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#define CRU_GPLL_CON0_FBDIV_SHIFT (0U)
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#define CRU_GPLL_CON0_FBDIV_MASK (0xFFFU << CRU_GPLL_CON0_FBDIV_SHIFT) /* 0x00000FFF */
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#define CRU_GPLL_CON0_POSTDIV1_SHIFT (12U)
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#define CRU_GPLL_CON0_POSTDIV1_MASK (0x7U << CRU_GPLL_CON0_POSTDIV1_SHIFT) /* 0x00007000 */
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#define CRU_GPLL_CON0_BYPASS_SHIFT (15U)
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#define CRU_GPLL_CON0_BYPASS_MASK (0x1U << CRU_GPLL_CON0_BYPASS_SHIFT) /* 0x00008000 */
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/* GPLL_CON1 */
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#define CRU_GPLL_CON1_OFFSET (0x44U)
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#define CRU_GPLL_CON1_REFDIV_SHIFT (0U)
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#define CRU_GPLL_CON1_REFDIV_MASK (0x3FU << CRU_GPLL_CON1_REFDIV_SHIFT) /* 0x0000003F */
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#define CRU_GPLL_CON1_POSTDIV2_SHIFT (6U)
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#define CRU_GPLL_CON1_POSTDIV2_MASK (0x7U << CRU_GPLL_CON1_POSTDIV2_SHIFT) /* 0x000001C0 */
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#define CRU_GPLL_CON1_PLL_LOCK_SHIFT (10U)
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#define CRU_GPLL_CON1_PLL_LOCK_MASK (0x1U << CRU_GPLL_CON1_PLL_LOCK_SHIFT) /* 0x00000400 */
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#define CRU_GPLL_CON1_DSMPD_SHIFT (12U)
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#define CRU_GPLL_CON1_DSMPD_MASK (0x1U << CRU_GPLL_CON1_DSMPD_SHIFT) /* 0x00001000 */
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#define CRU_GPLL_CON1_PLLPD0_SHIFT (13U)
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#define CRU_GPLL_CON1_PLLPD0_MASK (0x1U << CRU_GPLL_CON1_PLLPD0_SHIFT) /* 0x00002000 */
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#define CRU_GPLL_CON1_PLLPD1_SHIFT (14U)
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#define CRU_GPLL_CON1_PLLPD1_MASK (0x1U << CRU_GPLL_CON1_PLLPD1_SHIFT) /* 0x00004000 */
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#define CRU_GPLL_CON1_PLLPDSEL_SHIFT (15U)
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#define CRU_GPLL_CON1_PLLPDSEL_MASK (0x1U << CRU_GPLL_CON1_PLLPDSEL_SHIFT) /* 0x00008000 */
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/* GPLL_CON2 */
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#define CRU_GPLL_CON2_OFFSET (0x48U)
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#define CRU_GPLL_CON2_FRACDIV_SHIFT (0U)
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#define CRU_GPLL_CON2_FRACDIV_MASK (0xFFFFFFU << CRU_GPLL_CON2_FRACDIV_SHIFT) /* 0x00FFFFFF */
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#define CRU_GPLL_CON2_DACPD_SHIFT (24U)
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#define CRU_GPLL_CON2_DACPD_MASK (0x1U << CRU_GPLL_CON2_DACPD_SHIFT) /* 0x01000000 */
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#define CRU_GPLL_CON2_FOUTPOSTDIVPD_SHIFT (25U)
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#define CRU_GPLL_CON2_FOUTPOSTDIVPD_MASK (0x1U << CRU_GPLL_CON2_FOUTPOSTDIVPD_SHIFT) /* 0x02000000 */
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#define CRU_GPLL_CON2_FOUTVCOPD_SHIFT (26U)
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#define CRU_GPLL_CON2_FOUTVCOPD_MASK (0x1U << CRU_GPLL_CON2_FOUTVCOPD_SHIFT) /* 0x04000000 */
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#define CRU_GPLL_CON2_FOUT4PHASEPD_SHIFT (27U)
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#define CRU_GPLL_CON2_FOUT4PHASEPD_MASK (0x1U << CRU_GPLL_CON2_FOUT4PHASEPD_SHIFT) /* 0x08000000 */
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/* GPLL_CON3 */
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#define CRU_GPLL_CON3_OFFSET (0x4CU)
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#define CRU_GPLL_CON3_SSMOD_BP_SHIFT (0U)
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#define CRU_GPLL_CON3_SSMOD_BP_MASK (0x1U << CRU_GPLL_CON3_SSMOD_BP_SHIFT) /* 0x00000001 */
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#define CRU_GPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT (1U)
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#define CRU_GPLL_CON3_SSMOD_DISABLE_SSCG_MASK (0x1U << CRU_GPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT) /* 0x00000002 */
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#define CRU_GPLL_CON3_SSMOD_RESET_SHIFT (2U)
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#define CRU_GPLL_CON3_SSMOD_RESET_MASK (0x1U << CRU_GPLL_CON3_SSMOD_RESET_SHIFT) /* 0x00000004 */
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#define CRU_GPLL_CON3_SSMOD_DOWNSPREAD_SHIFT (3U)
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#define CRU_GPLL_CON3_SSMOD_DOWNSPREAD_MASK (0x1U << CRU_GPLL_CON3_SSMOD_DOWNSPREAD_SHIFT) /* 0x00000008 */
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#define CRU_GPLL_CON3_SSMOD_DIVVAL_SHIFT (4U)
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#define CRU_GPLL_CON3_SSMOD_DIVVAL_MASK (0xFU << CRU_GPLL_CON3_SSMOD_DIVVAL_SHIFT) /* 0x000000F0 */
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#define CRU_GPLL_CON3_SSMOD_SPREAD_SHIFT (8U)
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#define CRU_GPLL_CON3_SSMOD_SPREAD_MASK (0x1FU << CRU_GPLL_CON3_SSMOD_SPREAD_SHIFT) /* 0x00001F00 */
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/* GPLL_CON4 */
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#define CRU_GPLL_CON4_OFFSET (0x50U)
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#define CRU_GPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT (0U)
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#define CRU_GPLL_CON4_SSMOD_SEL_EXT_WAVE_MASK (0x1U << CRU_GPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT) /* 0x00000001 */
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#define CRU_GPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT (8U)
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#define CRU_GPLL_CON4_SSMOD_EXT_MAXADDR_MASK (0xFFU << CRU_GPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT) /* 0x0000FF00 */
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/* CPLL_CON0 */
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#define CRU_CPLL_CON0_OFFSET (0x60U)
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#define CRU_CPLL_CON0_FBDIV_SHIFT (0U)
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#define CRU_CPLL_CON0_FBDIV_MASK (0xFFFU << CRU_CPLL_CON0_FBDIV_SHIFT) /* 0x00000FFF */
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#define CRU_CPLL_CON0_POSTDIV1_SHIFT (12U)
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#define CRU_CPLL_CON0_POSTDIV1_MASK (0x7U << CRU_CPLL_CON0_POSTDIV1_SHIFT) /* 0x00007000 */
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#define CRU_CPLL_CON0_BYPASS_SHIFT (15U)
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#define CRU_CPLL_CON0_BYPASS_MASK (0x1U << CRU_CPLL_CON0_BYPASS_SHIFT) /* 0x00008000 */
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/* CPLL_CON1 */
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#define CRU_CPLL_CON1_OFFSET (0x64U)
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#define CRU_CPLL_CON1_REFDIV_SHIFT (0U)
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#define CRU_CPLL_CON1_REFDIV_MASK (0x3FU << CRU_CPLL_CON1_REFDIV_SHIFT) /* 0x0000003F */
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#define CRU_CPLL_CON1_POSTDIV2_SHIFT (6U)
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#define CRU_CPLL_CON1_POSTDIV2_MASK (0x7U << CRU_CPLL_CON1_POSTDIV2_SHIFT) /* 0x000001C0 */
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#define CRU_CPLL_CON1_PLL_LOCK_SHIFT (10U)
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#define CRU_CPLL_CON1_PLL_LOCK_MASK (0x1U << CRU_CPLL_CON1_PLL_LOCK_SHIFT) /* 0x00000400 */
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#define CRU_CPLL_CON1_DSMPD_SHIFT (12U)
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#define CRU_CPLL_CON1_DSMPD_MASK (0x1U << CRU_CPLL_CON1_DSMPD_SHIFT) /* 0x00001000 */
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#define CRU_CPLL_CON1_PLLPD0_SHIFT (13U)
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#define CRU_CPLL_CON1_PLLPD0_MASK (0x1U << CRU_CPLL_CON1_PLLPD0_SHIFT) /* 0x00002000 */
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#define CRU_CPLL_CON1_PLLPD1_SHIFT (14U)
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#define CRU_CPLL_CON1_PLLPD1_MASK (0x1U << CRU_CPLL_CON1_PLLPD1_SHIFT) /* 0x00004000 */
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#define CRU_CPLL_CON1_PLLPDSEL_SHIFT (15U)
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#define CRU_CPLL_CON1_PLLPDSEL_MASK (0x1U << CRU_CPLL_CON1_PLLPDSEL_SHIFT) /* 0x00008000 */
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/* CPLL_CON2 */
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#define CRU_CPLL_CON2_OFFSET (0x68U)
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#define CRU_CPLL_CON2_FRACDIV_SHIFT (0U)
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#define CRU_CPLL_CON2_FRACDIV_MASK (0xFFFFFFU << CRU_CPLL_CON2_FRACDIV_SHIFT) /* 0x00FFFFFF */
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#define CRU_CPLL_CON2_DACPD_SHIFT (24U)
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#define CRU_CPLL_CON2_DACPD_MASK (0x1U << CRU_CPLL_CON2_DACPD_SHIFT) /* 0x01000000 */
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#define CRU_CPLL_CON2_FOUTPOSTDIVPD_SHIFT (25U)
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#define CRU_CPLL_CON2_FOUTPOSTDIVPD_MASK (0x1U << CRU_CPLL_CON2_FOUTPOSTDIVPD_SHIFT) /* 0x02000000 */
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#define CRU_CPLL_CON2_FOUTVCOPD_SHIFT (26U)
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#define CRU_CPLL_CON2_FOUTVCOPD_MASK (0x1U << CRU_CPLL_CON2_FOUTVCOPD_SHIFT) /* 0x04000000 */
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#define CRU_CPLL_CON2_FOUT4PHASEPD_SHIFT (27U)
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#define CRU_CPLL_CON2_FOUT4PHASEPD_MASK (0x1U << CRU_CPLL_CON2_FOUT4PHASEPD_SHIFT) /* 0x08000000 */
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/* CPLL_CON3 */
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#define CRU_CPLL_CON3_OFFSET (0x6CU)
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#define CRU_CPLL_CON3_SSMOD_BP_SHIFT (0U)
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#define CRU_CPLL_CON3_SSMOD_BP_MASK (0x1U << CRU_CPLL_CON3_SSMOD_BP_SHIFT) /* 0x00000001 */
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#define CRU_CPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT (1U)
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#define CRU_CPLL_CON3_SSMOD_DISABLE_SSCG_MASK (0x1U << CRU_CPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT) /* 0x00000002 */
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#define CRU_CPLL_CON3_SSMOD_RESET_SHIFT (2U)
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#define CRU_CPLL_CON3_SSMOD_RESET_MASK (0x1U << CRU_CPLL_CON3_SSMOD_RESET_SHIFT) /* 0x00000004 */
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#define CRU_CPLL_CON3_SSMOD_DOWNSPREAD_SHIFT (3U)
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#define CRU_CPLL_CON3_SSMOD_DOWNSPREAD_MASK (0x1U << CRU_CPLL_CON3_SSMOD_DOWNSPREAD_SHIFT) /* 0x00000008 */
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#define CRU_CPLL_CON3_SSMOD_DIVVAL_SHIFT (4U)
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#define CRU_CPLL_CON3_SSMOD_DIVVAL_MASK (0xFU << CRU_CPLL_CON3_SSMOD_DIVVAL_SHIFT) /* 0x000000F0 */
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#define CRU_CPLL_CON3_SSMOD_SPREAD_SHIFT (8U)
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#define CRU_CPLL_CON3_SSMOD_SPREAD_MASK (0x1FU << CRU_CPLL_CON3_SSMOD_SPREAD_SHIFT) /* 0x00001F00 */
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/* CPLL_CON4 */
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#define CRU_CPLL_CON4_OFFSET (0x70U)
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#define CRU_CPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT (0U)
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#define CRU_CPLL_CON4_SSMOD_SEL_EXT_WAVE_MASK (0x1U << CRU_CPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT) /* 0x00000001 */
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#define CRU_CPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT (8U)
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#define CRU_CPLL_CON4_SSMOD_EXT_MAXADDR_MASK (0xFFU << CRU_CPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT) /* 0x0000FF00 */
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/* NPLL_CON0 */
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#define CRU_NPLL_CON0_OFFSET (0x80U)
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#define CRU_NPLL_CON0_FBDIV_SHIFT (0U)
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#define CRU_NPLL_CON0_FBDIV_MASK (0xFFFU << CRU_NPLL_CON0_FBDIV_SHIFT) /* 0x00000FFF */
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#define CRU_NPLL_CON0_POSTDIV1_SHIFT (12U)
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#define CRU_NPLL_CON0_POSTDIV1_MASK (0x7U << CRU_NPLL_CON0_POSTDIV1_SHIFT) /* 0x00007000 */
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#define CRU_NPLL_CON0_BYPASS_SHIFT (15U)
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#define CRU_NPLL_CON0_BYPASS_MASK (0x1U << CRU_NPLL_CON0_BYPASS_SHIFT) /* 0x00008000 */
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/* NPLL_CON1 */
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#define CRU_NPLL_CON1_OFFSET (0x84U)
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#define CRU_NPLL_CON1_REFDIV_SHIFT (0U)
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#define CRU_NPLL_CON1_REFDIV_MASK (0x3FU << CRU_NPLL_CON1_REFDIV_SHIFT) /* 0x0000003F */
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#define CRU_NPLL_CON1_POSTDIV2_SHIFT (6U)
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#define CRU_NPLL_CON1_POSTDIV2_MASK (0x7U << CRU_NPLL_CON1_POSTDIV2_SHIFT) /* 0x000001C0 */
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#define CRU_NPLL_CON1_FOUTPOSTDIVPD_SHIFT (9U)
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#define CRU_NPLL_CON1_FOUTPOSTDIVPD_MASK (0x1U << CRU_NPLL_CON1_FOUTPOSTDIVPD_SHIFT) /* 0x00000200 */
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#define CRU_NPLL_CON1_PLL_LOCK_SHIFT (10U)
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#define CRU_NPLL_CON1_PLL_LOCK_MASK (0x1U << CRU_NPLL_CON1_PLL_LOCK_SHIFT) /* 0x00000400 */
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#define CRU_NPLL_CON1_FOUTVCOPD_SHIFT (11U)
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#define CRU_NPLL_CON1_FOUTVCOPD_MASK (0x1U << CRU_NPLL_CON1_FOUTVCOPD_SHIFT) /* 0x00000800 */
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#define CRU_NPLL_CON1_DSMPD_SHIFT (12U)
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#define CRU_NPLL_CON1_DSMPD_MASK (0x1U << CRU_NPLL_CON1_DSMPD_SHIFT) /* 0x00001000 */
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#define CRU_NPLL_CON1_PLLPD0_SHIFT (13U)
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#define CRU_NPLL_CON1_PLLPD0_MASK (0x1U << CRU_NPLL_CON1_PLLPD0_SHIFT) /* 0x00002000 */
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#define CRU_NPLL_CON1_PLLPD1_SHIFT (14U)
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#define CRU_NPLL_CON1_PLLPD1_MASK (0x1U << CRU_NPLL_CON1_PLLPD1_SHIFT) /* 0x00004000 */
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#define CRU_NPLL_CON1_PLLPDSEL_SHIFT (15U)
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#define CRU_NPLL_CON1_PLLPDSEL_MASK (0x1U << CRU_NPLL_CON1_PLLPDSEL_SHIFT) /* 0x00008000 */
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/* VPLL_CON0 */
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#define CRU_VPLL_CON0_OFFSET (0xA0U)
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#define CRU_VPLL_CON0_FBDIV_SHIFT (0U)
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#define CRU_VPLL_CON0_FBDIV_MASK (0xFFFU << CRU_VPLL_CON0_FBDIV_SHIFT) /* 0x00000FFF */
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#define CRU_VPLL_CON0_POSTDIV1_SHIFT (12U)
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#define CRU_VPLL_CON0_POSTDIV1_MASK (0x7U << CRU_VPLL_CON0_POSTDIV1_SHIFT) /* 0x00007000 */
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#define CRU_VPLL_CON0_BYPASS_SHIFT (15U)
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#define CRU_VPLL_CON0_BYPASS_MASK (0x1U << CRU_VPLL_CON0_BYPASS_SHIFT) /* 0x00008000 */
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/* VPLL_CON1 */
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#define CRU_VPLL_CON1_OFFSET (0xA4U)
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#define CRU_VPLL_CON1_REFDIV_SHIFT (0U)
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#define CRU_VPLL_CON1_REFDIV_MASK (0x3FU << CRU_VPLL_CON1_REFDIV_SHIFT) /* 0x0000003F */
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#define CRU_VPLL_CON1_POSTDIV2_SHIFT (6U)
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#define CRU_VPLL_CON1_POSTDIV2_MASK (0x7U << CRU_VPLL_CON1_POSTDIV2_SHIFT) /* 0x000001C0 */
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#define CRU_VPLL_CON1_FOUTPOSTDIVPD_SHIFT (9U)
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#define CRU_VPLL_CON1_FOUTPOSTDIVPD_MASK (0x1U << CRU_VPLL_CON1_FOUTPOSTDIVPD_SHIFT) /* 0x00000200 */
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#define CRU_VPLL_CON1_PLL_LOCK_SHIFT (10U)
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#define CRU_VPLL_CON1_PLL_LOCK_MASK (0x1U << CRU_VPLL_CON1_PLL_LOCK_SHIFT) /* 0x00000400 */
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#define CRU_VPLL_CON1_FOUTVCOPD_SHIFT (11U)
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#define CRU_VPLL_CON1_FOUTVCOPD_MASK (0x1U << CRU_VPLL_CON1_FOUTVCOPD_SHIFT) /* 0x00000800 */
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#define CRU_VPLL_CON1_DSMPD_SHIFT (12U)
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#define CRU_VPLL_CON1_DSMPD_MASK (0x1U << CRU_VPLL_CON1_DSMPD_SHIFT) /* 0x00001000 */
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#define CRU_VPLL_CON1_PLLPD0_SHIFT (13U)
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#define CRU_VPLL_CON1_PLLPD0_MASK (0x1U << CRU_VPLL_CON1_PLLPD0_SHIFT) /* 0x00002000 */
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#define CRU_VPLL_CON1_PLLPD1_SHIFT (14U)
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#define CRU_VPLL_CON1_PLLPD1_MASK (0x1U << CRU_VPLL_CON1_PLLPD1_SHIFT) /* 0x00004000 */
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#define CRU_VPLL_CON1_PLLPDSEL_SHIFT (15U)
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#define CRU_VPLL_CON1_PLLPDSEL_MASK (0x1U << CRU_VPLL_CON1_PLLPDSEL_SHIFT) /* 0x00008000 */
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/* MODE_CON00 */
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#define CRU_MODE_CON00_OFFSET (0xC0U)
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#define CRU_MODE_CON00_CLK_APLL_MODE_SHIFT (0U)
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#define CRU_MODE_CON00_CLK_APLL_MODE_MASK (0x3U << CRU_MODE_CON00_CLK_APLL_MODE_SHIFT) /* 0x00000003 */
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#define CRU_MODE_CON00_CLK_DPLL_MODE_SHIFT (2U)
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#define CRU_MODE_CON00_CLK_DPLL_MODE_MASK (0x3U << CRU_MODE_CON00_CLK_DPLL_MODE_SHIFT) /* 0x0000000C */
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#define CRU_MODE_CON00_CLK_CPLL_MODE_SHIFT (4U)
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#define CRU_MODE_CON00_CLK_CPLL_MODE_MASK (0x3U << CRU_MODE_CON00_CLK_CPLL_MODE_SHIFT) /* 0x00000030 */
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#define CRU_MODE_CON00_CLK_GPLL_MODE_SHIFT (6U)
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#define CRU_MODE_CON00_CLK_GPLL_MODE_MASK (0x3U << CRU_MODE_CON00_CLK_GPLL_MODE_SHIFT) /* 0x000000C0 */
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#define CRU_MODE_CON00_CLK_NPLL_MODE_SHIFT (10U)
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#define CRU_MODE_CON00_CLK_NPLL_MODE_MASK (0x3U << CRU_MODE_CON00_CLK_NPLL_MODE_SHIFT) /* 0x00000C00 */
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#define CRU_MODE_CON00_CLK_VPLL_MODE_SHIFT (12U)
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#define CRU_MODE_CON00_CLK_VPLL_MODE_MASK (0x3U << CRU_MODE_CON00_CLK_VPLL_MODE_SHIFT) /* 0x00003000 */
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#define CRU_MODE_CON00_USBPHY480M_PLL_MODE_SHIFT (14U)
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#define CRU_MODE_CON00_USBPHY480M_PLL_MODE_MASK (0x3U << CRU_MODE_CON00_USBPHY480M_PLL_MODE_SHIFT) /* 0x0000C000 */
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/* MISC_CON0 */
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#define CRU_MISC_CON0_OFFSET (0xC4U)
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#define CRU_MISC_CON0_QCHANNEL_ENA_SCLK_CORE_SHIFT (0U)
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#define CRU_MISC_CON0_QCHANNEL_ENA_SCLK_CORE_MASK (0x1U << CRU_MISC_CON0_QCHANNEL_ENA_SCLK_CORE_SHIFT) /* 0x00000001 */
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#define CRU_MISC_CON0_QCHANNEL_ENA_PCLK_CORE_SHIFT (1U)
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#define CRU_MISC_CON0_QCHANNEL_ENA_PCLK_CORE_MASK (0x1U << CRU_MISC_CON0_QCHANNEL_ENA_PCLK_CORE_SHIFT) /* 0x00000002 */
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#define CRU_MISC_CON0_QCHANNEL_ENA_ATCLK_CORE_SHIFT (2U)
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#define CRU_MISC_CON0_QCHANNEL_ENA_ATCLK_CORE_MASK (0x1U << CRU_MISC_CON0_QCHANNEL_ENA_ATCLK_CORE_SHIFT) /* 0x00000004 */
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#define CRU_MISC_CON0_QCHANNEL_ENA_GICCLK_CORE_SHIFT (3U)
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#define CRU_MISC_CON0_QCHANNEL_ENA_GICCLK_CORE_MASK (0x1U << CRU_MISC_CON0_QCHANNEL_ENA_GICCLK_CORE_SHIFT) /* 0x00000008 */
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#define CRU_MISC_CON0_QCHANNEL_ENA_PDBGCLK_CORE_SHIFT (4U)
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#define CRU_MISC_CON0_QCHANNEL_ENA_PDBGCLK_CORE_MASK (0x1U << CRU_MISC_CON0_QCHANNEL_ENA_PDBGCLK_CORE_SHIFT) /* 0x00000010 */
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#define CRU_MISC_CON0_QCHANNEL_ENA_CLK_GPU_SHIFT (5U)
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#define CRU_MISC_CON0_QCHANNEL_ENA_CLK_GPU_MASK (0x1U << CRU_MISC_CON0_QCHANNEL_ENA_CLK_GPU_SHIFT) /* 0x00000020 */
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#define CRU_MISC_CON0_QCHANNEL_ENA_CLK_PDCORE_CORE2GIC_SHIFT (6U)
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#define CRU_MISC_CON0_QCHANNEL_ENA_CLK_PDCORE_CORE2GIC_MASK (0x1U << CRU_MISC_CON0_QCHANNEL_ENA_CLK_PDCORE_CORE2GIC_SHIFT) /* 0x00000040 */
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#define CRU_MISC_CON0_QCHANNEL_ENA_CLK_PDCORE_GIC2CORE_SHIFT (7U)
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#define CRU_MISC_CON0_QCHANNEL_ENA_CLK_PDCORE_GIC2CORE_MASK (0x1U << CRU_MISC_CON0_QCHANNEL_ENA_CLK_PDCORE_GIC2CORE_SHIFT) /* 0x00000080 */
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#define CRU_MISC_CON0_QCHANNEL_ENA_CLK_PDGIC_CORE2GIC_SHIFT (8U)
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#define CRU_MISC_CON0_QCHANNEL_ENA_CLK_PDGIC_CORE2GIC_MASK (0x1U << CRU_MISC_CON0_QCHANNEL_ENA_CLK_PDGIC_CORE2GIC_SHIFT) /* 0x00000100 */
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#define CRU_MISC_CON0_QCHANNEL_ENA_CLK_PDGIC_GIC2CORE_SHIFT (9U)
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#define CRU_MISC_CON0_QCHANNEL_ENA_CLK_PDGIC_GIC2CORE_MASK (0x1U << CRU_MISC_CON0_QCHANNEL_ENA_CLK_PDGIC_GIC2CORE_SHIFT) /* 0x00000200 */
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#define CRU_MISC_CON0_QCHANNEL_ENA_CLK_GIC600_SHIFT (10U)
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#define CRU_MISC_CON0_QCHANNEL_ENA_CLK_GIC600_MASK (0x1U << CRU_MISC_CON0_QCHANNEL_ENA_CLK_GIC600_SHIFT) /* 0x00000400 */
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#define CRU_MISC_CON0_QCHANNEL_GATING_ENABLE_SHIFT (11U)
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#define CRU_MISC_CON0_QCHANNEL_GATING_ENABLE_MASK (0x1U << CRU_MISC_CON0_QCHANNEL_GATING_ENABLE_SHIFT) /* 0x00000800 */
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#define CRU_MISC_CON0_DBGRST_EN_SHIFT (12U)
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#define CRU_MISC_CON0_DBGRST_EN_MASK (0x1U << CRU_MISC_CON0_DBGRST_EN_SHIFT) /* 0x00001000 */
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#define CRU_MISC_CON0_HWFFC_CLK_SWITCH2CRU_ENA_SHIFT (13U)
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#define CRU_MISC_CON0_HWFFC_CLK_SWITCH2CRU_ENA_MASK (0x1U << CRU_MISC_CON0_HWFFC_CLK_SWITCH2CRU_ENA_SHIFT) /* 0x00002000 */
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#define CRU_MISC_CON0_CPU_CLK_GATE_EMA_ENA_SHIFT (14U)
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#define CRU_MISC_CON0_CPU_CLK_GATE_EMA_ENA_MASK (0x1U << CRU_MISC_CON0_CPU_CLK_GATE_EMA_ENA_SHIFT) /* 0x00004000 */
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#define CRU_MISC_CON0_GPU_CLK_GATE_EMA_ENA_SHIFT (15U)
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#define CRU_MISC_CON0_GPU_CLK_GATE_EMA_ENA_MASK (0x1U << CRU_MISC_CON0_GPU_CLK_GATE_EMA_ENA_SHIFT) /* 0x00008000 */
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/* MISC_CON1 */
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#define CRU_MISC_CON1_OFFSET (0xC8U)
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#define CRU_MISC_CON1_PD_CORE_DWN_CLK_EN_MASK_SHIFT (0U)
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#define CRU_MISC_CON1_PD_CORE_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_CORE_DWN_CLK_EN_MASK_SHIFT) /* 0x00000001 */
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#define CRU_MISC_CON1_PD_GPU_DWN_CLK_EN_MASK_SHIFT (1U)
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#define CRU_MISC_CON1_PD_GPU_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_GPU_DWN_CLK_EN_MASK_SHIFT) /* 0x00000002 */
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#define CRU_MISC_CON1_PD_NPU_DWN_CLK_EN_MASK_SHIFT (2U)
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#define CRU_MISC_CON1_PD_NPU_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_NPU_DWN_CLK_EN_MASK_SHIFT) /* 0x00000004 */
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#define CRU_MISC_CON1_PD_DDR_DWN_CLK_EN_MASK_SHIFT (3U)
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#define CRU_MISC_CON1_PD_DDR_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_DDR_DWN_CLK_EN_MASK_SHIFT) /* 0x00000008 */
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#define CRU_MISC_CON1_PD_PERI_DWN_CLK_EN_MASK_SHIFT (4U)
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#define CRU_MISC_CON1_PD_PERI_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_PERI_DWN_CLK_EN_MASK_SHIFT) /* 0x00000010 */
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#define CRU_MISC_CON1_PD_PIPE_DWN_CLK_EN_MASK_SHIFT (5U)
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#define CRU_MISC_CON1_PD_PIPE_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_PIPE_DWN_CLK_EN_MASK_SHIFT) /* 0x00000020 */
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#define CRU_MISC_CON1_PD_USB_DWN_CLK_EN_MASK_SHIFT (8U)
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#define CRU_MISC_CON1_PD_USB_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_USB_DWN_CLK_EN_MASK_SHIFT) /* 0x00000100 */
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#define CRU_MISC_CON1_PD_VI_DWN_CLK_EN_MASK_SHIFT (9U)
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#define CRU_MISC_CON1_PD_VI_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_VI_DWN_CLK_EN_MASK_SHIFT) /* 0x00000200 */
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#define CRU_MISC_CON1_PD_VO_DWN_CLK_EN_MASK_SHIFT (10U)
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#define CRU_MISC_CON1_PD_VO_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_VO_DWN_CLK_EN_MASK_SHIFT) /* 0x00000400 */
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#define CRU_MISC_CON1_PD_RGA_DWN_CLK_EN_MASK_SHIFT (11U)
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#define CRU_MISC_CON1_PD_RGA_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_RGA_DWN_CLK_EN_MASK_SHIFT) /* 0x00000800 */
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#define CRU_MISC_CON1_PD_VPU_DWN_CLK_EN_MASK_SHIFT (12U)
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#define CRU_MISC_CON1_PD_VPU_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_VPU_DWN_CLK_EN_MASK_SHIFT) /* 0x00001000 */
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#define CRU_MISC_CON1_PD_RKVENC_DWN_CLK_EN_MASK_SHIFT (13U)
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#define CRU_MISC_CON1_PD_RKVENC_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_RKVENC_DWN_CLK_EN_MASK_SHIFT) /* 0x00002000 */
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#define CRU_MISC_CON1_PD_RKVDEC_DWN_CLK_EN_MASK_SHIFT (14U)
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#define CRU_MISC_CON1_PD_RKVDEC_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_RKVDEC_DWN_CLK_EN_MASK_SHIFT) /* 0x00004000 */
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#define CRU_MISC_CON1_PD_BUS_DWN_CLK_EN_MASK_SHIFT (15U)
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#define CRU_MISC_CON1_PD_BUS_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_BUS_DWN_CLK_EN_MASK_SHIFT) /* 0x00008000 */
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/* MISC_CON2 */
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#define CRU_MISC_CON2_OFFSET (0xCCU)
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#define CRU_MISC_CON2_CLK_RGA_CORE_IDLE_ENABLE_SHIFT (0U)
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#define CRU_MISC_CON2_CLK_RGA_CORE_IDLE_ENABLE_MASK (0x1U << CRU_MISC_CON2_CLK_RGA_CORE_IDLE_ENABLE_SHIFT) /* 0x00000001 */
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#define CRU_MISC_CON2_CLK_IEP_CORE_IDLE_ENABLE_SHIFT (1U)
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#define CRU_MISC_CON2_CLK_IEP_CORE_IDLE_ENABLE_MASK (0x1U << CRU_MISC_CON2_CLK_IEP_CORE_IDLE_ENABLE_SHIFT) /* 0x00000002 */
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#define CRU_MISC_CON2_ACLK_VPU_IDLE_ENABLE_SHIFT (2U)
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#define CRU_MISC_CON2_ACLK_VPU_IDLE_ENABLE_MASK (0x1U << CRU_MISC_CON2_ACLK_VPU_IDLE_ENABLE_SHIFT) /* 0x00000004 */
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#define CRU_MISC_CON2_ACLK_RKVENC_IDLE_ENABLE_SHIFT (3U)
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#define CRU_MISC_CON2_ACLK_RKVENC_IDLE_ENABLE_MASK (0x1U << CRU_MISC_CON2_ACLK_RKVENC_IDLE_ENABLE_SHIFT) /* 0x00000008 */
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#define CRU_MISC_CON2_HCLK_RKVENC_IDLE_ENABLE_SHIFT (4U)
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#define CRU_MISC_CON2_HCLK_RKVENC_IDLE_ENABLE_MASK (0x1U << CRU_MISC_CON2_HCLK_RKVENC_IDLE_ENABLE_SHIFT) /* 0x00000010 */
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#define CRU_MISC_CON2_CLK_RKVENC_CORE_IDLE_ENABLE_SHIFT (5U)
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#define CRU_MISC_CON2_CLK_RKVENC_CORE_IDLE_ENABLE_MASK (0x1U << CRU_MISC_CON2_CLK_RKVENC_CORE_IDLE_ENABLE_SHIFT) /* 0x00000020 */
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#define CRU_MISC_CON2_ACLK_RKVDEC_IDLE_ENABLE_SHIFT (6U)
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#define CRU_MISC_CON2_ACLK_RKVDEC_IDLE_ENABLE_MASK (0x1U << CRU_MISC_CON2_ACLK_RKVDEC_IDLE_ENABLE_SHIFT) /* 0x00000040 */
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#define CRU_MISC_CON2_CLK_RKVDEC_CORE_IDLE_ENABLE_SHIFT (7U)
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#define CRU_MISC_CON2_CLK_RKVDEC_CORE_IDLE_ENABLE_MASK (0x1U << CRU_MISC_CON2_CLK_RKVDEC_CORE_IDLE_ENABLE_SHIFT) /* 0x00000080 */
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#define CRU_MISC_CON2_CLK_RKVDEC_CA_IDLE_ENABLE_SHIFT (8U)
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#define CRU_MISC_CON2_CLK_RKVDEC_CA_IDLE_ENABLE_MASK (0x1U << CRU_MISC_CON2_CLK_RKVDEC_CA_IDLE_ENABLE_SHIFT) /* 0x00000100 */
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#define CRU_MISC_CON2_CLK_RKVDEC_HEVC_CA_IDLE_ENABLE_SHIFT (9U)
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#define CRU_MISC_CON2_CLK_RKVDEC_HEVC_CA_IDLE_ENABLE_MASK (0x1U << CRU_MISC_CON2_CLK_RKVDEC_HEVC_CA_IDLE_ENABLE_SHIFT) /* 0x00000200 */
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#define CRU_MISC_CON2_USBPHY480M_SRC_SEL_SHIFT (15U)
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#define CRU_MISC_CON2_USBPHY480M_SRC_SEL_MASK (0x1U << CRU_MISC_CON2_USBPHY480M_SRC_SEL_SHIFT) /* 0x00008000 */
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/* GLB_CNT_TH */
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#define CRU_GLB_CNT_TH_OFFSET (0xD0U)
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#define CRU_GLB_CNT_TH_GLOBAL_RESET_COUNTER_THRESHOLD_SHIFT (0U)
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#define CRU_GLB_CNT_TH_GLOBAL_RESET_COUNTER_THRESHOLD_MASK (0xFFFFU << CRU_GLB_CNT_TH_GLOBAL_RESET_COUNTER_THRESHOLD_SHIFT) /* 0x0000FFFF */
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#define CRU_GLB_CNT_TH_RESERVED_SHIFT (16U)
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#define CRU_GLB_CNT_TH_RESERVED_MASK (0xFFFFU << CRU_GLB_CNT_TH_RESERVED_SHIFT) /* 0xFFFF0000 */
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/* GLB_SRST_FST */
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#define CRU_GLB_SRST_FST_OFFSET (0xD4U)
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#define CRU_GLB_SRST_FST_GLB_SRST_FST_SHIFT (0U)
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#define CRU_GLB_SRST_FST_GLB_SRST_FST_MASK (0xFFFFU << CRU_GLB_SRST_FST_GLB_SRST_FST_SHIFT) /* 0x0000FFFF */
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/* GLB_SRST_SND */
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#define CRU_GLB_SRST_SND_OFFSET (0xD8U)
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#define CRU_GLB_SRST_SND_GLB_SRST_SND_SHIFT (0U)
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#define CRU_GLB_SRST_SND_GLB_SRST_SND_MASK (0xFFFFU << CRU_GLB_SRST_SND_GLB_SRST_SND_SHIFT) /* 0x0000FFFF */
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/* GLB_RST_CON */
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#define CRU_GLB_RST_CON_OFFSET (0xDCU)
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#define CRU_GLB_RST_CON_TSADC_GLB_SRST_CTRL_SHIFT (0U)
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#define CRU_GLB_RST_CON_TSADC_GLB_SRST_CTRL_MASK (0x1U << CRU_GLB_RST_CON_TSADC_GLB_SRST_CTRL_SHIFT) /* 0x00000001 */
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#define CRU_GLB_RST_CON_WDT_GLB_SRST_CTRL_SHIFT (1U)
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#define CRU_GLB_RST_CON_WDT_GLB_SRST_CTRL_MASK (0x1U << CRU_GLB_RST_CON_WDT_GLB_SRST_CTRL_SHIFT) /* 0x00000002 */
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#define CRU_GLB_RST_CON_PMU_SRST_GLB_CTRL_SHIFT (2U)
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#define CRU_GLB_RST_CON_PMU_SRST_GLB_CTRL_MASK (0x1U << CRU_GLB_RST_CON_PMU_SRST_GLB_CTRL_SHIFT) /* 0x00000004 */
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#define CRU_GLB_RST_CON_PMU_SRST_GLB_EN_SHIFT (3U)
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#define CRU_GLB_RST_CON_PMU_SRST_GLB_EN_MASK (0x1U << CRU_GLB_RST_CON_PMU_SRST_GLB_EN_SHIFT) /* 0x00000008 */
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#define CRU_GLB_RST_CON_PMU_SRST_WDT_EN_SHIFT (4U)
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#define CRU_GLB_RST_CON_PMU_SRST_WDT_EN_MASK (0x1U << CRU_GLB_RST_CON_PMU_SRST_WDT_EN_SHIFT) /* 0x00000010 */
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#define CRU_GLB_RST_CON_TSADC_SHUT_RESET_EXT_EN_SHIFT (6U)
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#define CRU_GLB_RST_CON_TSADC_SHUT_RESET_EXT_EN_MASK (0x1U << CRU_GLB_RST_CON_TSADC_SHUT_RESET_EXT_EN_SHIFT) /* 0x00000040 */
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#define CRU_GLB_RST_CON_WDT_RESET_EXT_EN_SHIFT (7U)
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#define CRU_GLB_RST_CON_WDT_RESET_EXT_EN_MASK (0x1U << CRU_GLB_RST_CON_WDT_RESET_EXT_EN_SHIFT) /* 0x00000080 */
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#define CRU_GLB_RST_CON_JDB_GLB_SRST_CTRL_ENABLE_SHIFT (8U)
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#define CRU_GLB_RST_CON_JDB_GLB_SRST_CTRL_ENABLE_MASK (0x1U << CRU_GLB_RST_CON_JDB_GLB_SRST_CTRL_ENABLE_SHIFT) /* 0x00000100 */
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#define CRU_GLB_RST_CON_OSC_CHK_GLB_SRST_CTRL_ENABLE_SHIFT (9U)
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#define CRU_GLB_RST_CON_OSC_CHK_GLB_SRST_CTRL_ENABLE_MASK (0x1U << CRU_GLB_RST_CON_OSC_CHK_GLB_SRST_CTRL_ENABLE_SHIFT) /* 0x00000200 */
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#define CRU_GLB_RST_CON_SGRF_CRC_CHK_GLB_SRST_CTRL_ENABLE_SHIFT (10U)
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#define CRU_GLB_RST_CON_SGRF_CRC_CHK_GLB_SRST_CTRL_ENABLE_MASK (0x1U << CRU_GLB_RST_CON_SGRF_CRC_CHK_GLB_SRST_CTRL_ENABLE_SHIFT) /* 0x00000400 */
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#define CRU_GLB_RST_CON_PMUSGRF_CRC_CHK_GLB_SRST_CTRL_ENABLE_SHIFT (11U)
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#define CRU_GLB_RST_CON_PMUSGRF_CRC_CHK_GLB_SRST_CTRL_ENABLE_MASK (0x1U << CRU_GLB_RST_CON_PMUSGRF_CRC_CHK_GLB_SRST_CTRL_ENABLE_SHIFT) /* 0x00000800 */
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#define CRU_GLB_RST_CON_JDB_GLB_SRST_CTRL_SHIFT (12U)
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#define CRU_GLB_RST_CON_JDB_GLB_SRST_CTRL_MASK (0x1U << CRU_GLB_RST_CON_JDB_GLB_SRST_CTRL_SHIFT) /* 0x00001000 */
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#define CRU_GLB_RST_CON_OSC_CHK_GLB_SRST_CTRL_SHIFT (13U)
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#define CRU_GLB_RST_CON_OSC_CHK_GLB_SRST_CTRL_MASK (0x1U << CRU_GLB_RST_CON_OSC_CHK_GLB_SRST_CTRL_SHIFT) /* 0x00002000 */
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#define CRU_GLB_RST_CON_SGRF_CRC_CHK_GLB_SRST_CTRL_SHIFT (14U)
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#define CRU_GLB_RST_CON_SGRF_CRC_CHK_GLB_SRST_CTRL_MASK (0x1U << CRU_GLB_RST_CON_SGRF_CRC_CHK_GLB_SRST_CTRL_SHIFT) /* 0x00004000 */
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#define CRU_GLB_RST_CON_PMUSGRF_CRC_CHK_GLB_SRST_CTRL_SHIFT (15U)
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#define CRU_GLB_RST_CON_PMUSGRF_CRC_CHK_GLB_SRST_CTRL_MASK (0x1U << CRU_GLB_RST_CON_PMUSGRF_CRC_CHK_GLB_SRST_CTRL_SHIFT) /* 0x00008000 */
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/* GLB_RST_ST */
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#define CRU_GLB_RST_ST_OFFSET (0xE0U)
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#define CRU_GLB_RST_ST_FST_GLB_RST_ST_SHIFT (0U)
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#define CRU_GLB_RST_ST_FST_GLB_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_FST_GLB_RST_ST_SHIFT) /* 0x00000001 */
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#define CRU_GLB_RST_ST_SND_GLB_RST_ST_SHIFT (1U)
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#define CRU_GLB_RST_ST_SND_GLB_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_SND_GLB_RST_ST_SHIFT) /* 0x00000002 */
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#define CRU_GLB_RST_ST_FST_GLB_TSADC_RST_ST_SHIFT (2U)
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#define CRU_GLB_RST_ST_FST_GLB_TSADC_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_FST_GLB_TSADC_RST_ST_SHIFT) /* 0x00000004 */
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#define CRU_GLB_RST_ST_SND_GLB_TSADC_RST_ST_SHIFT (3U)
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#define CRU_GLB_RST_ST_SND_GLB_TSADC_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_SND_GLB_TSADC_RST_ST_SHIFT) /* 0x00000008 */
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#define CRU_GLB_RST_ST_FST_GLB_WDT_RST_ST_SHIFT (4U)
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#define CRU_GLB_RST_ST_FST_GLB_WDT_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_FST_GLB_WDT_RST_ST_SHIFT) /* 0x00000010 */
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#define CRU_GLB_RST_ST_SND_GLB_WDT_RST_ST_SHIFT (5U)
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#define CRU_GLB_RST_ST_SND_GLB_WDT_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_SND_GLB_WDT_RST_ST_SHIFT) /* 0x00000020 */
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#define CRU_GLB_RST_ST_GLB_JDB_RST_ST_SHIFT (6U)
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#define CRU_GLB_RST_ST_GLB_JDB_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_GLB_JDB_RST_ST_SHIFT) /* 0x00000040 */
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#define CRU_GLB_RST_ST_GLB_OSC_CHK_RST_ST_SHIFT (7U)
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#define CRU_GLB_RST_ST_GLB_OSC_CHK_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_GLB_OSC_CHK_RST_ST_SHIFT) /* 0x00000080 */
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#define CRU_GLB_RST_ST_GLB_SGRF_CRC_RST_ST_SHIFT (8U)
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#define CRU_GLB_RST_ST_GLB_SGRF_CRC_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_GLB_SGRF_CRC_RST_ST_SHIFT) /* 0x00000100 */
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#define CRU_GLB_RST_ST_GLB_PMUSGRF_CRC_RST_ST_SHIFT (9U)
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#define CRU_GLB_RST_ST_GLB_PMUSGRF_CRC_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_GLB_PMUSGRF_CRC_RST_ST_SHIFT) /* 0x00000200 */
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/* CLKSEL_CON00 */
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#define CRU_CLKSEL_CON00_OFFSET (0x100U)
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#define CRU_CLKSEL_CON00_CLK_CORE0_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON00_CLK_CORE0_DIV_MASK (0x1FU << CRU_CLKSEL_CON00_CLK_CORE0_DIV_SHIFT) /* 0x0000001F */
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#define CRU_CLKSEL_CON00_CLK_CORE_I_SEL_SHIFT (6U)
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#define CRU_CLKSEL_CON00_CLK_CORE_I_SEL_MASK (0x1U << CRU_CLKSEL_CON00_CLK_CORE_I_SEL_SHIFT) /* 0x00000040 */
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#define CRU_CLKSEL_CON00_CLK_CORE_NDFT_SEL_SHIFT (7U)
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#define CRU_CLKSEL_CON00_CLK_CORE_NDFT_SEL_MASK (0x1U << CRU_CLKSEL_CON00_CLK_CORE_NDFT_SEL_SHIFT) /* 0x00000080 */
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#define CRU_CLKSEL_CON00_CLK_CORE1_DIV_SHIFT (8U)
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#define CRU_CLKSEL_CON00_CLK_CORE1_DIV_MASK (0x1FU << CRU_CLKSEL_CON00_CLK_CORE1_DIV_SHIFT) /* 0x00001F00 */
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#define CRU_CLKSEL_CON00_CLK_CORE_NDFT_MUX_SEL_SHIFT (15U)
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#define CRU_CLKSEL_CON00_CLK_CORE_NDFT_MUX_SEL_MASK (0x1U << CRU_CLKSEL_CON00_CLK_CORE_NDFT_MUX_SEL_SHIFT) /* 0x00008000 */
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/* CLKSEL_CON01 */
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#define CRU_CLKSEL_CON01_OFFSET (0x104U)
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#define CRU_CLKSEL_CON01_CLK_CORE2_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON01_CLK_CORE2_DIV_MASK (0x1FU << CRU_CLKSEL_CON01_CLK_CORE2_DIV_SHIFT) /* 0x0000001F */
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#define CRU_CLKSEL_CON01_CLK_CORE3_DIV_SHIFT (8U)
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#define CRU_CLKSEL_CON01_CLK_CORE3_DIV_MASK (0x1FU << CRU_CLKSEL_CON01_CLK_CORE3_DIV_SHIFT) /* 0x00001F00 */
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/* CLKSEL_CON02 */
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#define CRU_CLKSEL_CON02_OFFSET (0x108U)
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#define CRU_CLKSEL_CON02_SCLK_CORE_SRC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON02_SCLK_CORE_SRC_DIV_MASK (0xFU << CRU_CLKSEL_CON02_SCLK_CORE_SRC_DIV_SHIFT) /* 0x0000000F */
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#define CRU_CLKSEL_CON02_SCLK_CORE_SRC_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON02_SCLK_CORE_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON02_SCLK_CORE_SRC_SEL_SHIFT) /* 0x00000300 */
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#define CRU_CLKSEL_CON02_SCLK_CORE_PRE_SEL_SHIFT (15U)
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#define CRU_CLKSEL_CON02_SCLK_CORE_PRE_SEL_MASK (0x1U << CRU_CLKSEL_CON02_SCLK_CORE_PRE_SEL_SHIFT) /* 0x00008000 */
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/* CLKSEL_CON03 */
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#define CRU_CLKSEL_CON03_OFFSET (0x10CU)
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#define CRU_CLKSEL_CON03_ATCLK_CORE_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON03_ATCLK_CORE_DIV_MASK (0x1FU << CRU_CLKSEL_CON03_ATCLK_CORE_DIV_SHIFT) /* 0x0000001F */
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#define CRU_CLKSEL_CON03_GICCLK_CORE_DIV_SHIFT (8U)
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#define CRU_CLKSEL_CON03_GICCLK_CORE_DIV_MASK (0x1FU << CRU_CLKSEL_CON03_GICCLK_CORE_DIV_SHIFT) /* 0x00001F00 */
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/* CLKSEL_CON04 */
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#define CRU_CLKSEL_CON04_OFFSET (0x110U)
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#define CRU_CLKSEL_CON04_PCLK_CORE_PRE_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON04_PCLK_CORE_PRE_DIV_MASK (0x1FU << CRU_CLKSEL_CON04_PCLK_CORE_PRE_DIV_SHIFT) /* 0x0000001F */
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#define CRU_CLKSEL_CON04_PERIPHCLK_CORE_PRE_DIV_SHIFT (8U)
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#define CRU_CLKSEL_CON04_PERIPHCLK_CORE_PRE_DIV_MASK (0x1FU << CRU_CLKSEL_CON04_PERIPHCLK_CORE_PRE_DIV_SHIFT) /* 0x00001F00 */
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/* CLKSEL_CON05 */
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#define CRU_CLKSEL_CON05_OFFSET (0x114U)
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#define CRU_CLKSEL_CON05_RESERVED_SHIFT (0U)
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#define CRU_CLKSEL_CON05_RESERVED_MASK (0xFFU << CRU_CLKSEL_CON05_RESERVED_SHIFT) /* 0x000000FF */
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#define CRU_CLKSEL_CON05_ACLK_CORE_NDFT_DIV_SHIFT (8U)
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#define CRU_CLKSEL_CON05_ACLK_CORE_NDFT_DIV_MASK (0x1FU << CRU_CLKSEL_CON05_ACLK_CORE_NDFT_DIV_SHIFT) /* 0x00001F00 */
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#define CRU_CLKSEL_CON05_ACLK_CORE_NIU2BUS_SEL_SHIFT (14U)
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#define CRU_CLKSEL_CON05_ACLK_CORE_NIU2BUS_SEL_MASK (0x3U << CRU_CLKSEL_CON05_ACLK_CORE_NIU2BUS_SEL_SHIFT) /* 0x0000C000 */
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/* CLKSEL_CON06 */
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#define CRU_CLKSEL_CON06_OFFSET (0x118U)
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#define CRU_CLKSEL_CON06_CLK_GPU_PRE_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON06_CLK_GPU_PRE_DIV_MASK (0xFU << CRU_CLKSEL_CON06_CLK_GPU_PRE_DIV_SHIFT) /* 0x0000000F */
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#define CRU_CLKSEL_CON06_CLK_GPU_PRE_SEL_SHIFT (6U)
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#define CRU_CLKSEL_CON06_CLK_GPU_PRE_SEL_MASK (0x3U << CRU_CLKSEL_CON06_CLK_GPU_PRE_SEL_SHIFT) /* 0x000000C0 */
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#define CRU_CLKSEL_CON06_ACLK_GPU_PRE_DIV_SHIFT (8U)
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#define CRU_CLKSEL_CON06_ACLK_GPU_PRE_DIV_MASK (0x3U << CRU_CLKSEL_CON06_ACLK_GPU_PRE_DIV_SHIFT) /* 0x00000300 */
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#define CRU_CLKSEL_CON06_CLK_GPU_PRE_MUX_SEL_SHIFT (11U)
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#define CRU_CLKSEL_CON06_CLK_GPU_PRE_MUX_SEL_MASK (0x1U << CRU_CLKSEL_CON06_CLK_GPU_PRE_MUX_SEL_SHIFT) /* 0x00000800 */
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#define CRU_CLKSEL_CON06_PCLK_GPU_PRE_DIV_SHIFT (12U)
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#define CRU_CLKSEL_CON06_PCLK_GPU_PRE_DIV_MASK (0xFU << CRU_CLKSEL_CON06_PCLK_GPU_PRE_DIV_SHIFT) /* 0x0000F000 */
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/* CLKSEL_CON07 */
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#define CRU_CLKSEL_CON07_OFFSET (0x11CU)
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#define CRU_CLKSEL_CON07_CLK_NPU_SRC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON07_CLK_NPU_SRC_DIV_MASK (0xFU << CRU_CLKSEL_CON07_CLK_NPU_SRC_DIV_SHIFT) /* 0x0000000F */
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#define CRU_CLKSEL_CON07_CLK_NPU_NP5_DIV_SHIFT (4U)
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#define CRU_CLKSEL_CON07_CLK_NPU_NP5_DIV_MASK (0x3U << CRU_CLKSEL_CON07_CLK_NPU_NP5_DIV_SHIFT) /* 0x00000030 */
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#define CRU_CLKSEL_CON07_CLK_NPU_SRC_SEL_SHIFT (6U)
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#define CRU_CLKSEL_CON07_CLK_NPU_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON07_CLK_NPU_SRC_SEL_SHIFT) /* 0x00000040 */
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#define CRU_CLKSEL_CON07_CLK_NPU_NP5_SEL_SHIFT (7U)
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#define CRU_CLKSEL_CON07_CLK_NPU_NP5_SEL_MASK (0x1U << CRU_CLKSEL_CON07_CLK_NPU_NP5_SEL_SHIFT) /* 0x00000080 */
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#define CRU_CLKSEL_CON07_CLK_NPU_PRE_NDFT_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON07_CLK_NPU_PRE_NDFT_SEL_MASK (0x1U << CRU_CLKSEL_CON07_CLK_NPU_PRE_NDFT_SEL_SHIFT) /* 0x00000100 */
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#define CRU_CLKSEL_CON07_CLK_NPU_PRE_MUX_SEL_SHIFT (15U)
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#define CRU_CLKSEL_CON07_CLK_NPU_PRE_MUX_SEL_MASK (0x1U << CRU_CLKSEL_CON07_CLK_NPU_PRE_MUX_SEL_SHIFT) /* 0x00008000 */
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/* CLKSEL_CON08 */
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#define CRU_CLKSEL_CON08_OFFSET (0x120U)
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#define CRU_CLKSEL_CON08_HCLK_NPU_PRE_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON08_HCLK_NPU_PRE_DIV_MASK (0xFU << CRU_CLKSEL_CON08_HCLK_NPU_PRE_DIV_SHIFT) /* 0x0000000F */
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#define CRU_CLKSEL_CON08_PCLK_NPU_PRE_DIV_SHIFT (4U)
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#define CRU_CLKSEL_CON08_PCLK_NPU_PRE_DIV_MASK (0xFU << CRU_CLKSEL_CON08_PCLK_NPU_PRE_DIV_SHIFT) /* 0x000000F0 */
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/* CLKSEL_CON09 */
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#define CRU_CLKSEL_CON09_OFFSET (0x124U)
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#define CRU_CLKSEL_CON09_CLK_DDRPHY1X_SRC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON09_CLK_DDRPHY1X_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON09_CLK_DDRPHY1X_SRC_DIV_SHIFT) /* 0x0000001F */
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#define CRU_CLKSEL_CON09_CLK_DDRPHY1X_SRC_SEL_SHIFT (6U)
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#define CRU_CLKSEL_CON09_CLK_DDRPHY1X_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON09_CLK_DDRPHY1X_SRC_SEL_SHIFT) /* 0x000000C0 */
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#define CRU_CLKSEL_CON09_CLK_DDRPHY1X_SEL_SHIFT (15U)
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#define CRU_CLKSEL_CON09_CLK_DDRPHY1X_SEL_MASK (0x1U << CRU_CLKSEL_CON09_CLK_DDRPHY1X_SEL_SHIFT) /* 0x00008000 */
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/* CLKSEL_CON10 */
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#define CRU_CLKSEL_CON10_OFFSET (0x128U)
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#define CRU_CLKSEL_CON10_CLK_MSCH_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON10_CLK_MSCH_DIV_MASK (0x3U << CRU_CLKSEL_CON10_CLK_MSCH_DIV_SHIFT) /* 0x00000003 */
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#define CRU_CLKSEL_CON10_ACLK_PERIMID_SEL_SHIFT (4U)
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#define CRU_CLKSEL_CON10_ACLK_PERIMID_SEL_MASK (0x3U << CRU_CLKSEL_CON10_ACLK_PERIMID_SEL_SHIFT) /* 0x00000030 */
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#define CRU_CLKSEL_CON10_HCLK_PERIMID_SEL_SHIFT (6U)
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#define CRU_CLKSEL_CON10_HCLK_PERIMID_SEL_MASK (0x3U << CRU_CLKSEL_CON10_HCLK_PERIMID_SEL_SHIFT) /* 0x000000C0 */
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#define CRU_CLKSEL_CON10_ACLK_GIC_AUDIO_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON10_ACLK_GIC_AUDIO_SEL_MASK (0x3U << CRU_CLKSEL_CON10_ACLK_GIC_AUDIO_SEL_SHIFT) /* 0x00000300 */
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#define CRU_CLKSEL_CON10_HCLK_GIC_AUDIO_SEL_SHIFT (10U)
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#define CRU_CLKSEL_CON10_HCLK_GIC_AUDIO_SEL_MASK (0x3U << CRU_CLKSEL_CON10_HCLK_GIC_AUDIO_SEL_SHIFT) /* 0x00000C00 */
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#define CRU_CLKSEL_CON10_DCLK_SDMMC_BUFFER_SEL_SHIFT (12U)
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#define CRU_CLKSEL_CON10_DCLK_SDMMC_BUFFER_SEL_MASK (0x3U << CRU_CLKSEL_CON10_DCLK_SDMMC_BUFFER_SEL_SHIFT) /* 0x00003000 */
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/* CLKSEL_CON11 */
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#define CRU_CLKSEL_CON11_OFFSET (0x12CU)
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#define CRU_CLKSEL_CON11_CLK_I2S0_8CH_TX_SRC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON11_CLK_I2S0_8CH_TX_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON11_CLK_I2S0_8CH_TX_SRC_DIV_SHIFT) /* 0x0000007F */
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#define CRU_CLKSEL_CON11_CLK_I2S0_8CH_TX_SRC_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON11_CLK_I2S0_8CH_TX_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON11_CLK_I2S0_8CH_TX_SRC_SEL_SHIFT) /* 0x00000300 */
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#define CRU_CLKSEL_CON11_MCLK_I2S0_8CH_TX_SEL_SHIFT (10U)
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#define CRU_CLKSEL_CON11_MCLK_I2S0_8CH_TX_SEL_MASK (0x3U << CRU_CLKSEL_CON11_MCLK_I2S0_8CH_TX_SEL_SHIFT) /* 0x00000C00 */
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#define CRU_CLKSEL_CON11_I2S0_MCLKOUT_TX_SEL_SHIFT (15U)
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#define CRU_CLKSEL_CON11_I2S0_MCLKOUT_TX_SEL_MASK (0x1U << CRU_CLKSEL_CON11_I2S0_MCLKOUT_TX_SEL_SHIFT) /* 0x00008000 */
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/* CLKSEL_CON12 */
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#define CRU_CLKSEL_CON12_OFFSET (0x130U)
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#define CRU_CLKSEL_CON12_CLK_I2S0_8CH_TX_FRAC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON12_CLK_I2S0_8CH_TX_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON12_CLK_I2S0_8CH_TX_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */
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/* CLKSEL_CON13 */
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#define CRU_CLKSEL_CON13_OFFSET (0x134U)
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#define CRU_CLKSEL_CON13_CLK_I2S0_8CH_RX_SRC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON13_CLK_I2S0_8CH_RX_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON13_CLK_I2S0_8CH_RX_SRC_DIV_SHIFT) /* 0x0000007F */
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#define CRU_CLKSEL_CON13_CLK_I2S0_8CH_RX_SRC_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON13_CLK_I2S0_8CH_RX_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON13_CLK_I2S0_8CH_RX_SRC_SEL_SHIFT) /* 0x00000300 */
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#define CRU_CLKSEL_CON13_MCLK_I2S0_8CH_RX_SEL_SHIFT (10U)
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#define CRU_CLKSEL_CON13_MCLK_I2S0_8CH_RX_SEL_MASK (0x3U << CRU_CLKSEL_CON13_MCLK_I2S0_8CH_RX_SEL_SHIFT) /* 0x00000C00 */
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#define CRU_CLKSEL_CON13_I2S0_MCLKOUT_RX_SEL_SHIFT (15U)
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#define CRU_CLKSEL_CON13_I2S0_MCLKOUT_RX_SEL_MASK (0x1U << CRU_CLKSEL_CON13_I2S0_MCLKOUT_RX_SEL_SHIFT) /* 0x00008000 */
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/* CLKSEL_CON14 */
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#define CRU_CLKSEL_CON14_OFFSET (0x138U)
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#define CRU_CLKSEL_CON14_CLK_I2S0_8CH_RX_FRAC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON14_CLK_I2S0_8CH_RX_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON14_CLK_I2S0_8CH_RX_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */
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/* CLKSEL_CON15 */
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#define CRU_CLKSEL_CON15_OFFSET (0x13CU)
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#define CRU_CLKSEL_CON15_CLK_I2S1_8CH_TX_SRC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON15_CLK_I2S1_8CH_TX_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON15_CLK_I2S1_8CH_TX_SRC_DIV_SHIFT) /* 0x0000007F */
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#define CRU_CLKSEL_CON15_CLK_I2S1_8CH_TX_SRC_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON15_CLK_I2S1_8CH_TX_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON15_CLK_I2S1_8CH_TX_SRC_SEL_SHIFT) /* 0x00000300 */
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#define CRU_CLKSEL_CON15_MCLK_I2S1_8CH_TX_SEL_SHIFT (10U)
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#define CRU_CLKSEL_CON15_MCLK_I2S1_8CH_TX_SEL_MASK (0x3U << CRU_CLKSEL_CON15_MCLK_I2S1_8CH_TX_SEL_SHIFT) /* 0x00000C00 */
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#define CRU_CLKSEL_CON15_I2S1_MCLKOUT_TX_SEL_SHIFT (15U)
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#define CRU_CLKSEL_CON15_I2S1_MCLKOUT_TX_SEL_MASK (0x1U << CRU_CLKSEL_CON15_I2S1_MCLKOUT_TX_SEL_SHIFT) /* 0x00008000 */
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/* CLKSEL_CON16 */
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#define CRU_CLKSEL_CON16_OFFSET (0x140U)
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#define CRU_CLKSEL_CON16_CLK_I2S1_8CH_TX_FRAC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON16_CLK_I2S1_8CH_TX_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON16_CLK_I2S1_8CH_TX_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */
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/* CLKSEL_CON17 */
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#define CRU_CLKSEL_CON17_OFFSET (0x144U)
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#define CRU_CLKSEL_CON17_CLK_I2S1_8CH_RX_SRC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON17_CLK_I2S1_8CH_RX_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON17_CLK_I2S1_8CH_RX_SRC_DIV_SHIFT) /* 0x0000007F */
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#define CRU_CLKSEL_CON17_CLK_I2S1_8CH_RX_SRC_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON17_CLK_I2S1_8CH_RX_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON17_CLK_I2S1_8CH_RX_SRC_SEL_SHIFT) /* 0x00000300 */
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#define CRU_CLKSEL_CON17_MCLK_I2S1_8CH_RX_SEL_SHIFT (10U)
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#define CRU_CLKSEL_CON17_MCLK_I2S1_8CH_RX_SEL_MASK (0x3U << CRU_CLKSEL_CON17_MCLK_I2S1_8CH_RX_SEL_SHIFT) /* 0x00000C00 */
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#define CRU_CLKSEL_CON17_I2S1_MCLKOUT_RX_SEL_SHIFT (15U)
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#define CRU_CLKSEL_CON17_I2S1_MCLKOUT_RX_SEL_MASK (0x1U << CRU_CLKSEL_CON17_I2S1_MCLKOUT_RX_SEL_SHIFT) /* 0x00008000 */
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/* CLKSEL_CON18 */
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#define CRU_CLKSEL_CON18_OFFSET (0x148U)
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#define CRU_CLKSEL_CON18_CLK_I2S1_8CH_RX_FRAC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON18_CLK_I2S1_8CH_RX_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON18_CLK_I2S1_8CH_RX_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */
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/* CLKSEL_CON19 */
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#define CRU_CLKSEL_CON19_OFFSET (0x14CU)
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#define CRU_CLKSEL_CON19_CLK_I2S2_2CH_SRC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON19_CLK_I2S2_2CH_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON19_CLK_I2S2_2CH_SRC_DIV_SHIFT) /* 0x0000007F */
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#define CRU_CLKSEL_CON19_CLK_I2S2_2CH_SRC_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON19_CLK_I2S2_2CH_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON19_CLK_I2S2_2CH_SRC_SEL_SHIFT) /* 0x00000300 */
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#define CRU_CLKSEL_CON19_MCLK_I2S2_2CH_SEL_SHIFT (10U)
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#define CRU_CLKSEL_CON19_MCLK_I2S2_2CH_SEL_MASK (0x3U << CRU_CLKSEL_CON19_MCLK_I2S2_2CH_SEL_SHIFT) /* 0x00000C00 */
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#define CRU_CLKSEL_CON19_I2S2_MCLKOUT_SEL_SHIFT (15U)
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#define CRU_CLKSEL_CON19_I2S2_MCLKOUT_SEL_MASK (0x1U << CRU_CLKSEL_CON19_I2S2_MCLKOUT_SEL_SHIFT) /* 0x00008000 */
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/* CLKSEL_CON20 */
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#define CRU_CLKSEL_CON20_OFFSET (0x150U)
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#define CRU_CLKSEL_CON20_CLK_I2S2_2CH_FRAC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON20_CLK_I2S2_2CH_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON20_CLK_I2S2_2CH_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */
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/* CLKSEL_CON21 */
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#define CRU_CLKSEL_CON21_OFFSET (0x154U)
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#define CRU_CLKSEL_CON21_CLK_I2S3_2CH_TX_SRC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON21_CLK_I2S3_2CH_TX_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON21_CLK_I2S3_2CH_TX_SRC_DIV_SHIFT) /* 0x0000007F */
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#define CRU_CLKSEL_CON21_CLK_I2S3_2CH_TX_SRC_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON21_CLK_I2S3_2CH_TX_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON21_CLK_I2S3_2CH_TX_SRC_SEL_SHIFT) /* 0x00000300 */
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#define CRU_CLKSEL_CON21_MCLK_I2S3_2CH_TX_SEL_SHIFT (10U)
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#define CRU_CLKSEL_CON21_MCLK_I2S3_2CH_TX_SEL_MASK (0x3U << CRU_CLKSEL_CON21_MCLK_I2S3_2CH_TX_SEL_SHIFT) /* 0x00000C00 */
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#define CRU_CLKSEL_CON21_I2S3_MCLKOUT_TX_SEL_SHIFT (15U)
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#define CRU_CLKSEL_CON21_I2S3_MCLKOUT_TX_SEL_MASK (0x1U << CRU_CLKSEL_CON21_I2S3_MCLKOUT_TX_SEL_SHIFT) /* 0x00008000 */
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/* CLKSEL_CON22 */
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#define CRU_CLKSEL_CON22_OFFSET (0x158U)
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#define CRU_CLKSEL_CON22_CLK_I2S3_2CH_TX_FRAC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON22_CLK_I2S3_2CH_TX_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON22_CLK_I2S3_2CH_TX_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */
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/* CLKSEL_CON23 */
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#define CRU_CLKSEL_CON23_OFFSET (0x15CU)
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#define CRU_CLKSEL_CON23_MCLK_SPDIF_8CH_SRC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON23_MCLK_SPDIF_8CH_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON23_MCLK_SPDIF_8CH_SRC_DIV_SHIFT) /* 0x0000007F */
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#define CRU_CLKSEL_CON23_MCLK_PDM_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON23_MCLK_PDM_SEL_MASK (0x3U << CRU_CLKSEL_CON23_MCLK_PDM_SEL_SHIFT) /* 0x00000300 */
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#define CRU_CLKSEL_CON23_CLK_ACDCDIG_I2C_SEL_SHIFT (10U)
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#define CRU_CLKSEL_CON23_CLK_ACDCDIG_I2C_SEL_MASK (0x3U << CRU_CLKSEL_CON23_CLK_ACDCDIG_I2C_SEL_SHIFT) /* 0x00000C00 */
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#define CRU_CLKSEL_CON23_MCLK_SPDIF_8CH_SRC_SEL_SHIFT (14U)
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#define CRU_CLKSEL_CON23_MCLK_SPDIF_8CH_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON23_MCLK_SPDIF_8CH_SRC_SEL_SHIFT) /* 0x00004000 */
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#define CRU_CLKSEL_CON23_MCLK_SPDIF_8CH_SEL_SHIFT (15U)
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#define CRU_CLKSEL_CON23_MCLK_SPDIF_8CH_SEL_MASK (0x1U << CRU_CLKSEL_CON23_MCLK_SPDIF_8CH_SEL_SHIFT) /* 0x00008000 */
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/* CLKSEL_CON24 */
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#define CRU_CLKSEL_CON24_OFFSET (0x160U)
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#define CRU_CLKSEL_CON24_MCLK_SPDIF_8CH_FRAC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON24_MCLK_SPDIF_8CH_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON24_MCLK_SPDIF_8CH_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */
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/* CLKSEL_CON25 */
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#define CRU_CLKSEL_CON25_OFFSET (0x164U)
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#define CRU_CLKSEL_CON25_SCLK_AUDPWM_SRC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON25_SCLK_AUDPWM_SRC_DIV_MASK (0x3FU << CRU_CLKSEL_CON25_SCLK_AUDPWM_SRC_DIV_SHIFT) /* 0x0000003F */
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#define CRU_CLKSEL_CON25_SCLK_AUDPWM_SRC_SEL_SHIFT (14U)
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#define CRU_CLKSEL_CON25_SCLK_AUDPWM_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON25_SCLK_AUDPWM_SRC_SEL_SHIFT) /* 0x00004000 */
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#define CRU_CLKSEL_CON25_SCLK_AUDPWM_SEL_SHIFT (15U)
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#define CRU_CLKSEL_CON25_SCLK_AUDPWM_SEL_MASK (0x1U << CRU_CLKSEL_CON25_SCLK_AUDPWM_SEL_SHIFT) /* 0x00008000 */
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/* CLKSEL_CON26 */
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#define CRU_CLKSEL_CON26_OFFSET (0x168U)
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#define CRU_CLKSEL_CON26_SCLK_AUDPWM_FRAC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON26_SCLK_AUDPWM_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON26_SCLK_AUDPWM_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */
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/* CLKSEL_CON27 */
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#define CRU_CLKSEL_CON27_OFFSET (0x16CU)
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#define CRU_CLKSEL_CON27_ACLK_SECURE_FLASH_SEL_SHIFT (0U)
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#define CRU_CLKSEL_CON27_ACLK_SECURE_FLASH_SEL_MASK (0x3U << CRU_CLKSEL_CON27_ACLK_SECURE_FLASH_SEL_SHIFT) /* 0x00000003 */
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#define CRU_CLKSEL_CON27_HCLK_SECURE_FLASH_SEL_SHIFT (2U)
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#define CRU_CLKSEL_CON27_HCLK_SECURE_FLASH_SEL_MASK (0x3U << CRU_CLKSEL_CON27_HCLK_SECURE_FLASH_SEL_SHIFT) /* 0x0000000C */
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#define CRU_CLKSEL_CON27_CLK_CRYPTO_NS_CORE_SEL_SHIFT (4U)
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#define CRU_CLKSEL_CON27_CLK_CRYPTO_NS_CORE_SEL_MASK (0x3U << CRU_CLKSEL_CON27_CLK_CRYPTO_NS_CORE_SEL_SHIFT) /* 0x00000030 */
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#define CRU_CLKSEL_CON27_CLK_CRYPTO_NS_PKA_SEL_SHIFT (6U)
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#define CRU_CLKSEL_CON27_CLK_CRYPTO_NS_PKA_SEL_MASK (0x3U << CRU_CLKSEL_CON27_CLK_CRYPTO_NS_PKA_SEL_SHIFT) /* 0x000000C0 */
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/* CLKSEL_CON28 */
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#define CRU_CLKSEL_CON28_OFFSET (0x170U)
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#define CRU_CLKSEL_CON28_NCLK_NANDC_SEL_SHIFT (0U)
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#define CRU_CLKSEL_CON28_NCLK_NANDC_SEL_MASK (0x3U << CRU_CLKSEL_CON28_NCLK_NANDC_SEL_SHIFT) /* 0x00000003 */
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#define CRU_CLKSEL_CON28_SCLK_SFC_SEL_SHIFT (4U)
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#define CRU_CLKSEL_CON28_SCLK_SFC_SEL_MASK (0x7U << CRU_CLKSEL_CON28_SCLK_SFC_SEL_SHIFT) /* 0x00000070 */
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#define CRU_CLKSEL_CON28_BCLK_EMMC_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON28_BCLK_EMMC_SEL_MASK (0x3U << CRU_CLKSEL_CON28_BCLK_EMMC_SEL_SHIFT) /* 0x00000300 */
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#define CRU_CLKSEL_CON28_CCLK_EMMC_SEL_SHIFT (12U)
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#define CRU_CLKSEL_CON28_CCLK_EMMC_SEL_MASK (0x7U << CRU_CLKSEL_CON28_CCLK_EMMC_SEL_SHIFT) /* 0x00007000 */
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/* CLKSEL_CON29 */
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#define CRU_CLKSEL_CON29_OFFSET (0x174U)
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#define CRU_CLKSEL_CON29_ACLK_PIPE_SEL_SHIFT (0U)
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#define CRU_CLKSEL_CON29_ACLK_PIPE_SEL_MASK (0x3U << CRU_CLKSEL_CON29_ACLK_PIPE_SEL_SHIFT) /* 0x00000003 */
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#define CRU_CLKSEL_CON29_PCLK_PIPE_DIV_SHIFT (4U)
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#define CRU_CLKSEL_CON29_PCLK_PIPE_DIV_MASK (0xFU << CRU_CLKSEL_CON29_PCLK_PIPE_DIV_SHIFT) /* 0x000000F0 */
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#define CRU_CLKSEL_CON29_CLK_USB3OTG0_SUSPEND_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON29_CLK_USB3OTG0_SUSPEND_SEL_MASK (0x1U << CRU_CLKSEL_CON29_CLK_USB3OTG0_SUSPEND_SEL_SHIFT) /* 0x00000100 */
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#define CRU_CLKSEL_CON29_CLK_USB3OTG1_SUSPEND_SEL_SHIFT (9U)
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#define CRU_CLKSEL_CON29_CLK_USB3OTG1_SUSPEND_SEL_MASK (0x1U << CRU_CLKSEL_CON29_CLK_USB3OTG1_SUSPEND_SEL_SHIFT) /* 0x00000200 */
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#define CRU_CLKSEL_CON29_CLK_XPCS_EEE_SEL_SHIFT (13U)
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#define CRU_CLKSEL_CON29_CLK_XPCS_EEE_SEL_MASK (0x1U << CRU_CLKSEL_CON29_CLK_XPCS_EEE_SEL_SHIFT) /* 0x00002000 */
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/* CLKSEL_CON30 */
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#define CRU_CLKSEL_CON30_OFFSET (0x178U)
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#define CRU_CLKSEL_CON30_ACLK_PHP_SEL_SHIFT (0U)
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#define CRU_CLKSEL_CON30_ACLK_PHP_SEL_MASK (0x3U << CRU_CLKSEL_CON30_ACLK_PHP_SEL_SHIFT) /* 0x00000003 */
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#define CRU_CLKSEL_CON30_HCLK_PHP_SEL_SHIFT (2U)
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#define CRU_CLKSEL_CON30_HCLK_PHP_SEL_MASK (0x3U << CRU_CLKSEL_CON30_HCLK_PHP_SEL_SHIFT) /* 0x0000000C */
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#define CRU_CLKSEL_CON30_PCLK_PHP_DIV_SHIFT (4U)
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#define CRU_CLKSEL_CON30_PCLK_PHP_DIV_MASK (0xFU << CRU_CLKSEL_CON30_PCLK_PHP_DIV_SHIFT) /* 0x000000F0 */
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#define CRU_CLKSEL_CON30_CLK_SDMMC0_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON30_CLK_SDMMC0_SEL_MASK (0x7U << CRU_CLKSEL_CON30_CLK_SDMMC0_SEL_SHIFT) /* 0x00000700 */
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#define CRU_CLKSEL_CON30_CLK_SDMMC1_SEL_SHIFT (12U)
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#define CRU_CLKSEL_CON30_CLK_SDMMC1_SEL_MASK (0x7U << CRU_CLKSEL_CON30_CLK_SDMMC1_SEL_SHIFT) /* 0x00007000 */
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/* CLKSEL_CON31 */
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#define CRU_CLKSEL_CON31_OFFSET (0x17CU)
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#define CRU_CLKSEL_CON31_RMII0_MODE_SHIFT (0U)
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#define CRU_CLKSEL_CON31_RMII0_MODE_MASK (0x3U << CRU_CLKSEL_CON31_RMII0_MODE_SHIFT) /* 0x00000003 */
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#define CRU_CLKSEL_CON31_RMII0_EXTCLK_SEL_SHIFT (2U)
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#define CRU_CLKSEL_CON31_RMII0_EXTCLK_SEL_MASK (0x1U << CRU_CLKSEL_CON31_RMII0_EXTCLK_SEL_SHIFT) /* 0x00000004 */
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#define CRU_CLKSEL_CON31_RMII0_CLK_SEL_SHIFT (3U)
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#define CRU_CLKSEL_CON31_RMII0_CLK_SEL_MASK (0x1U << CRU_CLKSEL_CON31_RMII0_CLK_SEL_SHIFT) /* 0x00000008 */
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#define CRU_CLKSEL_CON31_RGMII0_CLK_SEL_SHIFT (4U)
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#define CRU_CLKSEL_CON31_RGMII0_CLK_SEL_MASK (0x3U << CRU_CLKSEL_CON31_RGMII0_CLK_SEL_SHIFT) /* 0x00000030 */
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#define CRU_CLKSEL_CON31_CLK_MAC0_2TOP_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON31_CLK_MAC0_2TOP_SEL_MASK (0x3U << CRU_CLKSEL_CON31_CLK_MAC0_2TOP_SEL_SHIFT) /* 0x00000300 */
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#define CRU_CLKSEL_CON31_CLK_GMAC0_PTP_REF_SEL_SHIFT (12U)
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#define CRU_CLKSEL_CON31_CLK_GMAC0_PTP_REF_SEL_MASK (0x3U << CRU_CLKSEL_CON31_CLK_GMAC0_PTP_REF_SEL_SHIFT) /* 0x00003000 */
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#define CRU_CLKSEL_CON31_CLK_MAC0_OUT_SEL_SHIFT (14U)
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#define CRU_CLKSEL_CON31_CLK_MAC0_OUT_SEL_MASK (0x3U << CRU_CLKSEL_CON31_CLK_MAC0_OUT_SEL_SHIFT) /* 0x0000C000 */
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/* CLKSEL_CON32 */
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#define CRU_CLKSEL_CON32_OFFSET (0x180U)
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#define CRU_CLKSEL_CON32_ACLK_USB_SEL_SHIFT (0U)
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#define CRU_CLKSEL_CON32_ACLK_USB_SEL_MASK (0x3U << CRU_CLKSEL_CON32_ACLK_USB_SEL_SHIFT) /* 0x00000003 */
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#define CRU_CLKSEL_CON32_HCLK_USB_SEL_SHIFT (2U)
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#define CRU_CLKSEL_CON32_HCLK_USB_SEL_MASK (0x3U << CRU_CLKSEL_CON32_HCLK_USB_SEL_SHIFT) /* 0x0000000C */
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#define CRU_CLKSEL_CON32_PCLK_USB_DIV_SHIFT (4U)
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#define CRU_CLKSEL_CON32_PCLK_USB_DIV_MASK (0xFU << CRU_CLKSEL_CON32_PCLK_USB_DIV_SHIFT) /* 0x000000F0 */
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#define CRU_CLKSEL_CON32_CLK_SDMMC2_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON32_CLK_SDMMC2_SEL_MASK (0x7U << CRU_CLKSEL_CON32_CLK_SDMMC2_SEL_SHIFT) /* 0x00000700 */
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/* CLKSEL_CON33 */
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#define CRU_CLKSEL_CON33_OFFSET (0x184U)
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#define CRU_CLKSEL_CON33_RMII1_MODE_SHIFT (0U)
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#define CRU_CLKSEL_CON33_RMII1_MODE_MASK (0x3U << CRU_CLKSEL_CON33_RMII1_MODE_SHIFT) /* 0x00000003 */
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#define CRU_CLKSEL_CON33_RMII1_EXTCLK_SEL_SHIFT (2U)
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#define CRU_CLKSEL_CON33_RMII1_EXTCLK_SEL_MASK (0x1U << CRU_CLKSEL_CON33_RMII1_EXTCLK_SEL_SHIFT) /* 0x00000004 */
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#define CRU_CLKSEL_CON33_RMII1_CLK_SEL_SHIFT (3U)
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#define CRU_CLKSEL_CON33_RMII1_CLK_SEL_MASK (0x1U << CRU_CLKSEL_CON33_RMII1_CLK_SEL_SHIFT) /* 0x00000008 */
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#define CRU_CLKSEL_CON33_RGMII1_CLK_SEL_SHIFT (4U)
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#define CRU_CLKSEL_CON33_RGMII1_CLK_SEL_MASK (0x3U << CRU_CLKSEL_CON33_RGMII1_CLK_SEL_SHIFT) /* 0x00000030 */
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#define CRU_CLKSEL_CON33_CLK_MAC1_2TOP_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON33_CLK_MAC1_2TOP_SEL_MASK (0x3U << CRU_CLKSEL_CON33_CLK_MAC1_2TOP_SEL_SHIFT) /* 0x00000300 */
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#define CRU_CLKSEL_CON33_CLK_GMAC1_PTP_REF_SEL_SHIFT (12U)
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#define CRU_CLKSEL_CON33_CLK_GMAC1_PTP_REF_SEL_MASK (0x3U << CRU_CLKSEL_CON33_CLK_GMAC1_PTP_REF_SEL_SHIFT) /* 0x00003000 */
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#define CRU_CLKSEL_CON33_CLK_MAC1_OUT_SEL_SHIFT (14U)
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#define CRU_CLKSEL_CON33_CLK_MAC1_OUT_SEL_MASK (0x3U << CRU_CLKSEL_CON33_CLK_MAC1_OUT_SEL_SHIFT) /* 0x0000C000 */
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/* CLKSEL_CON34 */
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#define CRU_CLKSEL_CON34_OFFSET (0x188U)
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#define CRU_CLKSEL_CON34_ACLK_VI_SEL_SHIFT (0U)
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#define CRU_CLKSEL_CON34_ACLK_VI_SEL_MASK (0x3U << CRU_CLKSEL_CON34_ACLK_VI_SEL_SHIFT) /* 0x00000003 */
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#define CRU_CLKSEL_CON34_HCLK_VI_DIV_SHIFT (4U)
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#define CRU_CLKSEL_CON34_HCLK_VI_DIV_MASK (0xFU << CRU_CLKSEL_CON34_HCLK_VI_DIV_SHIFT) /* 0x000000F0 */
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#define CRU_CLKSEL_CON34_PCLK_VI_DIV_SHIFT (8U)
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#define CRU_CLKSEL_CON34_PCLK_VI_DIV_MASK (0xFU << CRU_CLKSEL_CON34_PCLK_VI_DIV_SHIFT) /* 0x00000F00 */
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#define CRU_CLKSEL_CON34_DCLK_VICAP1_SEL_SHIFT (14U)
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#define CRU_CLKSEL_CON34_DCLK_VICAP1_SEL_MASK (0x3U << CRU_CLKSEL_CON34_DCLK_VICAP1_SEL_SHIFT) /* 0x0000C000 */
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/* CLKSEL_CON35 */
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#define CRU_CLKSEL_CON35_OFFSET (0x18CU)
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#define CRU_CLKSEL_CON35_CLK_ISP_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON35_CLK_ISP_DIV_MASK (0x1FU << CRU_CLKSEL_CON35_CLK_ISP_DIV_SHIFT) /* 0x0000001F */
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#define CRU_CLKSEL_CON35_CLK_ISP_SEL_SHIFT (6U)
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#define CRU_CLKSEL_CON35_CLK_ISP_SEL_MASK (0x3U << CRU_CLKSEL_CON35_CLK_ISP_SEL_SHIFT) /* 0x000000C0 */
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#define CRU_CLKSEL_CON35_CLK_CIF_OUT_DIV_SHIFT (8U)
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#define CRU_CLKSEL_CON35_CLK_CIF_OUT_DIV_MASK (0x3FU << CRU_CLKSEL_CON35_CLK_CIF_OUT_DIV_SHIFT) /* 0x00003F00 */
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#define CRU_CLKSEL_CON35_CLK_CIF_OUT_SEL_SHIFT (14U)
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#define CRU_CLKSEL_CON35_CLK_CIF_OUT_SEL_MASK (0x3U << CRU_CLKSEL_CON35_CLK_CIF_OUT_SEL_SHIFT) /* 0x0000C000 */
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/* CLKSEL_CON36 */
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#define CRU_CLKSEL_CON36_OFFSET (0x190U)
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#define CRU_CLKSEL_CON36_CLK_CAM0_OUT_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON36_CLK_CAM0_OUT_DIV_MASK (0x3FU << CRU_CLKSEL_CON36_CLK_CAM0_OUT_DIV_SHIFT) /* 0x0000003F */
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#define CRU_CLKSEL_CON36_CLK_CAM0_OUT_SEL_SHIFT (6U)
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#define CRU_CLKSEL_CON36_CLK_CAM0_OUT_SEL_MASK (0x3U << CRU_CLKSEL_CON36_CLK_CAM0_OUT_SEL_SHIFT) /* 0x000000C0 */
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#define CRU_CLKSEL_CON36_CLK_CAM1_OUT_DIV_SHIFT (8U)
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#define CRU_CLKSEL_CON36_CLK_CAM1_OUT_DIV_MASK (0x3FU << CRU_CLKSEL_CON36_CLK_CAM1_OUT_DIV_SHIFT) /* 0x00003F00 */
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#define CRU_CLKSEL_CON36_CLK_CAM1_OUT_SEL_SHIFT (14U)
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#define CRU_CLKSEL_CON36_CLK_CAM1_OUT_SEL_MASK (0x3U << CRU_CLKSEL_CON36_CLK_CAM1_OUT_SEL_SHIFT) /* 0x0000C000 */
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/* CLKSEL_CON37 */
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#define CRU_CLKSEL_CON37_OFFSET (0x194U)
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#define CRU_CLKSEL_CON37_ACLK_VO_SEL_SHIFT (0U)
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#define CRU_CLKSEL_CON37_ACLK_VO_SEL_MASK (0x3U << CRU_CLKSEL_CON37_ACLK_VO_SEL_SHIFT) /* 0x00000003 */
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#define CRU_CLKSEL_CON37_HCLK_VO_DIV_SHIFT (8U)
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#define CRU_CLKSEL_CON37_HCLK_VO_DIV_MASK (0xFU << CRU_CLKSEL_CON37_HCLK_VO_DIV_SHIFT) /* 0x00000F00 */
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#define CRU_CLKSEL_CON37_PCLK_VO_DIV_SHIFT (12U)
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#define CRU_CLKSEL_CON37_PCLK_VO_DIV_MASK (0xFU << CRU_CLKSEL_CON37_PCLK_VO_DIV_SHIFT) /* 0x0000F000 */
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/* CLKSEL_CON38 */
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#define CRU_CLKSEL_CON38_OFFSET (0x198U)
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#define CRU_CLKSEL_CON38_ACLK_VOP_PRE_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON38_ACLK_VOP_PRE_DIV_MASK (0x1FU << CRU_CLKSEL_CON38_ACLK_VOP_PRE_DIV_SHIFT) /* 0x0000001F */
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#define CRU_CLKSEL_CON38_ACLK_VOP_PRE_SEL_SHIFT (6U)
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#define CRU_CLKSEL_CON38_ACLK_VOP_PRE_SEL_MASK (0x3U << CRU_CLKSEL_CON38_ACLK_VOP_PRE_SEL_SHIFT) /* 0x000000C0 */
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#define CRU_CLKSEL_CON38_CLK_EDP_200M_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON38_CLK_EDP_200M_SEL_MASK (0x3U << CRU_CLKSEL_CON38_CLK_EDP_200M_SEL_SHIFT) /* 0x00000300 */
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/* CLKSEL_CON39 */
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#define CRU_CLKSEL_CON39_OFFSET (0x19CU)
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#define CRU_CLKSEL_CON39_DCLK0_VOP_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON39_DCLK0_VOP_DIV_MASK (0xFFU << CRU_CLKSEL_CON39_DCLK0_VOP_DIV_SHIFT) /* 0x000000FF */
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#define CRU_CLKSEL_CON39_DCLK0_VOP_SEL_SHIFT (10U)
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#define CRU_CLKSEL_CON39_DCLK0_VOP_SEL_MASK (0x3U << CRU_CLKSEL_CON39_DCLK0_VOP_SEL_SHIFT) /* 0x00000C00 */
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/* CLKSEL_CON40 */
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#define CRU_CLKSEL_CON40_OFFSET (0x1A0U)
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#define CRU_CLKSEL_CON40_DCLK1_VOP_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON40_DCLK1_VOP_DIV_MASK (0xFFU << CRU_CLKSEL_CON40_DCLK1_VOP_DIV_SHIFT) /* 0x000000FF */
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#define CRU_CLKSEL_CON40_DCLK1_VOP_SEL_SHIFT (10U)
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#define CRU_CLKSEL_CON40_DCLK1_VOP_SEL_MASK (0x3U << CRU_CLKSEL_CON40_DCLK1_VOP_SEL_SHIFT) /* 0x00000C00 */
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/* CLKSEL_CON41 */
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#define CRU_CLKSEL_CON41_OFFSET (0x1A4U)
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#define CRU_CLKSEL_CON41_DCLK2_VOP_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON41_DCLK2_VOP_DIV_MASK (0xFFU << CRU_CLKSEL_CON41_DCLK2_VOP_DIV_SHIFT) /* 0x000000FF */
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#define CRU_CLKSEL_CON41_DCLK2_VOP_SEL_SHIFT (10U)
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#define CRU_CLKSEL_CON41_DCLK2_VOP_SEL_MASK (0x3U << CRU_CLKSEL_CON41_DCLK2_VOP_SEL_SHIFT) /* 0x00000C00 */
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/* CLKSEL_CON42 */
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#define CRU_CLKSEL_CON42_OFFSET (0x1A8U)
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#define CRU_CLKSEL_CON42_ACLK_VPU_PRE_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON42_ACLK_VPU_PRE_DIV_MASK (0x1FU << CRU_CLKSEL_CON42_ACLK_VPU_PRE_DIV_SHIFT) /* 0x0000001F */
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#define CRU_CLKSEL_CON42_ACLK_VPU_PRE_SEL_SHIFT (7U)
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#define CRU_CLKSEL_CON42_ACLK_VPU_PRE_SEL_MASK (0x1U << CRU_CLKSEL_CON42_ACLK_VPU_PRE_SEL_SHIFT) /* 0x00000080 */
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#define CRU_CLKSEL_CON42_HCLK_VPU_PRE_DIV_SHIFT (8U)
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#define CRU_CLKSEL_CON42_HCLK_VPU_PRE_DIV_MASK (0xFU << CRU_CLKSEL_CON42_HCLK_VPU_PRE_DIV_SHIFT) /* 0x00000F00 */
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/* CLKSEL_CON43 */
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#define CRU_CLKSEL_CON43_OFFSET (0x1ACU)
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#define CRU_CLKSEL_CON43_ACLK_RGA_PRE_SEL_SHIFT (0U)
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#define CRU_CLKSEL_CON43_ACLK_RGA_PRE_SEL_MASK (0x3U << CRU_CLKSEL_CON43_ACLK_RGA_PRE_SEL_SHIFT) /* 0x00000003 */
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#define CRU_CLKSEL_CON43_CLK_RGA_CORE_SEL_SHIFT (2U)
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#define CRU_CLKSEL_CON43_CLK_RGA_CORE_SEL_MASK (0x3U << CRU_CLKSEL_CON43_CLK_RGA_CORE_SEL_SHIFT) /* 0x0000000C */
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#define CRU_CLKSEL_CON43_CLK_IEP_CORE_SEL_SHIFT (4U)
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#define CRU_CLKSEL_CON43_CLK_IEP_CORE_SEL_MASK (0x3U << CRU_CLKSEL_CON43_CLK_IEP_CORE_SEL_SHIFT) /* 0x00000030 */
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#define CRU_CLKSEL_CON43_DCLK_EBC_SEL_SHIFT (6U)
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#define CRU_CLKSEL_CON43_DCLK_EBC_SEL_MASK (0x3U << CRU_CLKSEL_CON43_DCLK_EBC_SEL_SHIFT) /* 0x000000C0 */
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#define CRU_CLKSEL_CON43_HCLK_RGA_PRE_DIV_SHIFT (8U)
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#define CRU_CLKSEL_CON43_HCLK_RGA_PRE_DIV_MASK (0xFU << CRU_CLKSEL_CON43_HCLK_RGA_PRE_DIV_SHIFT) /* 0x00000F00 */
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#define CRU_CLKSEL_CON43_PCLK_RGA_PRE_DIV_SHIFT (12U)
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#define CRU_CLKSEL_CON43_PCLK_RGA_PRE_DIV_MASK (0xFU << CRU_CLKSEL_CON43_PCLK_RGA_PRE_DIV_SHIFT) /* 0x0000F000 */
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/* CLKSEL_CON44 */
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#define CRU_CLKSEL_CON44_OFFSET (0x1B0U)
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#define CRU_CLKSEL_CON44_ACLK_RKVENC_PRE_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON44_ACLK_RKVENC_PRE_DIV_MASK (0x1FU << CRU_CLKSEL_CON44_ACLK_RKVENC_PRE_DIV_SHIFT) /* 0x0000001F */
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#define CRU_CLKSEL_CON44_ACLK_RKVENC_PRE_SEL_SHIFT (6U)
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#define CRU_CLKSEL_CON44_ACLK_RKVENC_PRE_SEL_MASK (0x3U << CRU_CLKSEL_CON44_ACLK_RKVENC_PRE_SEL_SHIFT) /* 0x000000C0 */
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#define CRU_CLKSEL_CON44_HCLK_RKVENC_PRE_DIV_SHIFT (8U)
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#define CRU_CLKSEL_CON44_HCLK_RKVENC_PRE_DIV_MASK (0xFU << CRU_CLKSEL_CON44_HCLK_RKVENC_PRE_DIV_SHIFT) /* 0x00000F00 */
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/* CLKSEL_CON45 */
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#define CRU_CLKSEL_CON45_OFFSET (0x1B4U)
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#define CRU_CLKSEL_CON45_CLK_RKVENC_CORE_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON45_CLK_RKVENC_CORE_DIV_MASK (0x1FU << CRU_CLKSEL_CON45_CLK_RKVENC_CORE_DIV_SHIFT) /* 0x0000001F */
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#define CRU_CLKSEL_CON45_CLK_RKVENC_CORE_SEL_SHIFT (14U)
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#define CRU_CLKSEL_CON45_CLK_RKVENC_CORE_SEL_MASK (0x3U << CRU_CLKSEL_CON45_CLK_RKVENC_CORE_SEL_SHIFT) /* 0x0000C000 */
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/* CLKSEL_CON47 */
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#define CRU_CLKSEL_CON47_OFFSET (0x1BCU)
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#define CRU_CLKSEL_CON47_ACLK_RKVDEC_PRE_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON47_ACLK_RKVDEC_PRE_DIV_MASK (0x1FU << CRU_CLKSEL_CON47_ACLK_RKVDEC_PRE_DIV_SHIFT) /* 0x0000001F */
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#define CRU_CLKSEL_CON47_ACLK_RKVDEC_PRE_SEL_SHIFT (7U)
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#define CRU_CLKSEL_CON47_ACLK_RKVDEC_PRE_SEL_MASK (0x1U << CRU_CLKSEL_CON47_ACLK_RKVDEC_PRE_SEL_SHIFT) /* 0x00000080 */
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#define CRU_CLKSEL_CON47_HCLK_RKVDEC_PRE_DIV_SHIFT (8U)
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#define CRU_CLKSEL_CON47_HCLK_RKVDEC_PRE_DIV_MASK (0xFU << CRU_CLKSEL_CON47_HCLK_RKVDEC_PRE_DIV_SHIFT) /* 0x00000F00 */
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/* CLKSEL_CON48 */
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#define CRU_CLKSEL_CON48_OFFSET (0x1C0U)
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#define CRU_CLKSEL_CON48_CLK_RKVDEC_CA_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON48_CLK_RKVDEC_CA_DIV_MASK (0x1FU << CRU_CLKSEL_CON48_CLK_RKVDEC_CA_DIV_SHIFT) /* 0x0000001F */
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#define CRU_CLKSEL_CON48_CLK_RKVDEC_CA_SEL_SHIFT (6U)
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#define CRU_CLKSEL_CON48_CLK_RKVDEC_CA_SEL_MASK (0x3U << CRU_CLKSEL_CON48_CLK_RKVDEC_CA_SEL_SHIFT) /* 0x000000C0 */
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/* CLKSEL_CON49 */
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#define CRU_CLKSEL_CON49_OFFSET (0x1C4U)
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#define CRU_CLKSEL_CON49_CLK_RKVDEC_HEVC_CA_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON49_CLK_RKVDEC_HEVC_CA_DIV_MASK (0x1FU << CRU_CLKSEL_CON49_CLK_RKVDEC_HEVC_CA_DIV_SHIFT) /* 0x0000001F */
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#define CRU_CLKSEL_CON49_CLK_RKVDEC_HEVC_CA_SEL_SHIFT (6U)
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#define CRU_CLKSEL_CON49_CLK_RKVDEC_HEVC_CA_SEL_MASK (0x3U << CRU_CLKSEL_CON49_CLK_RKVDEC_HEVC_CA_SEL_SHIFT) /* 0x000000C0 */
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#define CRU_CLKSEL_CON49_CLK_RKVDEC_CORE_DIV_SHIFT (8U)
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#define CRU_CLKSEL_CON49_CLK_RKVDEC_CORE_DIV_MASK (0x1FU << CRU_CLKSEL_CON49_CLK_RKVDEC_CORE_DIV_SHIFT) /* 0x00001F00 */
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#define CRU_CLKSEL_CON49_CLK_RKVDEC_CORE_SEL_SHIFT (14U)
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#define CRU_CLKSEL_CON49_CLK_RKVDEC_CORE_SEL_MASK (0x3U << CRU_CLKSEL_CON49_CLK_RKVDEC_CORE_SEL_SHIFT) /* 0x0000C000 */
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/* CLKSEL_CON50 */
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#define CRU_CLKSEL_CON50_OFFSET (0x1C8U)
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#define CRU_CLKSEL_CON50_ACLK_BUS_SEL_SHIFT (0U)
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#define CRU_CLKSEL_CON50_ACLK_BUS_SEL_MASK (0x3U << CRU_CLKSEL_CON50_ACLK_BUS_SEL_SHIFT) /* 0x00000003 */
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#define CRU_CLKSEL_CON50_PCLK_BUS_SEL_SHIFT (4U)
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#define CRU_CLKSEL_CON50_PCLK_BUS_SEL_MASK (0x3U << CRU_CLKSEL_CON50_PCLK_BUS_SEL_SHIFT) /* 0x00000030 */
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/* CLKSEL_CON51 */
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#define CRU_CLKSEL_CON51_OFFSET (0x1CCU)
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#define CRU_CLKSEL_CON51_CLK_TSADC_TSEN_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON51_CLK_TSADC_TSEN_DIV_MASK (0x7U << CRU_CLKSEL_CON51_CLK_TSADC_TSEN_DIV_SHIFT) /* 0x00000007 */
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#define CRU_CLKSEL_CON51_CLK_TSADC_TSEN_SEL_SHIFT (4U)
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#define CRU_CLKSEL_CON51_CLK_TSADC_TSEN_SEL_MASK (0x3U << CRU_CLKSEL_CON51_CLK_TSADC_TSEN_SEL_SHIFT) /* 0x00000030 */
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#define CRU_CLKSEL_CON51_CLK_TSADC_DIV_SHIFT (8U)
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#define CRU_CLKSEL_CON51_CLK_TSADC_DIV_MASK (0x7FU << CRU_CLKSEL_CON51_CLK_TSADC_DIV_SHIFT) /* 0x00007F00 */
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/* CLKSEL_CON52 */
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#define CRU_CLKSEL_CON52_OFFSET (0x1D0U)
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#define CRU_CLKSEL_CON52_CLK_UART1_SRC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON52_CLK_UART1_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON52_CLK_UART1_SRC_DIV_SHIFT) /* 0x0000007F */
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#define CRU_CLKSEL_CON52_CLK_UART1_SRC_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON52_CLK_UART1_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON52_CLK_UART1_SRC_SEL_SHIFT) /* 0x00000300 */
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#define CRU_CLKSEL_CON52_SCLK_UART1_SEL_SHIFT (12U)
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#define CRU_CLKSEL_CON52_SCLK_UART1_SEL_MASK (0x3U << CRU_CLKSEL_CON52_SCLK_UART1_SEL_SHIFT) /* 0x00003000 */
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/* CLKSEL_CON53 */
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#define CRU_CLKSEL_CON53_OFFSET (0x1D4U)
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#define CRU_CLKSEL_CON53_CLK_UART1_FRAC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON53_CLK_UART1_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON53_CLK_UART1_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */
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/* CLKSEL_CON54 */
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#define CRU_CLKSEL_CON54_OFFSET (0x1D8U)
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#define CRU_CLKSEL_CON54_CLK_UART2_SRC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON54_CLK_UART2_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON54_CLK_UART2_SRC_DIV_SHIFT) /* 0x0000007F */
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#define CRU_CLKSEL_CON54_CLK_UART2_SRC_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON54_CLK_UART2_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON54_CLK_UART2_SRC_SEL_SHIFT) /* 0x00000300 */
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#define CRU_CLKSEL_CON54_SCLK_UART2_SEL_SHIFT (12U)
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#define CRU_CLKSEL_CON54_SCLK_UART2_SEL_MASK (0x3U << CRU_CLKSEL_CON54_SCLK_UART2_SEL_SHIFT) /* 0x00003000 */
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/* CLKSEL_CON55 */
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#define CRU_CLKSEL_CON55_OFFSET (0x1DCU)
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#define CRU_CLKSEL_CON55_CLK_UART2_FRAC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON55_CLK_UART2_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON55_CLK_UART2_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */
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/* CLKSEL_CON56 */
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#define CRU_CLKSEL_CON56_OFFSET (0x1E0U)
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#define CRU_CLKSEL_CON56_CLK_UART3_SRC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON56_CLK_UART3_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON56_CLK_UART3_SRC_DIV_SHIFT) /* 0x0000007F */
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#define CRU_CLKSEL_CON56_CLK_UART3_SRC_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON56_CLK_UART3_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON56_CLK_UART3_SRC_SEL_SHIFT) /* 0x00000300 */
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#define CRU_CLKSEL_CON56_SCLK_UART3_SEL_SHIFT (12U)
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#define CRU_CLKSEL_CON56_SCLK_UART3_SEL_MASK (0x3U << CRU_CLKSEL_CON56_SCLK_UART3_SEL_SHIFT) /* 0x00003000 */
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/* CLKSEL_CON57 */
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#define CRU_CLKSEL_CON57_OFFSET (0x1E4U)
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#define CRU_CLKSEL_CON57_CLK_UART3_FRAC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON57_CLK_UART3_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON57_CLK_UART3_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */
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/* CLKSEL_CON58 */
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#define CRU_CLKSEL_CON58_OFFSET (0x1E8U)
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#define CRU_CLKSEL_CON58_CLK_UART4_SRC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON58_CLK_UART4_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON58_CLK_UART4_SRC_DIV_SHIFT) /* 0x0000007F */
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#define CRU_CLKSEL_CON58_CLK_UART4_SRC_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON58_CLK_UART4_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON58_CLK_UART4_SRC_SEL_SHIFT) /* 0x00000300 */
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#define CRU_CLKSEL_CON58_SCLK_UART4_SEL_SHIFT (12U)
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#define CRU_CLKSEL_CON58_SCLK_UART4_SEL_MASK (0x3U << CRU_CLKSEL_CON58_SCLK_UART4_SEL_SHIFT) /* 0x00003000 */
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/* CLKSEL_CON59 */
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#define CRU_CLKSEL_CON59_OFFSET (0x1ECU)
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#define CRU_CLKSEL_CON59_CLK_UART4_FRAC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON59_CLK_UART4_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON59_CLK_UART4_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */
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/* CLKSEL_CON60 */
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#define CRU_CLKSEL_CON60_OFFSET (0x1F0U)
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#define CRU_CLKSEL_CON60_CLK_UART5_SRC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON60_CLK_UART5_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON60_CLK_UART5_SRC_DIV_SHIFT) /* 0x0000007F */
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#define CRU_CLKSEL_CON60_CLK_UART5_SRC_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON60_CLK_UART5_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON60_CLK_UART5_SRC_SEL_SHIFT) /* 0x00000300 */
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#define CRU_CLKSEL_CON60_SCLK_UART5_SEL_SHIFT (12U)
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#define CRU_CLKSEL_CON60_SCLK_UART5_SEL_MASK (0x3U << CRU_CLKSEL_CON60_SCLK_UART5_SEL_SHIFT) /* 0x00003000 */
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/* CLKSEL_CON61 */
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#define CRU_CLKSEL_CON61_OFFSET (0x1F4U)
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#define CRU_CLKSEL_CON61_CLK_UART5_FRAC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON61_CLK_UART5_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON61_CLK_UART5_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */
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/* CLKSEL_CON62 */
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#define CRU_CLKSEL_CON62_OFFSET (0x1F8U)
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#define CRU_CLKSEL_CON62_CLK_UART6_SRC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON62_CLK_UART6_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON62_CLK_UART6_SRC_DIV_SHIFT) /* 0x0000007F */
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#define CRU_CLKSEL_CON62_CLK_UART6_SRC_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON62_CLK_UART6_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON62_CLK_UART6_SRC_SEL_SHIFT) /* 0x00000300 */
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#define CRU_CLKSEL_CON62_SCLK_UART6_SEL_SHIFT (12U)
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#define CRU_CLKSEL_CON62_SCLK_UART6_SEL_MASK (0x3U << CRU_CLKSEL_CON62_SCLK_UART6_SEL_SHIFT) /* 0x00003000 */
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/* CLKSEL_CON63 */
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#define CRU_CLKSEL_CON63_OFFSET (0x1FCU)
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#define CRU_CLKSEL_CON63_CLK_UART6_FRAC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON63_CLK_UART6_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON63_CLK_UART6_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */
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/* CLKSEL_CON64 */
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#define CRU_CLKSEL_CON64_OFFSET (0x200U)
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#define CRU_CLKSEL_CON64_CLK_UART7_SRC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON64_CLK_UART7_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON64_CLK_UART7_SRC_DIV_SHIFT) /* 0x0000007F */
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#define CRU_CLKSEL_CON64_CLK_UART7_SRC_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON64_CLK_UART7_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON64_CLK_UART7_SRC_SEL_SHIFT) /* 0x00000300 */
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#define CRU_CLKSEL_CON64_SCLK_UART7_SEL_SHIFT (12U)
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#define CRU_CLKSEL_CON64_SCLK_UART7_SEL_MASK (0x3U << CRU_CLKSEL_CON64_SCLK_UART7_SEL_SHIFT) /* 0x00003000 */
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/* CLKSEL_CON65 */
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#define CRU_CLKSEL_CON65_OFFSET (0x204U)
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#define CRU_CLKSEL_CON65_CLK_UART7_FRAC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON65_CLK_UART7_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON65_CLK_UART7_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */
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/* CLKSEL_CON66 */
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#define CRU_CLKSEL_CON66_OFFSET (0x208U)
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#define CRU_CLKSEL_CON66_CLK_UART8_SRC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON66_CLK_UART8_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON66_CLK_UART8_SRC_DIV_SHIFT) /* 0x0000007F */
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#define CRU_CLKSEL_CON66_CLK_UART8_SRC_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON66_CLK_UART8_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON66_CLK_UART8_SRC_SEL_SHIFT) /* 0x00000300 */
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#define CRU_CLKSEL_CON66_SCLK_UART8_SEL_SHIFT (12U)
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#define CRU_CLKSEL_CON66_SCLK_UART8_SEL_MASK (0x3U << CRU_CLKSEL_CON66_SCLK_UART8_SEL_SHIFT) /* 0x00003000 */
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/* CLKSEL_CON67 */
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#define CRU_CLKSEL_CON67_OFFSET (0x20CU)
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#define CRU_CLKSEL_CON67_CLK_UART8_FRAC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON67_CLK_UART8_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON67_CLK_UART8_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */
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/* CLKSEL_CON68 */
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#define CRU_CLKSEL_CON68_OFFSET (0x210U)
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#define CRU_CLKSEL_CON68_CLK_UART9_SRC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON68_CLK_UART9_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON68_CLK_UART9_SRC_DIV_SHIFT) /* 0x0000007F */
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#define CRU_CLKSEL_CON68_CLK_UART9_SRC_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON68_CLK_UART9_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON68_CLK_UART9_SRC_SEL_SHIFT) /* 0x00000300 */
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#define CRU_CLKSEL_CON68_SCLK_UART9_SEL_SHIFT (12U)
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#define CRU_CLKSEL_CON68_SCLK_UART9_SEL_MASK (0x3U << CRU_CLKSEL_CON68_SCLK_UART9_SEL_SHIFT) /* 0x00003000 */
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/* CLKSEL_CON69 */
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#define CRU_CLKSEL_CON69_OFFSET (0x214U)
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#define CRU_CLKSEL_CON69_CLK_UART9_FRAC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON69_CLK_UART9_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON69_CLK_UART9_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */
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/* CLKSEL_CON70 */
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#define CRU_CLKSEL_CON70_OFFSET (0x218U)
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#define CRU_CLKSEL_CON70_CLK_CAN0_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON70_CLK_CAN0_DIV_MASK (0x1FU << CRU_CLKSEL_CON70_CLK_CAN0_DIV_SHIFT) /* 0x0000001F */
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#define CRU_CLKSEL_CON70_CLK_CAN0_SEL_SHIFT (7U)
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#define CRU_CLKSEL_CON70_CLK_CAN0_SEL_MASK (0x1U << CRU_CLKSEL_CON70_CLK_CAN0_SEL_SHIFT) /* 0x00000080 */
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#define CRU_CLKSEL_CON70_CLK_CAN1_DIV_SHIFT (8U)
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#define CRU_CLKSEL_CON70_CLK_CAN1_DIV_MASK (0x1FU << CRU_CLKSEL_CON70_CLK_CAN1_DIV_SHIFT) /* 0x00001F00 */
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#define CRU_CLKSEL_CON70_CLK_CAN1_SEL_SHIFT (15U)
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#define CRU_CLKSEL_CON70_CLK_CAN1_SEL_MASK (0x1U << CRU_CLKSEL_CON70_CLK_CAN1_SEL_SHIFT) /* 0x00008000 */
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/* CLKSEL_CON71 */
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#define CRU_CLKSEL_CON71_OFFSET (0x21CU)
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#define CRU_CLKSEL_CON71_CLK_CAN2_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON71_CLK_CAN2_DIV_MASK (0x1FU << CRU_CLKSEL_CON71_CLK_CAN2_DIV_SHIFT) /* 0x0000001F */
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#define CRU_CLKSEL_CON71_CLK_CAN2_SEL_SHIFT (7U)
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#define CRU_CLKSEL_CON71_CLK_CAN2_SEL_MASK (0x1U << CRU_CLKSEL_CON71_CLK_CAN2_SEL_SHIFT) /* 0x00000080 */
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#define CRU_CLKSEL_CON71_CLK_I2C_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON71_CLK_I2C_SEL_MASK (0x3U << CRU_CLKSEL_CON71_CLK_I2C_SEL_SHIFT) /* 0x00000300 */
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/* CLKSEL_CON72 */
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#define CRU_CLKSEL_CON72_OFFSET (0x220U)
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#define CRU_CLKSEL_CON72_CLK_SPI0_SEL_SHIFT (0U)
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#define CRU_CLKSEL_CON72_CLK_SPI0_SEL_MASK (0x3U << CRU_CLKSEL_CON72_CLK_SPI0_SEL_SHIFT) /* 0x00000003 */
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#define CRU_CLKSEL_CON72_CLK_SPI1_SEL_SHIFT (2U)
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#define CRU_CLKSEL_CON72_CLK_SPI1_SEL_MASK (0x3U << CRU_CLKSEL_CON72_CLK_SPI1_SEL_SHIFT) /* 0x0000000C */
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#define CRU_CLKSEL_CON72_CLK_SPI2_SEL_SHIFT (4U)
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#define CRU_CLKSEL_CON72_CLK_SPI2_SEL_MASK (0x3U << CRU_CLKSEL_CON72_CLK_SPI2_SEL_SHIFT) /* 0x00000030 */
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#define CRU_CLKSEL_CON72_CLK_SPI3_SEL_SHIFT (6U)
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#define CRU_CLKSEL_CON72_CLK_SPI3_SEL_MASK (0x3U << CRU_CLKSEL_CON72_CLK_SPI3_SEL_SHIFT) /* 0x000000C0 */
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#define CRU_CLKSEL_CON72_CLK_PWM1_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON72_CLK_PWM1_SEL_MASK (0x3U << CRU_CLKSEL_CON72_CLK_PWM1_SEL_SHIFT) /* 0x00000300 */
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#define CRU_CLKSEL_CON72_CLK_PWM2_SEL_SHIFT (10U)
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#define CRU_CLKSEL_CON72_CLK_PWM2_SEL_MASK (0x3U << CRU_CLKSEL_CON72_CLK_PWM2_SEL_SHIFT) /* 0x00000C00 */
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#define CRU_CLKSEL_CON72_CLK_PWM3_SEL_SHIFT (12U)
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#define CRU_CLKSEL_CON72_CLK_PWM3_SEL_MASK (0x3U << CRU_CLKSEL_CON72_CLK_PWM3_SEL_SHIFT) /* 0x00003000 */
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#define CRU_CLKSEL_CON72_DBCLK_GPIO_SEL_SHIFT (14U)
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#define CRU_CLKSEL_CON72_DBCLK_GPIO_SEL_MASK (0x1U << CRU_CLKSEL_CON72_DBCLK_GPIO_SEL_SHIFT) /* 0x00004000 */
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/* CLKSEL_CON73 */
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#define CRU_CLKSEL_CON73_OFFSET (0x224U)
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#define CRU_CLKSEL_CON73_ACLK_TOP_HIGH_SEL_SHIFT (0U)
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#define CRU_CLKSEL_CON73_ACLK_TOP_HIGH_SEL_MASK (0x3U << CRU_CLKSEL_CON73_ACLK_TOP_HIGH_SEL_SHIFT) /* 0x00000003 */
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#define CRU_CLKSEL_CON73_ACLK_TOP_LOW_SEL_SHIFT (4U)
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#define CRU_CLKSEL_CON73_ACLK_TOP_LOW_SEL_MASK (0x3U << CRU_CLKSEL_CON73_ACLK_TOP_LOW_SEL_SHIFT) /* 0x00000030 */
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#define CRU_CLKSEL_CON73_HCLK_TOP_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON73_HCLK_TOP_SEL_MASK (0x3U << CRU_CLKSEL_CON73_HCLK_TOP_SEL_SHIFT) /* 0x00000300 */
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#define CRU_CLKSEL_CON73_PCLK_TOP_SEL_SHIFT (12U)
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#define CRU_CLKSEL_CON73_PCLK_TOP_SEL_MASK (0x3U << CRU_CLKSEL_CON73_PCLK_TOP_SEL_SHIFT) /* 0x00003000 */
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#define CRU_CLKSEL_CON73_CLK_OTPC_ARB_SEL_SHIFT (15U)
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#define CRU_CLKSEL_CON73_CLK_OTPC_ARB_SEL_MASK (0x1U << CRU_CLKSEL_CON73_CLK_OTPC_ARB_SEL_SHIFT) /* 0x00008000 */
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/* CLKSEL_CON74 */
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#define CRU_CLKSEL_CON74_OFFSET (0x228U)
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#define CRU_CLKSEL_CON74_CLK_TESTOUT_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON74_CLK_TESTOUT_DIV_MASK (0xFFU << CRU_CLKSEL_CON74_CLK_TESTOUT_DIV_SHIFT) /* 0x000000FF */
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#define CRU_CLKSEL_CON74_CLK_TESTOUT_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON74_CLK_TESTOUT_SEL_MASK (0x1FU << CRU_CLKSEL_CON74_CLK_TESTOUT_SEL_SHIFT) /* 0x00001F00 */
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/* CLKSEL_CON75 */
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#define CRU_CLKSEL_CON75_OFFSET (0x22CU)
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#define CRU_CLKSEL_CON75_CLK_GPLL_DIV_400M_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON75_CLK_GPLL_DIV_400M_DIV_MASK (0x1FU << CRU_CLKSEL_CON75_CLK_GPLL_DIV_400M_DIV_SHIFT) /* 0x0000001F */
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#define CRU_CLKSEL_CON75_CLK_GPLL_DIV_300M_DIV_SHIFT (8U)
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#define CRU_CLKSEL_CON75_CLK_GPLL_DIV_300M_DIV_MASK (0x1FU << CRU_CLKSEL_CON75_CLK_GPLL_DIV_300M_DIV_SHIFT) /* 0x00001F00 */
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/* CLKSEL_CON76 */
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#define CRU_CLKSEL_CON76_OFFSET (0x230U)
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#define CRU_CLKSEL_CON76_CLK_GPLL_DIV_200M_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON76_CLK_GPLL_DIV_200M_DIV_MASK (0x1FU << CRU_CLKSEL_CON76_CLK_GPLL_DIV_200M_DIV_SHIFT) /* 0x0000001F */
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#define CRU_CLKSEL_CON76_CLK_GPLL_DIV_150M_DIV_SHIFT (8U)
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#define CRU_CLKSEL_CON76_CLK_GPLL_DIV_150M_DIV_MASK (0x1FU << CRU_CLKSEL_CON76_CLK_GPLL_DIV_150M_DIV_SHIFT) /* 0x00001F00 */
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/* CLKSEL_CON77 */
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#define CRU_CLKSEL_CON77_OFFSET (0x234U)
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#define CRU_CLKSEL_CON77_CLK_GPLL_DIV_100M_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON77_CLK_GPLL_DIV_100M_DIV_MASK (0x1FU << CRU_CLKSEL_CON77_CLK_GPLL_DIV_100M_DIV_SHIFT) /* 0x0000001F */
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#define CRU_CLKSEL_CON77_CLK_GPLL_DIV_75M_DIV_SHIFT (8U)
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#define CRU_CLKSEL_CON77_CLK_GPLL_DIV_75M_DIV_MASK (0x1FU << CRU_CLKSEL_CON77_CLK_GPLL_DIV_75M_DIV_SHIFT) /* 0x00001F00 */
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/* CLKSEL_CON78 */
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#define CRU_CLKSEL_CON78_OFFSET (0x238U)
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#define CRU_CLKSEL_CON78_CLK_GPLL_DIV_20M_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON78_CLK_GPLL_DIV_20M_DIV_MASK (0x3FU << CRU_CLKSEL_CON78_CLK_GPLL_DIV_20M_DIV_SHIFT) /* 0x0000003F */
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#define CRU_CLKSEL_CON78_CLK_CPLL_DIV_500M_DIV_SHIFT (8U)
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#define CRU_CLKSEL_CON78_CLK_CPLL_DIV_500M_DIV_MASK (0x1FU << CRU_CLKSEL_CON78_CLK_CPLL_DIV_500M_DIV_SHIFT) /* 0x00001F00 */
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/* CLKSEL_CON79 */
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#define CRU_CLKSEL_CON79_OFFSET (0x23CU)
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#define CRU_CLKSEL_CON79_CLK_CPLL_DIV_333M_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON79_CLK_CPLL_DIV_333M_DIV_MASK (0x1FU << CRU_CLKSEL_CON79_CLK_CPLL_DIV_333M_DIV_SHIFT) /* 0x0000001F */
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#define CRU_CLKSEL_CON79_CLK_CPLL_DIV_250M_DIV_SHIFT (8U)
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#define CRU_CLKSEL_CON79_CLK_CPLL_DIV_250M_DIV_MASK (0x1FU << CRU_CLKSEL_CON79_CLK_CPLL_DIV_250M_DIV_SHIFT) /* 0x00001F00 */
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/* CLKSEL_CON80 */
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#define CRU_CLKSEL_CON80_OFFSET (0x240U)
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#define CRU_CLKSEL_CON80_CLK_CPLL_DIV_125M_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON80_CLK_CPLL_DIV_125M_DIV_MASK (0x1FU << CRU_CLKSEL_CON80_CLK_CPLL_DIV_125M_DIV_SHIFT) /* 0x0000001F */
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#define CRU_CLKSEL_CON80_CLK_CPLL_DIV_62P5_DIV_SHIFT (8U)
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#define CRU_CLKSEL_CON80_CLK_CPLL_DIV_62P5_DIV_MASK (0x1FU << CRU_CLKSEL_CON80_CLK_CPLL_DIV_62P5_DIV_SHIFT) /* 0x00001F00 */
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/* CLKSEL_CON81 */
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#define CRU_CLKSEL_CON81_OFFSET (0x244U)
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#define CRU_CLKSEL_CON81_CLK_CPLL_DIV_50M_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON81_CLK_CPLL_DIV_50M_DIV_MASK (0x1FU << CRU_CLKSEL_CON81_CLK_CPLL_DIV_50M_DIV_SHIFT) /* 0x0000001F */
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#define CRU_CLKSEL_CON81_CLK_CPLL_DIV_25M_DIV_SHIFT (8U)
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#define CRU_CLKSEL_CON81_CLK_CPLL_DIV_25M_DIV_MASK (0x3FU << CRU_CLKSEL_CON81_CLK_CPLL_DIV_25M_DIV_SHIFT) /* 0x00003F00 */
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/* CLKSEL_CON82 */
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#define CRU_CLKSEL_CON82_OFFSET (0x248U)
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#define CRU_CLKSEL_CON82_CLK_CPLL_DIV_100M_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON82_CLK_CPLL_DIV_100M_DIV_MASK (0x1FU << CRU_CLKSEL_CON82_CLK_CPLL_DIV_100M_DIV_SHIFT) /* 0x0000001F */
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#define CRU_CLKSEL_CON82_CLK_OSC0_DIV_750K_DIV_SHIFT (8U)
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#define CRU_CLKSEL_CON82_CLK_OSC0_DIV_750K_DIV_MASK (0x3FU << CRU_CLKSEL_CON82_CLK_OSC0_DIV_750K_DIV_SHIFT) /* 0x00003F00 */
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/* CLKSEL_CON83 */
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#define CRU_CLKSEL_CON83_OFFSET (0x24CU)
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#define CRU_CLKSEL_CON83_CLK_I2S3_2CH_RX_SRC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON83_CLK_I2S3_2CH_RX_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON83_CLK_I2S3_2CH_RX_SRC_DIV_SHIFT) /* 0x0000007F */
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#define CRU_CLKSEL_CON83_CLK_I2S3_2CH_RX_SRC_SEL_SHIFT (8U)
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#define CRU_CLKSEL_CON83_CLK_I2S3_2CH_RX_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON83_CLK_I2S3_2CH_RX_SRC_SEL_SHIFT) /* 0x00000300 */
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#define CRU_CLKSEL_CON83_MCLK_I2S3_2CH_RX_SEL_SHIFT (10U)
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#define CRU_CLKSEL_CON83_MCLK_I2S3_2CH_RX_SEL_MASK (0x3U << CRU_CLKSEL_CON83_MCLK_I2S3_2CH_RX_SEL_SHIFT) /* 0x00000C00 */
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#define CRU_CLKSEL_CON83_I2S3_MCLKOUT_RX_SEL_SHIFT (15U)
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#define CRU_CLKSEL_CON83_I2S3_MCLKOUT_RX_SEL_MASK (0x1U << CRU_CLKSEL_CON83_I2S3_MCLKOUT_RX_SEL_SHIFT) /* 0x00008000 */
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/* CLKSEL_CON84 */
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#define CRU_CLKSEL_CON84_OFFSET (0x250U)
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#define CRU_CLKSEL_CON84_CLK_I2S3_2CH_RX_FRAC_DIV_SHIFT (0U)
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#define CRU_CLKSEL_CON84_CLK_I2S3_2CH_RX_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON84_CLK_I2S3_2CH_RX_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */
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/* GATE_CON00 */
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#define CRU_GATE_CON00_OFFSET (0x300U)
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#define CRU_GATE_CON00_CLK_CORE_EN_SHIFT (0U)
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#define CRU_GATE_CON00_CLK_CORE_EN_MASK (0x1U << CRU_GATE_CON00_CLK_CORE_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON00_CLK_CORE0_EN_SHIFT (1U)
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#define CRU_GATE_CON00_CLK_CORE0_EN_MASK (0x1U << CRU_GATE_CON00_CLK_CORE0_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON00_CLK_CORE1_EN_SHIFT (2U)
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#define CRU_GATE_CON00_CLK_CORE1_EN_MASK (0x1U << CRU_GATE_CON00_CLK_CORE1_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON00_CLK_CORE2_EN_SHIFT (3U)
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#define CRU_GATE_CON00_CLK_CORE2_EN_MASK (0x1U << CRU_GATE_CON00_CLK_CORE2_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON00_CLK_CORE3_EN_SHIFT (4U)
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#define CRU_GATE_CON00_CLK_CORE3_EN_MASK (0x1U << CRU_GATE_CON00_CLK_CORE3_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON00_SCLK_CORE_SRC_EN_SHIFT (5U)
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#define CRU_GATE_CON00_SCLK_CORE_SRC_EN_MASK (0x1U << CRU_GATE_CON00_SCLK_CORE_SRC_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON00_CLK_NPLL_CORE_EN_SHIFT (6U)
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#define CRU_GATE_CON00_CLK_NPLL_CORE_EN_MASK (0x1U << CRU_GATE_CON00_CLK_NPLL_CORE_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON00_SCLK_CORE_EN_SHIFT (7U)
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#define CRU_GATE_CON00_SCLK_CORE_EN_MASK (0x1U << CRU_GATE_CON00_SCLK_CORE_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON00_ATCLK_CORE_EN_SHIFT (8U)
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#define CRU_GATE_CON00_ATCLK_CORE_EN_MASK (0x1U << CRU_GATE_CON00_ATCLK_CORE_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON00_GICCLK_CORE_EN_SHIFT (9U)
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#define CRU_GATE_CON00_GICCLK_CORE_EN_MASK (0x1U << CRU_GATE_CON00_GICCLK_CORE_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON00_PCLK_CORE_PRE_EN_SHIFT (10U)
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#define CRU_GATE_CON00_PCLK_CORE_PRE_EN_MASK (0x1U << CRU_GATE_CON00_PCLK_CORE_PRE_EN_SHIFT) /* 0x00000400 */
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#define CRU_GATE_CON00_PERIPHCLK_CORE_PRE_EN_SHIFT (11U)
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#define CRU_GATE_CON00_PERIPHCLK_CORE_PRE_EN_MASK (0x1U << CRU_GATE_CON00_PERIPHCLK_CORE_PRE_EN_SHIFT) /* 0x00000800 */
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#define CRU_GATE_CON00_PCLK_CORE_EN_SHIFT (12U)
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#define CRU_GATE_CON00_PCLK_CORE_EN_MASK (0x1U << CRU_GATE_CON00_PCLK_CORE_EN_SHIFT) /* 0x00001000 */
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#define CRU_GATE_CON00_PERIPHCLK_CORE_EN_SHIFT (13U)
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#define CRU_GATE_CON00_PERIPHCLK_CORE_EN_MASK (0x1U << CRU_GATE_CON00_PERIPHCLK_CORE_EN_SHIFT) /* 0x00002000 */
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#define CRU_GATE_CON00_TSCLK_CORE_EN_SHIFT (14U)
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#define CRU_GATE_CON00_TSCLK_CORE_EN_MASK (0x1U << CRU_GATE_CON00_TSCLK_CORE_EN_SHIFT) /* 0x00004000 */
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#define CRU_GATE_CON00_CNTCLK_CORE_EN_SHIFT (15U)
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#define CRU_GATE_CON00_CNTCLK_CORE_EN_MASK (0x1U << CRU_GATE_CON00_CNTCLK_CORE_EN_SHIFT) /* 0x00008000 */
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/* GATE_CON01 */
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#define CRU_GATE_CON01_OFFSET (0x304U)
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#define CRU_GATE_CON01_ACLK_CORE_EN_SHIFT (0U)
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#define CRU_GATE_CON01_ACLK_CORE_EN_MASK (0x1U << CRU_GATE_CON01_ACLK_CORE_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON01_ACLK_CORE_NIU2DDR_EN_SHIFT (1U)
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#define CRU_GATE_CON01_ACLK_CORE_NIU2DDR_EN_MASK (0x1U << CRU_GATE_CON01_ACLK_CORE_NIU2DDR_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON01_ACLK_CORE_NIU2BUS_EN_SHIFT (2U)
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#define CRU_GATE_CON01_ACLK_CORE_NIU2BUS_EN_MASK (0x1U << CRU_GATE_CON01_ACLK_CORE_NIU2BUS_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON01_PCLK_DBG_NIU_EN_SHIFT (3U)
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#define CRU_GATE_CON01_PCLK_DBG_NIU_EN_MASK (0x1U << CRU_GATE_CON01_PCLK_DBG_NIU_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON01_PCLK_DBG_EN_SHIFT (4U)
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#define CRU_GATE_CON01_PCLK_DBG_EN_MASK (0x1U << CRU_GATE_CON01_PCLK_DBG_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON01_PCLK_DBG_DAPLITE_EN_SHIFT (5U)
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#define CRU_GATE_CON01_PCLK_DBG_DAPLITE_EN_MASK (0x1U << CRU_GATE_CON01_PCLK_DBG_DAPLITE_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON01_ACLK_ADB400_CORE2GIC_EN_SHIFT (6U)
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#define CRU_GATE_CON01_ACLK_ADB400_CORE2GIC_EN_MASK (0x1U << CRU_GATE_CON01_ACLK_ADB400_CORE2GIC_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON01_ACLK_ADB400_GIC2CORE_EN_SHIFT (7U)
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#define CRU_GATE_CON01_ACLK_ADB400_GIC2CORE_EN_MASK (0x1U << CRU_GATE_CON01_ACLK_ADB400_GIC2CORE_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON01_PCLK_CORE_GRF_EN_SHIFT (8U)
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#define CRU_GATE_CON01_PCLK_CORE_GRF_EN_MASK (0x1U << CRU_GATE_CON01_PCLK_CORE_GRF_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON01_PCLK_CORE_PVTM_EN_SHIFT (9U)
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#define CRU_GATE_CON01_PCLK_CORE_PVTM_EN_MASK (0x1U << CRU_GATE_CON01_PCLK_CORE_PVTM_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON01_CLK_CORE_PVTM_EN_SHIFT (10U)
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#define CRU_GATE_CON01_CLK_CORE_PVTM_EN_MASK (0x1U << CRU_GATE_CON01_CLK_CORE_PVTM_EN_SHIFT) /* 0x00000400 */
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#define CRU_GATE_CON01_CLK_CORE_PVTM_CORE_EN_SHIFT (11U)
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#define CRU_GATE_CON01_CLK_CORE_PVTM_CORE_EN_MASK (0x1U << CRU_GATE_CON01_CLK_CORE_PVTM_CORE_EN_SHIFT) /* 0x00000800 */
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#define CRU_GATE_CON01_CLK_CORE_PVTPLL_EN_SHIFT (12U)
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#define CRU_GATE_CON01_CLK_CORE_PVTPLL_EN_MASK (0x1U << CRU_GATE_CON01_CLK_CORE_PVTPLL_EN_SHIFT) /* 0x00001000 */
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#define CRU_GATE_CON01_CLK_CORE_DIV2_EN_SHIFT (13U)
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#define CRU_GATE_CON01_CLK_CORE_DIV2_EN_MASK (0x1U << CRU_GATE_CON01_CLK_CORE_DIV2_EN_SHIFT) /* 0x00002000 */
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#define CRU_GATE_CON01_CLK_APLL_CORE_EN_SHIFT (14U)
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#define CRU_GATE_CON01_CLK_APLL_CORE_EN_MASK (0x1U << CRU_GATE_CON01_CLK_APLL_CORE_EN_SHIFT) /* 0x00004000 */
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#define CRU_GATE_CON01_CLK_JTAG_EN_SHIFT (15U)
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#define CRU_GATE_CON01_CLK_JTAG_EN_MASK (0x1U << CRU_GATE_CON01_CLK_JTAG_EN_SHIFT) /* 0x00008000 */
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/* GATE_CON02 */
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#define CRU_GATE_CON02_OFFSET (0x308U)
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#define CRU_GATE_CON02_CLK_GPU_SRC_EN_SHIFT (0U)
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#define CRU_GATE_CON02_CLK_GPU_SRC_EN_MASK (0x1U << CRU_GATE_CON02_CLK_GPU_SRC_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON02_PCLK_GPU_PRE_EN_SHIFT (2U)
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#define CRU_GATE_CON02_PCLK_GPU_PRE_EN_MASK (0x1U << CRU_GATE_CON02_PCLK_GPU_PRE_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON02_ACLK_GPU_EN_SHIFT (3U)
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#define CRU_GATE_CON02_ACLK_GPU_EN_MASK (0x1U << CRU_GATE_CON02_ACLK_GPU_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON02_ACLK_GPU_NIU_EN_SHIFT (4U)
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#define CRU_GATE_CON02_ACLK_GPU_NIU_EN_MASK (0x1U << CRU_GATE_CON02_ACLK_GPU_NIU_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON02_PCLK_GPU_NIU_EN_SHIFT (5U)
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#define CRU_GATE_CON02_PCLK_GPU_NIU_EN_MASK (0x1U << CRU_GATE_CON02_PCLK_GPU_NIU_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON02_PCLK_GPU_PVTM_EN_SHIFT (6U)
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#define CRU_GATE_CON02_PCLK_GPU_PVTM_EN_MASK (0x1U << CRU_GATE_CON02_PCLK_GPU_PVTM_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON02_CLK_GPU_PVTM_EN_SHIFT (7U)
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#define CRU_GATE_CON02_CLK_GPU_PVTM_EN_MASK (0x1U << CRU_GATE_CON02_CLK_GPU_PVTM_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON02_CLK_GPU_PVTM_CORE_EN_SHIFT (8U)
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#define CRU_GATE_CON02_CLK_GPU_PVTM_CORE_EN_MASK (0x1U << CRU_GATE_CON02_CLK_GPU_PVTM_CORE_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON02_CLK_GPU_PVTPLL_EN_SHIFT (9U)
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#define CRU_GATE_CON02_CLK_GPU_PVTPLL_EN_MASK (0x1U << CRU_GATE_CON02_CLK_GPU_PVTPLL_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON02_CLK_GPU_DIV2_EN_SHIFT (10U)
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#define CRU_GATE_CON02_CLK_GPU_DIV2_EN_MASK (0x1U << CRU_GATE_CON02_CLK_GPU_DIV2_EN_SHIFT) /* 0x00000400 */
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#define CRU_GATE_CON02_ACLK_GPU_PRE_EN_SHIFT (11U)
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#define CRU_GATE_CON02_ACLK_GPU_PRE_EN_MASK (0x1U << CRU_GATE_CON02_ACLK_GPU_PRE_EN_SHIFT) /* 0x00000800 */
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/* GATE_CON03 */
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#define CRU_GATE_CON03_OFFSET (0x30CU)
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#define CRU_GATE_CON03_CLK_NPU_SRC_EN_SHIFT (0U)
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#define CRU_GATE_CON03_CLK_NPU_SRC_EN_MASK (0x1U << CRU_GATE_CON03_CLK_NPU_SRC_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON03_CLK_NPU_NP5_EN_SHIFT (1U)
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#define CRU_GATE_CON03_CLK_NPU_NP5_EN_MASK (0x1U << CRU_GATE_CON03_CLK_NPU_NP5_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON03_HCLK_NPU_PRE_EN_SHIFT (2U)
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#define CRU_GATE_CON03_HCLK_NPU_PRE_EN_MASK (0x1U << CRU_GATE_CON03_HCLK_NPU_PRE_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON03_PCLK_NPU_PRE_EN_SHIFT (3U)
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#define CRU_GATE_CON03_PCLK_NPU_PRE_EN_MASK (0x1U << CRU_GATE_CON03_PCLK_NPU_PRE_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON03_ACLK_NPU_NIU_EN_SHIFT (4U)
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#define CRU_GATE_CON03_ACLK_NPU_NIU_EN_MASK (0x1U << CRU_GATE_CON03_ACLK_NPU_NIU_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON03_HCLK_NPU_NIU_EN_SHIFT (5U)
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#define CRU_GATE_CON03_HCLK_NPU_NIU_EN_MASK (0x1U << CRU_GATE_CON03_HCLK_NPU_NIU_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON03_PCLK_NPU_NIU_EN_SHIFT (6U)
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#define CRU_GATE_CON03_PCLK_NPU_NIU_EN_MASK (0x1U << CRU_GATE_CON03_PCLK_NPU_NIU_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON03_ACLK_RKNN_EN_SHIFT (7U)
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#define CRU_GATE_CON03_ACLK_RKNN_EN_MASK (0x1U << CRU_GATE_CON03_ACLK_RKNN_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON03_HCLK_RKNN_EN_SHIFT (8U)
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#define CRU_GATE_CON03_HCLK_RKNN_EN_MASK (0x1U << CRU_GATE_CON03_HCLK_RKNN_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON03_PCLK_NPU_PVTM_EN_SHIFT (9U)
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#define CRU_GATE_CON03_PCLK_NPU_PVTM_EN_MASK (0x1U << CRU_GATE_CON03_PCLK_NPU_PVTM_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON03_CLK_NPU_PVTM_EN_SHIFT (10U)
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#define CRU_GATE_CON03_CLK_NPU_PVTM_EN_MASK (0x1U << CRU_GATE_CON03_CLK_NPU_PVTM_EN_SHIFT) /* 0x00000400 */
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#define CRU_GATE_CON03_CLK_NPU_PVTM_CORE_EN_SHIFT (11U)
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#define CRU_GATE_CON03_CLK_NPU_PVTM_CORE_EN_MASK (0x1U << CRU_GATE_CON03_CLK_NPU_PVTM_CORE_EN_SHIFT) /* 0x00000800 */
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#define CRU_GATE_CON03_CLK_NPU_PVTPLL_EN_SHIFT (12U)
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#define CRU_GATE_CON03_CLK_NPU_PVTPLL_EN_MASK (0x1U << CRU_GATE_CON03_CLK_NPU_PVTPLL_EN_SHIFT) /* 0x00001000 */
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#define CRU_GATE_CON03_CLK_NPU_DIV2_EN_SHIFT (13U)
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#define CRU_GATE_CON03_CLK_NPU_DIV2_EN_MASK (0x1U << CRU_GATE_CON03_CLK_NPU_DIV2_EN_SHIFT) /* 0x00002000 */
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/* GATE_CON04 */
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#define CRU_GATE_CON04_OFFSET (0x310U)
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#define CRU_GATE_CON04_CLK_DDRPHY1X_EN_SHIFT (0U)
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#define CRU_GATE_CON04_CLK_DDRPHY1X_EN_MASK (0x1U << CRU_GATE_CON04_CLK_DDRPHY1X_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON04_CLK_DPLL_DDR_EN_SHIFT (1U)
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#define CRU_GATE_CON04_CLK_DPLL_DDR_EN_MASK (0x1U << CRU_GATE_CON04_CLK_DPLL_DDR_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON04_ACLK_MSCH_DIV2_EN_SHIFT (2U)
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#define CRU_GATE_CON04_ACLK_MSCH_DIV2_EN_MASK (0x1U << CRU_GATE_CON04_ACLK_MSCH_DIV2_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON04_CLK_HWFFC_CTRL_EN_SHIFT (3U)
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#define CRU_GATE_CON04_CLK_HWFFC_CTRL_EN_MASK (0x1U << CRU_GATE_CON04_CLK_HWFFC_CTRL_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON04_ACLK_DDRSCRAMBLE_EN_SHIFT (4U)
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#define CRU_GATE_CON04_ACLK_DDRSCRAMBLE_EN_MASK (0x1U << CRU_GATE_CON04_ACLK_DDRSCRAMBLE_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON04_ACLK_MSCH_EN_SHIFT (5U)
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#define CRU_GATE_CON04_ACLK_MSCH_EN_MASK (0x1U << CRU_GATE_CON04_ACLK_MSCH_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON04_CLK_DDR_ALWAYSON_EN_SHIFT (6U)
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#define CRU_GATE_CON04_CLK_DDR_ALWAYSON_EN_MASK (0x1U << CRU_GATE_CON04_CLK_DDR_ALWAYSON_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON04_ACLK_DDRSPLIT_EN_SHIFT (8U)
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#define CRU_GATE_CON04_ACLK_DDRSPLIT_EN_MASK (0x1U << CRU_GATE_CON04_ACLK_DDRSPLIT_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON04_CLK_DDRDFI_CTL_EN_SHIFT (9U)
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#define CRU_GATE_CON04_CLK_DDRDFI_CTL_EN_MASK (0x1U << CRU_GATE_CON04_CLK_DDRDFI_CTL_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON04_ACLK_DMA2DDR_EN_SHIFT (11U)
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#define CRU_GATE_CON04_ACLK_DMA2DDR_EN_MASK (0x1U << CRU_GATE_CON04_ACLK_DMA2DDR_EN_SHIFT) /* 0x00000800 */
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#define CRU_GATE_CON04_CLK_DDRMON_EN_SHIFT (13U)
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#define CRU_GATE_CON04_CLK_DDRMON_EN_MASK (0x1U << CRU_GATE_CON04_CLK_DDRMON_EN_SHIFT) /* 0x00002000 */
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#define CRU_GATE_CON04_CLK24_DDRMON_EN_SHIFT (15U)
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#define CRU_GATE_CON04_CLK24_DDRMON_EN_MASK (0x1U << CRU_GATE_CON04_CLK24_DDRMON_EN_SHIFT) /* 0x00008000 */
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/* GATE_CON05 */
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#define CRU_GATE_CON05_OFFSET (0x314U)
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#define CRU_GATE_CON05_ACLK_GIC_AUDIO_EN_SHIFT (0U)
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#define CRU_GATE_CON05_ACLK_GIC_AUDIO_EN_MASK (0x1U << CRU_GATE_CON05_ACLK_GIC_AUDIO_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON05_HCLK_GIC_AUDIO_EN_SHIFT (1U)
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#define CRU_GATE_CON05_HCLK_GIC_AUDIO_EN_MASK (0x1U << CRU_GATE_CON05_HCLK_GIC_AUDIO_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON05_ACLK_GIC_AUDIO_NIU_EN_SHIFT (2U)
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#define CRU_GATE_CON05_ACLK_GIC_AUDIO_NIU_EN_MASK (0x1U << CRU_GATE_CON05_ACLK_GIC_AUDIO_NIU_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON05_HCLK_GIC_AUDIO_NIU_EN_SHIFT (3U)
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#define CRU_GATE_CON05_HCLK_GIC_AUDIO_NIU_EN_MASK (0x1U << CRU_GATE_CON05_HCLK_GIC_AUDIO_NIU_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON05_ACLK_GIC600_EN_SHIFT (4U)
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#define CRU_GATE_CON05_ACLK_GIC600_EN_MASK (0x1U << CRU_GATE_CON05_ACLK_GIC600_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON05_ACLK_GICADB_CORE2GIC_EN_SHIFT (5U)
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#define CRU_GATE_CON05_ACLK_GICADB_CORE2GIC_EN_MASK (0x1U << CRU_GATE_CON05_ACLK_GICADB_CORE2GIC_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON05_ACLK_GICADB_GIC2CORE_EN_SHIFT (6U)
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#define CRU_GATE_CON05_ACLK_GICADB_GIC2CORE_EN_MASK (0x1U << CRU_GATE_CON05_ACLK_GICADB_GIC2CORE_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON05_ACLK_SPINLOCK_EN_SHIFT (7U)
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#define CRU_GATE_CON05_ACLK_SPINLOCK_EN_MASK (0x1U << CRU_GATE_CON05_ACLK_SPINLOCK_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON05_HCLK_SDMMC_BUFFER_EN_SHIFT (8U)
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#define CRU_GATE_CON05_HCLK_SDMMC_BUFFER_EN_MASK (0x1U << CRU_GATE_CON05_HCLK_SDMMC_BUFFER_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON05_DCLK_SDMMC_BUFFER_EN_SHIFT (9U)
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#define CRU_GATE_CON05_DCLK_SDMMC_BUFFER_EN_MASK (0x1U << CRU_GATE_CON05_DCLK_SDMMC_BUFFER_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON05_HCLK_I2S0_8CH_EN_SHIFT (10U)
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#define CRU_GATE_CON05_HCLK_I2S0_8CH_EN_MASK (0x1U << CRU_GATE_CON05_HCLK_I2S0_8CH_EN_SHIFT) /* 0x00000400 */
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#define CRU_GATE_CON05_HCLK_I2S1_8CH_EN_SHIFT (11U)
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#define CRU_GATE_CON05_HCLK_I2S1_8CH_EN_MASK (0x1U << CRU_GATE_CON05_HCLK_I2S1_8CH_EN_SHIFT) /* 0x00000800 */
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#define CRU_GATE_CON05_HCLK_I2S2_2CH_EN_SHIFT (12U)
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#define CRU_GATE_CON05_HCLK_I2S2_2CH_EN_MASK (0x1U << CRU_GATE_CON05_HCLK_I2S2_2CH_EN_SHIFT) /* 0x00001000 */
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#define CRU_GATE_CON05_HCLK_I2S3_2CH_EN_SHIFT (13U)
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#define CRU_GATE_CON05_HCLK_I2S3_2CH_EN_MASK (0x1U << CRU_GATE_CON05_HCLK_I2S3_2CH_EN_SHIFT) /* 0x00002000 */
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#define CRU_GATE_CON05_HCLK_PDM_EN_SHIFT (14U)
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#define CRU_GATE_CON05_HCLK_PDM_EN_MASK (0x1U << CRU_GATE_CON05_HCLK_PDM_EN_SHIFT) /* 0x00004000 */
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#define CRU_GATE_CON05_MCLK_PDM_EN_SHIFT (15U)
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#define CRU_GATE_CON05_MCLK_PDM_EN_MASK (0x1U << CRU_GATE_CON05_MCLK_PDM_EN_SHIFT) /* 0x00008000 */
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/* GATE_CON06 */
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#define CRU_GATE_CON06_OFFSET (0x318U)
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#define CRU_GATE_CON06_CLK_I2S0_8CH_TX_SRC_EN_SHIFT (0U)
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#define CRU_GATE_CON06_CLK_I2S0_8CH_TX_SRC_EN_MASK (0x1U << CRU_GATE_CON06_CLK_I2S0_8CH_TX_SRC_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON06_CLK_I2S0_8CH_TX_FRAC_EN_SHIFT (1U)
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#define CRU_GATE_CON06_CLK_I2S0_8CH_TX_FRAC_EN_MASK (0x1U << CRU_GATE_CON06_CLK_I2S0_8CH_TX_FRAC_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON06_MCLK_I2S0_8CH_TX_EN_SHIFT (2U)
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#define CRU_GATE_CON06_MCLK_I2S0_8CH_TX_EN_MASK (0x1U << CRU_GATE_CON06_MCLK_I2S0_8CH_TX_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON06_I2S0_MCLKOUT_TX_EN_SHIFT (3U)
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#define CRU_GATE_CON06_I2S0_MCLKOUT_TX_EN_MASK (0x1U << CRU_GATE_CON06_I2S0_MCLKOUT_TX_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON06_CLK_I2S0_8CH_RX_SRC_EN_SHIFT (4U)
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#define CRU_GATE_CON06_CLK_I2S0_8CH_RX_SRC_EN_MASK (0x1U << CRU_GATE_CON06_CLK_I2S0_8CH_RX_SRC_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON06_CLK_I2S0_8CH_RX_FRAC_EN_SHIFT (5U)
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#define CRU_GATE_CON06_CLK_I2S0_8CH_RX_FRAC_EN_MASK (0x1U << CRU_GATE_CON06_CLK_I2S0_8CH_RX_FRAC_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON06_MCLK_I2S0_8CH_RX_EN_SHIFT (6U)
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#define CRU_GATE_CON06_MCLK_I2S0_8CH_RX_EN_MASK (0x1U << CRU_GATE_CON06_MCLK_I2S0_8CH_RX_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON06_I2S0_MCLKOUT_RX_EN_SHIFT (7U)
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#define CRU_GATE_CON06_I2S0_MCLKOUT_RX_EN_MASK (0x1U << CRU_GATE_CON06_I2S0_MCLKOUT_RX_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON06_CLK_I2S1_8CH_TX_SRC_EN_SHIFT (8U)
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#define CRU_GATE_CON06_CLK_I2S1_8CH_TX_SRC_EN_MASK (0x1U << CRU_GATE_CON06_CLK_I2S1_8CH_TX_SRC_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON06_CLK_I2S1_8CH_TX_FRAC_EN_SHIFT (9U)
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#define CRU_GATE_CON06_CLK_I2S1_8CH_TX_FRAC_EN_MASK (0x1U << CRU_GATE_CON06_CLK_I2S1_8CH_TX_FRAC_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON06_MCLK_I2S1_8CH_TX_EN_SHIFT (10U)
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#define CRU_GATE_CON06_MCLK_I2S1_8CH_TX_EN_MASK (0x1U << CRU_GATE_CON06_MCLK_I2S1_8CH_TX_EN_SHIFT) /* 0x00000400 */
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#define CRU_GATE_CON06_I2S1_MCLKOUT_TX_EN_SHIFT (11U)
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#define CRU_GATE_CON06_I2S1_MCLKOUT_TX_EN_MASK (0x1U << CRU_GATE_CON06_I2S1_MCLKOUT_TX_EN_SHIFT) /* 0x00000800 */
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#define CRU_GATE_CON06_CLK_I2S1_8CH_RX_SRC_EN_SHIFT (12U)
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#define CRU_GATE_CON06_CLK_I2S1_8CH_RX_SRC_EN_MASK (0x1U << CRU_GATE_CON06_CLK_I2S1_8CH_RX_SRC_EN_SHIFT) /* 0x00001000 */
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#define CRU_GATE_CON06_CLK_I2S1_8CH_RX_FRAC_EN_SHIFT (13U)
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#define CRU_GATE_CON06_CLK_I2S1_8CH_RX_FRAC_EN_MASK (0x1U << CRU_GATE_CON06_CLK_I2S1_8CH_RX_FRAC_EN_SHIFT) /* 0x00002000 */
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#define CRU_GATE_CON06_MCLK_I2S1_8CH_RX_EN_SHIFT (14U)
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#define CRU_GATE_CON06_MCLK_I2S1_8CH_RX_EN_MASK (0x1U << CRU_GATE_CON06_MCLK_I2S1_8CH_RX_EN_SHIFT) /* 0x00004000 */
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#define CRU_GATE_CON06_I2S1_MCLKOUT_RX_EN_SHIFT (15U)
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#define CRU_GATE_CON06_I2S1_MCLKOUT_RX_EN_MASK (0x1U << CRU_GATE_CON06_I2S1_MCLKOUT_RX_EN_SHIFT) /* 0x00008000 */
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/* GATE_CON07 */
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#define CRU_GATE_CON07_OFFSET (0x31CU)
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#define CRU_GATE_CON07_CLK_I2S2_2CH_SRC_EN_SHIFT (0U)
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#define CRU_GATE_CON07_CLK_I2S2_2CH_SRC_EN_MASK (0x1U << CRU_GATE_CON07_CLK_I2S2_2CH_SRC_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON07_CLK_I2S2_2CH_FRAC_EN_SHIFT (1U)
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#define CRU_GATE_CON07_CLK_I2S2_2CH_FRAC_EN_MASK (0x1U << CRU_GATE_CON07_CLK_I2S2_2CH_FRAC_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON07_MCLK_I2S2_2CH_EN_SHIFT (2U)
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#define CRU_GATE_CON07_MCLK_I2S2_2CH_EN_MASK (0x1U << CRU_GATE_CON07_MCLK_I2S2_2CH_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON07_I2S2_MCLKOUT_EN_SHIFT (3U)
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#define CRU_GATE_CON07_I2S2_MCLKOUT_EN_MASK (0x1U << CRU_GATE_CON07_I2S2_MCLKOUT_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON07_CLK_I2S3_2CH_TX_SRC_EN_SHIFT (4U)
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#define CRU_GATE_CON07_CLK_I2S3_2CH_TX_SRC_EN_MASK (0x1U << CRU_GATE_CON07_CLK_I2S3_2CH_TX_SRC_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON07_CLK_I2S3_2CH_TX_FRAC_EN_SHIFT (5U)
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#define CRU_GATE_CON07_CLK_I2S3_2CH_TX_FRAC_EN_MASK (0x1U << CRU_GATE_CON07_CLK_I2S3_2CH_TX_FRAC_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON07_MCLK_I2S3_2CH_TX_EN_SHIFT (6U)
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#define CRU_GATE_CON07_MCLK_I2S3_2CH_TX_EN_MASK (0x1U << CRU_GATE_CON07_MCLK_I2S3_2CH_TX_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON07_I2S3_MCLKOUT_TX_EN_SHIFT (7U)
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#define CRU_GATE_CON07_I2S3_MCLKOUT_TX_EN_MASK (0x1U << CRU_GATE_CON07_I2S3_MCLKOUT_TX_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON07_CLK_I2S3_2CH_RX_SRC_EN_SHIFT (8U)
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#define CRU_GATE_CON07_CLK_I2S3_2CH_RX_SRC_EN_MASK (0x1U << CRU_GATE_CON07_CLK_I2S3_2CH_RX_SRC_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON07_CLK_I2S3_2CH_RX_FRAC_EN_SHIFT (9U)
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#define CRU_GATE_CON07_CLK_I2S3_2CH_RX_FRAC_EN_MASK (0x1U << CRU_GATE_CON07_CLK_I2S3_2CH_RX_FRAC_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON07_MCLK_I2S3_2CH_RX_EN_SHIFT (10U)
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#define CRU_GATE_CON07_MCLK_I2S3_2CH_RX_EN_MASK (0x1U << CRU_GATE_CON07_MCLK_I2S3_2CH_RX_EN_SHIFT) /* 0x00000400 */
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#define CRU_GATE_CON07_I2S3_MCLKOUT_RX_EN_SHIFT (11U)
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#define CRU_GATE_CON07_I2S3_MCLKOUT_RX_EN_MASK (0x1U << CRU_GATE_CON07_I2S3_MCLKOUT_RX_EN_SHIFT) /* 0x00000800 */
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#define CRU_GATE_CON07_HCLK_VAD_EN_SHIFT (12U)
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#define CRU_GATE_CON07_HCLK_VAD_EN_MASK (0x1U << CRU_GATE_CON07_HCLK_VAD_EN_SHIFT) /* 0x00001000 */
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#define CRU_GATE_CON07_HCLK_SPDIF_8CH_EN_SHIFT (13U)
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#define CRU_GATE_CON07_HCLK_SPDIF_8CH_EN_MASK (0x1U << CRU_GATE_CON07_HCLK_SPDIF_8CH_EN_SHIFT) /* 0x00002000 */
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#define CRU_GATE_CON07_MCLK_SPDIF_8CH_SRC_EN_SHIFT (14U)
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#define CRU_GATE_CON07_MCLK_SPDIF_8CH_SRC_EN_MASK (0x1U << CRU_GATE_CON07_MCLK_SPDIF_8CH_SRC_EN_SHIFT) /* 0x00004000 */
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#define CRU_GATE_CON07_MCLK_SPDIF_8CH_FRAC_EN_SHIFT (15U)
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#define CRU_GATE_CON07_MCLK_SPDIF_8CH_FRAC_EN_MASK (0x1U << CRU_GATE_CON07_MCLK_SPDIF_8CH_FRAC_EN_SHIFT) /* 0x00008000 */
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/* GATE_CON08 */
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#define CRU_GATE_CON08_OFFSET (0x320U)
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#define CRU_GATE_CON08_HCLK_AUDPWM_EN_SHIFT (0U)
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#define CRU_GATE_CON08_HCLK_AUDPWM_EN_MASK (0x1U << CRU_GATE_CON08_HCLK_AUDPWM_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON08_SCLK_AUDPWM_SRC_EN_SHIFT (1U)
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#define CRU_GATE_CON08_SCLK_AUDPWM_SRC_EN_MASK (0x1U << CRU_GATE_CON08_SCLK_AUDPWM_SRC_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON08_SCLK_AUDPWM_FRAC_EN_SHIFT (2U)
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#define CRU_GATE_CON08_SCLK_AUDPWM_FRAC_EN_MASK (0x1U << CRU_GATE_CON08_SCLK_AUDPWM_FRAC_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON08_HCLK_ACDCDIG_EN_SHIFT (3U)
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#define CRU_GATE_CON08_HCLK_ACDCDIG_EN_MASK (0x1U << CRU_GATE_CON08_HCLK_ACDCDIG_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON08_CLK_ACDCDIG_I2C_EN_SHIFT (4U)
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#define CRU_GATE_CON08_CLK_ACDCDIG_I2C_EN_MASK (0x1U << CRU_GATE_CON08_CLK_ACDCDIG_I2C_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON08_CLK_ACDCDIG_DAC_EN_SHIFT (5U)
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#define CRU_GATE_CON08_CLK_ACDCDIG_DAC_EN_MASK (0x1U << CRU_GATE_CON08_CLK_ACDCDIG_DAC_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON08_CLK_ACDCDIG_ADC_EN_SHIFT (6U)
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#define CRU_GATE_CON08_CLK_ACDCDIG_ADC_EN_MASK (0x1U << CRU_GATE_CON08_CLK_ACDCDIG_ADC_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON08_ACLK_SECURE_FLASH_EN_SHIFT (7U)
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#define CRU_GATE_CON08_ACLK_SECURE_FLASH_EN_MASK (0x1U << CRU_GATE_CON08_ACLK_SECURE_FLASH_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON08_HCLK_SECURE_FLASH_EN_SHIFT (8U)
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#define CRU_GATE_CON08_HCLK_SECURE_FLASH_EN_MASK (0x1U << CRU_GATE_CON08_HCLK_SECURE_FLASH_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON08_ACLK_SECURE_FLASH_NIU_EN_SHIFT (9U)
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#define CRU_GATE_CON08_ACLK_SECURE_FLASH_NIU_EN_MASK (0x1U << CRU_GATE_CON08_ACLK_SECURE_FLASH_NIU_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON08_HCLK_SECURE_FLASH_NIU_EN_SHIFT (10U)
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#define CRU_GATE_CON08_HCLK_SECURE_FLASH_NIU_EN_MASK (0x1U << CRU_GATE_CON08_HCLK_SECURE_FLASH_NIU_EN_SHIFT) /* 0x00000400 */
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#define CRU_GATE_CON08_ACLK_CRYPTO_NS_EN_SHIFT (11U)
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#define CRU_GATE_CON08_ACLK_CRYPTO_NS_EN_MASK (0x1U << CRU_GATE_CON08_ACLK_CRYPTO_NS_EN_SHIFT) /* 0x00000800 */
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#define CRU_GATE_CON08_HCLK_CRYPTO_NS_EN_SHIFT (12U)
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#define CRU_GATE_CON08_HCLK_CRYPTO_NS_EN_MASK (0x1U << CRU_GATE_CON08_HCLK_CRYPTO_NS_EN_SHIFT) /* 0x00001000 */
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#define CRU_GATE_CON08_CLK_CRYPTO_NS_CORE_EN_SHIFT (13U)
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#define CRU_GATE_CON08_CLK_CRYPTO_NS_CORE_EN_MASK (0x1U << CRU_GATE_CON08_CLK_CRYPTO_NS_CORE_EN_SHIFT) /* 0x00002000 */
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#define CRU_GATE_CON08_CLK_CRYPTO_NS_PKA_EN_SHIFT (14U)
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#define CRU_GATE_CON08_CLK_CRYPTO_NS_PKA_EN_MASK (0x1U << CRU_GATE_CON08_CLK_CRYPTO_NS_PKA_EN_SHIFT) /* 0x00004000 */
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#define CRU_GATE_CON08_CLK_CRYPTO_NS_RNG_EN_SHIFT (15U)
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#define CRU_GATE_CON08_CLK_CRYPTO_NS_RNG_EN_MASK (0x1U << CRU_GATE_CON08_CLK_CRYPTO_NS_RNG_EN_SHIFT) /* 0x00008000 */
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/* GATE_CON09 */
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#define CRU_GATE_CON09_OFFSET (0x324U)
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#define CRU_GATE_CON09_HCLK_NANDC_EN_SHIFT (0U)
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#define CRU_GATE_CON09_HCLK_NANDC_EN_MASK (0x1U << CRU_GATE_CON09_HCLK_NANDC_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON09_NCLK_NANDC_EN_SHIFT (1U)
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#define CRU_GATE_CON09_NCLK_NANDC_EN_MASK (0x1U << CRU_GATE_CON09_NCLK_NANDC_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON09_HCLK_SFC_EN_SHIFT (2U)
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#define CRU_GATE_CON09_HCLK_SFC_EN_MASK (0x1U << CRU_GATE_CON09_HCLK_SFC_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON09_HCLK_SFC_XIP_EN_SHIFT (3U)
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#define CRU_GATE_CON09_HCLK_SFC_XIP_EN_MASK (0x1U << CRU_GATE_CON09_HCLK_SFC_XIP_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON09_SCLK_SFC_EN_SHIFT (4U)
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#define CRU_GATE_CON09_SCLK_SFC_EN_MASK (0x1U << CRU_GATE_CON09_SCLK_SFC_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON09_ACLK_EMMC_EN_SHIFT (5U)
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#define CRU_GATE_CON09_ACLK_EMMC_EN_MASK (0x1U << CRU_GATE_CON09_ACLK_EMMC_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON09_HCLK_EMMC_EN_SHIFT (6U)
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#define CRU_GATE_CON09_HCLK_EMMC_EN_MASK (0x1U << CRU_GATE_CON09_HCLK_EMMC_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON09_BCLK_EMMC_EN_SHIFT (7U)
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#define CRU_GATE_CON09_BCLK_EMMC_EN_MASK (0x1U << CRU_GATE_CON09_BCLK_EMMC_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON09_CCLK_EMMC_EN_SHIFT (8U)
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#define CRU_GATE_CON09_CCLK_EMMC_EN_MASK (0x1U << CRU_GATE_CON09_CCLK_EMMC_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON09_TCLK_EMMC_EN_SHIFT (9U)
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#define CRU_GATE_CON09_TCLK_EMMC_EN_MASK (0x1U << CRU_GATE_CON09_TCLK_EMMC_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON09_HCLK_TRNG_NS_EN_SHIFT (10U)
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#define CRU_GATE_CON09_HCLK_TRNG_NS_EN_MASK (0x1U << CRU_GATE_CON09_HCLK_TRNG_NS_EN_SHIFT) /* 0x00000400 */
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#define CRU_GATE_CON09_CLK_TRNG_NS_EN_SHIFT (11U)
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#define CRU_GATE_CON09_CLK_TRNG_NS_EN_MASK (0x1U << CRU_GATE_CON09_CLK_TRNG_NS_EN_SHIFT) /* 0x00000800 */
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/* GATE_CON10 */
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#define CRU_GATE_CON10_OFFSET (0x328U)
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#define CRU_GATE_CON10_ACLK_PIPE_EN_SHIFT (0U)
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#define CRU_GATE_CON10_ACLK_PIPE_EN_MASK (0x1U << CRU_GATE_CON10_ACLK_PIPE_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON10_PCLK_PIPE_EN_SHIFT (1U)
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#define CRU_GATE_CON10_PCLK_PIPE_EN_MASK (0x1U << CRU_GATE_CON10_PCLK_PIPE_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON10_ACLK_PIPE_NIU_EN_SHIFT (2U)
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#define CRU_GATE_CON10_ACLK_PIPE_NIU_EN_MASK (0x1U << CRU_GATE_CON10_ACLK_PIPE_NIU_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON10_PCLK_PIPE_NIU_EN_SHIFT (3U)
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#define CRU_GATE_CON10_PCLK_PIPE_NIU_EN_MASK (0x1U << CRU_GATE_CON10_PCLK_PIPE_NIU_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON10_CLK_XPCS_EEE_EN_SHIFT (4U)
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#define CRU_GATE_CON10_CLK_XPCS_EEE_EN_MASK (0x1U << CRU_GATE_CON10_CLK_XPCS_EEE_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON10_CLK_XPCS_RX_DIV10_EN_SHIFT (5U)
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#define CRU_GATE_CON10_CLK_XPCS_RX_DIV10_EN_MASK (0x1U << CRU_GATE_CON10_CLK_XPCS_RX_DIV10_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON10_CLK_XPCS_TX_DIV10_EN_SHIFT (6U)
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#define CRU_GATE_CON10_CLK_XPCS_TX_DIV10_EN_MASK (0x1U << CRU_GATE_CON10_CLK_XPCS_TX_DIV10_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON10_PCLK_PIPE_GRF_EN_SHIFT (7U)
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#define CRU_GATE_CON10_PCLK_PIPE_GRF_EN_MASK (0x1U << CRU_GATE_CON10_PCLK_PIPE_GRF_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON10_ACLK_USB3OTG0_EN_SHIFT (8U)
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#define CRU_GATE_CON10_ACLK_USB3OTG0_EN_MASK (0x1U << CRU_GATE_CON10_ACLK_USB3OTG0_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON10_CLK_USB3OTG0_REF_EN_SHIFT (9U)
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#define CRU_GATE_CON10_CLK_USB3OTG0_REF_EN_MASK (0x1U << CRU_GATE_CON10_CLK_USB3OTG0_REF_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON10_CLK_USB3OTG0_SUSPEND_EN_SHIFT (10U)
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#define CRU_GATE_CON10_CLK_USB3OTG0_SUSPEND_EN_MASK (0x1U << CRU_GATE_CON10_CLK_USB3OTG0_SUSPEND_EN_SHIFT) /* 0x00000400 */
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#define CRU_GATE_CON10_CLK_USB3OTG0_PIPE_EN_SHIFT (11U)
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#define CRU_GATE_CON10_CLK_USB3OTG0_PIPE_EN_MASK (0x1U << CRU_GATE_CON10_CLK_USB3OTG0_PIPE_EN_SHIFT) /* 0x00000800 */
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#define CRU_GATE_CON10_ACLK_USB3OTG1_EN_SHIFT (12U)
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#define CRU_GATE_CON10_ACLK_USB3OTG1_EN_MASK (0x1U << CRU_GATE_CON10_ACLK_USB3OTG1_EN_SHIFT) /* 0x00001000 */
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#define CRU_GATE_CON10_CLK_USB3OTG1_REF_EN_SHIFT (13U)
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#define CRU_GATE_CON10_CLK_USB3OTG1_REF_EN_MASK (0x1U << CRU_GATE_CON10_CLK_USB3OTG1_REF_EN_SHIFT) /* 0x00002000 */
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#define CRU_GATE_CON10_CLK_USB3OTG1_SUSPEND_EN_SHIFT (14U)
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#define CRU_GATE_CON10_CLK_USB3OTG1_SUSPEND_EN_MASK (0x1U << CRU_GATE_CON10_CLK_USB3OTG1_SUSPEND_EN_SHIFT) /* 0x00004000 */
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#define CRU_GATE_CON10_CLK_USB3OTG1_PIPE_EN_SHIFT (15U)
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#define CRU_GATE_CON10_CLK_USB3OTG1_PIPE_EN_MASK (0x1U << CRU_GATE_CON10_CLK_USB3OTG1_PIPE_EN_SHIFT) /* 0x00008000 */
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/* GATE_CON11 */
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#define CRU_GATE_CON11_OFFSET (0x32CU)
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#define CRU_GATE_CON11_ACLK_SATA0_EN_SHIFT (0U)
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#define CRU_GATE_CON11_ACLK_SATA0_EN_MASK (0x1U << CRU_GATE_CON11_ACLK_SATA0_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON11_CLK_SATA0_PMALIVE_EN_SHIFT (1U)
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#define CRU_GATE_CON11_CLK_SATA0_PMALIVE_EN_MASK (0x1U << CRU_GATE_CON11_CLK_SATA0_PMALIVE_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON11_CLK_SATA0_RXOOB_EN_SHIFT (2U)
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#define CRU_GATE_CON11_CLK_SATA0_RXOOB_EN_MASK (0x1U << CRU_GATE_CON11_CLK_SATA0_RXOOB_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON11_CLK_SATA0_PIPE_EN_SHIFT (3U)
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#define CRU_GATE_CON11_CLK_SATA0_PIPE_EN_MASK (0x1U << CRU_GATE_CON11_CLK_SATA0_PIPE_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON11_ACLK_SATA1_EN_SHIFT (4U)
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#define CRU_GATE_CON11_ACLK_SATA1_EN_MASK (0x1U << CRU_GATE_CON11_ACLK_SATA1_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON11_CLK_SATA1_PMALIVE_EN_SHIFT (5U)
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#define CRU_GATE_CON11_CLK_SATA1_PMALIVE_EN_MASK (0x1U << CRU_GATE_CON11_CLK_SATA1_PMALIVE_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON11_CLK_SATA1_RXOOB_EN_SHIFT (6U)
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#define CRU_GATE_CON11_CLK_SATA1_RXOOB_EN_MASK (0x1U << CRU_GATE_CON11_CLK_SATA1_RXOOB_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON11_CLK_SATA1_PIPE_EN_SHIFT (7U)
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#define CRU_GATE_CON11_CLK_SATA1_PIPE_EN_MASK (0x1U << CRU_GATE_CON11_CLK_SATA1_PIPE_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON11_ACLK_SATA2_EN_SHIFT (8U)
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#define CRU_GATE_CON11_ACLK_SATA2_EN_MASK (0x1U << CRU_GATE_CON11_ACLK_SATA2_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON11_CLK_SATA2_PMALIVE_EN_SHIFT (9U)
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#define CRU_GATE_CON11_CLK_SATA2_PMALIVE_EN_MASK (0x1U << CRU_GATE_CON11_CLK_SATA2_PMALIVE_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON11_CLK_SATA2_RXOOB_EN_SHIFT (10U)
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#define CRU_GATE_CON11_CLK_SATA2_RXOOB_EN_MASK (0x1U << CRU_GATE_CON11_CLK_SATA2_RXOOB_EN_SHIFT) /* 0x00000400 */
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#define CRU_GATE_CON11_CLK_SATA2_PIPE_EN_SHIFT (11U)
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#define CRU_GATE_CON11_CLK_SATA2_PIPE_EN_MASK (0x1U << CRU_GATE_CON11_CLK_SATA2_PIPE_EN_SHIFT) /* 0x00000800 */
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/* GATE_CON12 */
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#define CRU_GATE_CON12_OFFSET (0x330U)
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#define CRU_GATE_CON12_ACLK_PCIE20_MST_EN_SHIFT (0U)
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#define CRU_GATE_CON12_ACLK_PCIE20_MST_EN_MASK (0x1U << CRU_GATE_CON12_ACLK_PCIE20_MST_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON12_ACLK_PCIE20_SLV_EN_SHIFT (1U)
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#define CRU_GATE_CON12_ACLK_PCIE20_SLV_EN_MASK (0x1U << CRU_GATE_CON12_ACLK_PCIE20_SLV_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON12_ACLK_PCIE20_DBI_EN_SHIFT (2U)
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#define CRU_GATE_CON12_ACLK_PCIE20_DBI_EN_MASK (0x1U << CRU_GATE_CON12_ACLK_PCIE20_DBI_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON12_PCLK_PCIE20_EN_SHIFT (3U)
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#define CRU_GATE_CON12_PCLK_PCIE20_EN_MASK (0x1U << CRU_GATE_CON12_PCLK_PCIE20_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON12_CLK_PCIE20_AUX_EN_SHIFT (4U)
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#define CRU_GATE_CON12_CLK_PCIE20_AUX_EN_MASK (0x1U << CRU_GATE_CON12_CLK_PCIE20_AUX_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON12_CLK_PCIE20_PIPE_EN_SHIFT (5U)
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#define CRU_GATE_CON12_CLK_PCIE20_PIPE_EN_MASK (0x1U << CRU_GATE_CON12_CLK_PCIE20_PIPE_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON12_ACLK_PCIE30X1_MST_EN_SHIFT (8U)
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#define CRU_GATE_CON12_ACLK_PCIE30X1_MST_EN_MASK (0x1U << CRU_GATE_CON12_ACLK_PCIE30X1_MST_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON12_ACLK_PCIE30X1_SLV_EN_SHIFT (9U)
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#define CRU_GATE_CON12_ACLK_PCIE30X1_SLV_EN_MASK (0x1U << CRU_GATE_CON12_ACLK_PCIE30X1_SLV_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON12_ACLK_PCIE30X1_DBI_EN_SHIFT (10U)
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#define CRU_GATE_CON12_ACLK_PCIE30X1_DBI_EN_MASK (0x1U << CRU_GATE_CON12_ACLK_PCIE30X1_DBI_EN_SHIFT) /* 0x00000400 */
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#define CRU_GATE_CON12_PCLK_PCIE30X1_EN_SHIFT (11U)
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#define CRU_GATE_CON12_PCLK_PCIE30X1_EN_MASK (0x1U << CRU_GATE_CON12_PCLK_PCIE30X1_EN_SHIFT) /* 0x00000800 */
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#define CRU_GATE_CON12_CLK_PCIE30X1_AUX_EN_SHIFT (12U)
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#define CRU_GATE_CON12_CLK_PCIE30X1_AUX_EN_MASK (0x1U << CRU_GATE_CON12_CLK_PCIE30X1_AUX_EN_SHIFT) /* 0x00001000 */
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#define CRU_GATE_CON12_CLK_PCIE30X1_PIPE_EN_SHIFT (13U)
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#define CRU_GATE_CON12_CLK_PCIE30X1_PIPE_EN_MASK (0x1U << CRU_GATE_CON12_CLK_PCIE30X1_PIPE_EN_SHIFT) /* 0x00002000 */
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/* GATE_CON13 */
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#define CRU_GATE_CON13_OFFSET (0x334U)
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#define CRU_GATE_CON13_ACLK_PCIE30X2_MST_EN_SHIFT (0U)
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#define CRU_GATE_CON13_ACLK_PCIE30X2_MST_EN_MASK (0x1U << CRU_GATE_CON13_ACLK_PCIE30X2_MST_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON13_ACLK_PCIE30X2_SLV_EN_SHIFT (1U)
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#define CRU_GATE_CON13_ACLK_PCIE30X2_SLV_EN_MASK (0x1U << CRU_GATE_CON13_ACLK_PCIE30X2_SLV_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON13_ACLK_PCIE30X2_DBI_EN_SHIFT (2U)
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#define CRU_GATE_CON13_ACLK_PCIE30X2_DBI_EN_MASK (0x1U << CRU_GATE_CON13_ACLK_PCIE30X2_DBI_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON13_PCLK_PCIE30X2_EN_SHIFT (3U)
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#define CRU_GATE_CON13_PCLK_PCIE30X2_EN_MASK (0x1U << CRU_GATE_CON13_PCLK_PCIE30X2_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON13_CLK_PCIE30X2_AUX_EN_SHIFT (4U)
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#define CRU_GATE_CON13_CLK_PCIE30X2_AUX_EN_MASK (0x1U << CRU_GATE_CON13_CLK_PCIE30X2_AUX_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON13_CLK_PCIE30X2_PIPE_EN_SHIFT (5U)
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#define CRU_GATE_CON13_CLK_PCIE30X2_PIPE_EN_MASK (0x1U << CRU_GATE_CON13_CLK_PCIE30X2_PIPE_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON13_PCLK_XPCS_EN_SHIFT (6U)
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#define CRU_GATE_CON13_PCLK_XPCS_EN_MASK (0x1U << CRU_GATE_CON13_PCLK_XPCS_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON13_CLK_XPCS_QSGMII_TX_EN_SHIFT (7U)
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#define CRU_GATE_CON13_CLK_XPCS_QSGMII_TX_EN_MASK (0x1U << CRU_GATE_CON13_CLK_XPCS_QSGMII_TX_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON13_CLK_XPCS_QSGMII_RX_EN_SHIFT (8U)
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#define CRU_GATE_CON13_CLK_XPCS_QSGMII_RX_EN_MASK (0x1U << CRU_GATE_CON13_CLK_XPCS_QSGMII_RX_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON13_CLK_XPCS_XGXS_TX_EN_SHIFT (9U)
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#define CRU_GATE_CON13_CLK_XPCS_XGXS_TX_EN_MASK (0x1U << CRU_GATE_CON13_CLK_XPCS_XGXS_TX_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON13_CLK_XPCS_XGXS_RX_EN_SHIFT (11U)
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#define CRU_GATE_CON13_CLK_XPCS_XGXS_RX_EN_MASK (0x1U << CRU_GATE_CON13_CLK_XPCS_XGXS_RX_EN_SHIFT) /* 0x00000800 */
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#define CRU_GATE_CON13_CLK_XPCS_MII0_TX_EN_SHIFT (12U)
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#define CRU_GATE_CON13_CLK_XPCS_MII0_TX_EN_MASK (0x1U << CRU_GATE_CON13_CLK_XPCS_MII0_TX_EN_SHIFT) /* 0x00001000 */
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#define CRU_GATE_CON13_CLK_XPCS_MII0_RX_EN_SHIFT (13U)
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#define CRU_GATE_CON13_CLK_XPCS_MII0_RX_EN_MASK (0x1U << CRU_GATE_CON13_CLK_XPCS_MII0_RX_EN_SHIFT) /* 0x00002000 */
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#define CRU_GATE_CON13_CLK_XPCS_MII1_TX_EN_SHIFT (14U)
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#define CRU_GATE_CON13_CLK_XPCS_MII1_TX_EN_MASK (0x1U << CRU_GATE_CON13_CLK_XPCS_MII1_TX_EN_SHIFT) /* 0x00004000 */
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#define CRU_GATE_CON13_CLK_XPCS_MII1_RX_EN_SHIFT (15U)
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#define CRU_GATE_CON13_CLK_XPCS_MII1_RX_EN_MASK (0x1U << CRU_GATE_CON13_CLK_XPCS_MII1_RX_EN_SHIFT) /* 0x00008000 */
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/* GATE_CON14 */
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#define CRU_GATE_CON14_OFFSET (0x338U)
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#define CRU_GATE_CON14_ACLK_PERIMID_EN_SHIFT (0U)
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#define CRU_GATE_CON14_ACLK_PERIMID_EN_MASK (0x1U << CRU_GATE_CON14_ACLK_PERIMID_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON14_HCLK_PERIMID_EN_SHIFT (1U)
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#define CRU_GATE_CON14_HCLK_PERIMID_EN_MASK (0x1U << CRU_GATE_CON14_HCLK_PERIMID_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON14_ACLK_PERIMID_NIU_EN_SHIFT (2U)
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#define CRU_GATE_CON14_ACLK_PERIMID_NIU_EN_MASK (0x1U << CRU_GATE_CON14_ACLK_PERIMID_NIU_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON14_HCLK_PERIMID_NIU_EN_SHIFT (3U)
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#define CRU_GATE_CON14_HCLK_PERIMID_NIU_EN_MASK (0x1U << CRU_GATE_CON14_HCLK_PERIMID_NIU_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON14_ACLK_PHP_EN_SHIFT (8U)
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#define CRU_GATE_CON14_ACLK_PHP_EN_MASK (0x1U << CRU_GATE_CON14_ACLK_PHP_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON14_HCLK_PHP_EN_SHIFT (9U)
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#define CRU_GATE_CON14_HCLK_PHP_EN_MASK (0x1U << CRU_GATE_CON14_HCLK_PHP_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON14_PCLK_PHP_EN_SHIFT (10U)
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#define CRU_GATE_CON14_PCLK_PHP_EN_MASK (0x1U << CRU_GATE_CON14_PCLK_PHP_EN_SHIFT) /* 0x00000400 */
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#define CRU_GATE_CON14_ACLK_PHP_NIU_EN_SHIFT (11U)
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#define CRU_GATE_CON14_ACLK_PHP_NIU_EN_MASK (0x1U << CRU_GATE_CON14_ACLK_PHP_NIU_EN_SHIFT) /* 0x00000800 */
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#define CRU_GATE_CON14_HCLK_PHP_NIU_EN_SHIFT (12U)
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#define CRU_GATE_CON14_HCLK_PHP_NIU_EN_MASK (0x1U << CRU_GATE_CON14_HCLK_PHP_NIU_EN_SHIFT) /* 0x00001000 */
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#define CRU_GATE_CON14_PCLK_PHP_NIU_EN_SHIFT (13U)
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#define CRU_GATE_CON14_PCLK_PHP_NIU_EN_MASK (0x1U << CRU_GATE_CON14_PCLK_PHP_NIU_EN_SHIFT) /* 0x00002000 */
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/* GATE_CON15 */
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#define CRU_GATE_CON15_OFFSET (0x33CU)
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#define CRU_GATE_CON15_HCLK_SDMMC0_EN_SHIFT (0U)
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#define CRU_GATE_CON15_HCLK_SDMMC0_EN_MASK (0x1U << CRU_GATE_CON15_HCLK_SDMMC0_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON15_CLK_SDMMC0_EN_SHIFT (1U)
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#define CRU_GATE_CON15_CLK_SDMMC0_EN_MASK (0x1U << CRU_GATE_CON15_CLK_SDMMC0_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON15_HCLK_SDMMC1_EN_SHIFT (2U)
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#define CRU_GATE_CON15_HCLK_SDMMC1_EN_MASK (0x1U << CRU_GATE_CON15_HCLK_SDMMC1_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON15_CLK_SDMMC1_EN_SHIFT (3U)
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#define CRU_GATE_CON15_CLK_SDMMC1_EN_MASK (0x1U << CRU_GATE_CON15_CLK_SDMMC1_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON15_CLK_GMAC0_PTP_REF_EN_SHIFT (4U)
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#define CRU_GATE_CON15_CLK_GMAC0_PTP_REF_EN_MASK (0x1U << CRU_GATE_CON15_CLK_GMAC0_PTP_REF_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON15_ACLK_GMAC0_EN_SHIFT (5U)
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#define CRU_GATE_CON15_ACLK_GMAC0_EN_MASK (0x1U << CRU_GATE_CON15_ACLK_GMAC0_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON15_PCLK_GMAC0_EN_SHIFT (6U)
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#define CRU_GATE_CON15_PCLK_GMAC0_EN_MASK (0x1U << CRU_GATE_CON15_PCLK_GMAC0_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON15_CLK_MAC0_2TOP_EN_SHIFT (7U)
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#define CRU_GATE_CON15_CLK_MAC0_2TOP_EN_MASK (0x1U << CRU_GATE_CON15_CLK_MAC0_2TOP_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON15_CLK_MAC0_OUT_EN_SHIFT (8U)
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#define CRU_GATE_CON15_CLK_MAC0_OUT_EN_MASK (0x1U << CRU_GATE_CON15_CLK_MAC0_OUT_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON15_CLK_MAC0_REFOUT_EN_SHIFT (12U)
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#define CRU_GATE_CON15_CLK_MAC0_REFOUT_EN_MASK (0x1U << CRU_GATE_CON15_CLK_MAC0_REFOUT_EN_SHIFT) /* 0x00001000 */
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/* GATE_CON16 */
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#define CRU_GATE_CON16_OFFSET (0x340U)
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#define CRU_GATE_CON16_ACLK_USB_EN_SHIFT (0U)
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#define CRU_GATE_CON16_ACLK_USB_EN_MASK (0x1U << CRU_GATE_CON16_ACLK_USB_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON16_HCLK_USB_EN_SHIFT (1U)
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#define CRU_GATE_CON16_HCLK_USB_EN_MASK (0x1U << CRU_GATE_CON16_HCLK_USB_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON16_PCLK_USB_EN_SHIFT (2U)
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#define CRU_GATE_CON16_PCLK_USB_EN_MASK (0x1U << CRU_GATE_CON16_PCLK_USB_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON16_ACLK_USB_NIU_EN_SHIFT (3U)
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#define CRU_GATE_CON16_ACLK_USB_NIU_EN_MASK (0x1U << CRU_GATE_CON16_ACLK_USB_NIU_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON16_HCLK_USB_NIU_EN_SHIFT (4U)
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#define CRU_GATE_CON16_HCLK_USB_NIU_EN_MASK (0x1U << CRU_GATE_CON16_HCLK_USB_NIU_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON16_PCLK_USB_NIU_EN_SHIFT (5U)
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#define CRU_GATE_CON16_PCLK_USB_NIU_EN_MASK (0x1U << CRU_GATE_CON16_PCLK_USB_NIU_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON16_PCLK_USB_GRF_EN_SHIFT (6U)
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#define CRU_GATE_CON16_PCLK_USB_GRF_EN_MASK (0x1U << CRU_GATE_CON16_PCLK_USB_GRF_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON16_HCLK_USB2HOST0_EN_SHIFT (12U)
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#define CRU_GATE_CON16_HCLK_USB2HOST0_EN_MASK (0x1U << CRU_GATE_CON16_HCLK_USB2HOST0_EN_SHIFT) /* 0x00001000 */
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#define CRU_GATE_CON16_HCLK_USB2HOST0_ARB_EN_SHIFT (13U)
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#define CRU_GATE_CON16_HCLK_USB2HOST0_ARB_EN_MASK (0x1U << CRU_GATE_CON16_HCLK_USB2HOST0_ARB_EN_SHIFT) /* 0x00002000 */
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#define CRU_GATE_CON16_HCLK_USB2HOST1_EN_SHIFT (14U)
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#define CRU_GATE_CON16_HCLK_USB2HOST1_EN_MASK (0x1U << CRU_GATE_CON16_HCLK_USB2HOST1_EN_SHIFT) /* 0x00004000 */
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#define CRU_GATE_CON16_HCLK_USB2HOST1_ARB_EN_SHIFT (15U)
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#define CRU_GATE_CON16_HCLK_USB2HOST1_ARB_EN_MASK (0x1U << CRU_GATE_CON16_HCLK_USB2HOST1_ARB_EN_SHIFT) /* 0x00008000 */
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/* GATE_CON17 */
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#define CRU_GATE_CON17_OFFSET (0x344U)
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#define CRU_GATE_CON17_HCLK_SDMMC2_EN_SHIFT (0U)
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#define CRU_GATE_CON17_HCLK_SDMMC2_EN_MASK (0x1U << CRU_GATE_CON17_HCLK_SDMMC2_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON17_CLK_SDMMC2_EN_SHIFT (1U)
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#define CRU_GATE_CON17_CLK_SDMMC2_EN_MASK (0x1U << CRU_GATE_CON17_CLK_SDMMC2_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON17_CLK_GMAC1_PTP_REF_EN_SHIFT (2U)
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#define CRU_GATE_CON17_CLK_GMAC1_PTP_REF_EN_MASK (0x1U << CRU_GATE_CON17_CLK_GMAC1_PTP_REF_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON17_ACLK_GMAC1_EN_SHIFT (3U)
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#define CRU_GATE_CON17_ACLK_GMAC1_EN_MASK (0x1U << CRU_GATE_CON17_ACLK_GMAC1_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON17_PCLK_GMAC1_EN_SHIFT (4U)
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#define CRU_GATE_CON17_PCLK_GMAC1_EN_MASK (0x1U << CRU_GATE_CON17_PCLK_GMAC1_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON17_CLK_MAC1_2TOP_EN_SHIFT (5U)
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#define CRU_GATE_CON17_CLK_MAC1_2TOP_EN_MASK (0x1U << CRU_GATE_CON17_CLK_MAC1_2TOP_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON17_CLK_MAC1_OUT_EN_SHIFT (6U)
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#define CRU_GATE_CON17_CLK_MAC1_OUT_EN_MASK (0x1U << CRU_GATE_CON17_CLK_MAC1_OUT_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON17_CLK_MAC1_REFOUT_EN_SHIFT (10U)
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#define CRU_GATE_CON17_CLK_MAC1_REFOUT_EN_MASK (0x1U << CRU_GATE_CON17_CLK_MAC1_REFOUT_EN_SHIFT) /* 0x00000400 */
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/* GATE_CON18 */
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#define CRU_GATE_CON18_OFFSET (0x348U)
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#define CRU_GATE_CON18_ACLK_VI_EN_SHIFT (0U)
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#define CRU_GATE_CON18_ACLK_VI_EN_MASK (0x1U << CRU_GATE_CON18_ACLK_VI_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON18_HCLK_VI_EN_SHIFT (1U)
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#define CRU_GATE_CON18_HCLK_VI_EN_MASK (0x1U << CRU_GATE_CON18_HCLK_VI_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON18_PCLK_VI_EN_SHIFT (2U)
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#define CRU_GATE_CON18_PCLK_VI_EN_MASK (0x1U << CRU_GATE_CON18_PCLK_VI_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON18_ACLK_VI_NIU_EN_SHIFT (3U)
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#define CRU_GATE_CON18_ACLK_VI_NIU_EN_MASK (0x1U << CRU_GATE_CON18_ACLK_VI_NIU_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON18_HCLK_VI_NIU_EN_SHIFT (4U)
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#define CRU_GATE_CON18_HCLK_VI_NIU_EN_MASK (0x1U << CRU_GATE_CON18_HCLK_VI_NIU_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON18_PCLK_VI_NIU_EN_SHIFT (5U)
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#define CRU_GATE_CON18_PCLK_VI_NIU_EN_MASK (0x1U << CRU_GATE_CON18_PCLK_VI_NIU_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON18_ACLK_VICAP1_EN_SHIFT (9U)
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#define CRU_GATE_CON18_ACLK_VICAP1_EN_MASK (0x1U << CRU_GATE_CON18_ACLK_VICAP1_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON18_HCLK_VICAP1_EN_SHIFT (10U)
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#define CRU_GATE_CON18_HCLK_VICAP1_EN_MASK (0x1U << CRU_GATE_CON18_HCLK_VICAP1_EN_SHIFT) /* 0x00000400 */
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#define CRU_GATE_CON18_DCLK_VICAP1_EN_SHIFT (11U)
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#define CRU_GATE_CON18_DCLK_VICAP1_EN_MASK (0x1U << CRU_GATE_CON18_DCLK_VICAP1_EN_SHIFT) /* 0x00000800 */
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/* GATE_CON19 */
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#define CRU_GATE_CON19_OFFSET (0x34CU)
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#define CRU_GATE_CON19_ACLK_ISP_EN_SHIFT (0U)
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#define CRU_GATE_CON19_ACLK_ISP_EN_MASK (0x1U << CRU_GATE_CON19_ACLK_ISP_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON19_HCLK_ISP_EN_SHIFT (1U)
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#define CRU_GATE_CON19_HCLK_ISP_EN_MASK (0x1U << CRU_GATE_CON19_HCLK_ISP_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON19_CLK_ISP_EN_SHIFT (2U)
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#define CRU_GATE_CON19_CLK_ISP_EN_MASK (0x1U << CRU_GATE_CON19_CLK_ISP_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON19_PCLK_CSI2HOST1_EN_SHIFT (4U)
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#define CRU_GATE_CON19_PCLK_CSI2HOST1_EN_MASK (0x1U << CRU_GATE_CON19_PCLK_CSI2HOST1_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON19_CLK_CIF_OUT_EN_SHIFT (8U)
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#define CRU_GATE_CON19_CLK_CIF_OUT_EN_MASK (0x1U << CRU_GATE_CON19_CLK_CIF_OUT_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON19_CLK_CAM0_OUT_EN_SHIFT (9U)
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#define CRU_GATE_CON19_CLK_CAM0_OUT_EN_MASK (0x1U << CRU_GATE_CON19_CLK_CAM0_OUT_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON19_CLK_CAM1_OUT_EN_SHIFT (10U)
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#define CRU_GATE_CON19_CLK_CAM1_OUT_EN_MASK (0x1U << CRU_GATE_CON19_CLK_CAM1_OUT_EN_SHIFT) /* 0x00000400 */
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/* GATE_CON20 */
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#define CRU_GATE_CON20_OFFSET (0x350U)
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#define CRU_GATE_CON20_HCLK_VO_EN_SHIFT (1U)
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#define CRU_GATE_CON20_HCLK_VO_EN_MASK (0x1U << CRU_GATE_CON20_HCLK_VO_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON20_PCLK_VO_EN_SHIFT (2U)
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#define CRU_GATE_CON20_PCLK_VO_EN_MASK (0x1U << CRU_GATE_CON20_PCLK_VO_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON20_ACLK_VO_NIU_EN_SHIFT (3U)
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#define CRU_GATE_CON20_ACLK_VO_NIU_EN_MASK (0x1U << CRU_GATE_CON20_ACLK_VO_NIU_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON20_HCLK_VO_NIU_EN_SHIFT (4U)
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#define CRU_GATE_CON20_HCLK_VO_NIU_EN_MASK (0x1U << CRU_GATE_CON20_HCLK_VO_NIU_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON20_PCLK_VO_NIU_EN_SHIFT (5U)
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#define CRU_GATE_CON20_PCLK_VO_NIU_EN_MASK (0x1U << CRU_GATE_CON20_PCLK_VO_NIU_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON20_ACLK_VOP_PRE_EN_SHIFT (6U)
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#define CRU_GATE_CON20_ACLK_VOP_PRE_EN_MASK (0x1U << CRU_GATE_CON20_ACLK_VOP_PRE_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON20_ACLK_VOP_NIU_EN_SHIFT (7U)
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#define CRU_GATE_CON20_ACLK_VOP_NIU_EN_MASK (0x1U << CRU_GATE_CON20_ACLK_VOP_NIU_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON20_ACLK_VOP_EN_SHIFT (8U)
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#define CRU_GATE_CON20_ACLK_VOP_EN_MASK (0x1U << CRU_GATE_CON20_ACLK_VOP_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON20_HCLK_VOP_EN_SHIFT (9U)
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#define CRU_GATE_CON20_HCLK_VOP_EN_MASK (0x1U << CRU_GATE_CON20_HCLK_VOP_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON20_DCLK0_VOP_EN_SHIFT (10U)
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#define CRU_GATE_CON20_DCLK0_VOP_EN_MASK (0x1U << CRU_GATE_CON20_DCLK0_VOP_EN_SHIFT) /* 0x00000400 */
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#define CRU_GATE_CON20_DCLK1_VOP_EN_SHIFT (11U)
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#define CRU_GATE_CON20_DCLK1_VOP_EN_MASK (0x1U << CRU_GATE_CON20_DCLK1_VOP_EN_SHIFT) /* 0x00000800 */
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#define CRU_GATE_CON20_DCLK2_VOP_EN_SHIFT (12U)
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#define CRU_GATE_CON20_DCLK2_VOP_EN_MASK (0x1U << CRU_GATE_CON20_DCLK2_VOP_EN_SHIFT) /* 0x00001000 */
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#define CRU_GATE_CON20_CLK_VOP_PWM_EN_SHIFT (13U)
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#define CRU_GATE_CON20_CLK_VOP_PWM_EN_MASK (0x1U << CRU_GATE_CON20_CLK_VOP_PWM_EN_SHIFT) /* 0x00002000 */
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/* GATE_CON21 */
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#define CRU_GATE_CON21_OFFSET (0x354U)
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#define CRU_GATE_CON21_ACLK_HDCP_EN_SHIFT (0U)
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#define CRU_GATE_CON21_ACLK_HDCP_EN_MASK (0x1U << CRU_GATE_CON21_ACLK_HDCP_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON21_HCLK_HDCP_EN_SHIFT (1U)
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#define CRU_GATE_CON21_HCLK_HDCP_EN_MASK (0x1U << CRU_GATE_CON21_HCLK_HDCP_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON21_PCLK_HDCP_EN_SHIFT (2U)
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#define CRU_GATE_CON21_PCLK_HDCP_EN_MASK (0x1U << CRU_GATE_CON21_PCLK_HDCP_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON21_PCLK_HDMI_HOST_EN_SHIFT (3U)
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#define CRU_GATE_CON21_PCLK_HDMI_HOST_EN_MASK (0x1U << CRU_GATE_CON21_PCLK_HDMI_HOST_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON21_CLK_HDMI_SFR_EN_SHIFT (4U)
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#define CRU_GATE_CON21_CLK_HDMI_SFR_EN_MASK (0x1U << CRU_GATE_CON21_CLK_HDMI_SFR_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON21_CLK_HDMI_CEC_EN_SHIFT (5U)
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#define CRU_GATE_CON21_CLK_HDMI_CEC_EN_MASK (0x1U << CRU_GATE_CON21_CLK_HDMI_CEC_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON21_PCLK_DSITX_0_EN_SHIFT (6U)
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#define CRU_GATE_CON21_PCLK_DSITX_0_EN_MASK (0x1U << CRU_GATE_CON21_PCLK_DSITX_0_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON21_PCLK_DSITX_1_EN_SHIFT (7U)
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#define CRU_GATE_CON21_PCLK_DSITX_1_EN_MASK (0x1U << CRU_GATE_CON21_PCLK_DSITX_1_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON21_PCLK_EDP_CTRL_EN_SHIFT (8U)
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#define CRU_GATE_CON21_PCLK_EDP_CTRL_EN_MASK (0x1U << CRU_GATE_CON21_PCLK_EDP_CTRL_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON21_CLK_EDP_200M_EN_SHIFT (9U)
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#define CRU_GATE_CON21_CLK_EDP_200M_EN_MASK (0x1U << CRU_GATE_CON21_CLK_EDP_200M_EN_SHIFT) /* 0x00000200 */
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/* GATE_CON22 */
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#define CRU_GATE_CON22_OFFSET (0x358U)
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#define CRU_GATE_CON22_ACLK_VPU_PRE_EN_SHIFT (0U)
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#define CRU_GATE_CON22_ACLK_VPU_PRE_EN_MASK (0x1U << CRU_GATE_CON22_ACLK_VPU_PRE_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON22_HCLK_VPU_PRE_EN_SHIFT (1U)
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#define CRU_GATE_CON22_HCLK_VPU_PRE_EN_MASK (0x1U << CRU_GATE_CON22_HCLK_VPU_PRE_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON22_ACLK_VPU_NIU_EN_SHIFT (2U)
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#define CRU_GATE_CON22_ACLK_VPU_NIU_EN_MASK (0x1U << CRU_GATE_CON22_ACLK_VPU_NIU_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON22_HCLK_VPU_NIU_EN_SHIFT (3U)
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#define CRU_GATE_CON22_HCLK_VPU_NIU_EN_MASK (0x1U << CRU_GATE_CON22_HCLK_VPU_NIU_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON22_ACLK_VPU_EN_SHIFT (4U)
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#define CRU_GATE_CON22_ACLK_VPU_EN_MASK (0x1U << CRU_GATE_CON22_ACLK_VPU_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON22_HCLK_VPU_EN_SHIFT (5U)
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#define CRU_GATE_CON22_HCLK_VPU_EN_MASK (0x1U << CRU_GATE_CON22_HCLK_VPU_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON22_PCLK_RGA_PRE_EN_SHIFT (12U)
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#define CRU_GATE_CON22_PCLK_RGA_PRE_EN_MASK (0x1U << CRU_GATE_CON22_PCLK_RGA_PRE_EN_SHIFT) /* 0x00001000 */
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#define CRU_GATE_CON22_PCLK_RGA_NIU_EN_SHIFT (13U)
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#define CRU_GATE_CON22_PCLK_RGA_NIU_EN_MASK (0x1U << CRU_GATE_CON22_PCLK_RGA_NIU_EN_SHIFT) /* 0x00002000 */
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#define CRU_GATE_CON22_PCLK_EINK_EN_SHIFT (14U)
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#define CRU_GATE_CON22_PCLK_EINK_EN_MASK (0x1U << CRU_GATE_CON22_PCLK_EINK_EN_SHIFT) /* 0x00004000 */
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#define CRU_GATE_CON22_HCLK_EINK_EN_SHIFT (15U)
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#define CRU_GATE_CON22_HCLK_EINK_EN_MASK (0x1U << CRU_GATE_CON22_HCLK_EINK_EN_SHIFT) /* 0x00008000 */
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/* GATE_CON23 */
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#define CRU_GATE_CON23_OFFSET (0x35CU)
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#define CRU_GATE_CON23_ACLK_RGA_PRE_EN_SHIFT (0U)
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#define CRU_GATE_CON23_ACLK_RGA_PRE_EN_MASK (0x1U << CRU_GATE_CON23_ACLK_RGA_PRE_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON23_HCLK_RGA_PRE_EN_SHIFT (1U)
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#define CRU_GATE_CON23_HCLK_RGA_PRE_EN_MASK (0x1U << CRU_GATE_CON23_HCLK_RGA_PRE_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON23_ACLK_RGA_NIU_EN_SHIFT (2U)
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#define CRU_GATE_CON23_ACLK_RGA_NIU_EN_MASK (0x1U << CRU_GATE_CON23_ACLK_RGA_NIU_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON23_HCLK_RGA_NIU_EN_SHIFT (3U)
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#define CRU_GATE_CON23_HCLK_RGA_NIU_EN_MASK (0x1U << CRU_GATE_CON23_HCLK_RGA_NIU_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON23_ACLK_RGA_EN_SHIFT (4U)
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#define CRU_GATE_CON23_ACLK_RGA_EN_MASK (0x1U << CRU_GATE_CON23_ACLK_RGA_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON23_HCLK_RGA_EN_SHIFT (5U)
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#define CRU_GATE_CON23_HCLK_RGA_EN_MASK (0x1U << CRU_GATE_CON23_HCLK_RGA_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON23_CLK_RGA_CORE_EN_SHIFT (6U)
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#define CRU_GATE_CON23_CLK_RGA_CORE_EN_MASK (0x1U << CRU_GATE_CON23_CLK_RGA_CORE_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON23_ACLK_IEP_EN_SHIFT (7U)
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#define CRU_GATE_CON23_ACLK_IEP_EN_MASK (0x1U << CRU_GATE_CON23_ACLK_IEP_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON23_HCLK_IEP_EN_SHIFT (8U)
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#define CRU_GATE_CON23_HCLK_IEP_EN_MASK (0x1U << CRU_GATE_CON23_HCLK_IEP_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON23_CLK_IEP_CORE_EN_SHIFT (9U)
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#define CRU_GATE_CON23_CLK_IEP_CORE_EN_MASK (0x1U << CRU_GATE_CON23_CLK_IEP_CORE_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON23_HCLK_EBC_EN_SHIFT (10U)
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#define CRU_GATE_CON23_HCLK_EBC_EN_MASK (0x1U << CRU_GATE_CON23_HCLK_EBC_EN_SHIFT) /* 0x00000400 */
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#define CRU_GATE_CON23_DCLK_EBC_EN_SHIFT (11U)
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#define CRU_GATE_CON23_DCLK_EBC_EN_MASK (0x1U << CRU_GATE_CON23_DCLK_EBC_EN_SHIFT) /* 0x00000800 */
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#define CRU_GATE_CON23_ACLK_JDEC_EN_SHIFT (12U)
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#define CRU_GATE_CON23_ACLK_JDEC_EN_MASK (0x1U << CRU_GATE_CON23_ACLK_JDEC_EN_SHIFT) /* 0x00001000 */
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#define CRU_GATE_CON23_HCLK_JDEC_EN_SHIFT (13U)
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#define CRU_GATE_CON23_HCLK_JDEC_EN_MASK (0x1U << CRU_GATE_CON23_HCLK_JDEC_EN_SHIFT) /* 0x00002000 */
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#define CRU_GATE_CON23_ACLK_JENC_EN_SHIFT (14U)
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#define CRU_GATE_CON23_ACLK_JENC_EN_MASK (0x1U << CRU_GATE_CON23_ACLK_JENC_EN_SHIFT) /* 0x00004000 */
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#define CRU_GATE_CON23_HCLK_JENC_EN_SHIFT (15U)
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#define CRU_GATE_CON23_HCLK_JENC_EN_MASK (0x1U << CRU_GATE_CON23_HCLK_JENC_EN_SHIFT) /* 0x00008000 */
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/* GATE_CON24 */
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#define CRU_GATE_CON24_OFFSET (0x360U)
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#define CRU_GATE_CON24_ACLK_RKVENC_PRE_EN_SHIFT (0U)
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#define CRU_GATE_CON24_ACLK_RKVENC_PRE_EN_MASK (0x1U << CRU_GATE_CON24_ACLK_RKVENC_PRE_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON24_HCLK_RKVENC_PRE_EN_SHIFT (1U)
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#define CRU_GATE_CON24_HCLK_RKVENC_PRE_EN_MASK (0x1U << CRU_GATE_CON24_HCLK_RKVENC_PRE_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON24_ACLK_RKVENC_NIU_EN_SHIFT (3U)
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#define CRU_GATE_CON24_ACLK_RKVENC_NIU_EN_MASK (0x1U << CRU_GATE_CON24_ACLK_RKVENC_NIU_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON24_HCLK_RKVENC_NIU_EN_SHIFT (4U)
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#define CRU_GATE_CON24_HCLK_RKVENC_NIU_EN_MASK (0x1U << CRU_GATE_CON24_HCLK_RKVENC_NIU_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON24_ACLK_RKVENC_EN_SHIFT (6U)
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#define CRU_GATE_CON24_ACLK_RKVENC_EN_MASK (0x1U << CRU_GATE_CON24_ACLK_RKVENC_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON24_HCLK_RKVENC_EN_SHIFT (7U)
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#define CRU_GATE_CON24_HCLK_RKVENC_EN_MASK (0x1U << CRU_GATE_CON24_HCLK_RKVENC_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON24_CLK_RKVENC_CORE_EN_SHIFT (8U)
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#define CRU_GATE_CON24_CLK_RKVENC_CORE_EN_MASK (0x1U << CRU_GATE_CON24_CLK_RKVENC_CORE_EN_SHIFT) /* 0x00000100 */
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/* GATE_CON25 */
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#define CRU_GATE_CON25_OFFSET (0x364U)
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#define CRU_GATE_CON25_ACLK_RKVDEC_PRE_EN_SHIFT (0U)
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#define CRU_GATE_CON25_ACLK_RKVDEC_PRE_EN_MASK (0x1U << CRU_GATE_CON25_ACLK_RKVDEC_PRE_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON25_HCLK_RKVDEC_PRE_EN_SHIFT (1U)
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#define CRU_GATE_CON25_HCLK_RKVDEC_PRE_EN_MASK (0x1U << CRU_GATE_CON25_HCLK_RKVDEC_PRE_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON25_ACLK_RKVDEC_NIU_EN_SHIFT (2U)
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#define CRU_GATE_CON25_ACLK_RKVDEC_NIU_EN_MASK (0x1U << CRU_GATE_CON25_ACLK_RKVDEC_NIU_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON25_HCLK_RKVDEC_NIU_EN_SHIFT (3U)
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#define CRU_GATE_CON25_HCLK_RKVDEC_NIU_EN_MASK (0x1U << CRU_GATE_CON25_HCLK_RKVDEC_NIU_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON25_ACLK_RKVDEC_EN_SHIFT (4U)
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#define CRU_GATE_CON25_ACLK_RKVDEC_EN_MASK (0x1U << CRU_GATE_CON25_ACLK_RKVDEC_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON25_HCLK_RKVDEC_EN_SHIFT (5U)
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#define CRU_GATE_CON25_HCLK_RKVDEC_EN_MASK (0x1U << CRU_GATE_CON25_HCLK_RKVDEC_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON25_CLK_RKVDEC_CA_EN_SHIFT (6U)
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#define CRU_GATE_CON25_CLK_RKVDEC_CA_EN_MASK (0x1U << CRU_GATE_CON25_CLK_RKVDEC_CA_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON25_CLK_RKVDEC_CORE_EN_SHIFT (7U)
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#define CRU_GATE_CON25_CLK_RKVDEC_CORE_EN_MASK (0x1U << CRU_GATE_CON25_CLK_RKVDEC_CORE_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON25_CLK_RKVDEC_HEVC_CA_EN_SHIFT (8U)
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#define CRU_GATE_CON25_CLK_RKVDEC_HEVC_CA_EN_MASK (0x1U << CRU_GATE_CON25_CLK_RKVDEC_HEVC_CA_EN_SHIFT) /* 0x00000100 */
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/* GATE_CON26 */
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#define CRU_GATE_CON26_OFFSET (0x368U)
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#define CRU_GATE_CON26_ACLK_BUS_EN_SHIFT (0U)
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#define CRU_GATE_CON26_ACLK_BUS_EN_MASK (0x1U << CRU_GATE_CON26_ACLK_BUS_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON26_PCLK_BUS_EN_SHIFT (1U)
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#define CRU_GATE_CON26_PCLK_BUS_EN_MASK (0x1U << CRU_GATE_CON26_PCLK_BUS_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON26_ACLK_BUS_NIU_EN_SHIFT (2U)
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#define CRU_GATE_CON26_ACLK_BUS_NIU_EN_MASK (0x1U << CRU_GATE_CON26_ACLK_BUS_NIU_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON26_PCLK_BUS_NIU_EN_SHIFT (3U)
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#define CRU_GATE_CON26_PCLK_BUS_NIU_EN_MASK (0x1U << CRU_GATE_CON26_PCLK_BUS_NIU_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON26_PCLK_TSADC_EN_SHIFT (4U)
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#define CRU_GATE_CON26_PCLK_TSADC_EN_MASK (0x1U << CRU_GATE_CON26_PCLK_TSADC_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON26_CLK_TSADC_TSEN_EN_SHIFT (5U)
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#define CRU_GATE_CON26_CLK_TSADC_TSEN_EN_MASK (0x1U << CRU_GATE_CON26_CLK_TSADC_TSEN_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON26_CLK_TSADC_EN_SHIFT (6U)
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#define CRU_GATE_CON26_CLK_TSADC_EN_MASK (0x1U << CRU_GATE_CON26_CLK_TSADC_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON26_PCLK_SARADC_EN_SHIFT (7U)
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#define CRU_GATE_CON26_PCLK_SARADC_EN_MASK (0x1U << CRU_GATE_CON26_PCLK_SARADC_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON26_CLK_SARADC_EN_SHIFT (8U)
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#define CRU_GATE_CON26_CLK_SARADC_EN_MASK (0x1U << CRU_GATE_CON26_CLK_SARADC_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON26_PCLK_OTPC_NS_EN_SHIFT (9U)
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#define CRU_GATE_CON26_PCLK_OTPC_NS_EN_MASK (0x1U << CRU_GATE_CON26_PCLK_OTPC_NS_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON26_CLK_OTPC_NS_SBPI_EN_SHIFT (10U)
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#define CRU_GATE_CON26_CLK_OTPC_NS_SBPI_EN_MASK (0x1U << CRU_GATE_CON26_CLK_OTPC_NS_SBPI_EN_SHIFT) /* 0x00000400 */
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#define CRU_GATE_CON26_CLK_OTPC_NS_USR_EN_SHIFT (11U)
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#define CRU_GATE_CON26_CLK_OTPC_NS_USR_EN_MASK (0x1U << CRU_GATE_CON26_CLK_OTPC_NS_USR_EN_SHIFT) /* 0x00000800 */
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#define CRU_GATE_CON26_PCLK_SCR_EN_SHIFT (12U)
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#define CRU_GATE_CON26_PCLK_SCR_EN_MASK (0x1U << CRU_GATE_CON26_PCLK_SCR_EN_SHIFT) /* 0x00001000 */
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#define CRU_GATE_CON26_PCLK_WDT_NS_EN_SHIFT (13U)
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#define CRU_GATE_CON26_PCLK_WDT_NS_EN_MASK (0x1U << CRU_GATE_CON26_PCLK_WDT_NS_EN_SHIFT) /* 0x00002000 */
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#define CRU_GATE_CON26_TCLK_WDT_NS_EN_SHIFT (14U)
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#define CRU_GATE_CON26_TCLK_WDT_NS_EN_MASK (0x1U << CRU_GATE_CON26_TCLK_WDT_NS_EN_SHIFT) /* 0x00004000 */
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/* GATE_CON27 */
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#define CRU_GATE_CON27_OFFSET (0x36CU)
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#define CRU_GATE_CON27_PCLK_GRF_EN_SHIFT (0U)
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#define CRU_GATE_CON27_PCLK_GRF_EN_MASK (0x1U << CRU_GATE_CON27_PCLK_GRF_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON27_PCLK_GRF_VCCIO12_EN_SHIFT (1U)
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#define CRU_GATE_CON27_PCLK_GRF_VCCIO12_EN_MASK (0x1U << CRU_GATE_CON27_PCLK_GRF_VCCIO12_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON27_PCLK_GRF_VCCIO34_EN_SHIFT (2U)
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#define CRU_GATE_CON27_PCLK_GRF_VCCIO34_EN_MASK (0x1U << CRU_GATE_CON27_PCLK_GRF_VCCIO34_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON27_PCLK_GRF_VCCIO567_EN_SHIFT (3U)
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#define CRU_GATE_CON27_PCLK_GRF_VCCIO567_EN_MASK (0x1U << CRU_GATE_CON27_PCLK_GRF_VCCIO567_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON27_PCLK_DFT2APB_EN_SHIFT (4U)
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#define CRU_GATE_CON27_PCLK_DFT2APB_EN_MASK (0x1U << CRU_GATE_CON27_PCLK_DFT2APB_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON27_PCLK_CAN0_EN_SHIFT (5U)
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#define CRU_GATE_CON27_PCLK_CAN0_EN_MASK (0x1U << CRU_GATE_CON27_PCLK_CAN0_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON27_CLK_CAN0_EN_SHIFT (6U)
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#define CRU_GATE_CON27_CLK_CAN0_EN_MASK (0x1U << CRU_GATE_CON27_CLK_CAN0_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON27_PCLK_CAN1_EN_SHIFT (7U)
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#define CRU_GATE_CON27_PCLK_CAN1_EN_MASK (0x1U << CRU_GATE_CON27_PCLK_CAN1_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON27_CLK_CAN1_EN_SHIFT (8U)
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#define CRU_GATE_CON27_CLK_CAN1_EN_MASK (0x1U << CRU_GATE_CON27_CLK_CAN1_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON27_PCLK_CAN2_EN_SHIFT (9U)
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#define CRU_GATE_CON27_PCLK_CAN2_EN_MASK (0x1U << CRU_GATE_CON27_PCLK_CAN2_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON27_CLK_CAN2_EN_SHIFT (10U)
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#define CRU_GATE_CON27_CLK_CAN2_EN_MASK (0x1U << CRU_GATE_CON27_CLK_CAN2_EN_SHIFT) /* 0x00000400 */
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#define CRU_GATE_CON27_PCLK_UART1_EN_SHIFT (12U)
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#define CRU_GATE_CON27_PCLK_UART1_EN_MASK (0x1U << CRU_GATE_CON27_PCLK_UART1_EN_SHIFT) /* 0x00001000 */
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#define CRU_GATE_CON27_CLK_UART1_EN_SHIFT (13U)
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#define CRU_GATE_CON27_CLK_UART1_EN_MASK (0x1U << CRU_GATE_CON27_CLK_UART1_EN_SHIFT) /* 0x00002000 */
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#define CRU_GATE_CON27_CLK_UART1_FRAC_EN_SHIFT (14U)
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#define CRU_GATE_CON27_CLK_UART1_FRAC_EN_MASK (0x1U << CRU_GATE_CON27_CLK_UART1_FRAC_EN_SHIFT) /* 0x00004000 */
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#define CRU_GATE_CON27_SCLK_UART1_EN_SHIFT (15U)
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#define CRU_GATE_CON27_SCLK_UART1_EN_MASK (0x1U << CRU_GATE_CON27_SCLK_UART1_EN_SHIFT) /* 0x00008000 */
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/* GATE_CON28 */
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#define CRU_GATE_CON28_OFFSET (0x370U)
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#define CRU_GATE_CON28_PCLK_UART2_EN_SHIFT (0U)
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#define CRU_GATE_CON28_PCLK_UART2_EN_MASK (0x1U << CRU_GATE_CON28_PCLK_UART2_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON28_CLK_UART2_EN_SHIFT (1U)
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#define CRU_GATE_CON28_CLK_UART2_EN_MASK (0x1U << CRU_GATE_CON28_CLK_UART2_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON28_CLK_UART2_FRAC_EN_SHIFT (2U)
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#define CRU_GATE_CON28_CLK_UART2_FRAC_EN_MASK (0x1U << CRU_GATE_CON28_CLK_UART2_FRAC_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON28_SCLK_UART2_EN_SHIFT (3U)
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#define CRU_GATE_CON28_SCLK_UART2_EN_MASK (0x1U << CRU_GATE_CON28_SCLK_UART2_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON28_PCLK_UART3_EN_SHIFT (4U)
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#define CRU_GATE_CON28_PCLK_UART3_EN_MASK (0x1U << CRU_GATE_CON28_PCLK_UART3_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON28_CLK_UART3_EN_SHIFT (5U)
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#define CRU_GATE_CON28_CLK_UART3_EN_MASK (0x1U << CRU_GATE_CON28_CLK_UART3_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON28_CLK_UART3_FRAC_EN_SHIFT (6U)
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#define CRU_GATE_CON28_CLK_UART3_FRAC_EN_MASK (0x1U << CRU_GATE_CON28_CLK_UART3_FRAC_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON28_SCLK_UART3_EN_SHIFT (7U)
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#define CRU_GATE_CON28_SCLK_UART3_EN_MASK (0x1U << CRU_GATE_CON28_SCLK_UART3_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON28_PCLK_UART4_EN_SHIFT (8U)
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#define CRU_GATE_CON28_PCLK_UART4_EN_MASK (0x1U << CRU_GATE_CON28_PCLK_UART4_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON28_CLK_UART4_EN_SHIFT (9U)
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#define CRU_GATE_CON28_CLK_UART4_EN_MASK (0x1U << CRU_GATE_CON28_CLK_UART4_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON28_CLK_UART4_FRAC_EN_SHIFT (10U)
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#define CRU_GATE_CON28_CLK_UART4_FRAC_EN_MASK (0x1U << CRU_GATE_CON28_CLK_UART4_FRAC_EN_SHIFT) /* 0x00000400 */
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#define CRU_GATE_CON28_SCLK_UART4_EN_SHIFT (11U)
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#define CRU_GATE_CON28_SCLK_UART4_EN_MASK (0x1U << CRU_GATE_CON28_SCLK_UART4_EN_SHIFT) /* 0x00000800 */
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#define CRU_GATE_CON28_PCLK_UART5_EN_SHIFT (12U)
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#define CRU_GATE_CON28_PCLK_UART5_EN_MASK (0x1U << CRU_GATE_CON28_PCLK_UART5_EN_SHIFT) /* 0x00001000 */
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#define CRU_GATE_CON28_CLK_UART5_EN_SHIFT (13U)
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#define CRU_GATE_CON28_CLK_UART5_EN_MASK (0x1U << CRU_GATE_CON28_CLK_UART5_EN_SHIFT) /* 0x00002000 */
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#define CRU_GATE_CON28_CLK_UART5_FRAC_EN_SHIFT (14U)
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#define CRU_GATE_CON28_CLK_UART5_FRAC_EN_MASK (0x1U << CRU_GATE_CON28_CLK_UART5_FRAC_EN_SHIFT) /* 0x00004000 */
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#define CRU_GATE_CON28_SCLK_UART5_EN_SHIFT (15U)
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#define CRU_GATE_CON28_SCLK_UART5_EN_MASK (0x1U << CRU_GATE_CON28_SCLK_UART5_EN_SHIFT) /* 0x00008000 */
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/* GATE_CON29 */
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#define CRU_GATE_CON29_OFFSET (0x374U)
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#define CRU_GATE_CON29_PCLK_UART6_EN_SHIFT (0U)
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#define CRU_GATE_CON29_PCLK_UART6_EN_MASK (0x1U << CRU_GATE_CON29_PCLK_UART6_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON29_CLK_UART6_EN_SHIFT (1U)
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#define CRU_GATE_CON29_CLK_UART6_EN_MASK (0x1U << CRU_GATE_CON29_CLK_UART6_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON29_CLK_UART6_FRAC_EN_SHIFT (2U)
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#define CRU_GATE_CON29_CLK_UART6_FRAC_EN_MASK (0x1U << CRU_GATE_CON29_CLK_UART6_FRAC_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON29_SCLK_UART6_EN_SHIFT (3U)
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#define CRU_GATE_CON29_SCLK_UART6_EN_MASK (0x1U << CRU_GATE_CON29_SCLK_UART6_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON29_PCLK_UART7_EN_SHIFT (4U)
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#define CRU_GATE_CON29_PCLK_UART7_EN_MASK (0x1U << CRU_GATE_CON29_PCLK_UART7_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON29_CLK_UART7_EN_SHIFT (5U)
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#define CRU_GATE_CON29_CLK_UART7_EN_MASK (0x1U << CRU_GATE_CON29_CLK_UART7_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON29_CLK_UART7_FRAC_EN_SHIFT (6U)
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#define CRU_GATE_CON29_CLK_UART7_FRAC_EN_MASK (0x1U << CRU_GATE_CON29_CLK_UART7_FRAC_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON29_SCLK_UART7_EN_SHIFT (7U)
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#define CRU_GATE_CON29_SCLK_UART7_EN_MASK (0x1U << CRU_GATE_CON29_SCLK_UART7_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON29_PCLK_UART8_EN_SHIFT (8U)
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#define CRU_GATE_CON29_PCLK_UART8_EN_MASK (0x1U << CRU_GATE_CON29_PCLK_UART8_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON29_CLK_UART8_EN_SHIFT (9U)
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#define CRU_GATE_CON29_CLK_UART8_EN_MASK (0x1U << CRU_GATE_CON29_CLK_UART8_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON29_CLK_UART8_FRAC_EN_SHIFT (10U)
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#define CRU_GATE_CON29_CLK_UART8_FRAC_EN_MASK (0x1U << CRU_GATE_CON29_CLK_UART8_FRAC_EN_SHIFT) /* 0x00000400 */
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#define CRU_GATE_CON29_SCLK_UART8_EN_SHIFT (11U)
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#define CRU_GATE_CON29_SCLK_UART8_EN_MASK (0x1U << CRU_GATE_CON29_SCLK_UART8_EN_SHIFT) /* 0x00000800 */
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#define CRU_GATE_CON29_PCLK_UART9_EN_SHIFT (12U)
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#define CRU_GATE_CON29_PCLK_UART9_EN_MASK (0x1U << CRU_GATE_CON29_PCLK_UART9_EN_SHIFT) /* 0x00001000 */
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#define CRU_GATE_CON29_CLK_UART9_EN_SHIFT (13U)
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#define CRU_GATE_CON29_CLK_UART9_EN_MASK (0x1U << CRU_GATE_CON29_CLK_UART9_EN_SHIFT) /* 0x00002000 */
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#define CRU_GATE_CON29_CLK_UART9_FRAC_EN_SHIFT (14U)
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#define CRU_GATE_CON29_CLK_UART9_FRAC_EN_MASK (0x1U << CRU_GATE_CON29_CLK_UART9_FRAC_EN_SHIFT) /* 0x00004000 */
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#define CRU_GATE_CON29_SCLK_UART9_EN_SHIFT (15U)
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#define CRU_GATE_CON29_SCLK_UART9_EN_MASK (0x1U << CRU_GATE_CON29_SCLK_UART9_EN_SHIFT) /* 0x00008000 */
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/* GATE_CON30 */
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#define CRU_GATE_CON30_OFFSET (0x378U)
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#define CRU_GATE_CON30_PCLK_I2C1_EN_SHIFT (0U)
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#define CRU_GATE_CON30_PCLK_I2C1_EN_MASK (0x1U << CRU_GATE_CON30_PCLK_I2C1_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON30_CLK_I2C1_EN_SHIFT (1U)
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#define CRU_GATE_CON30_CLK_I2C1_EN_MASK (0x1U << CRU_GATE_CON30_CLK_I2C1_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON30_PCLK_I2C2_EN_SHIFT (2U)
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#define CRU_GATE_CON30_PCLK_I2C2_EN_MASK (0x1U << CRU_GATE_CON30_PCLK_I2C2_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON30_CLK_I2C2_EN_SHIFT (3U)
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#define CRU_GATE_CON30_CLK_I2C2_EN_MASK (0x1U << CRU_GATE_CON30_CLK_I2C2_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON30_PCLK_I2C3_EN_SHIFT (4U)
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#define CRU_GATE_CON30_PCLK_I2C3_EN_MASK (0x1U << CRU_GATE_CON30_PCLK_I2C3_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON30_CLK_I2C3_EN_SHIFT (5U)
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#define CRU_GATE_CON30_CLK_I2C3_EN_MASK (0x1U << CRU_GATE_CON30_CLK_I2C3_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON30_PCLK_I2C4_EN_SHIFT (6U)
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#define CRU_GATE_CON30_PCLK_I2C4_EN_MASK (0x1U << CRU_GATE_CON30_PCLK_I2C4_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON30_CLK_I2C4_EN_SHIFT (7U)
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#define CRU_GATE_CON30_CLK_I2C4_EN_MASK (0x1U << CRU_GATE_CON30_CLK_I2C4_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON30_PCLK_I2C5_EN_SHIFT (8U)
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#define CRU_GATE_CON30_PCLK_I2C5_EN_MASK (0x1U << CRU_GATE_CON30_PCLK_I2C5_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON30_CLK_I2C5_EN_SHIFT (9U)
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#define CRU_GATE_CON30_CLK_I2C5_EN_MASK (0x1U << CRU_GATE_CON30_CLK_I2C5_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON30_PCLK_SPI0_EN_SHIFT (10U)
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#define CRU_GATE_CON30_PCLK_SPI0_EN_MASK (0x1U << CRU_GATE_CON30_PCLK_SPI0_EN_SHIFT) /* 0x00000400 */
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#define CRU_GATE_CON30_CLK_SPI0_EN_SHIFT (11U)
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#define CRU_GATE_CON30_CLK_SPI0_EN_MASK (0x1U << CRU_GATE_CON30_CLK_SPI0_EN_SHIFT) /* 0x00000800 */
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#define CRU_GATE_CON30_PCLK_SPI1_EN_SHIFT (12U)
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#define CRU_GATE_CON30_PCLK_SPI1_EN_MASK (0x1U << CRU_GATE_CON30_PCLK_SPI1_EN_SHIFT) /* 0x00001000 */
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#define CRU_GATE_CON30_CLK_SPI1_EN_SHIFT (13U)
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#define CRU_GATE_CON30_CLK_SPI1_EN_MASK (0x1U << CRU_GATE_CON30_CLK_SPI1_EN_SHIFT) /* 0x00002000 */
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#define CRU_GATE_CON30_PCLK_SPI2_EN_SHIFT (14U)
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#define CRU_GATE_CON30_PCLK_SPI2_EN_MASK (0x1U << CRU_GATE_CON30_PCLK_SPI2_EN_SHIFT) /* 0x00004000 */
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#define CRU_GATE_CON30_CLK_SPI2_EN_SHIFT (15U)
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#define CRU_GATE_CON30_CLK_SPI2_EN_MASK (0x1U << CRU_GATE_CON30_CLK_SPI2_EN_SHIFT) /* 0x00008000 */
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/* GATE_CON31 */
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#define CRU_GATE_CON31_OFFSET (0x37CU)
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#define CRU_GATE_CON31_PCLK_SPI3_EN_SHIFT (0U)
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#define CRU_GATE_CON31_PCLK_SPI3_EN_MASK (0x1U << CRU_GATE_CON31_PCLK_SPI3_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON31_CLK_SPI3_EN_SHIFT (1U)
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#define CRU_GATE_CON31_CLK_SPI3_EN_MASK (0x1U << CRU_GATE_CON31_CLK_SPI3_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON31_PCLK_GPIO1_EN_SHIFT (2U)
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#define CRU_GATE_CON31_PCLK_GPIO1_EN_MASK (0x1U << CRU_GATE_CON31_PCLK_GPIO1_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON31_DBCLK_GPIO1_EN_SHIFT (3U)
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#define CRU_GATE_CON31_DBCLK_GPIO1_EN_MASK (0x1U << CRU_GATE_CON31_DBCLK_GPIO1_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON31_PCLK_GPIO2_EN_SHIFT (4U)
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#define CRU_GATE_CON31_PCLK_GPIO2_EN_MASK (0x1U << CRU_GATE_CON31_PCLK_GPIO2_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON31_DBCLK_GPIO2_EN_SHIFT (5U)
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#define CRU_GATE_CON31_DBCLK_GPIO2_EN_MASK (0x1U << CRU_GATE_CON31_DBCLK_GPIO2_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON31_PCLK_GPIO3_EN_SHIFT (6U)
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#define CRU_GATE_CON31_PCLK_GPIO3_EN_MASK (0x1U << CRU_GATE_CON31_PCLK_GPIO3_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON31_DBCLK_GPIO3_EN_SHIFT (7U)
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#define CRU_GATE_CON31_DBCLK_GPIO3_EN_MASK (0x1U << CRU_GATE_CON31_DBCLK_GPIO3_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON31_PCLK_GPIO4_EN_SHIFT (8U)
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#define CRU_GATE_CON31_PCLK_GPIO4_EN_MASK (0x1U << CRU_GATE_CON31_PCLK_GPIO4_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON31_DBCLK_GPIO4_EN_SHIFT (9U)
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#define CRU_GATE_CON31_DBCLK_GPIO4_EN_MASK (0x1U << CRU_GATE_CON31_DBCLK_GPIO4_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON31_PCLK_PWM1_EN_SHIFT (10U)
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#define CRU_GATE_CON31_PCLK_PWM1_EN_MASK (0x1U << CRU_GATE_CON31_PCLK_PWM1_EN_SHIFT) /* 0x00000400 */
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#define CRU_GATE_CON31_CLK_PWM1_EN_SHIFT (11U)
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#define CRU_GATE_CON31_CLK_PWM1_EN_MASK (0x1U << CRU_GATE_CON31_CLK_PWM1_EN_SHIFT) /* 0x00000800 */
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#define CRU_GATE_CON31_CLK_PWM1_CAPTURE_EN_SHIFT (12U)
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#define CRU_GATE_CON31_CLK_PWM1_CAPTURE_EN_MASK (0x1U << CRU_GATE_CON31_CLK_PWM1_CAPTURE_EN_SHIFT) /* 0x00001000 */
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#define CRU_GATE_CON31_PCLK_PWM2_EN_SHIFT (13U)
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#define CRU_GATE_CON31_PCLK_PWM2_EN_MASK (0x1U << CRU_GATE_CON31_PCLK_PWM2_EN_SHIFT) /* 0x00002000 */
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#define CRU_GATE_CON31_CLK_PWM2_EN_SHIFT (14U)
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#define CRU_GATE_CON31_CLK_PWM2_EN_MASK (0x1U << CRU_GATE_CON31_CLK_PWM2_EN_SHIFT) /* 0x00004000 */
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#define CRU_GATE_CON31_CLK_PWM2_CAPTURE_EN_SHIFT (15U)
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#define CRU_GATE_CON31_CLK_PWM2_CAPTURE_EN_MASK (0x1U << CRU_GATE_CON31_CLK_PWM2_CAPTURE_EN_SHIFT) /* 0x00008000 */
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/* GATE_CON32 */
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#define CRU_GATE_CON32_OFFSET (0x380U)
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#define CRU_GATE_CON32_PCLK_PWM3_EN_SHIFT (0U)
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#define CRU_GATE_CON32_PCLK_PWM3_EN_MASK (0x1U << CRU_GATE_CON32_PCLK_PWM3_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON32_CLK_PWM3_EN_SHIFT (1U)
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#define CRU_GATE_CON32_CLK_PWM3_EN_MASK (0x1U << CRU_GATE_CON32_CLK_PWM3_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON32_CLK_PWM3_CAPTURE_EN_SHIFT (2U)
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#define CRU_GATE_CON32_CLK_PWM3_CAPTURE_EN_MASK (0x1U << CRU_GATE_CON32_CLK_PWM3_CAPTURE_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON32_PCLK_TIMER_EN_SHIFT (3U)
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#define CRU_GATE_CON32_PCLK_TIMER_EN_MASK (0x1U << CRU_GATE_CON32_PCLK_TIMER_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON32_CLK_TIMER0_EN_SHIFT (4U)
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#define CRU_GATE_CON32_CLK_TIMER0_EN_MASK (0x1U << CRU_GATE_CON32_CLK_TIMER0_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON32_CLK_TIMER1_EN_SHIFT (5U)
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#define CRU_GATE_CON32_CLK_TIMER1_EN_MASK (0x1U << CRU_GATE_CON32_CLK_TIMER1_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON32_CLK_TIMER2_EN_SHIFT (6U)
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#define CRU_GATE_CON32_CLK_TIMER2_EN_MASK (0x1U << CRU_GATE_CON32_CLK_TIMER2_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON32_CLK_TIMER3_EN_SHIFT (7U)
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#define CRU_GATE_CON32_CLK_TIMER3_EN_MASK (0x1U << CRU_GATE_CON32_CLK_TIMER3_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON32_CLK_TIMER4_EN_SHIFT (8U)
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#define CRU_GATE_CON32_CLK_TIMER4_EN_MASK (0x1U << CRU_GATE_CON32_CLK_TIMER4_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON32_CLK_TIMER5_EN_SHIFT (9U)
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#define CRU_GATE_CON32_CLK_TIMER5_EN_MASK (0x1U << CRU_GATE_CON32_CLK_TIMER5_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON32_CLK_I2C_EN_SHIFT (10U)
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#define CRU_GATE_CON32_CLK_I2C_EN_MASK (0x1U << CRU_GATE_CON32_CLK_I2C_EN_SHIFT) /* 0x00000400 */
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#define CRU_GATE_CON32_DBCLK_GPIO_EN_SHIFT (11U)
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#define CRU_GATE_CON32_DBCLK_GPIO_EN_MASK (0x1U << CRU_GATE_CON32_DBCLK_GPIO_EN_SHIFT) /* 0x00000800 */
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#define CRU_GATE_CON32_CLK_TIMER_EN_SHIFT (12U)
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#define CRU_GATE_CON32_CLK_TIMER_EN_MASK (0x1U << CRU_GATE_CON32_CLK_TIMER_EN_SHIFT) /* 0x00001000 */
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#define CRU_GATE_CON32_ACLK_MCU_EN_SHIFT (13U)
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#define CRU_GATE_CON32_ACLK_MCU_EN_MASK (0x1U << CRU_GATE_CON32_ACLK_MCU_EN_SHIFT) /* 0x00002000 */
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#define CRU_GATE_CON32_PCLK_INTMUX_EN_SHIFT (14U)
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#define CRU_GATE_CON32_PCLK_INTMUX_EN_MASK (0x1U << CRU_GATE_CON32_PCLK_INTMUX_EN_SHIFT) /* 0x00004000 */
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#define CRU_GATE_CON32_PCLK_MAILBOX_EN_SHIFT (15U)
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#define CRU_GATE_CON32_PCLK_MAILBOX_EN_MASK (0x1U << CRU_GATE_CON32_PCLK_MAILBOX_EN_SHIFT) /* 0x00008000 */
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/* GATE_CON33 */
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#define CRU_GATE_CON33_OFFSET (0x384U)
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#define CRU_GATE_CON33_ACLK_TOP_HIGH_EN_SHIFT (0U)
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#define CRU_GATE_CON33_ACLK_TOP_HIGH_EN_MASK (0x1U << CRU_GATE_CON33_ACLK_TOP_HIGH_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON33_ACLK_TOP_LOW_EN_SHIFT (1U)
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#define CRU_GATE_CON33_ACLK_TOP_LOW_EN_MASK (0x1U << CRU_GATE_CON33_ACLK_TOP_LOW_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON33_HCLK_TOP_EN_SHIFT (2U)
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#define CRU_GATE_CON33_HCLK_TOP_EN_MASK (0x1U << CRU_GATE_CON33_HCLK_TOP_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON33_PCLK_TOP_EN_SHIFT (3U)
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#define CRU_GATE_CON33_PCLK_TOP_EN_MASK (0x1U << CRU_GATE_CON33_PCLK_TOP_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON33_ACLK_TOP_HIGH_NIU_EN_SHIFT (4U)
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#define CRU_GATE_CON33_ACLK_TOP_HIGH_NIU_EN_MASK (0x1U << CRU_GATE_CON33_ACLK_TOP_HIGH_NIU_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON33_ACLK_TOP_LOW_NIU_EN_SHIFT (5U)
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#define CRU_GATE_CON33_ACLK_TOP_LOW_NIU_EN_MASK (0x1U << CRU_GATE_CON33_ACLK_TOP_LOW_NIU_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON33_HCLK_TOP_NIU_EN_SHIFT (6U)
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#define CRU_GATE_CON33_HCLK_TOP_NIU_EN_MASK (0x1U << CRU_GATE_CON33_HCLK_TOP_NIU_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON33_PCLK_TOP_NIU_EN_SHIFT (7U)
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#define CRU_GATE_CON33_PCLK_TOP_NIU_EN_MASK (0x1U << CRU_GATE_CON33_PCLK_TOP_NIU_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON33_PCLK_PCIE30PHY_EN_SHIFT (8U)
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#define CRU_GATE_CON33_PCLK_PCIE30PHY_EN_MASK (0x1U << CRU_GATE_CON33_PCLK_PCIE30PHY_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON33_CLK_OTPC_ARB_EN_SHIFT (9U)
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#define CRU_GATE_CON33_CLK_OTPC_ARB_EN_MASK (0x1U << CRU_GATE_CON33_CLK_OTPC_ARB_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON33_PCLK_TOP_CRU_EN_SHIFT (12U)
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#define CRU_GATE_CON33_PCLK_TOP_CRU_EN_MASK (0x1U << CRU_GATE_CON33_PCLK_TOP_CRU_EN_SHIFT) /* 0x00001000 */
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#define CRU_GATE_CON33_PCLK_MIPICSIPHY_EN_SHIFT (13U)
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#define CRU_GATE_CON33_PCLK_MIPICSIPHY_EN_MASK (0x1U << CRU_GATE_CON33_PCLK_MIPICSIPHY_EN_SHIFT) /* 0x00002000 */
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#define CRU_GATE_CON33_PCLK_MIPIDSIPHY0_EN_SHIFT (14U)
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#define CRU_GATE_CON33_PCLK_MIPIDSIPHY0_EN_MASK (0x1U << CRU_GATE_CON33_PCLK_MIPIDSIPHY0_EN_SHIFT) /* 0x00004000 */
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#define CRU_GATE_CON33_PCLK_MIPIDSIPHY1_EN_SHIFT (15U)
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#define CRU_GATE_CON33_PCLK_MIPIDSIPHY1_EN_MASK (0x1U << CRU_GATE_CON33_PCLK_MIPIDSIPHY1_EN_SHIFT) /* 0x00008000 */
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/* GATE_CON34 */
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#define CRU_GATE_CON34_OFFSET (0x388U)
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#define CRU_GATE_CON34_PCLK_APB2ASB_CHIP_LEFT_EN_SHIFT (0U)
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#define CRU_GATE_CON34_PCLK_APB2ASB_CHIP_LEFT_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_APB2ASB_CHIP_LEFT_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON34_PCLK_APB2ASB_CHIP_BOTTOM_EN_SHIFT (1U)
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#define CRU_GATE_CON34_PCLK_APB2ASB_CHIP_BOTTOM_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_APB2ASB_CHIP_BOTTOM_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON34_PCLK_ASB2APB_CHIP_LEFT_EN_SHIFT (2U)
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#define CRU_GATE_CON34_PCLK_ASB2APB_CHIP_LEFT_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_ASB2APB_CHIP_LEFT_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON34_PCLK_ASB2APB_CHIP_BOTTOM_EN_SHIFT (3U)
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#define CRU_GATE_CON34_PCLK_ASB2APB_CHIP_BOTTOM_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_ASB2APB_CHIP_BOTTOM_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON34_PCLK_PIPEPHY0_EN_SHIFT (4U)
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#define CRU_GATE_CON34_PCLK_PIPEPHY0_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_PIPEPHY0_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON34_PCLK_PIPEPHY1_EN_SHIFT (5U)
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#define CRU_GATE_CON34_PCLK_PIPEPHY1_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_PIPEPHY1_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON34_PCLK_PIPEPHY2_EN_SHIFT (6U)
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#define CRU_GATE_CON34_PCLK_PIPEPHY2_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_PIPEPHY2_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON34_PCLK_USB2PHY0_GRF_EN_SHIFT (7U)
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#define CRU_GATE_CON34_PCLK_USB2PHY0_GRF_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_USB2PHY0_GRF_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON34_PCLK_USB2PHY1_GRF_EN_SHIFT (8U)
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#define CRU_GATE_CON34_PCLK_USB2PHY1_GRF_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_USB2PHY1_GRF_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON34_PCLK_DDRPHY_EN_SHIFT (9U)
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#define CRU_GATE_CON34_PCLK_DDRPHY_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_DDRPHY_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON34_CLK_DDRPHY_EN_SHIFT (10U)
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#define CRU_GATE_CON34_CLK_DDRPHY_EN_MASK (0x1U << CRU_GATE_CON34_CLK_DDRPHY_EN_SHIFT) /* 0x00000400 */
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#define CRU_GATE_CON34_PCLK_CPU_BOOST_EN_SHIFT (11U)
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#define CRU_GATE_CON34_PCLK_CPU_BOOST_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_CPU_BOOST_EN_SHIFT) /* 0x00000800 */
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#define CRU_GATE_CON34_CLK_CPU_BOOST_EN_SHIFT (12U)
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#define CRU_GATE_CON34_CLK_CPU_BOOST_EN_MASK (0x1U << CRU_GATE_CON34_CLK_CPU_BOOST_EN_SHIFT) /* 0x00001000 */
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#define CRU_GATE_CON34_PCLK_OTPPHY_EN_SHIFT (13U)
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#define CRU_GATE_CON34_PCLK_OTPPHY_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_OTPPHY_EN_SHIFT) /* 0x00002000 */
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#define CRU_GATE_CON34_PCLK_EDPPHY_GRF_EN_SHIFT (14U)
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#define CRU_GATE_CON34_PCLK_EDPPHY_GRF_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_EDPPHY_GRF_EN_SHIFT) /* 0x00004000 */
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#define CRU_GATE_CON34_CLK_TESTOUT_EN_SHIFT (15U)
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#define CRU_GATE_CON34_CLK_TESTOUT_EN_MASK (0x1U << CRU_GATE_CON34_CLK_TESTOUT_EN_SHIFT) /* 0x00008000 */
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/* GATE_CON35 */
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#define CRU_GATE_CON35_OFFSET (0x38CU)
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#define CRU_GATE_CON35_CLK_GPLL_DIV_400M_EN_SHIFT (0U)
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#define CRU_GATE_CON35_CLK_GPLL_DIV_400M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_GPLL_DIV_400M_EN_SHIFT) /* 0x00000001 */
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#define CRU_GATE_CON35_CLK_GPLL_DIV_300M_EN_SHIFT (1U)
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#define CRU_GATE_CON35_CLK_GPLL_DIV_300M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_GPLL_DIV_300M_EN_SHIFT) /* 0x00000002 */
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#define CRU_GATE_CON35_CLK_GPLL_DIV_200M_EN_SHIFT (2U)
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#define CRU_GATE_CON35_CLK_GPLL_DIV_200M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_GPLL_DIV_200M_EN_SHIFT) /* 0x00000004 */
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#define CRU_GATE_CON35_CLK_GPLL_DIV_150M_EN_SHIFT (3U)
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#define CRU_GATE_CON35_CLK_GPLL_DIV_150M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_GPLL_DIV_150M_EN_SHIFT) /* 0x00000008 */
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#define CRU_GATE_CON35_CLK_GPLL_DIV_100M_EN_SHIFT (4U)
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#define CRU_GATE_CON35_CLK_GPLL_DIV_100M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_GPLL_DIV_100M_EN_SHIFT) /* 0x00000010 */
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#define CRU_GATE_CON35_CLK_GPLL_DIV_75M_EN_SHIFT (5U)
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#define CRU_GATE_CON35_CLK_GPLL_DIV_75M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_GPLL_DIV_75M_EN_SHIFT) /* 0x00000020 */
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#define CRU_GATE_CON35_CLK_GPLL_DIV_20M_EN_SHIFT (6U)
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#define CRU_GATE_CON35_CLK_GPLL_DIV_20M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_GPLL_DIV_20M_EN_SHIFT) /* 0x00000040 */
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#define CRU_GATE_CON35_CLK_CPLL_DIV_500M_EN_SHIFT (7U)
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#define CRU_GATE_CON35_CLK_CPLL_DIV_500M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_CPLL_DIV_500M_EN_SHIFT) /* 0x00000080 */
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#define CRU_GATE_CON35_CLK_CPLL_DIV_333M_EN_SHIFT (8U)
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#define CRU_GATE_CON35_CLK_CPLL_DIV_333M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_CPLL_DIV_333M_EN_SHIFT) /* 0x00000100 */
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#define CRU_GATE_CON35_CLK_CPLL_DIV_250M_EN_SHIFT (9U)
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#define CRU_GATE_CON35_CLK_CPLL_DIV_250M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_CPLL_DIV_250M_EN_SHIFT) /* 0x00000200 */
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#define CRU_GATE_CON35_CLK_CPLL_DIV_125M_EN_SHIFT (10U)
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#define CRU_GATE_CON35_CLK_CPLL_DIV_125M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_CPLL_DIV_125M_EN_SHIFT) /* 0x00000400 */
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#define CRU_GATE_CON35_CLK_CPLL_DIV_100M_EN_SHIFT (11U)
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#define CRU_GATE_CON35_CLK_CPLL_DIV_100M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_CPLL_DIV_100M_EN_SHIFT) /* 0x00000800 */
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#define CRU_GATE_CON35_CLK_CPLL_DIV_62P5_EN_SHIFT (12U)
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#define CRU_GATE_CON35_CLK_CPLL_DIV_62P5_EN_MASK (0x1U << CRU_GATE_CON35_CLK_CPLL_DIV_62P5_EN_SHIFT) /* 0x00001000 */
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#define CRU_GATE_CON35_CLK_CPLL_DIV_50M_EN_SHIFT (13U)
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#define CRU_GATE_CON35_CLK_CPLL_DIV_50M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_CPLL_DIV_50M_EN_SHIFT) /* 0x00002000 */
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#define CRU_GATE_CON35_CLK_CPLL_DIV_25M_EN_SHIFT (14U)
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#define CRU_GATE_CON35_CLK_CPLL_DIV_25M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_CPLL_DIV_25M_EN_SHIFT) /* 0x00004000 */
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#define CRU_GATE_CON35_CLK_OSC0_DIV_750K_EN_SHIFT (15U)
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#define CRU_GATE_CON35_CLK_OSC0_DIV_750K_EN_MASK (0x1U << CRU_GATE_CON35_CLK_OSC0_DIV_750K_EN_SHIFT) /* 0x00008000 */
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/* SOFTRST_CON00 */
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#define CRU_SOFTRST_CON00_OFFSET (0x400U)
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#define CRU_SOFTRST_CON00_NCORERESET0_SHIFT (0U)
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#define CRU_SOFTRST_CON00_NCORERESET0_MASK (0x1U << CRU_SOFTRST_CON00_NCORERESET0_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON00_NCORERESET1_SHIFT (1U)
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#define CRU_SOFTRST_CON00_NCORERESET1_MASK (0x1U << CRU_SOFTRST_CON00_NCORERESET1_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON00_NCORERESET2_SHIFT (2U)
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#define CRU_SOFTRST_CON00_NCORERESET2_MASK (0x1U << CRU_SOFTRST_CON00_NCORERESET2_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON00_NCORERESET3_SHIFT (3U)
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#define CRU_SOFTRST_CON00_NCORERESET3_MASK (0x1U << CRU_SOFTRST_CON00_NCORERESET3_SHIFT) /* 0x00000008 */
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#define CRU_SOFTRST_CON00_NCPUPORESET0_SHIFT (4U)
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#define CRU_SOFTRST_CON00_NCPUPORESET0_MASK (0x1U << CRU_SOFTRST_CON00_NCPUPORESET0_SHIFT) /* 0x00000010 */
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#define CRU_SOFTRST_CON00_NCPUPORESET1_SHIFT (5U)
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#define CRU_SOFTRST_CON00_NCPUPORESET1_MASK (0x1U << CRU_SOFTRST_CON00_NCPUPORESET1_SHIFT) /* 0x00000020 */
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#define CRU_SOFTRST_CON00_NCPUPORESET2_SHIFT (6U)
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#define CRU_SOFTRST_CON00_NCPUPORESET2_MASK (0x1U << CRU_SOFTRST_CON00_NCPUPORESET2_SHIFT) /* 0x00000040 */
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#define CRU_SOFTRST_CON00_NCPUPORESET3_SHIFT (7U)
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#define CRU_SOFTRST_CON00_NCPUPORESET3_MASK (0x1U << CRU_SOFTRST_CON00_NCPUPORESET3_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON00_NSRESET_SHIFT (8U)
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#define CRU_SOFTRST_CON00_NSRESET_MASK (0x1U << CRU_SOFTRST_CON00_NSRESET_SHIFT) /* 0x00000100 */
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#define CRU_SOFTRST_CON00_NSPORESET_SHIFT (9U)
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#define CRU_SOFTRST_CON00_NSPORESET_MASK (0x1U << CRU_SOFTRST_CON00_NSPORESET_SHIFT) /* 0x00000200 */
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#define CRU_SOFTRST_CON00_NATRESET_SHIFT (10U)
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#define CRU_SOFTRST_CON00_NATRESET_MASK (0x1U << CRU_SOFTRST_CON00_NATRESET_SHIFT) /* 0x00000400 */
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#define CRU_SOFTRST_CON00_NGICRESET_SHIFT (11U)
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#define CRU_SOFTRST_CON00_NGICRESET_MASK (0x1U << CRU_SOFTRST_CON00_NGICRESET_SHIFT) /* 0x00000800 */
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#define CRU_SOFTRST_CON00_NPRESET_SHIFT (12U)
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#define CRU_SOFTRST_CON00_NPRESET_MASK (0x1U << CRU_SOFTRST_CON00_NPRESET_SHIFT) /* 0x00001000 */
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#define CRU_SOFTRST_CON00_NPERIPHRESET_SHIFT (13U)
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#define CRU_SOFTRST_CON00_NPERIPHRESET_MASK (0x1U << CRU_SOFTRST_CON00_NPERIPHRESET_SHIFT) /* 0x00002000 */
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/* SOFTRST_CON01 */
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#define CRU_SOFTRST_CON01_OFFSET (0x404U)
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#define CRU_SOFTRST_CON01_ARESETN_CORE_NIU2DDR_SHIFT (0U)
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#define CRU_SOFTRST_CON01_ARESETN_CORE_NIU2DDR_MASK (0x1U << CRU_SOFTRST_CON01_ARESETN_CORE_NIU2DDR_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON01_ARESETN_CORE_NIU2BUS_SHIFT (1U)
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#define CRU_SOFTRST_CON01_ARESETN_CORE_NIU2BUS_MASK (0x1U << CRU_SOFTRST_CON01_ARESETN_CORE_NIU2BUS_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON01_PRESETN_DBG_NIU_SHIFT (2U)
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#define CRU_SOFTRST_CON01_PRESETN_DBG_NIU_MASK (0x1U << CRU_SOFTRST_CON01_PRESETN_DBG_NIU_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON01_PRESETN_DBG_SHIFT (3U)
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#define CRU_SOFTRST_CON01_PRESETN_DBG_MASK (0x1U << CRU_SOFTRST_CON01_PRESETN_DBG_SHIFT) /* 0x00000008 */
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#define CRU_SOFTRST_CON01_PRESETN_DBG_DAPLITE_SHIFT (4U)
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#define CRU_SOFTRST_CON01_PRESETN_DBG_DAPLITE_MASK (0x1U << CRU_SOFTRST_CON01_PRESETN_DBG_DAPLITE_SHIFT) /* 0x00000010 */
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#define CRU_SOFTRST_CON01_RESETN_DAP_SHIFT (5U)
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#define CRU_SOFTRST_CON01_RESETN_DAP_MASK (0x1U << CRU_SOFTRST_CON01_RESETN_DAP_SHIFT) /* 0x00000020 */
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#define CRU_SOFTRST_CON01_ARESETN_ADB400_CORE2GIC_SHIFT (6U)
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#define CRU_SOFTRST_CON01_ARESETN_ADB400_CORE2GIC_MASK (0x1U << CRU_SOFTRST_CON01_ARESETN_ADB400_CORE2GIC_SHIFT) /* 0x00000040 */
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#define CRU_SOFTRST_CON01_ARESETN_ADB400_GIC2CORE_SHIFT (7U)
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#define CRU_SOFTRST_CON01_ARESETN_ADB400_GIC2CORE_MASK (0x1U << CRU_SOFTRST_CON01_ARESETN_ADB400_GIC2CORE_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON01_PRESETN_CORE_GRF_SHIFT (8U)
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#define CRU_SOFTRST_CON01_PRESETN_CORE_GRF_MASK (0x1U << CRU_SOFTRST_CON01_PRESETN_CORE_GRF_SHIFT) /* 0x00000100 */
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#define CRU_SOFTRST_CON01_PRESETN_CORE_PVTM_SHIFT (9U)
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#define CRU_SOFTRST_CON01_PRESETN_CORE_PVTM_MASK (0x1U << CRU_SOFTRST_CON01_PRESETN_CORE_PVTM_SHIFT) /* 0x00000200 */
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#define CRU_SOFTRST_CON01_RESETN_CORE_PVTM_SHIFT (10U)
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#define CRU_SOFTRST_CON01_RESETN_CORE_PVTM_MASK (0x1U << CRU_SOFTRST_CON01_RESETN_CORE_PVTM_SHIFT) /* 0x00000400 */
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#define CRU_SOFTRST_CON01_RESETN_CORE_PVTPLL_SHIFT (11U)
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#define CRU_SOFTRST_CON01_RESETN_CORE_PVTPLL_MASK (0x1U << CRU_SOFTRST_CON01_RESETN_CORE_PVTPLL_SHIFT) /* 0x00000800 */
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/* SOFTRST_CON02 */
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#define CRU_SOFTRST_CON02_OFFSET (0x408U)
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#define CRU_SOFTRST_CON02_RESETN_GPU_SHIFT (0U)
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#define CRU_SOFTRST_CON02_RESETN_GPU_MASK (0x1U << CRU_SOFTRST_CON02_RESETN_GPU_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON02_ARESETN_GPU_NIU_SHIFT (1U)
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#define CRU_SOFTRST_CON02_ARESETN_GPU_NIU_MASK (0x1U << CRU_SOFTRST_CON02_ARESETN_GPU_NIU_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON02_PRESETN_GPU_NIU_SHIFT (2U)
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#define CRU_SOFTRST_CON02_PRESETN_GPU_NIU_MASK (0x1U << CRU_SOFTRST_CON02_PRESETN_GPU_NIU_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON02_PRESETN_GPU_PVTM_SHIFT (3U)
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#define CRU_SOFTRST_CON02_PRESETN_GPU_PVTM_MASK (0x1U << CRU_SOFTRST_CON02_PRESETN_GPU_PVTM_SHIFT) /* 0x00000008 */
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#define CRU_SOFTRST_CON02_RESETN_GPU_PVTM_SHIFT (4U)
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#define CRU_SOFTRST_CON02_RESETN_GPU_PVTM_MASK (0x1U << CRU_SOFTRST_CON02_RESETN_GPU_PVTM_SHIFT) /* 0x00000010 */
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#define CRU_SOFTRST_CON02_RESETN_GPU_PVTPLL_SHIFT (5U)
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#define CRU_SOFTRST_CON02_RESETN_GPU_PVTPLL_MASK (0x1U << CRU_SOFTRST_CON02_RESETN_GPU_PVTPLL_SHIFT) /* 0x00000020 */
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#define CRU_SOFTRST_CON02_ARESETN_NPU_NIU_SHIFT (8U)
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#define CRU_SOFTRST_CON02_ARESETN_NPU_NIU_MASK (0x1U << CRU_SOFTRST_CON02_ARESETN_NPU_NIU_SHIFT) /* 0x00000100 */
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#define CRU_SOFTRST_CON02_HRESETN_NPU_NIU_SHIFT (9U)
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#define CRU_SOFTRST_CON02_HRESETN_NPU_NIU_MASK (0x1U << CRU_SOFTRST_CON02_HRESETN_NPU_NIU_SHIFT) /* 0x00000200 */
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#define CRU_SOFTRST_CON02_PRESETN_NPU_NIU_SHIFT (10U)
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#define CRU_SOFTRST_CON02_PRESETN_NPU_NIU_MASK (0x1U << CRU_SOFTRST_CON02_PRESETN_NPU_NIU_SHIFT) /* 0x00000400 */
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#define CRU_SOFTRST_CON02_ARESETN_RKNN_SHIFT (11U)
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#define CRU_SOFTRST_CON02_ARESETN_RKNN_MASK (0x1U << CRU_SOFTRST_CON02_ARESETN_RKNN_SHIFT) /* 0x00000800 */
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#define CRU_SOFTRST_CON02_HRESETN_RKNN_SHIFT (12U)
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#define CRU_SOFTRST_CON02_HRESETN_RKNN_MASK (0x1U << CRU_SOFTRST_CON02_HRESETN_RKNN_SHIFT) /* 0x00001000 */
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#define CRU_SOFTRST_CON02_PRESETN_NPU_PVTM_SHIFT (13U)
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#define CRU_SOFTRST_CON02_PRESETN_NPU_PVTM_MASK (0x1U << CRU_SOFTRST_CON02_PRESETN_NPU_PVTM_SHIFT) /* 0x00002000 */
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#define CRU_SOFTRST_CON02_RESETN_NPU_PVTM_SHIFT (14U)
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#define CRU_SOFTRST_CON02_RESETN_NPU_PVTM_MASK (0x1U << CRU_SOFTRST_CON02_RESETN_NPU_PVTM_SHIFT) /* 0x00004000 */
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#define CRU_SOFTRST_CON02_RESETN_NPU_PVTPLL_SHIFT (15U)
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#define CRU_SOFTRST_CON02_RESETN_NPU_PVTPLL_MASK (0x1U << CRU_SOFTRST_CON02_RESETN_NPU_PVTPLL_SHIFT) /* 0x00008000 */
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/* SOFTRST_CON03 */
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#define CRU_SOFTRST_CON03_OFFSET (0x40CU)
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#define CRU_SOFTRST_CON03_ARESETN_MSCH_SHIFT (3U)
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#define CRU_SOFTRST_CON03_ARESETN_MSCH_MASK (0x1U << CRU_SOFTRST_CON03_ARESETN_MSCH_SHIFT) /* 0x00000008 */
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#define CRU_SOFTRST_CON03_RESETN_HWFFC_CTRL_SHIFT (4U)
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#define CRU_SOFTRST_CON03_RESETN_HWFFC_CTRL_MASK (0x1U << CRU_SOFTRST_CON03_RESETN_HWFFC_CTRL_SHIFT) /* 0x00000010 */
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#define CRU_SOFTRST_CON03_RESETN_DDR_ALWAYSON_SHIFT (5U)
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#define CRU_SOFTRST_CON03_RESETN_DDR_ALWAYSON_MASK (0x1U << CRU_SOFTRST_CON03_RESETN_DDR_ALWAYSON_SHIFT) /* 0x00000020 */
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#define CRU_SOFTRST_CON03_ARESETN_DDRSPLIT_SHIFT (6U)
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#define CRU_SOFTRST_CON03_ARESETN_DDRSPLIT_MASK (0x1U << CRU_SOFTRST_CON03_ARESETN_DDRSPLIT_SHIFT) /* 0x00000040 */
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#define CRU_SOFTRST_CON03_RESETN_DDRDFI_CTL_SHIFT (7U)
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#define CRU_SOFTRST_CON03_RESETN_DDRDFI_CTL_MASK (0x1U << CRU_SOFTRST_CON03_RESETN_DDRDFI_CTL_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON03_ARESETN_DMA2DDR_SHIFT (9U)
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#define CRU_SOFTRST_CON03_ARESETN_DMA2DDR_MASK (0x1U << CRU_SOFTRST_CON03_ARESETN_DMA2DDR_SHIFT) /* 0x00000200 */
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/* SOFTRST_CON04 */
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#define CRU_SOFTRST_CON04_OFFSET (0x410U)
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#define CRU_SOFTRST_CON04_ARESETN_PERIMID_NIU_SHIFT (0U)
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#define CRU_SOFTRST_CON04_ARESETN_PERIMID_NIU_MASK (0x1U << CRU_SOFTRST_CON04_ARESETN_PERIMID_NIU_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON04_HRESETN_PERIMID_NIU_SHIFT (1U)
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#define CRU_SOFTRST_CON04_HRESETN_PERIMID_NIU_MASK (0x1U << CRU_SOFTRST_CON04_HRESETN_PERIMID_NIU_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON04_ARESETN_GIC_AUDIO_NIU_SHIFT (2U)
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#define CRU_SOFTRST_CON04_ARESETN_GIC_AUDIO_NIU_MASK (0x1U << CRU_SOFTRST_CON04_ARESETN_GIC_AUDIO_NIU_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON04_HRESETN_GIC_AUDIO_NIU_SHIFT (3U)
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#define CRU_SOFTRST_CON04_HRESETN_GIC_AUDIO_NIU_MASK (0x1U << CRU_SOFTRST_CON04_HRESETN_GIC_AUDIO_NIU_SHIFT) /* 0x00000008 */
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#define CRU_SOFTRST_CON04_ARESETN_GIC600_SHIFT (4U)
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#define CRU_SOFTRST_CON04_ARESETN_GIC600_MASK (0x1U << CRU_SOFTRST_CON04_ARESETN_GIC600_SHIFT) /* 0x00000010 */
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#define CRU_SOFTRST_CON04_ARESETN_GIC600_DEBUG_SHIFT (5U)
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#define CRU_SOFTRST_CON04_ARESETN_GIC600_DEBUG_MASK (0x1U << CRU_SOFTRST_CON04_ARESETN_GIC600_DEBUG_SHIFT) /* 0x00000020 */
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#define CRU_SOFTRST_CON04_ARESETN_GICADB_CORE2GIC_SHIFT (6U)
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#define CRU_SOFTRST_CON04_ARESETN_GICADB_CORE2GIC_MASK (0x1U << CRU_SOFTRST_CON04_ARESETN_GICADB_CORE2GIC_SHIFT) /* 0x00000040 */
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#define CRU_SOFTRST_CON04_ARESETN_GICADB_GIC2CORE_SHIFT (7U)
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#define CRU_SOFTRST_CON04_ARESETN_GICADB_GIC2CORE_MASK (0x1U << CRU_SOFTRST_CON04_ARESETN_GICADB_GIC2CORE_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON04_ARESETN_SPINLOCK_SHIFT (8U)
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#define CRU_SOFTRST_CON04_ARESETN_SPINLOCK_MASK (0x1U << CRU_SOFTRST_CON04_ARESETN_SPINLOCK_SHIFT) /* 0x00000100 */
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#define CRU_SOFTRST_CON04_HRESETN_SDMMC_BUFFER_SHIFT (9U)
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#define CRU_SOFTRST_CON04_HRESETN_SDMMC_BUFFER_MASK (0x1U << CRU_SOFTRST_CON04_HRESETN_SDMMC_BUFFER_SHIFT) /* 0x00000200 */
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#define CRU_SOFTRST_CON04_DRESETN_SDMMC_BUFFER_SHIFT (10U)
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#define CRU_SOFTRST_CON04_DRESETN_SDMMC_BUFFER_MASK (0x1U << CRU_SOFTRST_CON04_DRESETN_SDMMC_BUFFER_SHIFT) /* 0x00000400 */
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#define CRU_SOFTRST_CON04_HRESETN_I2S0_8CH_SHIFT (11U)
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#define CRU_SOFTRST_CON04_HRESETN_I2S0_8CH_MASK (0x1U << CRU_SOFTRST_CON04_HRESETN_I2S0_8CH_SHIFT) /* 0x00000800 */
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#define CRU_SOFTRST_CON04_HRESETN_I2S1_8CH_SHIFT (12U)
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#define CRU_SOFTRST_CON04_HRESETN_I2S1_8CH_MASK (0x1U << CRU_SOFTRST_CON04_HRESETN_I2S1_8CH_SHIFT) /* 0x00001000 */
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#define CRU_SOFTRST_CON04_HRESETN_I2S2_2CH_SHIFT (13U)
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#define CRU_SOFTRST_CON04_HRESETN_I2S2_2CH_MASK (0x1U << CRU_SOFTRST_CON04_HRESETN_I2S2_2CH_SHIFT) /* 0x00002000 */
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#define CRU_SOFTRST_CON04_HRESETN_I2S3_2CH_SHIFT (14U)
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#define CRU_SOFTRST_CON04_HRESETN_I2S3_2CH_MASK (0x1U << CRU_SOFTRST_CON04_HRESETN_I2S3_2CH_SHIFT) /* 0x00004000 */
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/* SOFTRST_CON05 */
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#define CRU_SOFTRST_CON05_OFFSET (0x414U)
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#define CRU_SOFTRST_CON05_MRESETN_I2S0_8CH_TX_SHIFT (0U)
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#define CRU_SOFTRST_CON05_MRESETN_I2S0_8CH_TX_MASK (0x1U << CRU_SOFTRST_CON05_MRESETN_I2S0_8CH_TX_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON05_MRESETN_I2S0_8CH_RX_SHIFT (1U)
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#define CRU_SOFTRST_CON05_MRESETN_I2S0_8CH_RX_MASK (0x1U << CRU_SOFTRST_CON05_MRESETN_I2S0_8CH_RX_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON05_MRESETN_I2S1_8CH_TX_SHIFT (2U)
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#define CRU_SOFTRST_CON05_MRESETN_I2S1_8CH_TX_MASK (0x1U << CRU_SOFTRST_CON05_MRESETN_I2S1_8CH_TX_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON05_MRESETN_I2S1_8CH_RX_SHIFT (3U)
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#define CRU_SOFTRST_CON05_MRESETN_I2S1_8CH_RX_MASK (0x1U << CRU_SOFTRST_CON05_MRESETN_I2S1_8CH_RX_SHIFT) /* 0x00000008 */
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#define CRU_SOFTRST_CON05_MRESETN_I2S2_2CH_SHIFT (4U)
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#define CRU_SOFTRST_CON05_MRESETN_I2S2_2CH_MASK (0x1U << CRU_SOFTRST_CON05_MRESETN_I2S2_2CH_SHIFT) /* 0x00000010 */
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#define CRU_SOFTRST_CON05_MRESETN_I2S3_2CH_TX_SHIFT (5U)
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#define CRU_SOFTRST_CON05_MRESETN_I2S3_2CH_TX_MASK (0x1U << CRU_SOFTRST_CON05_MRESETN_I2S3_2CH_TX_SHIFT) /* 0x00000020 */
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#define CRU_SOFTRST_CON05_MRESETN_I2S3_2CH_RX_SHIFT (6U)
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#define CRU_SOFTRST_CON05_MRESETN_I2S3_2CH_RX_MASK (0x1U << CRU_SOFTRST_CON05_MRESETN_I2S3_2CH_RX_SHIFT) /* 0x00000040 */
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#define CRU_SOFTRST_CON05_HRESETN_PDM_SHIFT (7U)
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#define CRU_SOFTRST_CON05_HRESETN_PDM_MASK (0x1U << CRU_SOFTRST_CON05_HRESETN_PDM_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON05_MRESETN_PDM_SHIFT (8U)
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#define CRU_SOFTRST_CON05_MRESETN_PDM_MASK (0x1U << CRU_SOFTRST_CON05_MRESETN_PDM_SHIFT) /* 0x00000100 */
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#define CRU_SOFTRST_CON05_HRESETN_VAD_SHIFT (9U)
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#define CRU_SOFTRST_CON05_HRESETN_VAD_MASK (0x1U << CRU_SOFTRST_CON05_HRESETN_VAD_SHIFT) /* 0x00000200 */
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#define CRU_SOFTRST_CON05_HRESETN_SPDIF_8CH_SHIFT (10U)
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#define CRU_SOFTRST_CON05_HRESETN_SPDIF_8CH_MASK (0x1U << CRU_SOFTRST_CON05_HRESETN_SPDIF_8CH_SHIFT) /* 0x00000400 */
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#define CRU_SOFTRST_CON05_MRESETN_SPDIF_8CH_SHIFT (11U)
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#define CRU_SOFTRST_CON05_MRESETN_SPDIF_8CH_MASK (0x1U << CRU_SOFTRST_CON05_MRESETN_SPDIF_8CH_SHIFT) /* 0x00000800 */
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#define CRU_SOFTRST_CON05_HRESETN_AUDPWM_SHIFT (12U)
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#define CRU_SOFTRST_CON05_HRESETN_AUDPWM_MASK (0x1U << CRU_SOFTRST_CON05_HRESETN_AUDPWM_SHIFT) /* 0x00001000 */
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#define CRU_SOFTRST_CON05_SRESETN_AUDPWM_SHIFT (13U)
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#define CRU_SOFTRST_CON05_SRESETN_AUDPWM_MASK (0x1U << CRU_SOFTRST_CON05_SRESETN_AUDPWM_SHIFT) /* 0x00002000 */
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#define CRU_SOFTRST_CON05_HRESETN_ACDCDIG_SHIFT (14U)
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#define CRU_SOFTRST_CON05_HRESETN_ACDCDIG_MASK (0x1U << CRU_SOFTRST_CON05_HRESETN_ACDCDIG_SHIFT) /* 0x00004000 */
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#define CRU_SOFTRST_CON05_RESETN_ACDCDIG_SHIFT (15U)
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#define CRU_SOFTRST_CON05_RESETN_ACDCDIG_MASK (0x1U << CRU_SOFTRST_CON05_RESETN_ACDCDIG_SHIFT) /* 0x00008000 */
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/* SOFTRST_CON06 */
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#define CRU_SOFTRST_CON06_OFFSET (0x418U)
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#define CRU_SOFTRST_CON06_ARESETN_SECURE_FLASH_NIU_SHIFT (0U)
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#define CRU_SOFTRST_CON06_ARESETN_SECURE_FLASH_NIU_MASK (0x1U << CRU_SOFTRST_CON06_ARESETN_SECURE_FLASH_NIU_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON06_HRESETN_SECURE_FLASH_NIU_SHIFT (1U)
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#define CRU_SOFTRST_CON06_HRESETN_SECURE_FLASH_NIU_MASK (0x1U << CRU_SOFTRST_CON06_HRESETN_SECURE_FLASH_NIU_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON06_ARESETN_CRYPTO_NS_SHIFT (7U)
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#define CRU_SOFTRST_CON06_ARESETN_CRYPTO_NS_MASK (0x1U << CRU_SOFTRST_CON06_ARESETN_CRYPTO_NS_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON06_HRESETN_CRYPTO_NS_SHIFT (8U)
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#define CRU_SOFTRST_CON06_HRESETN_CRYPTO_NS_MASK (0x1U << CRU_SOFTRST_CON06_HRESETN_CRYPTO_NS_SHIFT) /* 0x00000100 */
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#define CRU_SOFTRST_CON06_RESETN_CRYPTO_NS_CORE_SHIFT (9U)
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#define CRU_SOFTRST_CON06_RESETN_CRYPTO_NS_CORE_MASK (0x1U << CRU_SOFTRST_CON06_RESETN_CRYPTO_NS_CORE_SHIFT) /* 0x00000200 */
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#define CRU_SOFTRST_CON06_RESETN_CRYPTO_NS_PKA_SHIFT (10U)
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#define CRU_SOFTRST_CON06_RESETN_CRYPTO_NS_PKA_MASK (0x1U << CRU_SOFTRST_CON06_RESETN_CRYPTO_NS_PKA_SHIFT) /* 0x00000400 */
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#define CRU_SOFTRST_CON06_RESETN_CRYPTO_NS_RNG_SHIFT (11U)
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#define CRU_SOFTRST_CON06_RESETN_CRYPTO_NS_RNG_MASK (0x1U << CRU_SOFTRST_CON06_RESETN_CRYPTO_NS_RNG_SHIFT) /* 0x00000800 */
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#define CRU_SOFTRST_CON06_HRESETN_TRNG_NS_SHIFT (12U)
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#define CRU_SOFTRST_CON06_HRESETN_TRNG_NS_MASK (0x1U << CRU_SOFTRST_CON06_HRESETN_TRNG_NS_SHIFT) /* 0x00001000 */
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#define CRU_SOFTRST_CON06_RESETN_TRNG_NS_SHIFT (13U)
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#define CRU_SOFTRST_CON06_RESETN_TRNG_NS_MASK (0x1U << CRU_SOFTRST_CON06_RESETN_TRNG_NS_SHIFT) /* 0x00002000 */
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/* SOFTRST_CON07 */
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#define CRU_SOFTRST_CON07_OFFSET (0x41CU)
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#define CRU_SOFTRST_CON07_HRESETN_NANDC_SHIFT (0U)
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#define CRU_SOFTRST_CON07_HRESETN_NANDC_MASK (0x1U << CRU_SOFTRST_CON07_HRESETN_NANDC_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON07_NRESETN_NANDC_SHIFT (1U)
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#define CRU_SOFTRST_CON07_NRESETN_NANDC_MASK (0x1U << CRU_SOFTRST_CON07_NRESETN_NANDC_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON07_HRESETN_SFC_SHIFT (2U)
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#define CRU_SOFTRST_CON07_HRESETN_SFC_MASK (0x1U << CRU_SOFTRST_CON07_HRESETN_SFC_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON07_HRESETN_SFC_XIP_SHIFT (3U)
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#define CRU_SOFTRST_CON07_HRESETN_SFC_XIP_MASK (0x1U << CRU_SOFTRST_CON07_HRESETN_SFC_XIP_SHIFT) /* 0x00000008 */
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#define CRU_SOFTRST_CON07_SRESETN_SFC_SHIFT (4U)
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#define CRU_SOFTRST_CON07_SRESETN_SFC_MASK (0x1U << CRU_SOFTRST_CON07_SRESETN_SFC_SHIFT) /* 0x00000010 */
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#define CRU_SOFTRST_CON07_ARESETN_EMMC_SHIFT (5U)
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#define CRU_SOFTRST_CON07_ARESETN_EMMC_MASK (0x1U << CRU_SOFTRST_CON07_ARESETN_EMMC_SHIFT) /* 0x00000020 */
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#define CRU_SOFTRST_CON07_HRESETN_EMMC_SHIFT (6U)
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#define CRU_SOFTRST_CON07_HRESETN_EMMC_MASK (0x1U << CRU_SOFTRST_CON07_HRESETN_EMMC_SHIFT) /* 0x00000040 */
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#define CRU_SOFTRST_CON07_BRESETN_EMMC_SHIFT (7U)
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#define CRU_SOFTRST_CON07_BRESETN_EMMC_MASK (0x1U << CRU_SOFTRST_CON07_BRESETN_EMMC_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON07_CRESETN_EMMC_SHIFT (8U)
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#define CRU_SOFTRST_CON07_CRESETN_EMMC_MASK (0x1U << CRU_SOFTRST_CON07_CRESETN_EMMC_SHIFT) /* 0x00000100 */
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#define CRU_SOFTRST_CON07_TRESETN_EMMC_SHIFT (9U)
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#define CRU_SOFTRST_CON07_TRESETN_EMMC_MASK (0x1U << CRU_SOFTRST_CON07_TRESETN_EMMC_SHIFT) /* 0x00000200 */
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/* SOFTRST_CON08 */
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#define CRU_SOFTRST_CON08_OFFSET (0x420U)
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#define CRU_SOFTRST_CON08_ARESETN_PIPE_NIU_SHIFT (0U)
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#define CRU_SOFTRST_CON08_ARESETN_PIPE_NIU_MASK (0x1U << CRU_SOFTRST_CON08_ARESETN_PIPE_NIU_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON08_PRESETN_PIPE_NIU_SHIFT (2U)
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#define CRU_SOFTRST_CON08_PRESETN_PIPE_NIU_MASK (0x1U << CRU_SOFTRST_CON08_PRESETN_PIPE_NIU_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON08_PRESETN_PIPE_GRF_SHIFT (5U)
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#define CRU_SOFTRST_CON08_PRESETN_PIPE_GRF_MASK (0x1U << CRU_SOFTRST_CON08_PRESETN_PIPE_GRF_SHIFT) /* 0x00000020 */
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#define CRU_SOFTRST_CON08_ARESETN_SATA0_SHIFT (6U)
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#define CRU_SOFTRST_CON08_ARESETN_SATA0_MASK (0x1U << CRU_SOFTRST_CON08_ARESETN_SATA0_SHIFT) /* 0x00000040 */
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#define CRU_SOFTRST_CON08_RESETN_SATA0_PIPE_SHIFT (7U)
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#define CRU_SOFTRST_CON08_RESETN_SATA0_PIPE_MASK (0x1U << CRU_SOFTRST_CON08_RESETN_SATA0_PIPE_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON08_RESETN_SATA0_PMALIVE_SHIFT (8U)
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#define CRU_SOFTRST_CON08_RESETN_SATA0_PMALIVE_MASK (0x1U << CRU_SOFTRST_CON08_RESETN_SATA0_PMALIVE_SHIFT) /* 0x00000100 */
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#define CRU_SOFTRST_CON08_RESETN_SATA0_RXOOB_SHIFT (9U)
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#define CRU_SOFTRST_CON08_RESETN_SATA0_RXOOB_MASK (0x1U << CRU_SOFTRST_CON08_RESETN_SATA0_RXOOB_SHIFT) /* 0x00000200 */
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#define CRU_SOFTRST_CON08_ARESETN_SATA1_SHIFT (10U)
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#define CRU_SOFTRST_CON08_ARESETN_SATA1_MASK (0x1U << CRU_SOFTRST_CON08_ARESETN_SATA1_SHIFT) /* 0x00000400 */
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#define CRU_SOFTRST_CON08_RESETN_SATA1_PIPE_SHIFT (11U)
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#define CRU_SOFTRST_CON08_RESETN_SATA1_PIPE_MASK (0x1U << CRU_SOFTRST_CON08_RESETN_SATA1_PIPE_SHIFT) /* 0x00000800 */
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#define CRU_SOFTRST_CON08_RESETN_SATA1_PMALIVE_SHIFT (12U)
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#define CRU_SOFTRST_CON08_RESETN_SATA1_PMALIVE_MASK (0x1U << CRU_SOFTRST_CON08_RESETN_SATA1_PMALIVE_SHIFT) /* 0x00001000 */
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#define CRU_SOFTRST_CON08_RESETN_SATA1_RXOOB_SHIFT (13U)
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#define CRU_SOFTRST_CON08_RESETN_SATA1_RXOOB_MASK (0x1U << CRU_SOFTRST_CON08_RESETN_SATA1_RXOOB_SHIFT) /* 0x00002000 */
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/* SOFTRST_CON09 */
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#define CRU_SOFTRST_CON09_OFFSET (0x424U)
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#define CRU_SOFTRST_CON09_ARESETN_SATA2_SHIFT (0U)
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#define CRU_SOFTRST_CON09_ARESETN_SATA2_MASK (0x1U << CRU_SOFTRST_CON09_ARESETN_SATA2_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON09_RESETN_SATA2_PIPE_SHIFT (1U)
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#define CRU_SOFTRST_CON09_RESETN_SATA2_PIPE_MASK (0x1U << CRU_SOFTRST_CON09_RESETN_SATA2_PIPE_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON09_RESETN_SATA2_PMALIVE_SHIFT (2U)
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#define CRU_SOFTRST_CON09_RESETN_SATA2_PMALIVE_MASK (0x1U << CRU_SOFTRST_CON09_RESETN_SATA2_PMALIVE_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON09_RESETN_SATA2_RXOOB_SHIFT (3U)
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#define CRU_SOFTRST_CON09_RESETN_SATA2_RXOOB_MASK (0x1U << CRU_SOFTRST_CON09_RESETN_SATA2_RXOOB_SHIFT) /* 0x00000008 */
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#define CRU_SOFTRST_CON09_RESETN_USB3OTG0_SHIFT (4U)
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#define CRU_SOFTRST_CON09_RESETN_USB3OTG0_MASK (0x1U << CRU_SOFTRST_CON09_RESETN_USB3OTG0_SHIFT) /* 0x00000010 */
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#define CRU_SOFTRST_CON09_RESETN_USB3OTG1_SHIFT (5U)
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#define CRU_SOFTRST_CON09_RESETN_USB3OTG1_MASK (0x1U << CRU_SOFTRST_CON09_RESETN_USB3OTG1_SHIFT) /* 0x00000020 */
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#define CRU_SOFTRST_CON09_RESETN_XPCS_SHIFT (6U)
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#define CRU_SOFTRST_CON09_RESETN_XPCS_MASK (0x1U << CRU_SOFTRST_CON09_RESETN_XPCS_SHIFT) /* 0x00000040 */
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#define CRU_SOFTRST_CON09_RESETN_XPCS_TX_DIV10_SHIFT (7U)
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#define CRU_SOFTRST_CON09_RESETN_XPCS_TX_DIV10_MASK (0x1U << CRU_SOFTRST_CON09_RESETN_XPCS_TX_DIV10_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON09_RESETN_XPCS_RX_DIV10_SHIFT (8U)
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#define CRU_SOFTRST_CON09_RESETN_XPCS_RX_DIV10_MASK (0x1U << CRU_SOFTRST_CON09_RESETN_XPCS_RX_DIV10_SHIFT) /* 0x00000100 */
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#define CRU_SOFTRST_CON09_RESETN_XPCS_XGXS_RX_SHIFT (9U)
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#define CRU_SOFTRST_CON09_RESETN_XPCS_XGXS_RX_MASK (0x1U << CRU_SOFTRST_CON09_RESETN_XPCS_XGXS_RX_SHIFT) /* 0x00000200 */
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/* SOFTRST_CON10 */
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#define CRU_SOFTRST_CON10_OFFSET (0x428U)
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#define CRU_SOFTRST_CON10_PRESETN_PCIE20_SHIFT (0U)
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#define CRU_SOFTRST_CON10_PRESETN_PCIE20_MASK (0x1U << CRU_SOFTRST_CON10_PRESETN_PCIE20_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON10_RESETN_PCIE20_POWERUP_REQ_SHIFT (1U)
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#define CRU_SOFTRST_CON10_RESETN_PCIE20_POWERUP_REQ_MASK (0x1U << CRU_SOFTRST_CON10_RESETN_PCIE20_POWERUP_REQ_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON10_MSTR_ARESET_PCIE20_REQ_SHIFT (2U)
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#define CRU_SOFTRST_CON10_MSTR_ARESET_PCIE20_REQ_MASK (0x1U << CRU_SOFTRST_CON10_MSTR_ARESET_PCIE20_REQ_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON10_SLV_ARESET_PCIE20_REQ_SHIFT (3U)
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#define CRU_SOFTRST_CON10_SLV_ARESET_PCIE20_REQ_MASK (0x1U << CRU_SOFTRST_CON10_SLV_ARESET_PCIE20_REQ_SHIFT) /* 0x00000008 */
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#define CRU_SOFTRST_CON10_DBI_ARESET_PCIE20_REQ_SHIFT (4U)
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#define CRU_SOFTRST_CON10_DBI_ARESET_PCIE20_REQ_MASK (0x1U << CRU_SOFTRST_CON10_DBI_ARESET_PCIE20_REQ_SHIFT) /* 0x00000010 */
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#define CRU_SOFTRST_CON10_BRESET_PCIE20_REQ_SHIFT (5U)
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#define CRU_SOFTRST_CON10_BRESET_PCIE20_REQ_MASK (0x1U << CRU_SOFTRST_CON10_BRESET_PCIE20_REQ_SHIFT) /* 0x00000020 */
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#define CRU_SOFTRST_CON10_PERST_PCIE20_REQ_SHIFT (6U)
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#define CRU_SOFTRST_CON10_PERST_PCIE20_REQ_MASK (0x1U << CRU_SOFTRST_CON10_PERST_PCIE20_REQ_SHIFT) /* 0x00000040 */
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#define CRU_SOFTRST_CON10_CORE_RST_PCIE20_REQ_SHIFT (7U)
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#define CRU_SOFTRST_CON10_CORE_RST_PCIE20_REQ_MASK (0x1U << CRU_SOFTRST_CON10_CORE_RST_PCIE20_REQ_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON10_NSTICKY_RST_PCIE20_REQ_SHIFT (8U)
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#define CRU_SOFTRST_CON10_NSTICKY_RST_PCIE20_REQ_MASK (0x1U << CRU_SOFTRST_CON10_NSTICKY_RST_PCIE20_REQ_SHIFT) /* 0x00000100 */
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#define CRU_SOFTRST_CON10_STICKY_RST_PCIE20_REQ_SHIFT (9U)
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#define CRU_SOFTRST_CON10_STICKY_RST_PCIE20_REQ_MASK (0x1U << CRU_SOFTRST_CON10_STICKY_RST_PCIE20_REQ_SHIFT) /* 0x00000200 */
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#define CRU_SOFTRST_CON10_PWR_RST_PCIE20_REQ_SHIFT (10U)
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#define CRU_SOFTRST_CON10_PWR_RST_PCIE20_REQ_MASK (0x1U << CRU_SOFTRST_CON10_PWR_RST_PCIE20_REQ_SHIFT) /* 0x00000400 */
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/* SOFTRST_CON11 */
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#define CRU_SOFTRST_CON11_OFFSET (0x42CU)
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#define CRU_SOFTRST_CON11_PRESETN_PCIE30X1_SHIFT (0U)
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#define CRU_SOFTRST_CON11_PRESETN_PCIE30X1_MASK (0x1U << CRU_SOFTRST_CON11_PRESETN_PCIE30X1_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON11_RESETN_PCIE30X1_POWERUP_REQ_SHIFT (1U)
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#define CRU_SOFTRST_CON11_RESETN_PCIE30X1_POWERUP_REQ_MASK (0x1U << CRU_SOFTRST_CON11_RESETN_PCIE30X1_POWERUP_REQ_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON11_MSTR_ARESET_PCIE30X1_REQ_SHIFT (2U)
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#define CRU_SOFTRST_CON11_MSTR_ARESET_PCIE30X1_REQ_MASK (0x1U << CRU_SOFTRST_CON11_MSTR_ARESET_PCIE30X1_REQ_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON11_SLV_ARESET_PCIE30X1_REQ_SHIFT (3U)
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#define CRU_SOFTRST_CON11_SLV_ARESET_PCIE30X1_REQ_MASK (0x1U << CRU_SOFTRST_CON11_SLV_ARESET_PCIE30X1_REQ_SHIFT) /* 0x00000008 */
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#define CRU_SOFTRST_CON11_DBI_ARESET_PCIE30X1_REQ_SHIFT (4U)
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#define CRU_SOFTRST_CON11_DBI_ARESET_PCIE30X1_REQ_MASK (0x1U << CRU_SOFTRST_CON11_DBI_ARESET_PCIE30X1_REQ_SHIFT) /* 0x00000010 */
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#define CRU_SOFTRST_CON11_BRESET_PCIE30X1_REQ_SHIFT (5U)
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#define CRU_SOFTRST_CON11_BRESET_PCIE30X1_REQ_MASK (0x1U << CRU_SOFTRST_CON11_BRESET_PCIE30X1_REQ_SHIFT) /* 0x00000020 */
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#define CRU_SOFTRST_CON11_PERST_PCIE30X1_REQ_SHIFT (6U)
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#define CRU_SOFTRST_CON11_PERST_PCIE30X1_REQ_MASK (0x1U << CRU_SOFTRST_CON11_PERST_PCIE30X1_REQ_SHIFT) /* 0x00000040 */
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#define CRU_SOFTRST_CON11_CORE_RST_PCIE30X1_REQ_SHIFT (7U)
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#define CRU_SOFTRST_CON11_CORE_RST_PCIE30X1_REQ_MASK (0x1U << CRU_SOFTRST_CON11_CORE_RST_PCIE30X1_REQ_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON11_NSTICKY_RST_PCIE30X1_REQ_SHIFT (8U)
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#define CRU_SOFTRST_CON11_NSTICKY_RST_PCIE30X1_REQ_MASK (0x1U << CRU_SOFTRST_CON11_NSTICKY_RST_PCIE30X1_REQ_SHIFT) /* 0x00000100 */
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#define CRU_SOFTRST_CON11_STICKY_RST_PCIE30X1_REQ_SHIFT (9U)
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#define CRU_SOFTRST_CON11_STICKY_RST_PCIE30X1_REQ_MASK (0x1U << CRU_SOFTRST_CON11_STICKY_RST_PCIE30X1_REQ_SHIFT) /* 0x00000200 */
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#define CRU_SOFTRST_CON11_PWR_RST_PCIE30X1_REQ_SHIFT (10U)
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#define CRU_SOFTRST_CON11_PWR_RST_PCIE30X1_REQ_MASK (0x1U << CRU_SOFTRST_CON11_PWR_RST_PCIE30X1_REQ_SHIFT) /* 0x00000400 */
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/* SOFTRST_CON12 */
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#define CRU_SOFTRST_CON12_OFFSET (0x430U)
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#define CRU_SOFTRST_CON12_PRESETN_PCIE30X2_SHIFT (0U)
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#define CRU_SOFTRST_CON12_PRESETN_PCIE30X2_MASK (0x1U << CRU_SOFTRST_CON12_PRESETN_PCIE30X2_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON12_RESETN_PCIE30X2_POWERUP_REQ_SHIFT (1U)
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#define CRU_SOFTRST_CON12_RESETN_PCIE30X2_POWERUP_REQ_MASK (0x1U << CRU_SOFTRST_CON12_RESETN_PCIE30X2_POWERUP_REQ_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON12_MSTR_ARESET_PCIE30X2_REQ_SHIFT (2U)
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#define CRU_SOFTRST_CON12_MSTR_ARESET_PCIE30X2_REQ_MASK (0x1U << CRU_SOFTRST_CON12_MSTR_ARESET_PCIE30X2_REQ_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON12_SLV_ARESET_PCIE30X2_REQ_SHIFT (3U)
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#define CRU_SOFTRST_CON12_SLV_ARESET_PCIE30X2_REQ_MASK (0x1U << CRU_SOFTRST_CON12_SLV_ARESET_PCIE30X2_REQ_SHIFT) /* 0x00000008 */
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#define CRU_SOFTRST_CON12_DBI_ARESET_PCIE30X2_REQ_SHIFT (4U)
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#define CRU_SOFTRST_CON12_DBI_ARESET_PCIE30X2_REQ_MASK (0x1U << CRU_SOFTRST_CON12_DBI_ARESET_PCIE30X2_REQ_SHIFT) /* 0x00000010 */
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#define CRU_SOFTRST_CON12_BRESET_PCIE30X2_REQ_SHIFT (5U)
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#define CRU_SOFTRST_CON12_BRESET_PCIE30X2_REQ_MASK (0x1U << CRU_SOFTRST_CON12_BRESET_PCIE30X2_REQ_SHIFT) /* 0x00000020 */
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#define CRU_SOFTRST_CON12_PERST_PCIE30X2_REQ_SHIFT (6U)
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#define CRU_SOFTRST_CON12_PERST_PCIE30X2_REQ_MASK (0x1U << CRU_SOFTRST_CON12_PERST_PCIE30X2_REQ_SHIFT) /* 0x00000040 */
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#define CRU_SOFTRST_CON12_CORE_RST_PCIE30X2_REQ_SHIFT (7U)
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#define CRU_SOFTRST_CON12_CORE_RST_PCIE30X2_REQ_MASK (0x1U << CRU_SOFTRST_CON12_CORE_RST_PCIE30X2_REQ_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON12_NSTICKY_RST_PCIE30X2_REQ_SHIFT (8U)
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#define CRU_SOFTRST_CON12_NSTICKY_RST_PCIE30X2_REQ_MASK (0x1U << CRU_SOFTRST_CON12_NSTICKY_RST_PCIE30X2_REQ_SHIFT) /* 0x00000100 */
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#define CRU_SOFTRST_CON12_STICKY_RST_PCIE30X2_REQ_SHIFT (9U)
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#define CRU_SOFTRST_CON12_STICKY_RST_PCIE30X2_REQ_MASK (0x1U << CRU_SOFTRST_CON12_STICKY_RST_PCIE30X2_REQ_SHIFT) /* 0x00000200 */
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#define CRU_SOFTRST_CON12_PWR_RST_PCIE30X2_REQ_SHIFT (10U)
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#define CRU_SOFTRST_CON12_PWR_RST_PCIE30X2_REQ_MASK (0x1U << CRU_SOFTRST_CON12_PWR_RST_PCIE30X2_REQ_SHIFT) /* 0x00000400 */
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/* SOFTRST_CON13 */
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#define CRU_SOFTRST_CON13_OFFSET (0x434U)
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#define CRU_SOFTRST_CON13_ARESETN_PHP_NIU_SHIFT (0U)
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#define CRU_SOFTRST_CON13_ARESETN_PHP_NIU_MASK (0x1U << CRU_SOFTRST_CON13_ARESETN_PHP_NIU_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON13_HRESETN_PHP_NIU_SHIFT (1U)
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#define CRU_SOFTRST_CON13_HRESETN_PHP_NIU_MASK (0x1U << CRU_SOFTRST_CON13_HRESETN_PHP_NIU_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON13_PRESETN_PHP_NIU_SHIFT (2U)
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#define CRU_SOFTRST_CON13_PRESETN_PHP_NIU_MASK (0x1U << CRU_SOFTRST_CON13_PRESETN_PHP_NIU_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON13_HRESETN_SDMMC0_SHIFT (3U)
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#define CRU_SOFTRST_CON13_HRESETN_SDMMC0_MASK (0x1U << CRU_SOFTRST_CON13_HRESETN_SDMMC0_SHIFT) /* 0x00000008 */
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#define CRU_SOFTRST_CON13_RESETN_SDMMC0_SHIFT (4U)
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#define CRU_SOFTRST_CON13_RESETN_SDMMC0_MASK (0x1U << CRU_SOFTRST_CON13_RESETN_SDMMC0_SHIFT) /* 0x00000010 */
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#define CRU_SOFTRST_CON13_HRESETN_SDMMC1_SHIFT (5U)
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#define CRU_SOFTRST_CON13_HRESETN_SDMMC1_MASK (0x1U << CRU_SOFTRST_CON13_HRESETN_SDMMC1_SHIFT) /* 0x00000020 */
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#define CRU_SOFTRST_CON13_RESETN_SDMMC1_SHIFT (6U)
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#define CRU_SOFTRST_CON13_RESETN_SDMMC1_MASK (0x1U << CRU_SOFTRST_CON13_RESETN_SDMMC1_SHIFT) /* 0x00000040 */
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#define CRU_SOFTRST_CON13_ARESETN_GMAC0_SHIFT (7U)
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#define CRU_SOFTRST_CON13_ARESETN_GMAC0_MASK (0x1U << CRU_SOFTRST_CON13_ARESETN_GMAC0_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON13_RESETN_GMAC0_TIMESTAMP_SHIFT (8U)
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#define CRU_SOFTRST_CON13_RESETN_GMAC0_TIMESTAMP_MASK (0x1U << CRU_SOFTRST_CON13_RESETN_GMAC0_TIMESTAMP_SHIFT) /* 0x00000100 */
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/* SOFTRST_CON14 */
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#define CRU_SOFTRST_CON14_OFFSET (0x438U)
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#define CRU_SOFTRST_CON14_ARESETN_USB_NIU_SHIFT (0U)
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#define CRU_SOFTRST_CON14_ARESETN_USB_NIU_MASK (0x1U << CRU_SOFTRST_CON14_ARESETN_USB_NIU_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON14_HRESETN_USB_NIU_SHIFT (1U)
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#define CRU_SOFTRST_CON14_HRESETN_USB_NIU_MASK (0x1U << CRU_SOFTRST_CON14_HRESETN_USB_NIU_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON14_PRESETN_USB_NIU_SHIFT (2U)
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#define CRU_SOFTRST_CON14_PRESETN_USB_NIU_MASK (0x1U << CRU_SOFTRST_CON14_PRESETN_USB_NIU_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON14_PRESETN_USB_GRF_SHIFT (3U)
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#define CRU_SOFTRST_CON14_PRESETN_USB_GRF_MASK (0x1U << CRU_SOFTRST_CON14_PRESETN_USB_GRF_SHIFT) /* 0x00000008 */
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#define CRU_SOFTRST_CON14_HRESETN_USB2HOST0_SHIFT (4U)
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#define CRU_SOFTRST_CON14_HRESETN_USB2HOST0_MASK (0x1U << CRU_SOFTRST_CON14_HRESETN_USB2HOST0_SHIFT) /* 0x00000010 */
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#define CRU_SOFTRST_CON14_HRESETN_USB2HOST0_ARB_SHIFT (5U)
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#define CRU_SOFTRST_CON14_HRESETN_USB2HOST0_ARB_MASK (0x1U << CRU_SOFTRST_CON14_HRESETN_USB2HOST0_ARB_SHIFT) /* 0x00000020 */
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#define CRU_SOFTRST_CON14_RESETN_USB2HOST0_UTMI_SHIFT (6U)
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#define CRU_SOFTRST_CON14_RESETN_USB2HOST0_UTMI_MASK (0x1U << CRU_SOFTRST_CON14_RESETN_USB2HOST0_UTMI_SHIFT) /* 0x00000040 */
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#define CRU_SOFTRST_CON14_HRESETN_USB2HOST1_SHIFT (7U)
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#define CRU_SOFTRST_CON14_HRESETN_USB2HOST1_MASK (0x1U << CRU_SOFTRST_CON14_HRESETN_USB2HOST1_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON14_HRESETN_USB2HOST1_ARB_SHIFT (8U)
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#define CRU_SOFTRST_CON14_HRESETN_USB2HOST1_ARB_MASK (0x1U << CRU_SOFTRST_CON14_HRESETN_USB2HOST1_ARB_SHIFT) /* 0x00000100 */
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#define CRU_SOFTRST_CON14_RESETN_USB2HOST1_UTMI_SHIFT (9U)
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#define CRU_SOFTRST_CON14_RESETN_USB2HOST1_UTMI_MASK (0x1U << CRU_SOFTRST_CON14_RESETN_USB2HOST1_UTMI_SHIFT) /* 0x00000200 */
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#define CRU_SOFTRST_CON14_HRESETN_SDMMC2_SHIFT (10U)
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#define CRU_SOFTRST_CON14_HRESETN_SDMMC2_MASK (0x1U << CRU_SOFTRST_CON14_HRESETN_SDMMC2_SHIFT) /* 0x00000400 */
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#define CRU_SOFTRST_CON14_RESETN_SDMMC2_SHIFT (11U)
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#define CRU_SOFTRST_CON14_RESETN_SDMMC2_MASK (0x1U << CRU_SOFTRST_CON14_RESETN_SDMMC2_SHIFT) /* 0x00000800 */
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#define CRU_SOFTRST_CON14_ARESETN_GMAC1_SHIFT (12U)
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#define CRU_SOFTRST_CON14_ARESETN_GMAC1_MASK (0x1U << CRU_SOFTRST_CON14_ARESETN_GMAC1_SHIFT) /* 0x00001000 */
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#define CRU_SOFTRST_CON14_RESETN_GMAC1_TIMESTAMP_SHIFT (13U)
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#define CRU_SOFTRST_CON14_RESETN_GMAC1_TIMESTAMP_MASK (0x1U << CRU_SOFTRST_CON14_RESETN_GMAC1_TIMESTAMP_SHIFT) /* 0x00002000 */
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/* SOFTRST_CON15 */
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#define CRU_SOFTRST_CON15_OFFSET (0x43CU)
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#define CRU_SOFTRST_CON15_ARESETN_VI_NIU_SHIFT (0U)
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#define CRU_SOFTRST_CON15_ARESETN_VI_NIU_MASK (0x1U << CRU_SOFTRST_CON15_ARESETN_VI_NIU_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON15_HRESETN_VI_NIU_SHIFT (1U)
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#define CRU_SOFTRST_CON15_HRESETN_VI_NIU_MASK (0x1U << CRU_SOFTRST_CON15_HRESETN_VI_NIU_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON15_PRESETN_VI_NIU_SHIFT (2U)
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#define CRU_SOFTRST_CON15_PRESETN_VI_NIU_MASK (0x1U << CRU_SOFTRST_CON15_PRESETN_VI_NIU_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON15_ARESETN_VICAP1_SHIFT (7U)
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#define CRU_SOFTRST_CON15_ARESETN_VICAP1_MASK (0x1U << CRU_SOFTRST_CON15_ARESETN_VICAP1_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON15_HRESETN_VICAP1_SHIFT (8U)
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#define CRU_SOFTRST_CON15_HRESETN_VICAP1_MASK (0x1U << CRU_SOFTRST_CON15_HRESETN_VICAP1_SHIFT) /* 0x00000100 */
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#define CRU_SOFTRST_CON15_DRESETN_VICAP1_SHIFT (9U)
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#define CRU_SOFTRST_CON15_DRESETN_VICAP1_MASK (0x1U << CRU_SOFTRST_CON15_DRESETN_VICAP1_SHIFT) /* 0x00000200 */
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#define CRU_SOFTRST_CON15_IRESETN_VICAP1_SHIFT (10U)
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#define CRU_SOFTRST_CON15_IRESETN_VICAP1_MASK (0x1U << CRU_SOFTRST_CON15_IRESETN_VICAP1_SHIFT) /* 0x00000400 */
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#define CRU_SOFTRST_CON15_PRESETN_VICAP1_SHIFT (11U)
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#define CRU_SOFTRST_CON15_PRESETN_VICAP1_MASK (0x1U << CRU_SOFTRST_CON15_PRESETN_VICAP1_SHIFT) /* 0x00000800 */
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#define CRU_SOFTRST_CON15_HRESETN_ISP_SHIFT (12U)
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#define CRU_SOFTRST_CON15_HRESETN_ISP_MASK (0x1U << CRU_SOFTRST_CON15_HRESETN_ISP_SHIFT) /* 0x00001000 */
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#define CRU_SOFTRST_CON15_RESETN_ISP_SHIFT (13U)
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#define CRU_SOFTRST_CON15_RESETN_ISP_MASK (0x1U << CRU_SOFTRST_CON15_RESETN_ISP_SHIFT) /* 0x00002000 */
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#define CRU_SOFTRST_CON15_PRESETN_CSI2HOST1_SHIFT (15U)
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#define CRU_SOFTRST_CON15_PRESETN_CSI2HOST1_MASK (0x1U << CRU_SOFTRST_CON15_PRESETN_CSI2HOST1_SHIFT) /* 0x00008000 */
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/* SOFTRST_CON16 */
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#define CRU_SOFTRST_CON16_OFFSET (0x440U)
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#define CRU_SOFTRST_CON16_ARESETN_VO_NIU_SHIFT (0U)
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#define CRU_SOFTRST_CON16_ARESETN_VO_NIU_MASK (0x1U << CRU_SOFTRST_CON16_ARESETN_VO_NIU_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON16_HRESETN_VO_NIU_SHIFT (1U)
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#define CRU_SOFTRST_CON16_HRESETN_VO_NIU_MASK (0x1U << CRU_SOFTRST_CON16_HRESETN_VO_NIU_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON16_PRESETN_VO_NIU_SHIFT (2U)
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#define CRU_SOFTRST_CON16_PRESETN_VO_NIU_MASK (0x1U << CRU_SOFTRST_CON16_PRESETN_VO_NIU_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON16_ARESETN_VOP_NIU_SHIFT (3U)
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#define CRU_SOFTRST_CON16_ARESETN_VOP_NIU_MASK (0x1U << CRU_SOFTRST_CON16_ARESETN_VOP_NIU_SHIFT) /* 0x00000008 */
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#define CRU_SOFTRST_CON16_ARESETN_VOP_SHIFT (4U)
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#define CRU_SOFTRST_CON16_ARESETN_VOP_MASK (0x1U << CRU_SOFTRST_CON16_ARESETN_VOP_SHIFT) /* 0x00000010 */
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#define CRU_SOFTRST_CON16_HRESETN_VOP_SHIFT (5U)
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#define CRU_SOFTRST_CON16_HRESETN_VOP_MASK (0x1U << CRU_SOFTRST_CON16_HRESETN_VOP_SHIFT) /* 0x00000020 */
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#define CRU_SOFTRST_CON16_DRESETN0_VOP_SHIFT (6U)
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#define CRU_SOFTRST_CON16_DRESETN0_VOP_MASK (0x1U << CRU_SOFTRST_CON16_DRESETN0_VOP_SHIFT) /* 0x00000040 */
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#define CRU_SOFTRST_CON16_DRESETN1_VOP_SHIFT (7U)
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#define CRU_SOFTRST_CON16_DRESETN1_VOP_MASK (0x1U << CRU_SOFTRST_CON16_DRESETN1_VOP_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON16_DRESETN2_VOP_SHIFT (8U)
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#define CRU_SOFTRST_CON16_DRESETN2_VOP_MASK (0x1U << CRU_SOFTRST_CON16_DRESETN2_VOP_SHIFT) /* 0x00000100 */
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#define CRU_SOFTRST_CON16_RESETN_VOP_PWM_SHIFT (9U)
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#define CRU_SOFTRST_CON16_RESETN_VOP_PWM_MASK (0x1U << CRU_SOFTRST_CON16_RESETN_VOP_PWM_SHIFT) /* 0x00000200 */
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#define CRU_SOFTRST_CON16_ARESETN_HDCP_SHIFT (10U)
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#define CRU_SOFTRST_CON16_ARESETN_HDCP_MASK (0x1U << CRU_SOFTRST_CON16_ARESETN_HDCP_SHIFT) /* 0x00000400 */
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#define CRU_SOFTRST_CON16_HRESETN_HDCP_SHIFT (11U)
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#define CRU_SOFTRST_CON16_HRESETN_HDCP_MASK (0x1U << CRU_SOFTRST_CON16_HRESETN_HDCP_SHIFT) /* 0x00000800 */
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#define CRU_SOFTRST_CON16_PRESETN_HDCP_SHIFT (12U)
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#define CRU_SOFTRST_CON16_PRESETN_HDCP_MASK (0x1U << CRU_SOFTRST_CON16_PRESETN_HDCP_SHIFT) /* 0x00001000 */
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#define CRU_SOFTRST_CON16_PRESETN_HDMI_HOST_SHIFT (14U)
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#define CRU_SOFTRST_CON16_PRESETN_HDMI_HOST_MASK (0x1U << CRU_SOFTRST_CON16_PRESETN_HDMI_HOST_SHIFT) /* 0x00004000 */
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#define CRU_SOFTRST_CON16_RESETN_HDMI_HOST_SHIFT (15U)
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#define CRU_SOFTRST_CON16_RESETN_HDMI_HOST_MASK (0x1U << CRU_SOFTRST_CON16_RESETN_HDMI_HOST_SHIFT) /* 0x00008000 */
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/* SOFTRST_CON17 */
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#define CRU_SOFTRST_CON17_OFFSET (0x444U)
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#define CRU_SOFTRST_CON17_PRESETN_DSITX_0_SHIFT (0U)
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#define CRU_SOFTRST_CON17_PRESETN_DSITX_0_MASK (0x1U << CRU_SOFTRST_CON17_PRESETN_DSITX_0_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON17_PRESETN_DSITX_1_SHIFT (1U)
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#define CRU_SOFTRST_CON17_PRESETN_DSITX_1_MASK (0x1U << CRU_SOFTRST_CON17_PRESETN_DSITX_1_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON17_PRESETN_EDP_CTRL_SHIFT (2U)
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#define CRU_SOFTRST_CON17_PRESETN_EDP_CTRL_MASK (0x1U << CRU_SOFTRST_CON17_PRESETN_EDP_CTRL_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON17_RESETN_EDP_24M_SHIFT (3U)
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#define CRU_SOFTRST_CON17_RESETN_EDP_24M_MASK (0x1U << CRU_SOFTRST_CON17_RESETN_EDP_24M_SHIFT) /* 0x00000008 */
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#define CRU_SOFTRST_CON17_ARESETN_VPU_NIU_SHIFT (8U)
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#define CRU_SOFTRST_CON17_ARESETN_VPU_NIU_MASK (0x1U << CRU_SOFTRST_CON17_ARESETN_VPU_NIU_SHIFT) /* 0x00000100 */
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#define CRU_SOFTRST_CON17_HRESETN_VPU_NIU_SHIFT (9U)
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#define CRU_SOFTRST_CON17_HRESETN_VPU_NIU_MASK (0x1U << CRU_SOFTRST_CON17_HRESETN_VPU_NIU_SHIFT) /* 0x00000200 */
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#define CRU_SOFTRST_CON17_ARESETN_VPU_SHIFT (10U)
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#define CRU_SOFTRST_CON17_ARESETN_VPU_MASK (0x1U << CRU_SOFTRST_CON17_ARESETN_VPU_SHIFT) /* 0x00000400 */
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#define CRU_SOFTRST_CON17_HRESETN_VPU_SHIFT (11U)
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#define CRU_SOFTRST_CON17_HRESETN_VPU_MASK (0x1U << CRU_SOFTRST_CON17_HRESETN_VPU_SHIFT) /* 0x00000800 */
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#define CRU_SOFTRST_CON17_HRESETN_EINK_SHIFT (14U)
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#define CRU_SOFTRST_CON17_HRESETN_EINK_MASK (0x1U << CRU_SOFTRST_CON17_HRESETN_EINK_SHIFT) /* 0x00004000 */
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#define CRU_SOFTRST_CON17_PRESETN_EINK_SHIFT (15U)
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#define CRU_SOFTRST_CON17_PRESETN_EINK_MASK (0x1U << CRU_SOFTRST_CON17_PRESETN_EINK_SHIFT) /* 0x00008000 */
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/* SOFTRST_CON18 */
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#define CRU_SOFTRST_CON18_OFFSET (0x448U)
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#define CRU_SOFTRST_CON18_ARESETN_RGA_NIU_SHIFT (0U)
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#define CRU_SOFTRST_CON18_ARESETN_RGA_NIU_MASK (0x1U << CRU_SOFTRST_CON18_ARESETN_RGA_NIU_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON18_HRESETN_RGA_NIU_SHIFT (1U)
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#define CRU_SOFTRST_CON18_HRESETN_RGA_NIU_MASK (0x1U << CRU_SOFTRST_CON18_HRESETN_RGA_NIU_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON18_PRESETN_RGA_NIU_SHIFT (2U)
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#define CRU_SOFTRST_CON18_PRESETN_RGA_NIU_MASK (0x1U << CRU_SOFTRST_CON18_PRESETN_RGA_NIU_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON18_ARESETN_RGA_SHIFT (4U)
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#define CRU_SOFTRST_CON18_ARESETN_RGA_MASK (0x1U << CRU_SOFTRST_CON18_ARESETN_RGA_SHIFT) /* 0x00000010 */
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#define CRU_SOFTRST_CON18_HRESETN_RGA_SHIFT (5U)
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#define CRU_SOFTRST_CON18_HRESETN_RGA_MASK (0x1U << CRU_SOFTRST_CON18_HRESETN_RGA_SHIFT) /* 0x00000020 */
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#define CRU_SOFTRST_CON18_RESETN_RGA_CORE_SHIFT (6U)
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#define CRU_SOFTRST_CON18_RESETN_RGA_CORE_MASK (0x1U << CRU_SOFTRST_CON18_RESETN_RGA_CORE_SHIFT) /* 0x00000040 */
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#define CRU_SOFTRST_CON18_ARESETN_IEP_SHIFT (7U)
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#define CRU_SOFTRST_CON18_ARESETN_IEP_MASK (0x1U << CRU_SOFTRST_CON18_ARESETN_IEP_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON18_HRESETN_IEP_SHIFT (8U)
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#define CRU_SOFTRST_CON18_HRESETN_IEP_MASK (0x1U << CRU_SOFTRST_CON18_HRESETN_IEP_SHIFT) /* 0x00000100 */
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#define CRU_SOFTRST_CON18_RESETN_IEP_CORE_SHIFT (9U)
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#define CRU_SOFTRST_CON18_RESETN_IEP_CORE_MASK (0x1U << CRU_SOFTRST_CON18_RESETN_IEP_CORE_SHIFT) /* 0x00000200 */
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#define CRU_SOFTRST_CON18_HRESETN_EBC_SHIFT (10U)
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#define CRU_SOFTRST_CON18_HRESETN_EBC_MASK (0x1U << CRU_SOFTRST_CON18_HRESETN_EBC_SHIFT) /* 0x00000400 */
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#define CRU_SOFTRST_CON18_DRESETN_EBC_SHIFT (11U)
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#define CRU_SOFTRST_CON18_DRESETN_EBC_MASK (0x1U << CRU_SOFTRST_CON18_DRESETN_EBC_SHIFT) /* 0x00000800 */
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#define CRU_SOFTRST_CON18_ARESETN_JDEC_SHIFT (12U)
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#define CRU_SOFTRST_CON18_ARESETN_JDEC_MASK (0x1U << CRU_SOFTRST_CON18_ARESETN_JDEC_SHIFT) /* 0x00001000 */
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#define CRU_SOFTRST_CON18_HRESETN_JDEC_SHIFT (13U)
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#define CRU_SOFTRST_CON18_HRESETN_JDEC_MASK (0x1U << CRU_SOFTRST_CON18_HRESETN_JDEC_SHIFT) /* 0x00002000 */
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#define CRU_SOFTRST_CON18_ARESETN_JENC_SHIFT (14U)
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#define CRU_SOFTRST_CON18_ARESETN_JENC_MASK (0x1U << CRU_SOFTRST_CON18_ARESETN_JENC_SHIFT) /* 0x00004000 */
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#define CRU_SOFTRST_CON18_HRESETN_JENC_SHIFT (15U)
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#define CRU_SOFTRST_CON18_HRESETN_JENC_MASK (0x1U << CRU_SOFTRST_CON18_HRESETN_JENC_SHIFT) /* 0x00008000 */
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/* SOFTRST_CON19 */
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#define CRU_SOFTRST_CON19_OFFSET (0x44CU)
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#define CRU_SOFTRST_CON19_ARESETN_VENC_NIU_SHIFT (0U)
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#define CRU_SOFTRST_CON19_ARESETN_VENC_NIU_MASK (0x1U << CRU_SOFTRST_CON19_ARESETN_VENC_NIU_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON19_HRESETN_VENC_NIU_SHIFT (1U)
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#define CRU_SOFTRST_CON19_HRESETN_VENC_NIU_MASK (0x1U << CRU_SOFTRST_CON19_HRESETN_VENC_NIU_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON19_ARESETN_RKVENC_SHIFT (3U)
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#define CRU_SOFTRST_CON19_ARESETN_RKVENC_MASK (0x1U << CRU_SOFTRST_CON19_ARESETN_RKVENC_SHIFT) /* 0x00000008 */
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#define CRU_SOFTRST_CON19_HRESETN_RKVENC_SHIFT (4U)
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#define CRU_SOFTRST_CON19_HRESETN_RKVENC_MASK (0x1U << CRU_SOFTRST_CON19_HRESETN_RKVENC_SHIFT) /* 0x00000010 */
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#define CRU_SOFTRST_CON19_RESETN_RKVENC_CORE_SHIFT (5U)
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#define CRU_SOFTRST_CON19_RESETN_RKVENC_CORE_MASK (0x1U << CRU_SOFTRST_CON19_RESETN_RKVENC_CORE_SHIFT) /* 0x00000020 */
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/* SOFTRST_CON20 */
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#define CRU_SOFTRST_CON20_OFFSET (0x450U)
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#define CRU_SOFTRST_CON20_ARESETN_RKVDEC_NIU_SHIFT (0U)
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#define CRU_SOFTRST_CON20_ARESETN_RKVDEC_NIU_MASK (0x1U << CRU_SOFTRST_CON20_ARESETN_RKVDEC_NIU_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON20_HRESETN_RKVDEC_NIU_SHIFT (1U)
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#define CRU_SOFTRST_CON20_HRESETN_RKVDEC_NIU_MASK (0x1U << CRU_SOFTRST_CON20_HRESETN_RKVDEC_NIU_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON20_ARESETN_RKVDEC_SHIFT (2U)
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#define CRU_SOFTRST_CON20_ARESETN_RKVDEC_MASK (0x1U << CRU_SOFTRST_CON20_ARESETN_RKVDEC_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON20_HRESETN_RKVDEC_SHIFT (3U)
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#define CRU_SOFTRST_CON20_HRESETN_RKVDEC_MASK (0x1U << CRU_SOFTRST_CON20_HRESETN_RKVDEC_SHIFT) /* 0x00000008 */
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#define CRU_SOFTRST_CON20_RESETN_RKVDEC_CA_SHIFT (4U)
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#define CRU_SOFTRST_CON20_RESETN_RKVDEC_CA_MASK (0x1U << CRU_SOFTRST_CON20_RESETN_RKVDEC_CA_SHIFT) /* 0x00000010 */
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#define CRU_SOFTRST_CON20_RESETN_RKVDEC_CORE_SHIFT (5U)
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#define CRU_SOFTRST_CON20_RESETN_RKVDEC_CORE_MASK (0x1U << CRU_SOFTRST_CON20_RESETN_RKVDEC_CORE_SHIFT) /* 0x00000020 */
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#define CRU_SOFTRST_CON20_RESETN_RKVDEC_HEVC_CA_SHIFT (6U)
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#define CRU_SOFTRST_CON20_RESETN_RKVDEC_HEVC_CA_MASK (0x1U << CRU_SOFTRST_CON20_RESETN_RKVDEC_HEVC_CA_SHIFT) /* 0x00000040 */
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/* SOFTRST_CON21 */
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#define CRU_SOFTRST_CON21_OFFSET (0x454U)
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#define CRU_SOFTRST_CON21_ARESETN_BUS_NIU_SHIFT (0U)
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#define CRU_SOFTRST_CON21_ARESETN_BUS_NIU_MASK (0x1U << CRU_SOFTRST_CON21_ARESETN_BUS_NIU_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON21_PRESETN_BUS_NIU_SHIFT (2U)
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#define CRU_SOFTRST_CON21_PRESETN_BUS_NIU_MASK (0x1U << CRU_SOFTRST_CON21_PRESETN_BUS_NIU_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON21_PRESETN_CAN0_SHIFT (4U)
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#define CRU_SOFTRST_CON21_PRESETN_CAN0_MASK (0x1U << CRU_SOFTRST_CON21_PRESETN_CAN0_SHIFT) /* 0x00000010 */
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#define CRU_SOFTRST_CON21_RESETN_CAN0_SHIFT (5U)
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#define CRU_SOFTRST_CON21_RESETN_CAN0_MASK (0x1U << CRU_SOFTRST_CON21_RESETN_CAN0_SHIFT) /* 0x00000020 */
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#define CRU_SOFTRST_CON21_PRESETN_CAN1_SHIFT (6U)
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#define CRU_SOFTRST_CON21_PRESETN_CAN1_MASK (0x1U << CRU_SOFTRST_CON21_PRESETN_CAN1_SHIFT) /* 0x00000040 */
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#define CRU_SOFTRST_CON21_RESETN_CAN1_SHIFT (7U)
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#define CRU_SOFTRST_CON21_RESETN_CAN1_MASK (0x1U << CRU_SOFTRST_CON21_RESETN_CAN1_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON21_PRESETN_CAN2_SHIFT (8U)
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#define CRU_SOFTRST_CON21_PRESETN_CAN2_MASK (0x1U << CRU_SOFTRST_CON21_PRESETN_CAN2_SHIFT) /* 0x00000100 */
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#define CRU_SOFTRST_CON21_RESETN_CAN2_SHIFT (9U)
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#define CRU_SOFTRST_CON21_RESETN_CAN2_MASK (0x1U << CRU_SOFTRST_CON21_RESETN_CAN2_SHIFT) /* 0x00000200 */
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#define CRU_SOFTRST_CON21_PRESETN_GPIO1_SHIFT (10U)
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#define CRU_SOFTRST_CON21_PRESETN_GPIO1_MASK (0x1U << CRU_SOFTRST_CON21_PRESETN_GPIO1_SHIFT) /* 0x00000400 */
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#define CRU_SOFTRST_CON21_DBRESETN_GPIO1_SHIFT (11U)
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#define CRU_SOFTRST_CON21_DBRESETN_GPIO1_MASK (0x1U << CRU_SOFTRST_CON21_DBRESETN_GPIO1_SHIFT) /* 0x00000800 */
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#define CRU_SOFTRST_CON21_PRESETN_GPIO2_SHIFT (12U)
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#define CRU_SOFTRST_CON21_PRESETN_GPIO2_MASK (0x1U << CRU_SOFTRST_CON21_PRESETN_GPIO2_SHIFT) /* 0x00001000 */
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#define CRU_SOFTRST_CON21_DBRESETN_GPIO2_SHIFT (13U)
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#define CRU_SOFTRST_CON21_DBRESETN_GPIO2_MASK (0x1U << CRU_SOFTRST_CON21_DBRESETN_GPIO2_SHIFT) /* 0x00002000 */
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#define CRU_SOFTRST_CON21_PRESETN_GPIO3_SHIFT (14U)
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#define CRU_SOFTRST_CON21_PRESETN_GPIO3_MASK (0x1U << CRU_SOFTRST_CON21_PRESETN_GPIO3_SHIFT) /* 0x00004000 */
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#define CRU_SOFTRST_CON21_DBRESETN_GPIO3_SHIFT (15U)
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#define CRU_SOFTRST_CON21_DBRESETN_GPIO3_MASK (0x1U << CRU_SOFTRST_CON21_DBRESETN_GPIO3_SHIFT) /* 0x00008000 */
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/* SOFTRST_CON22 */
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#define CRU_SOFTRST_CON22_OFFSET (0x458U)
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#define CRU_SOFTRST_CON22_PRESETN_GPIO4_SHIFT (0U)
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#define CRU_SOFTRST_CON22_PRESETN_GPIO4_MASK (0x1U << CRU_SOFTRST_CON22_PRESETN_GPIO4_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON22_DBRESETN_GPIO4_SHIFT (1U)
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#define CRU_SOFTRST_CON22_DBRESETN_GPIO4_MASK (0x1U << CRU_SOFTRST_CON22_DBRESETN_GPIO4_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON22_PRESETN_I2C1_SHIFT (2U)
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#define CRU_SOFTRST_CON22_PRESETN_I2C1_MASK (0x1U << CRU_SOFTRST_CON22_PRESETN_I2C1_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON22_RESETN_I2C1_SHIFT (3U)
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#define CRU_SOFTRST_CON22_RESETN_I2C1_MASK (0x1U << CRU_SOFTRST_CON22_RESETN_I2C1_SHIFT) /* 0x00000008 */
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#define CRU_SOFTRST_CON22_PRESETN_I2C2_SHIFT (4U)
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#define CRU_SOFTRST_CON22_PRESETN_I2C2_MASK (0x1U << CRU_SOFTRST_CON22_PRESETN_I2C2_SHIFT) /* 0x00000010 */
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#define CRU_SOFTRST_CON22_RESETN_I2C2_SHIFT (5U)
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#define CRU_SOFTRST_CON22_RESETN_I2C2_MASK (0x1U << CRU_SOFTRST_CON22_RESETN_I2C2_SHIFT) /* 0x00000020 */
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#define CRU_SOFTRST_CON22_PRESETN_I2C3_SHIFT (6U)
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#define CRU_SOFTRST_CON22_PRESETN_I2C3_MASK (0x1U << CRU_SOFTRST_CON22_PRESETN_I2C3_SHIFT) /* 0x00000040 */
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#define CRU_SOFTRST_CON22_RESETN_I2C3_SHIFT (7U)
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#define CRU_SOFTRST_CON22_RESETN_I2C3_MASK (0x1U << CRU_SOFTRST_CON22_RESETN_I2C3_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON22_PRESETN_I2C4_SHIFT (8U)
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#define CRU_SOFTRST_CON22_PRESETN_I2C4_MASK (0x1U << CRU_SOFTRST_CON22_PRESETN_I2C4_SHIFT) /* 0x00000100 */
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#define CRU_SOFTRST_CON22_RESETN_I2C4_SHIFT (9U)
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#define CRU_SOFTRST_CON22_RESETN_I2C4_MASK (0x1U << CRU_SOFTRST_CON22_RESETN_I2C4_SHIFT) /* 0x00000200 */
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#define CRU_SOFTRST_CON22_PRESETN_I2C5_SHIFT (10U)
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#define CRU_SOFTRST_CON22_PRESETN_I2C5_MASK (0x1U << CRU_SOFTRST_CON22_PRESETN_I2C5_SHIFT) /* 0x00000400 */
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#define CRU_SOFTRST_CON22_RESETN_I2C5_SHIFT (11U)
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#define CRU_SOFTRST_CON22_RESETN_I2C5_MASK (0x1U << CRU_SOFTRST_CON22_RESETN_I2C5_SHIFT) /* 0x00000800 */
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#define CRU_SOFTRST_CON22_PRESETN_OTPC_NS_SHIFT (12U)
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#define CRU_SOFTRST_CON22_PRESETN_OTPC_NS_MASK (0x1U << CRU_SOFTRST_CON22_PRESETN_OTPC_NS_SHIFT) /* 0x00001000 */
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#define CRU_SOFTRST_CON22_RESETN_OTPC_NS_SBPI_SHIFT (13U)
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#define CRU_SOFTRST_CON22_RESETN_OTPC_NS_SBPI_MASK (0x1U << CRU_SOFTRST_CON22_RESETN_OTPC_NS_SBPI_SHIFT) /* 0x00002000 */
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#define CRU_SOFTRST_CON22_RESETN_OTPC_NS_USR_SHIFT (14U)
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#define CRU_SOFTRST_CON22_RESETN_OTPC_NS_USR_MASK (0x1U << CRU_SOFTRST_CON22_RESETN_OTPC_NS_USR_SHIFT) /* 0x00004000 */
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/* SOFTRST_CON23 */
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#define CRU_SOFTRST_CON23_OFFSET (0x45CU)
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#define CRU_SOFTRST_CON23_PRESETN_PWM1_SHIFT (0U)
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#define CRU_SOFTRST_CON23_PRESETN_PWM1_MASK (0x1U << CRU_SOFTRST_CON23_PRESETN_PWM1_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON23_RESETN_PWM1_SHIFT (1U)
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#define CRU_SOFTRST_CON23_RESETN_PWM1_MASK (0x1U << CRU_SOFTRST_CON23_RESETN_PWM1_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON23_PRESETN_PWM2_SHIFT (2U)
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#define CRU_SOFTRST_CON23_PRESETN_PWM2_MASK (0x1U << CRU_SOFTRST_CON23_PRESETN_PWM2_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON23_RESETN_PWM2_SHIFT (3U)
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#define CRU_SOFTRST_CON23_RESETN_PWM2_MASK (0x1U << CRU_SOFTRST_CON23_RESETN_PWM2_SHIFT) /* 0x00000008 */
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#define CRU_SOFTRST_CON23_PRESETN_PWM3_SHIFT (4U)
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#define CRU_SOFTRST_CON23_PRESETN_PWM3_MASK (0x1U << CRU_SOFTRST_CON23_PRESETN_PWM3_SHIFT) /* 0x00000010 */
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#define CRU_SOFTRST_CON23_RESETN_PWM3_SHIFT (5U)
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#define CRU_SOFTRST_CON23_RESETN_PWM3_MASK (0x1U << CRU_SOFTRST_CON23_RESETN_PWM3_SHIFT) /* 0x00000020 */
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#define CRU_SOFTRST_CON23_PRESETN_SPI0_SHIFT (6U)
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#define CRU_SOFTRST_CON23_PRESETN_SPI0_MASK (0x1U << CRU_SOFTRST_CON23_PRESETN_SPI0_SHIFT) /* 0x00000040 */
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#define CRU_SOFTRST_CON23_RESETN_SPI0_SHIFT (7U)
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#define CRU_SOFTRST_CON23_RESETN_SPI0_MASK (0x1U << CRU_SOFTRST_CON23_RESETN_SPI0_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON23_PRESETN_SPI1_SHIFT (8U)
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#define CRU_SOFTRST_CON23_PRESETN_SPI1_MASK (0x1U << CRU_SOFTRST_CON23_PRESETN_SPI1_SHIFT) /* 0x00000100 */
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#define CRU_SOFTRST_CON23_RESETN_SPI1_SHIFT (9U)
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#define CRU_SOFTRST_CON23_RESETN_SPI1_MASK (0x1U << CRU_SOFTRST_CON23_RESETN_SPI1_SHIFT) /* 0x00000200 */
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#define CRU_SOFTRST_CON23_PRESETN_SPI2_SHIFT (10U)
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#define CRU_SOFTRST_CON23_PRESETN_SPI2_MASK (0x1U << CRU_SOFTRST_CON23_PRESETN_SPI2_SHIFT) /* 0x00000400 */
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#define CRU_SOFTRST_CON23_RESETN_SPI2_SHIFT (11U)
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#define CRU_SOFTRST_CON23_RESETN_SPI2_MASK (0x1U << CRU_SOFTRST_CON23_RESETN_SPI2_SHIFT) /* 0x00000800 */
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#define CRU_SOFTRST_CON23_PRESETN_SPI3_SHIFT (12U)
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#define CRU_SOFTRST_CON23_PRESETN_SPI3_MASK (0x1U << CRU_SOFTRST_CON23_PRESETN_SPI3_SHIFT) /* 0x00001000 */
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#define CRU_SOFTRST_CON23_RESETN_SPI3_SHIFT (13U)
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#define CRU_SOFTRST_CON23_RESETN_SPI3_MASK (0x1U << CRU_SOFTRST_CON23_RESETN_SPI3_SHIFT) /* 0x00002000 */
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/* SOFTRST_CON24 */
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#define CRU_SOFTRST_CON24_OFFSET (0x460U)
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#define CRU_SOFTRST_CON24_PRESETN_SARADC_SHIFT (0U)
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#define CRU_SOFTRST_CON24_PRESETN_SARADC_MASK (0x1U << CRU_SOFTRST_CON24_PRESETN_SARADC_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON24_PRESETN_TSADC_SHIFT (1U)
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#define CRU_SOFTRST_CON24_PRESETN_TSADC_MASK (0x1U << CRU_SOFTRST_CON24_PRESETN_TSADC_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON24_RESETN_TSADC_SHIFT (2U)
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#define CRU_SOFTRST_CON24_RESETN_TSADC_MASK (0x1U << CRU_SOFTRST_CON24_RESETN_TSADC_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON24_PRESETN_TIMER_SHIFT (3U)
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#define CRU_SOFTRST_CON24_PRESETN_TIMER_MASK (0x1U << CRU_SOFTRST_CON24_PRESETN_TIMER_SHIFT) /* 0x00000008 */
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#define CRU_SOFTRST_CON24_RESETN_TIMER0_SHIFT (4U)
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#define CRU_SOFTRST_CON24_RESETN_TIMER0_MASK (0x1U << CRU_SOFTRST_CON24_RESETN_TIMER0_SHIFT) /* 0x00000010 */
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#define CRU_SOFTRST_CON24_RESETN_TIMER1_SHIFT (5U)
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#define CRU_SOFTRST_CON24_RESETN_TIMER1_MASK (0x1U << CRU_SOFTRST_CON24_RESETN_TIMER1_SHIFT) /* 0x00000020 */
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#define CRU_SOFTRST_CON24_RESETN_TIMER2_SHIFT (6U)
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#define CRU_SOFTRST_CON24_RESETN_TIMER2_MASK (0x1U << CRU_SOFTRST_CON24_RESETN_TIMER2_SHIFT) /* 0x00000040 */
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#define CRU_SOFTRST_CON24_RESETN_TIMER3_SHIFT (7U)
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#define CRU_SOFTRST_CON24_RESETN_TIMER3_MASK (0x1U << CRU_SOFTRST_CON24_RESETN_TIMER3_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON24_RESETN_TIMER4_SHIFT (8U)
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#define CRU_SOFTRST_CON24_RESETN_TIMER4_MASK (0x1U << CRU_SOFTRST_CON24_RESETN_TIMER4_SHIFT) /* 0x00000100 */
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#define CRU_SOFTRST_CON24_RESETN_TIMER5_SHIFT (9U)
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#define CRU_SOFTRST_CON24_RESETN_TIMER5_MASK (0x1U << CRU_SOFTRST_CON24_RESETN_TIMER5_SHIFT) /* 0x00000200 */
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#define CRU_SOFTRST_CON24_PRESETN_UART1_SHIFT (10U)
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#define CRU_SOFTRST_CON24_PRESETN_UART1_MASK (0x1U << CRU_SOFTRST_CON24_PRESETN_UART1_SHIFT) /* 0x00000400 */
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#define CRU_SOFTRST_CON24_SRESETN_UART1_SHIFT (11U)
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#define CRU_SOFTRST_CON24_SRESETN_UART1_MASK (0x1U << CRU_SOFTRST_CON24_SRESETN_UART1_SHIFT) /* 0x00000800 */
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/* SOFTRST_CON25 */
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#define CRU_SOFTRST_CON25_OFFSET (0x464U)
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#define CRU_SOFTRST_CON25_PRESETN_UART2_SHIFT (0U)
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#define CRU_SOFTRST_CON25_PRESETN_UART2_MASK (0x1U << CRU_SOFTRST_CON25_PRESETN_UART2_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON25_SRESETN_UART2_SHIFT (1U)
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#define CRU_SOFTRST_CON25_SRESETN_UART2_MASK (0x1U << CRU_SOFTRST_CON25_SRESETN_UART2_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON25_PRESETN_UART3_SHIFT (2U)
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#define CRU_SOFTRST_CON25_PRESETN_UART3_MASK (0x1U << CRU_SOFTRST_CON25_PRESETN_UART3_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON25_SRESETN_UART3_SHIFT (3U)
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#define CRU_SOFTRST_CON25_SRESETN_UART3_MASK (0x1U << CRU_SOFTRST_CON25_SRESETN_UART3_SHIFT) /* 0x00000008 */
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#define CRU_SOFTRST_CON25_PRESETN_UART4_SHIFT (4U)
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#define CRU_SOFTRST_CON25_PRESETN_UART4_MASK (0x1U << CRU_SOFTRST_CON25_PRESETN_UART4_SHIFT) /* 0x00000010 */
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#define CRU_SOFTRST_CON25_SRESETN_UART4_SHIFT (5U)
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#define CRU_SOFTRST_CON25_SRESETN_UART4_MASK (0x1U << CRU_SOFTRST_CON25_SRESETN_UART4_SHIFT) /* 0x00000020 */
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#define CRU_SOFTRST_CON25_PRESETN_UART5_SHIFT (6U)
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#define CRU_SOFTRST_CON25_PRESETN_UART5_MASK (0x1U << CRU_SOFTRST_CON25_PRESETN_UART5_SHIFT) /* 0x00000040 */
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#define CRU_SOFTRST_CON25_SRESETN_UART5_SHIFT (7U)
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#define CRU_SOFTRST_CON25_SRESETN_UART5_MASK (0x1U << CRU_SOFTRST_CON25_SRESETN_UART5_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON25_PRESETN_UART6_SHIFT (8U)
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#define CRU_SOFTRST_CON25_PRESETN_UART6_MASK (0x1U << CRU_SOFTRST_CON25_PRESETN_UART6_SHIFT) /* 0x00000100 */
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#define CRU_SOFTRST_CON25_SRESETN_UART6_SHIFT (9U)
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#define CRU_SOFTRST_CON25_SRESETN_UART6_MASK (0x1U << CRU_SOFTRST_CON25_SRESETN_UART6_SHIFT) /* 0x00000200 */
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#define CRU_SOFTRST_CON25_PRESETN_UART7_SHIFT (10U)
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#define CRU_SOFTRST_CON25_PRESETN_UART7_MASK (0x1U << CRU_SOFTRST_CON25_PRESETN_UART7_SHIFT) /* 0x00000400 */
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#define CRU_SOFTRST_CON25_SRESETN_UART7_SHIFT (11U)
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#define CRU_SOFTRST_CON25_SRESETN_UART7_MASK (0x1U << CRU_SOFTRST_CON25_SRESETN_UART7_SHIFT) /* 0x00000800 */
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#define CRU_SOFTRST_CON25_PRESETN_UART8_SHIFT (12U)
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#define CRU_SOFTRST_CON25_PRESETN_UART8_MASK (0x1U << CRU_SOFTRST_CON25_PRESETN_UART8_SHIFT) /* 0x00001000 */
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#define CRU_SOFTRST_CON25_SRESETN_UART8_SHIFT (13U)
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#define CRU_SOFTRST_CON25_SRESETN_UART8_MASK (0x1U << CRU_SOFTRST_CON25_SRESETN_UART8_SHIFT) /* 0x00002000 */
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#define CRU_SOFTRST_CON25_PRESETN_UART9_SHIFT (14U)
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#define CRU_SOFTRST_CON25_PRESETN_UART9_MASK (0x1U << CRU_SOFTRST_CON25_PRESETN_UART9_SHIFT) /* 0x00004000 */
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#define CRU_SOFTRST_CON25_SRESETN_UART9_SHIFT (15U)
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#define CRU_SOFTRST_CON25_SRESETN_UART9_MASK (0x1U << CRU_SOFTRST_CON25_SRESETN_UART9_SHIFT) /* 0x00008000 */
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/* SOFTRST_CON26 */
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#define CRU_SOFTRST_CON26_OFFSET (0x468U)
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#define CRU_SOFTRST_CON26_PRESETN_GRF_SHIFT (0U)
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#define CRU_SOFTRST_CON26_PRESETN_GRF_MASK (0x1U << CRU_SOFTRST_CON26_PRESETN_GRF_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON26_PRESETN_GRF_VCCIO12_SHIFT (1U)
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#define CRU_SOFTRST_CON26_PRESETN_GRF_VCCIO12_MASK (0x1U << CRU_SOFTRST_CON26_PRESETN_GRF_VCCIO12_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON26_PRESETN_GRF_VCCIO34_SHIFT (2U)
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#define CRU_SOFTRST_CON26_PRESETN_GRF_VCCIO34_MASK (0x1U << CRU_SOFTRST_CON26_PRESETN_GRF_VCCIO34_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON26_PRESETN_GRF_VCCIO567_SHIFT (3U)
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#define CRU_SOFTRST_CON26_PRESETN_GRF_VCCIO567_MASK (0x1U << CRU_SOFTRST_CON26_PRESETN_GRF_VCCIO567_SHIFT) /* 0x00000008 */
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#define CRU_SOFTRST_CON26_PRESETN_SCR_SHIFT (4U)
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#define CRU_SOFTRST_CON26_PRESETN_SCR_MASK (0x1U << CRU_SOFTRST_CON26_PRESETN_SCR_SHIFT) /* 0x00000010 */
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#define CRU_SOFTRST_CON26_PRESETN_WDT_NS_SHIFT (5U)
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#define CRU_SOFTRST_CON26_PRESETN_WDT_NS_MASK (0x1U << CRU_SOFTRST_CON26_PRESETN_WDT_NS_SHIFT) /* 0x00000020 */
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#define CRU_SOFTRST_CON26_TRESETN_WDT_NS_SHIFT (6U)
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#define CRU_SOFTRST_CON26_TRESETN_WDT_NS_MASK (0x1U << CRU_SOFTRST_CON26_TRESETN_WDT_NS_SHIFT) /* 0x00000040 */
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#define CRU_SOFTRST_CON26_PRESETN_DFT2APB_SHIFT (7U)
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#define CRU_SOFTRST_CON26_PRESETN_DFT2APB_MASK (0x1U << CRU_SOFTRST_CON26_PRESETN_DFT2APB_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON26_ARESETN_MCU_SHIFT (10U)
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#define CRU_SOFTRST_CON26_ARESETN_MCU_MASK (0x1U << CRU_SOFTRST_CON26_ARESETN_MCU_SHIFT) /* 0x00000400 */
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#define CRU_SOFTRST_CON26_PRESETN_INTMUX_SHIFT (11U)
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#define CRU_SOFTRST_CON26_PRESETN_INTMUX_MASK (0x1U << CRU_SOFTRST_CON26_PRESETN_INTMUX_SHIFT) /* 0x00000800 */
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#define CRU_SOFTRST_CON26_PRESETN_MAILBOX_SHIFT (12U)
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#define CRU_SOFTRST_CON26_PRESETN_MAILBOX_MASK (0x1U << CRU_SOFTRST_CON26_PRESETN_MAILBOX_SHIFT) /* 0x00001000 */
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/* SOFTRST_CON27 */
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#define CRU_SOFTRST_CON27_OFFSET (0x46CU)
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#define CRU_SOFTRST_CON27_ARESETN_TOP_HIGH_NIU_SHIFT (0U)
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#define CRU_SOFTRST_CON27_ARESETN_TOP_HIGH_NIU_MASK (0x1U << CRU_SOFTRST_CON27_ARESETN_TOP_HIGH_NIU_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON27_ARESETN_TOP_LOW_NIU_SHIFT (1U)
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#define CRU_SOFTRST_CON27_ARESETN_TOP_LOW_NIU_MASK (0x1U << CRU_SOFTRST_CON27_ARESETN_TOP_LOW_NIU_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON27_HRESETN_TOP_NIU_SHIFT (2U)
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#define CRU_SOFTRST_CON27_HRESETN_TOP_NIU_MASK (0x1U << CRU_SOFTRST_CON27_HRESETN_TOP_NIU_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON27_PRESETN_TOP_NIU_SHIFT (3U)
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#define CRU_SOFTRST_CON27_PRESETN_TOP_NIU_MASK (0x1U << CRU_SOFTRST_CON27_PRESETN_TOP_NIU_SHIFT) /* 0x00000008 */
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#define CRU_SOFTRST_CON27_PRESETN_TOP_CRU_SHIFT (6U)
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#define CRU_SOFTRST_CON27_PRESETN_TOP_CRU_MASK (0x1U << CRU_SOFTRST_CON27_PRESETN_TOP_CRU_SHIFT) /* 0x00000040 */
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#define CRU_SOFTRST_CON27_PRESETN_DDRPHY_SHIFT (7U)
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#define CRU_SOFTRST_CON27_PRESETN_DDRPHY_MASK (0x1U << CRU_SOFTRST_CON27_PRESETN_DDRPHY_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON27_RESETN_DDRPHY_SHIFT (8U)
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#define CRU_SOFTRST_CON27_RESETN_DDRPHY_MASK (0x1U << CRU_SOFTRST_CON27_RESETN_DDRPHY_SHIFT) /* 0x00000100 */
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#define CRU_SOFTRST_CON27_PRESETN_MIPICSIPHY_SHIFT (10U)
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#define CRU_SOFTRST_CON27_PRESETN_MIPICSIPHY_MASK (0x1U << CRU_SOFTRST_CON27_PRESETN_MIPICSIPHY_SHIFT) /* 0x00000400 */
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#define CRU_SOFTRST_CON27_PRESETN_MIPIDSIPHY0_SHIFT (11U)
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#define CRU_SOFTRST_CON27_PRESETN_MIPIDSIPHY0_MASK (0x1U << CRU_SOFTRST_CON27_PRESETN_MIPIDSIPHY0_SHIFT) /* 0x00000800 */
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#define CRU_SOFTRST_CON27_PRESETN_MIPIDSIPHY1_SHIFT (12U)
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#define CRU_SOFTRST_CON27_PRESETN_MIPIDSIPHY1_MASK (0x1U << CRU_SOFTRST_CON27_PRESETN_MIPIDSIPHY1_SHIFT) /* 0x00001000 */
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#define CRU_SOFTRST_CON27_PRESETN_PCIE30PHY_SHIFT (13U)
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#define CRU_SOFTRST_CON27_PRESETN_PCIE30PHY_MASK (0x1U << CRU_SOFTRST_CON27_PRESETN_PCIE30PHY_SHIFT) /* 0x00002000 */
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#define CRU_SOFTRST_CON27_RESETN_PCIE30PHY_SHIFT (14U)
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#define CRU_SOFTRST_CON27_RESETN_PCIE30PHY_MASK (0x1U << CRU_SOFTRST_CON27_RESETN_PCIE30PHY_SHIFT) /* 0x00004000 */
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#define CRU_SOFTRST_CON27_PRESETN_PCIE30PHY_GRF_SHIFT (15U)
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#define CRU_SOFTRST_CON27_PRESETN_PCIE30PHY_GRF_MASK (0x1U << CRU_SOFTRST_CON27_PRESETN_PCIE30PHY_GRF_SHIFT) /* 0x00008000 */
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/* SOFTRST_CON28 */
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#define CRU_SOFTRST_CON28_OFFSET (0x470U)
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#define CRU_SOFTRST_CON28_PRESETN_APB2ASB_CHIP_LEFT_SHIFT (0U)
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#define CRU_SOFTRST_CON28_PRESETN_APB2ASB_CHIP_LEFT_MASK (0x1U << CRU_SOFTRST_CON28_PRESETN_APB2ASB_CHIP_LEFT_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON28_PRESETN_APB2ASB_CHIP_BOTTOM_SHIFT (1U)
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#define CRU_SOFTRST_CON28_PRESETN_APB2ASB_CHIP_BOTTOM_MASK (0x1U << CRU_SOFTRST_CON28_PRESETN_APB2ASB_CHIP_BOTTOM_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON28_PRESETN_ASB2APB_CHIP_LEFT_SHIFT (2U)
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#define CRU_SOFTRST_CON28_PRESETN_ASB2APB_CHIP_LEFT_MASK (0x1U << CRU_SOFTRST_CON28_PRESETN_ASB2APB_CHIP_LEFT_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON28_PRESETN_ASB2APB_CHIP_BOTTOM_SHIFT (3U)
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#define CRU_SOFTRST_CON28_PRESETN_ASB2APB_CHIP_BOTTOM_MASK (0x1U << CRU_SOFTRST_CON28_PRESETN_ASB2APB_CHIP_BOTTOM_SHIFT) /* 0x00000008 */
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#define CRU_SOFTRST_CON28_PRESETN_PIPEPHY0_SHIFT (4U)
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#define CRU_SOFTRST_CON28_PRESETN_PIPEPHY0_MASK (0x1U << CRU_SOFTRST_CON28_PRESETN_PIPEPHY0_SHIFT) /* 0x00000010 */
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#define CRU_SOFTRST_CON28_RESETN_PIPEPHY0_SHIFT (5U)
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#define CRU_SOFTRST_CON28_RESETN_PIPEPHY0_MASK (0x1U << CRU_SOFTRST_CON28_RESETN_PIPEPHY0_SHIFT) /* 0x00000020 */
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#define CRU_SOFTRST_CON28_PRESETN_PIPEPHY1_SHIFT (6U)
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#define CRU_SOFTRST_CON28_PRESETN_PIPEPHY1_MASK (0x1U << CRU_SOFTRST_CON28_PRESETN_PIPEPHY1_SHIFT) /* 0x00000040 */
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#define CRU_SOFTRST_CON28_RESETN_PIPEPHY1_SHIFT (7U)
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#define CRU_SOFTRST_CON28_RESETN_PIPEPHY1_MASK (0x1U << CRU_SOFTRST_CON28_RESETN_PIPEPHY1_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON28_PRESETN_PIPEPHY2_SHIFT (8U)
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#define CRU_SOFTRST_CON28_PRESETN_PIPEPHY2_MASK (0x1U << CRU_SOFTRST_CON28_PRESETN_PIPEPHY2_SHIFT) /* 0x00000100 */
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#define CRU_SOFTRST_CON28_RESETN_PIPEPHY2_SHIFT (9U)
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#define CRU_SOFTRST_CON28_RESETN_PIPEPHY2_MASK (0x1U << CRU_SOFTRST_CON28_RESETN_PIPEPHY2_SHIFT) /* 0x00000200 */
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#define CRU_SOFTRST_CON28_PRESETN_USB2PHY0_GRF_SHIFT (10U)
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#define CRU_SOFTRST_CON28_PRESETN_USB2PHY0_GRF_MASK (0x1U << CRU_SOFTRST_CON28_PRESETN_USB2PHY0_GRF_SHIFT) /* 0x00000400 */
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#define CRU_SOFTRST_CON28_PRESETN_USB2PHY1_GRF_SHIFT (11U)
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#define CRU_SOFTRST_CON28_PRESETN_USB2PHY1_GRF_MASK (0x1U << CRU_SOFTRST_CON28_PRESETN_USB2PHY1_GRF_SHIFT) /* 0x00000800 */
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#define CRU_SOFTRST_CON28_PRESETN_CPU_BOOST_SHIFT (12U)
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#define CRU_SOFTRST_CON28_PRESETN_CPU_BOOST_MASK (0x1U << CRU_SOFTRST_CON28_PRESETN_CPU_BOOST_SHIFT) /* 0x00001000 */
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#define CRU_SOFTRST_CON28_RESETN_CPU_BOOST_SHIFT (13U)
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#define CRU_SOFTRST_CON28_RESETN_CPU_BOOST_MASK (0x1U << CRU_SOFTRST_CON28_RESETN_CPU_BOOST_SHIFT) /* 0x00002000 */
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#define CRU_SOFTRST_CON28_PRESETN_OTPPHY_SHIFT (14U)
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#define CRU_SOFTRST_CON28_PRESETN_OTPPHY_MASK (0x1U << CRU_SOFTRST_CON28_PRESETN_OTPPHY_SHIFT) /* 0x00004000 */
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#define CRU_SOFTRST_CON28_RESETN_OTPPHY_SHIFT (15U)
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#define CRU_SOFTRST_CON28_RESETN_OTPPHY_MASK (0x1U << CRU_SOFTRST_CON28_RESETN_OTPPHY_SHIFT) /* 0x00008000 */
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/* SOFTRST_CON29 */
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#define CRU_SOFTRST_CON29_OFFSET (0x474U)
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#define CRU_SOFTRST_CON29_RESETN_USB2PHY0_POR_SHIFT (0U)
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#define CRU_SOFTRST_CON29_RESETN_USB2PHY0_POR_MASK (0x1U << CRU_SOFTRST_CON29_RESETN_USB2PHY0_POR_SHIFT) /* 0x00000001 */
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#define CRU_SOFTRST_CON29_RESETN_USB2PHY0_USB3OTG0_SHIFT (1U)
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#define CRU_SOFTRST_CON29_RESETN_USB2PHY0_USB3OTG0_MASK (0x1U << CRU_SOFTRST_CON29_RESETN_USB2PHY0_USB3OTG0_SHIFT) /* 0x00000002 */
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#define CRU_SOFTRST_CON29_RESETN_USB2PHY0_USB3OTG1_SHIFT (2U)
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#define CRU_SOFTRST_CON29_RESETN_USB2PHY0_USB3OTG1_MASK (0x1U << CRU_SOFTRST_CON29_RESETN_USB2PHY0_USB3OTG1_SHIFT) /* 0x00000004 */
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#define CRU_SOFTRST_CON29_RESETN_USB2PHY1_POR_SHIFT (3U)
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#define CRU_SOFTRST_CON29_RESETN_USB2PHY1_POR_MASK (0x1U << CRU_SOFTRST_CON29_RESETN_USB2PHY1_POR_SHIFT) /* 0x00000008 */
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#define CRU_SOFTRST_CON29_RESETN_USB2PHY1_USB2HOST0_SHIFT (4U)
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#define CRU_SOFTRST_CON29_RESETN_USB2PHY1_USB2HOST0_MASK (0x1U << CRU_SOFTRST_CON29_RESETN_USB2PHY1_USB2HOST0_SHIFT) /* 0x00000010 */
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#define CRU_SOFTRST_CON29_RESETN_USB2PHY1_USB2HOST1_SHIFT (5U)
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#define CRU_SOFTRST_CON29_RESETN_USB2PHY1_USB2HOST1_MASK (0x1U << CRU_SOFTRST_CON29_RESETN_USB2PHY1_USB2HOST1_SHIFT) /* 0x00000020 */
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#define CRU_SOFTRST_CON29_PRESETN_EDPPHY_GRF_SHIFT (6U)
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#define CRU_SOFTRST_CON29_PRESETN_EDPPHY_GRF_MASK (0x1U << CRU_SOFTRST_CON29_PRESETN_EDPPHY_GRF_SHIFT) /* 0x00000040 */
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#define CRU_SOFTRST_CON29_RESETN_TSADCPHY_SHIFT (7U)
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#define CRU_SOFTRST_CON29_RESETN_TSADCPHY_MASK (0x1U << CRU_SOFTRST_CON29_RESETN_TSADCPHY_SHIFT) /* 0x00000080 */
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#define CRU_SOFTRST_CON29_RESETN_GMAC0_DELAYLINE_SHIFT (8U)
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#define CRU_SOFTRST_CON29_RESETN_GMAC0_DELAYLINE_MASK (0x1U << CRU_SOFTRST_CON29_RESETN_GMAC0_DELAYLINE_SHIFT) /* 0x00000100 */
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#define CRU_SOFTRST_CON29_RESETN_GMAC1_DELAYLINE_SHIFT (9U)
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#define CRU_SOFTRST_CON29_RESETN_GMAC1_DELAYLINE_MASK (0x1U << CRU_SOFTRST_CON29_RESETN_GMAC1_DELAYLINE_SHIFT) /* 0x00000200 */
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#define CRU_SOFTRST_CON29_RESETN_OTPC_ARB_SHIFT (10U)
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#define CRU_SOFTRST_CON29_RESETN_OTPC_ARB_MASK (0x1U << CRU_SOFTRST_CON29_RESETN_OTPC_ARB_SHIFT) /* 0x00000400 */
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#define CRU_SOFTRST_CON29_PRESETN_PIPEPHY0_GRF_SHIFT (11U)
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#define CRU_SOFTRST_CON29_PRESETN_PIPEPHY0_GRF_MASK (0x1U << CRU_SOFTRST_CON29_PRESETN_PIPEPHY0_GRF_SHIFT) /* 0x00000800 */
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#define CRU_SOFTRST_CON29_PRESETN_PIPEPHY1_GRF_SHIFT (12U)
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#define CRU_SOFTRST_CON29_PRESETN_PIPEPHY1_GRF_MASK (0x1U << CRU_SOFTRST_CON29_PRESETN_PIPEPHY1_GRF_SHIFT) /* 0x00001000 */
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#define CRU_SOFTRST_CON29_PRESETN_PIPEPHY2_GRF_SHIFT (13U)
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#define CRU_SOFTRST_CON29_PRESETN_PIPEPHY2_GRF_MASK (0x1U << CRU_SOFTRST_CON29_PRESETN_PIPEPHY2_GRF_SHIFT) /* 0x00002000 */
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/* SSGTBL0_3 */
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#define CRU_SSGTBL0_3_OFFSET (0x480U)
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#define CRU_SSGTBL0_3_SSGTBL0_3_SHIFT (0U)
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#define CRU_SSGTBL0_3_SSGTBL0_3_MASK (0xFFFFFFFFU << CRU_SSGTBL0_3_SSGTBL0_3_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL4_7 */
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#define CRU_SSGTBL4_7_OFFSET (0x484U)
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#define CRU_SSGTBL4_7_SSGTBL4_7_SHIFT (0U)
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#define CRU_SSGTBL4_7_SSGTBL4_7_MASK (0xFFFFFFFFU << CRU_SSGTBL4_7_SSGTBL4_7_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL8_11 */
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#define CRU_SSGTBL8_11_OFFSET (0x488U)
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#define CRU_SSGTBL8_11_SSGTBL8_11_SHIFT (0U)
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#define CRU_SSGTBL8_11_SSGTBL8_11_MASK (0xFFFFFFFFU << CRU_SSGTBL8_11_SSGTBL8_11_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL12_15 */
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#define CRU_SSGTBL12_15_OFFSET (0x48CU)
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#define CRU_SSGTBL12_15_SSGTBL12_15_SHIFT (0U)
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#define CRU_SSGTBL12_15_SSGTBL12_15_MASK (0xFFFFFFFFU << CRU_SSGTBL12_15_SSGTBL12_15_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL16_19 */
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#define CRU_SSGTBL16_19_OFFSET (0x490U)
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#define CRU_SSGTBL16_19_SSGTBL16_19_SHIFT (0U)
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#define CRU_SSGTBL16_19_SSGTBL16_19_MASK (0xFFFFFFFFU << CRU_SSGTBL16_19_SSGTBL16_19_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL20_23 */
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#define CRU_SSGTBL20_23_OFFSET (0x494U)
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#define CRU_SSGTBL20_23_SSGTBL20_23_SHIFT (0U)
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#define CRU_SSGTBL20_23_SSGTBL20_23_MASK (0xFFFFFFFFU << CRU_SSGTBL20_23_SSGTBL20_23_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL24_27 */
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#define CRU_SSGTBL24_27_OFFSET (0x498U)
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#define CRU_SSGTBL24_27_SSGTBL24_27_SHIFT (0U)
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#define CRU_SSGTBL24_27_SSGTBL24_27_MASK (0xFFFFFFFFU << CRU_SSGTBL24_27_SSGTBL24_27_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL28_31 */
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#define CRU_SSGTBL28_31_OFFSET (0x49CU)
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#define CRU_SSGTBL28_31_SSGTBL28_31_SHIFT (0U)
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#define CRU_SSGTBL28_31_SSGTBL28_31_MASK (0xFFFFFFFFU << CRU_SSGTBL28_31_SSGTBL28_31_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL32_35 */
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#define CRU_SSGTBL32_35_OFFSET (0x4A0U)
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#define CRU_SSGTBL32_35_SSGTBL32_35_SHIFT (0U)
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#define CRU_SSGTBL32_35_SSGTBL32_35_MASK (0xFFFFFFFFU << CRU_SSGTBL32_35_SSGTBL32_35_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL36_39 */
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#define CRU_SSGTBL36_39_OFFSET (0x4A4U)
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#define CRU_SSGTBL36_39_SSGTBL36_39_SHIFT (0U)
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#define CRU_SSGTBL36_39_SSGTBL36_39_MASK (0xFFFFFFFFU << CRU_SSGTBL36_39_SSGTBL36_39_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL40_43 */
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#define CRU_SSGTBL40_43_OFFSET (0x4A8U)
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#define CRU_SSGTBL40_43_SSGTBL40_43_SHIFT (0U)
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#define CRU_SSGTBL40_43_SSGTBL40_43_MASK (0xFFFFFFFFU << CRU_SSGTBL40_43_SSGTBL40_43_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL44_47 */
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#define CRU_SSGTBL44_47_OFFSET (0x4ACU)
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#define CRU_SSGTBL44_47_SSGTBL44_47_SHIFT (0U)
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#define CRU_SSGTBL44_47_SSGTBL44_47_MASK (0xFFFFFFFFU << CRU_SSGTBL44_47_SSGTBL44_47_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL48_51 */
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#define CRU_SSGTBL48_51_OFFSET (0x4B0U)
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#define CRU_SSGTBL48_51_SSGTBL48_51_SHIFT (0U)
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#define CRU_SSGTBL48_51_SSGTBL48_51_MASK (0xFFFFFFFFU << CRU_SSGTBL48_51_SSGTBL48_51_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL52_55 */
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#define CRU_SSGTBL52_55_OFFSET (0x4B4U)
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#define CRU_SSGTBL52_55_SSGTBL52_55_SHIFT (0U)
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#define CRU_SSGTBL52_55_SSGTBL52_55_MASK (0xFFFFFFFFU << CRU_SSGTBL52_55_SSGTBL52_55_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL56_59 */
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#define CRU_SSGTBL56_59_OFFSET (0x4B8U)
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#define CRU_SSGTBL56_59_SSGTBL56_59_SHIFT (0U)
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#define CRU_SSGTBL56_59_SSGTBL56_59_MASK (0xFFFFFFFFU << CRU_SSGTBL56_59_SSGTBL56_59_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL60_63 */
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#define CRU_SSGTBL60_63_OFFSET (0x4BCU)
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#define CRU_SSGTBL60_63_SSGTBL60_63_SHIFT (0U)
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#define CRU_SSGTBL60_63_SSGTBL60_63_MASK (0xFFFFFFFFU << CRU_SSGTBL60_63_SSGTBL60_63_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL64_67 */
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#define CRU_SSGTBL64_67_OFFSET (0x4C0U)
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#define CRU_SSGTBL64_67_SSGTBL64_67_SHIFT (0U)
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#define CRU_SSGTBL64_67_SSGTBL64_67_MASK (0xFFFFFFFFU << CRU_SSGTBL64_67_SSGTBL64_67_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL68_71 */
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#define CRU_SSGTBL68_71_OFFSET (0x4C4U)
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#define CRU_SSGTBL68_71_SSGTBL68_71_SHIFT (0U)
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#define CRU_SSGTBL68_71_SSGTBL68_71_MASK (0xFFFFFFFFU << CRU_SSGTBL68_71_SSGTBL68_71_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL72_75 */
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#define CRU_SSGTBL72_75_OFFSET (0x4C8U)
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#define CRU_SSGTBL72_75_SSGTBL72_75_SHIFT (0U)
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#define CRU_SSGTBL72_75_SSGTBL72_75_MASK (0xFFFFFFFFU << CRU_SSGTBL72_75_SSGTBL72_75_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL76_79 */
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#define CRU_SSGTBL76_79_OFFSET (0x4CCU)
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#define CRU_SSGTBL76_79_SSGTBL76_79_SHIFT (0U)
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#define CRU_SSGTBL76_79_SSGTBL76_79_MASK (0xFFFFFFFFU << CRU_SSGTBL76_79_SSGTBL76_79_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL80_83 */
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#define CRU_SSGTBL80_83_OFFSET (0x4D0U)
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#define CRU_SSGTBL80_83_SSGTBL80_83_SHIFT (0U)
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#define CRU_SSGTBL80_83_SSGTBL80_83_MASK (0xFFFFFFFFU << CRU_SSGTBL80_83_SSGTBL80_83_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL84_87 */
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#define CRU_SSGTBL84_87_OFFSET (0x4D4U)
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#define CRU_SSGTBL84_87_SSGTBL84_87_SHIFT (0U)
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#define CRU_SSGTBL84_87_SSGTBL84_87_MASK (0xFFFFFFFFU << CRU_SSGTBL84_87_SSGTBL84_87_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL88_91 */
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#define CRU_SSGTBL88_91_OFFSET (0x4D8U)
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#define CRU_SSGTBL88_91_SSGTBL88_91_SHIFT (0U)
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#define CRU_SSGTBL88_91_SSGTBL88_91_MASK (0xFFFFFFFFU << CRU_SSGTBL88_91_SSGTBL88_91_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL92_95 */
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#define CRU_SSGTBL92_95_OFFSET (0x4DCU)
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#define CRU_SSGTBL92_95_SSGTBL92_95_SHIFT (0U)
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#define CRU_SSGTBL92_95_SSGTBL92_95_MASK (0xFFFFFFFFU << CRU_SSGTBL92_95_SSGTBL92_95_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL96_99 */
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#define CRU_SSGTBL96_99_OFFSET (0x4E0U)
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#define CRU_SSGTBL96_99_SSGTBL96_99_SHIFT (0U)
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#define CRU_SSGTBL96_99_SSGTBL96_99_MASK (0xFFFFFFFFU << CRU_SSGTBL96_99_SSGTBL96_99_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL100_103 */
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#define CRU_SSGTBL100_103_OFFSET (0x4E4U)
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#define CRU_SSGTBL100_103_SSGTBL100_103_SHIFT (0U)
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#define CRU_SSGTBL100_103_SSGTBL100_103_MASK (0xFFFFFFFFU << CRU_SSGTBL100_103_SSGTBL100_103_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL104_107 */
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#define CRU_SSGTBL104_107_OFFSET (0x4E8U)
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#define CRU_SSGTBL104_107_SSGTBL104_107_SHIFT (0U)
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#define CRU_SSGTBL104_107_SSGTBL104_107_MASK (0xFFFFFFFFU << CRU_SSGTBL104_107_SSGTBL104_107_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL108_111 */
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#define CRU_SSGTBL108_111_OFFSET (0x4ECU)
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#define CRU_SSGTBL108_111_SSGTBL108_111_SHIFT (0U)
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#define CRU_SSGTBL108_111_SSGTBL108_111_MASK (0xFFFFFFFFU << CRU_SSGTBL108_111_SSGTBL108_111_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL112_115 */
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#define CRU_SSGTBL112_115_OFFSET (0x4F0U)
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#define CRU_SSGTBL112_115_SSGTBL112_115_SHIFT (0U)
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#define CRU_SSGTBL112_115_SSGTBL112_115_MASK (0xFFFFFFFFU << CRU_SSGTBL112_115_SSGTBL112_115_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL116_119 */
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#define CRU_SSGTBL116_119_OFFSET (0x4F4U)
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#define CRU_SSGTBL116_119_SSGTBL116_119_SHIFT (0U)
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#define CRU_SSGTBL116_119_SSGTBL116_119_MASK (0xFFFFFFFFU << CRU_SSGTBL116_119_SSGTBL116_119_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL120_123 */
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#define CRU_SSGTBL120_123_OFFSET (0x4F8U)
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#define CRU_SSGTBL120_123_SSGTBL120_123_SHIFT (0U)
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#define CRU_SSGTBL120_123_SSGTBL120_123_MASK (0xFFFFFFFFU << CRU_SSGTBL120_123_SSGTBL120_123_SHIFT) /* 0xFFFFFFFF */
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/* SSGTBL124_127 */
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#define CRU_SSGTBL124_127_OFFSET (0x4FCU)
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#define CRU_SSGTBL124_127_SSGTBL124_127_SHIFT (0U)
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#define CRU_SSGTBL124_127_SSGTBL124_127_MASK (0xFFFFFFFFU << CRU_SSGTBL124_127_SSGTBL124_127_SHIFT) /* 0xFFFFFFFF */
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/* AUTOCS_CORE_CON0 */
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#define CRU_AUTOCS_CORE_CON0_OFFSET (0x500U)
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#define CRU_AUTOCS_CORE_CON0_PDCORE_IDLE_TH_SHIFT (0U)
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#define CRU_AUTOCS_CORE_CON0_PDCORE_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_CORE_CON0_PDCORE_IDLE_TH_SHIFT) /* 0x0000FFFF */
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#define CRU_AUTOCS_CORE_CON0_PDCORE_WAIT_TH_SHIFT (16U)
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#define CRU_AUTOCS_CORE_CON0_PDCORE_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_CORE_CON0_PDCORE_WAIT_TH_SHIFT) /* 0xFFFF0000 */
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/* AUTOCS_CORE_CON1 */
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#define CRU_AUTOCS_CORE_CON1_OFFSET (0x504U)
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#define CRU_AUTOCS_CORE_CON1_CPU_SWITCH_EN_SHIFT (0U)
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#define CRU_AUTOCS_CORE_CON1_CPU_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_CORE_CON1_CPU_SWITCH_EN_SHIFT) /* 0x00000001 */
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#define CRU_AUTOCS_CORE_CON1_DSU_SWITCH_EN_SHIFT (1U)
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#define CRU_AUTOCS_CORE_CON1_DSU_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_CORE_CON1_DSU_SWITCH_EN_SHIFT) /* 0x00000002 */
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#define CRU_AUTOCS_CORE_CON1_WFI_EN_SHIFT (2U)
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#define CRU_AUTOCS_CORE_CON1_WFI_EN_MASK (0x1U << CRU_AUTOCS_CORE_CON1_WFI_EN_SHIFT) /* 0x00000004 */
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#define CRU_AUTOCS_CORE_CON1_WFIL3_EN_SHIFT (3U)
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#define CRU_AUTOCS_CORE_CON1_WFIL3_EN_MASK (0x1U << CRU_AUTOCS_CORE_CON1_WFIL3_EN_SHIFT) /* 0x00000008 */
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#define CRU_AUTOCS_CORE_CON1_FIQIRQ_EN_SHIFT (4U)
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#define CRU_AUTOCS_CORE_CON1_FIQIRQ_EN_MASK (0x1U << CRU_AUTOCS_CORE_CON1_FIQIRQ_EN_SHIFT) /* 0x00000010 */
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#define CRU_AUTOCS_CORE_CON1_VFIQIRQ_EN_SHIFT (5U)
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#define CRU_AUTOCS_CORE_CON1_VFIQIRQ_EN_MASK (0x1U << CRU_AUTOCS_CORE_CON1_VFIQIRQ_EN_SHIFT) /* 0x00000020 */
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#define CRU_AUTOCS_CORE_CON1_NIU_ACTIVE_EN_SHIFT (6U)
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#define CRU_AUTOCS_CORE_CON1_NIU_ACTIVE_EN_MASK (0x1U << CRU_AUTOCS_CORE_CON1_NIU_ACTIVE_EN_SHIFT) /* 0x00000040 */
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#define CRU_AUTOCS_CORE_CON1_STEP_SHIFT (8U)
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#define CRU_AUTOCS_CORE_CON1_STEP_MASK (0x7U << CRU_AUTOCS_CORE_CON1_STEP_SHIFT) /* 0x00000700 */
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#define CRU_AUTOCS_CORE_CON1_CLKSEL_CFG_SHIFT (14U)
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#define CRU_AUTOCS_CORE_CON1_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_CORE_CON1_CLKSEL_CFG_SHIFT) /* 0x0000C000 */
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/* AUTOCS_GPU_CON0 */
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#define CRU_AUTOCS_GPU_CON0_OFFSET (0x508U)
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#define CRU_AUTOCS_GPU_CON0_IDLE_TH_SHIFT (0U)
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#define CRU_AUTOCS_GPU_CON0_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_GPU_CON0_IDLE_TH_SHIFT) /* 0x0000FFFF */
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#define CRU_AUTOCS_GPU_CON0_WAIT_TH_SHIFT (16U)
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#define CRU_AUTOCS_GPU_CON0_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_GPU_CON0_WAIT_TH_SHIFT) /* 0xFFFF0000 */
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/* AUTOCS_GPU_CON1 */
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#define CRU_AUTOCS_GPU_CON1_OFFSET (0x50CU)
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#define CRU_AUTOCS_GPU_CON1_SWITCH_EN_SHIFT (0U)
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#define CRU_AUTOCS_GPU_CON1_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_GPU_CON1_SWITCH_EN_SHIFT) /* 0x00000001 */
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#define CRU_AUTOCS_GPU_CON1_CLK_EN_SHIFT (1U)
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#define CRU_AUTOCS_GPU_CON1_CLK_EN_MASK (0x1U << CRU_AUTOCS_GPU_CON1_CLK_EN_SHIFT) /* 0x00000002 */
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#define CRU_AUTOCS_GPU_CON1_CLKSEL_CFG_SHIFT (14U)
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#define CRU_AUTOCS_GPU_CON1_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_GPU_CON1_CLKSEL_CFG_SHIFT) /* 0x0000C000 */
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/* AUTOCS_BUS_CON0 */
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#define CRU_AUTOCS_BUS_CON0_OFFSET (0x510U)
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#define CRU_AUTOCS_BUS_CON0_IDLE_TH_SHIFT (0U)
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#define CRU_AUTOCS_BUS_CON0_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_BUS_CON0_IDLE_TH_SHIFT) /* 0x0000FFFF */
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#define CRU_AUTOCS_BUS_CON0_WAIT_TH_SHIFT (16U)
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#define CRU_AUTOCS_BUS_CON0_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_BUS_CON0_WAIT_TH_SHIFT) /* 0xFFFF0000 */
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/* AUTOCS_BUS_CON1 */
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#define CRU_AUTOCS_BUS_CON1_OFFSET (0x514U)
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#define CRU_AUTOCS_BUS_CON1_SWITCH_EN_SHIFT (0U)
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#define CRU_AUTOCS_BUS_CON1_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_BUS_CON1_SWITCH_EN_SHIFT) /* 0x00000001 */
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#define CRU_AUTOCS_BUS_CON1_ACLK_EN_SHIFT (1U)
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#define CRU_AUTOCS_BUS_CON1_ACLK_EN_MASK (0x1U << CRU_AUTOCS_BUS_CON1_ACLK_EN_SHIFT) /* 0x00000002 */
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#define CRU_AUTOCS_BUS_CON1_PCLK_EN_SHIFT (3U)
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#define CRU_AUTOCS_BUS_CON1_PCLK_EN_MASK (0x1U << CRU_AUTOCS_BUS_CON1_PCLK_EN_SHIFT) /* 0x00000008 */
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#define CRU_AUTOCS_BUS_CON1_MASTER_EN_SHIFT (4U)
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#define CRU_AUTOCS_BUS_CON1_MASTER_EN_MASK (0x1U << CRU_AUTOCS_BUS_CON1_MASTER_EN_SHIFT) /* 0x00000010 */
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#define CRU_AUTOCS_BUS_CON1_SLAVE_EN_SHIFT (5U)
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#define CRU_AUTOCS_BUS_CON1_SLAVE_EN_MASK (0x1U << CRU_AUTOCS_BUS_CON1_SLAVE_EN_SHIFT) /* 0x00000020 */
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#define CRU_AUTOCS_BUS_CON1_DMAC_M_EN_SHIFT (7U)
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#define CRU_AUTOCS_BUS_CON1_DMAC_M_EN_MASK (0x1U << CRU_AUTOCS_BUS_CON1_DMAC_M_EN_SHIFT) /* 0x00000080 */
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#define CRU_AUTOCS_BUS_CON1_CLKSEL_CFG_SHIFT (14U)
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#define CRU_AUTOCS_BUS_CON1_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_BUS_CON1_CLKSEL_CFG_SHIFT) /* 0x0000C000 */
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/* AUTOCS_TOP_CON0 */
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#define CRU_AUTOCS_TOP_CON0_OFFSET (0x518U)
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#define CRU_AUTOCS_TOP_CON0_IDLE_TH_SHIFT (0U)
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#define CRU_AUTOCS_TOP_CON0_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_TOP_CON0_IDLE_TH_SHIFT) /* 0x0000FFFF */
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#define CRU_AUTOCS_TOP_CON0_WAIT_TH_SHIFT (16U)
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#define CRU_AUTOCS_TOP_CON0_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_TOP_CON0_WAIT_TH_SHIFT) /* 0xFFFF0000 */
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/* AUTOCS_TOP_CON1 */
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#define CRU_AUTOCS_TOP_CON1_OFFSET (0x51CU)
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#define CRU_AUTOCS_TOP_CON1_SWITCH_EN_SHIFT (0U)
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#define CRU_AUTOCS_TOP_CON1_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_TOP_CON1_SWITCH_EN_SHIFT) /* 0x00000001 */
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#define CRU_AUTOCS_TOP_CON1_ACLK_EN_SHIFT (1U)
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#define CRU_AUTOCS_TOP_CON1_ACLK_EN_MASK (0x1U << CRU_AUTOCS_TOP_CON1_ACLK_EN_SHIFT) /* 0x00000002 */
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#define CRU_AUTOCS_TOP_CON1_HCLK_EN_SHIFT (2U)
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#define CRU_AUTOCS_TOP_CON1_HCLK_EN_MASK (0x1U << CRU_AUTOCS_TOP_CON1_HCLK_EN_SHIFT) /* 0x00000004 */
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#define CRU_AUTOCS_TOP_CON1_PCLK_EN_SHIFT (3U)
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#define CRU_AUTOCS_TOP_CON1_PCLK_EN_MASK (0x1U << CRU_AUTOCS_TOP_CON1_PCLK_EN_SHIFT) /* 0x00000008 */
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#define CRU_AUTOCS_TOP_CON1_MASTER_EN_SHIFT (4U)
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#define CRU_AUTOCS_TOP_CON1_MASTER_EN_MASK (0x1U << CRU_AUTOCS_TOP_CON1_MASTER_EN_SHIFT) /* 0x00000010 */
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#define CRU_AUTOCS_TOP_CON1_SLAVE_EN_SHIFT (5U)
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#define CRU_AUTOCS_TOP_CON1_SLAVE_EN_MASK (0x1U << CRU_AUTOCS_TOP_CON1_SLAVE_EN_SHIFT) /* 0x00000020 */
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#define CRU_AUTOCS_TOP_CON1_DMAC_M_EN_SHIFT (7U)
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#define CRU_AUTOCS_TOP_CON1_DMAC_M_EN_MASK (0x1U << CRU_AUTOCS_TOP_CON1_DMAC_M_EN_SHIFT) /* 0x00000080 */
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#define CRU_AUTOCS_TOP_CON1_CLKSEL_CFG_SHIFT (14U)
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#define CRU_AUTOCS_TOP_CON1_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_TOP_CON1_CLKSEL_CFG_SHIFT) /* 0x0000C000 */
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/* AUTOCS_RKVDEC_CON0 */
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#define CRU_AUTOCS_RKVDEC_CON0_OFFSET (0x520U)
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#define CRU_AUTOCS_RKVDEC_CON0_IDLE_TH_SHIFT (0U)
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#define CRU_AUTOCS_RKVDEC_CON0_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_RKVDEC_CON0_IDLE_TH_SHIFT) /* 0x0000FFFF */
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#define CRU_AUTOCS_RKVDEC_CON0_WAIT_TH_SHIFT (16U)
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#define CRU_AUTOCS_RKVDEC_CON0_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_RKVDEC_CON0_WAIT_TH_SHIFT) /* 0xFFFF0000 */
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/* AUTOCS_RKVDEC_CON1 */
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#define CRU_AUTOCS_RKVDEC_CON1_OFFSET (0x524U)
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#define CRU_AUTOCS_RKVDEC_CON1_SWITCH_EN_SHIFT (0U)
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#define CRU_AUTOCS_RKVDEC_CON1_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_RKVDEC_CON1_SWITCH_EN_SHIFT) /* 0x00000001 */
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#define CRU_AUTOCS_RKVDEC_CON1_RKVDEC_ACLK_EN_SHIFT (1U)
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#define CRU_AUTOCS_RKVDEC_CON1_RKVDEC_ACLK_EN_MASK (0x1U << CRU_AUTOCS_RKVDEC_CON1_RKVDEC_ACLK_EN_SHIFT) /* 0x00000002 */
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#define CRU_AUTOCS_RKVDEC_CON1_RKVDEC_CLK_CA_EN_SHIFT (2U)
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#define CRU_AUTOCS_RKVDEC_CON1_RKVDEC_CLK_CA_EN_MASK (0x1U << CRU_AUTOCS_RKVDEC_CON1_RKVDEC_CLK_CA_EN_SHIFT) /* 0x00000004 */
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#define CRU_AUTOCS_RKVDEC_CON1_RKVDEC_CLK_CORE_EN_SHIFT (3U)
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#define CRU_AUTOCS_RKVDEC_CON1_RKVDEC_CLK_CORE_EN_MASK (0x1U << CRU_AUTOCS_RKVDEC_CON1_RKVDEC_CLK_CORE_EN_SHIFT) /* 0x00000008 */
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#define CRU_AUTOCS_RKVDEC_CON1_RKVDEC_CLK_HEVC_EN_SHIFT (4U)
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#define CRU_AUTOCS_RKVDEC_CON1_RKVDEC_CLK_HEVC_EN_MASK (0x1U << CRU_AUTOCS_RKVDEC_CON1_RKVDEC_CLK_HEVC_EN_SHIFT) /* 0x00000010 */
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#define CRU_AUTOCS_RKVDEC_CON1_CLK_CA_SEL_CFG_SHIFT (8U)
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#define CRU_AUTOCS_RKVDEC_CON1_CLK_CA_SEL_CFG_MASK (0x3U << CRU_AUTOCS_RKVDEC_CON1_CLK_CA_SEL_CFG_SHIFT) /* 0x00000300 */
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#define CRU_AUTOCS_RKVDEC_CON1_CLK_CORE_SEL_CFG_SHIFT (10U)
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#define CRU_AUTOCS_RKVDEC_CON1_CLK_CORE_SEL_CFG_MASK (0x3U << CRU_AUTOCS_RKVDEC_CON1_CLK_CORE_SEL_CFG_SHIFT) /* 0x00000C00 */
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#define CRU_AUTOCS_RKVDEC_CON1_CLK_HEVC_SEL_CFG_SHIFT (12U)
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#define CRU_AUTOCS_RKVDEC_CON1_CLK_HEVC_SEL_CFG_MASK (0x3U << CRU_AUTOCS_RKVDEC_CON1_CLK_HEVC_SEL_CFG_SHIFT) /* 0x00003000 */
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#define CRU_AUTOCS_RKVDEC_CON1_ACLKSEL_CFG_SHIFT (14U)
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#define CRU_AUTOCS_RKVDEC_CON1_ACLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_RKVDEC_CON1_ACLKSEL_CFG_SHIFT) /* 0x0000C000 */
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/* AUTOCS_RKVENC_CON0 */
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#define CRU_AUTOCS_RKVENC_CON0_OFFSET (0x528U)
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#define CRU_AUTOCS_RKVENC_CON0_IDLE_TH_SHIFT (0U)
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#define CRU_AUTOCS_RKVENC_CON0_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_RKVENC_CON0_IDLE_TH_SHIFT) /* 0x0000FFFF */
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#define CRU_AUTOCS_RKVENC_CON0_WAIT_TH_SHIFT (16U)
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#define CRU_AUTOCS_RKVENC_CON0_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_RKVENC_CON0_WAIT_TH_SHIFT) /* 0xFFFF0000 */
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/* AUTOCS_RKVENC_CON1 */
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#define CRU_AUTOCS_RKVENC_CON1_OFFSET (0x52CU)
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#define CRU_AUTOCS_RKVENC_CON1_SWITCH_EN_SHIFT (0U)
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#define CRU_AUTOCS_RKVENC_CON1_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_RKVENC_CON1_SWITCH_EN_SHIFT) /* 0x00000001 */
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#define CRU_AUTOCS_RKVENC_CON1_CLK_EN_SHIFT (1U)
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#define CRU_AUTOCS_RKVENC_CON1_CLK_EN_MASK (0x1U << CRU_AUTOCS_RKVENC_CON1_CLK_EN_SHIFT) /* 0x00000002 */
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#define CRU_AUTOCS_RKVENC_CON1_CLKSEL_CFG_SHIFT (14U)
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#define CRU_AUTOCS_RKVENC_CON1_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_RKVENC_CON1_CLKSEL_CFG_SHIFT) /* 0x0000C000 */
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/* AUTOCS_VPU_CON0 */
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#define CRU_AUTOCS_VPU_CON0_OFFSET (0x530U)
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#define CRU_AUTOCS_VPU_CON0_IDLE_TH_SHIFT (0U)
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#define CRU_AUTOCS_VPU_CON0_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_VPU_CON0_IDLE_TH_SHIFT) /* 0x0000FFFF */
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#define CRU_AUTOCS_VPU_CON0_WAIT_TH_SHIFT (16U)
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#define CRU_AUTOCS_VPU_CON0_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_VPU_CON0_WAIT_TH_SHIFT) /* 0xFFFF0000 */
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/* AUTOCS_VPU_CON1 */
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#define CRU_AUTOCS_VPU_CON1_OFFSET (0x534U)
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#define CRU_AUTOCS_VPU_CON1_SWITCH_EN_SHIFT (0U)
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#define CRU_AUTOCS_VPU_CON1_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_VPU_CON1_SWITCH_EN_SHIFT) /* 0x00000001 */
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#define CRU_AUTOCS_VPU_CON1_CLK_EN_SHIFT (1U)
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#define CRU_AUTOCS_VPU_CON1_CLK_EN_MASK (0x1U << CRU_AUTOCS_VPU_CON1_CLK_EN_SHIFT) /* 0x00000002 */
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#define CRU_AUTOCS_VPU_CON1_CLKSEL_CFG_SHIFT (14U)
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#define CRU_AUTOCS_VPU_CON1_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_VPU_CON1_CLKSEL_CFG_SHIFT) /* 0x0000C000 */
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/* AUTOCS_PERI_CON0 */
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#define CRU_AUTOCS_PERI_CON0_OFFSET (0x538U)
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#define CRU_AUTOCS_PERI_CON0_IDLE_TH_SHIFT (0U)
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#define CRU_AUTOCS_PERI_CON0_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_PERI_CON0_IDLE_TH_SHIFT) /* 0x0000FFFF */
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#define CRU_AUTOCS_PERI_CON0_WAIT_TH_SHIFT (16U)
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#define CRU_AUTOCS_PERI_CON0_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_PERI_CON0_WAIT_TH_SHIFT) /* 0xFFFF0000 */
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/* AUTOCS_PERI_CON1 */
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#define CRU_AUTOCS_PERI_CON1_OFFSET (0x53CU)
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#define CRU_AUTOCS_PERI_CON1_PERI_SWITCH_EN_SHIFT (0U)
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#define CRU_AUTOCS_PERI_CON1_PERI_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_PERI_SWITCH_EN_SHIFT) /* 0x00000001 */
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#define CRU_AUTOCS_PERI_CON1_PERI_ACLK_EN_SHIFT (1U)
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#define CRU_AUTOCS_PERI_CON1_PERI_ACLK_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_PERI_ACLK_EN_SHIFT) /* 0x00000002 */
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#define CRU_AUTOCS_PERI_CON1_PERI_HCLK_EN_SHIFT (2U)
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#define CRU_AUTOCS_PERI_CON1_PERI_HCLK_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_PERI_HCLK_EN_SHIFT) /* 0x00000004 */
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#define CRU_AUTOCS_PERI_CON1_PHP_SWITCH_EN_SHIFT (3U)
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#define CRU_AUTOCS_PERI_CON1_PHP_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_PHP_SWITCH_EN_SHIFT) /* 0x00000008 */
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#define CRU_AUTOCS_PERI_CON1_PHP_ACLK_EN_SHIFT (4U)
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#define CRU_AUTOCS_PERI_CON1_PHP_ACLK_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_PHP_ACLK_EN_SHIFT) /* 0x00000010 */
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#define CRU_AUTOCS_PERI_CON1_PHP_HCLK_EN_SHIFT (5U)
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#define CRU_AUTOCS_PERI_CON1_PHP_HCLK_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_PHP_HCLK_EN_SHIFT) /* 0x00000020 */
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#define CRU_AUTOCS_PERI_CON1_GA_SWITCH_EN_SHIFT (6U)
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#define CRU_AUTOCS_PERI_CON1_GA_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_GA_SWITCH_EN_SHIFT) /* 0x00000040 */
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#define CRU_AUTOCS_PERI_CON1_GA_ACLK_EN_SHIFT (7U)
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#define CRU_AUTOCS_PERI_CON1_GA_ACLK_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_GA_ACLK_EN_SHIFT) /* 0x00000080 */
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#define CRU_AUTOCS_PERI_CON1_GA_HCLK_EN_SHIFT (8U)
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#define CRU_AUTOCS_PERI_CON1_GA_HCLK_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_GA_HCLK_EN_SHIFT) /* 0x00000100 */
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#define CRU_AUTOCS_PERI_CON1_SF_SWITCH_EN_SHIFT (9U)
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#define CRU_AUTOCS_PERI_CON1_SF_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_SF_SWITCH_EN_SHIFT) /* 0x00000200 */
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#define CRU_AUTOCS_PERI_CON1_SF_ACLK_EN_SHIFT (10U)
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#define CRU_AUTOCS_PERI_CON1_SF_ACLK_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_SF_ACLK_EN_SHIFT) /* 0x00000400 */
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#define CRU_AUTOCS_PERI_CON1_SF_HCLK_EN_SHIFT (11U)
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#define CRU_AUTOCS_PERI_CON1_SF_HCLK_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_SF_HCLK_EN_SHIFT) /* 0x00000800 */
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#define CRU_AUTOCS_PERI_CON1_DCF_M_EN_SHIFT (12U)
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#define CRU_AUTOCS_PERI_CON1_DCF_M_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_DCF_M_EN_SHIFT) /* 0x00001000 */
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#define CRU_AUTOCS_PERI_CON1_CLKSEL_CFG_SHIFT (14U)
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#define CRU_AUTOCS_PERI_CON1_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_PERI_CON1_CLKSEL_CFG_SHIFT) /* 0x0000C000 */
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/* AUTOCS_GPLL_CON0 */
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#define CRU_AUTOCS_GPLL_CON0_OFFSET (0x540U)
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#define CRU_AUTOCS_GPLL_CON0_IDLE_TH_SHIFT (0U)
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#define CRU_AUTOCS_GPLL_CON0_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_GPLL_CON0_IDLE_TH_SHIFT) /* 0x0000FFFF */
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#define CRU_AUTOCS_GPLL_CON0_WAIT_TH_SHIFT (16U)
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#define CRU_AUTOCS_GPLL_CON0_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_GPLL_CON0_WAIT_TH_SHIFT) /* 0xFFFF0000 */
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/* AUTOCS_GPLL_CON1 */
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#define CRU_AUTOCS_GPLL_CON1_OFFSET (0x544U)
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#define CRU_AUTOCS_GPLL_CON1_SWITCH_EN_SHIFT (0U)
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#define CRU_AUTOCS_GPLL_CON1_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_GPLL_CON1_SWITCH_EN_SHIFT) /* 0x00000001 */
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#define CRU_AUTOCS_GPLL_CON1_WFI_EN_SHIFT (2U)
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#define CRU_AUTOCS_GPLL_CON1_WFI_EN_MASK (0x1U << CRU_AUTOCS_GPLL_CON1_WFI_EN_SHIFT) /* 0x00000004 */
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#define CRU_AUTOCS_GPLL_CON1_WFIL3_EN_SHIFT (3U)
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#define CRU_AUTOCS_GPLL_CON1_WFIL3_EN_MASK (0x1U << CRU_AUTOCS_GPLL_CON1_WFIL3_EN_SHIFT) /* 0x00000008 */
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#define CRU_AUTOCS_GPLL_CON1_FIQIRQ_EN_SHIFT (4U)
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#define CRU_AUTOCS_GPLL_CON1_FIQIRQ_EN_MASK (0x1U << CRU_AUTOCS_GPLL_CON1_FIQIRQ_EN_SHIFT) /* 0x00000010 */
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#define CRU_AUTOCS_GPLL_CON1_VFIQIRQ_EN_SHIFT (5U)
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#define CRU_AUTOCS_GPLL_CON1_VFIQIRQ_EN_MASK (0x1U << CRU_AUTOCS_GPLL_CON1_VFIQIRQ_EN_SHIFT) /* 0x00000020 */
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/* AUTOCS_CPLL_CON0 */
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#define CRU_AUTOCS_CPLL_CON0_OFFSET (0x548U)
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#define CRU_AUTOCS_CPLL_CON0_IDLE_TH_SHIFT (0U)
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#define CRU_AUTOCS_CPLL_CON0_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_CPLL_CON0_IDLE_TH_SHIFT) /* 0x0000FFFF */
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#define CRU_AUTOCS_CPLL_CON0_WAIT_TH_SHIFT (16U)
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#define CRU_AUTOCS_CPLL_CON0_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_CPLL_CON0_WAIT_TH_SHIFT) /* 0xFFFF0000 */
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/* AUTOCS_CPLL_CON1 */
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#define CRU_AUTOCS_CPLL_CON1_OFFSET (0x54CU)
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#define CRU_AUTOCS_CPLL_CON1_SWITCH_EN_SHIFT (0U)
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#define CRU_AUTOCS_CPLL_CON1_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_CPLL_CON1_SWITCH_EN_SHIFT) /* 0x00000001 */
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#define CRU_AUTOCS_CPLL_CON1_WFI_EN_SHIFT (2U)
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#define CRU_AUTOCS_CPLL_CON1_WFI_EN_MASK (0x1U << CRU_AUTOCS_CPLL_CON1_WFI_EN_SHIFT) /* 0x00000004 */
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#define CRU_AUTOCS_CPLL_CON1_WFIL3_EN_SHIFT (3U)
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#define CRU_AUTOCS_CPLL_CON1_WFIL3_EN_MASK (0x1U << CRU_AUTOCS_CPLL_CON1_WFIL3_EN_SHIFT) /* 0x00000008 */
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#define CRU_AUTOCS_CPLL_CON1_FIQIRQ_EN_SHIFT (4U)
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#define CRU_AUTOCS_CPLL_CON1_FIQIRQ_EN_MASK (0x1U << CRU_AUTOCS_CPLL_CON1_FIQIRQ_EN_SHIFT) /* 0x00000010 */
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#define CRU_AUTOCS_CPLL_CON1_VFIQIRQ_EN_SHIFT (5U)
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#define CRU_AUTOCS_CPLL_CON1_VFIQIRQ_EN_MASK (0x1U << CRU_AUTOCS_CPLL_CON1_VFIQIRQ_EN_SHIFT) /* 0x00000020 */
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/* SDMMC0_CON0 */
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#define CRU_SDMMC0_CON0_OFFSET (0x580U)
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#define CRU_SDMMC0_CON0_INIT_STATE_SHIFT (0U)
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#define CRU_SDMMC0_CON0_INIT_STATE_MASK (0x1U << CRU_SDMMC0_CON0_INIT_STATE_SHIFT) /* 0x00000001 */
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#define CRU_SDMMC0_CON0_DRV_DEGREE_SHIFT (1U)
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#define CRU_SDMMC0_CON0_DRV_DEGREE_MASK (0x3U << CRU_SDMMC0_CON0_DRV_DEGREE_SHIFT) /* 0x00000006 */
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#define CRU_SDMMC0_CON0_DRV_DELAYNUM_SHIFT (3U)
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#define CRU_SDMMC0_CON0_DRV_DELAYNUM_MASK (0xFFU << CRU_SDMMC0_CON0_DRV_DELAYNUM_SHIFT) /* 0x000007F8 */
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#define CRU_SDMMC0_CON0_DRV_SEL_SHIFT (11U)
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#define CRU_SDMMC0_CON0_DRV_SEL_MASK (0x1U << CRU_SDMMC0_CON0_DRV_SEL_SHIFT) /* 0x00000800 */
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/* SDMMC0_CON1 */
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#define CRU_SDMMC0_CON1_OFFSET (0x584U)
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#define CRU_SDMMC0_CON1_SAMPLE_DEGREE_SHIFT (0U)
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#define CRU_SDMMC0_CON1_SAMPLE_DEGREE_MASK (0x3U << CRU_SDMMC0_CON1_SAMPLE_DEGREE_SHIFT) /* 0x00000003 */
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#define CRU_SDMMC0_CON1_SAMPLE_DELAYNUM_SHIFT (2U)
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#define CRU_SDMMC0_CON1_SAMPLE_DELAYNUM_MASK (0xFFU << CRU_SDMMC0_CON1_SAMPLE_DELAYNUM_SHIFT) /* 0x000003FC */
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#define CRU_SDMMC0_CON1_SAMPLE_SEL_SHIFT (10U)
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#define CRU_SDMMC0_CON1_SAMPLE_SEL_MASK (0x1U << CRU_SDMMC0_CON1_SAMPLE_SEL_SHIFT) /* 0x00000400 */
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/* SDMMC1_CON0 */
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#define CRU_SDMMC1_CON0_OFFSET (0x588U)
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#define CRU_SDMMC1_CON0_INIT_STATE_SHIFT (0U)
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#define CRU_SDMMC1_CON0_INIT_STATE_MASK (0x1U << CRU_SDMMC1_CON0_INIT_STATE_SHIFT) /* 0x00000001 */
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#define CRU_SDMMC1_CON0_DRV_DEGREE_SHIFT (1U)
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#define CRU_SDMMC1_CON0_DRV_DEGREE_MASK (0x3U << CRU_SDMMC1_CON0_DRV_DEGREE_SHIFT) /* 0x00000006 */
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#define CRU_SDMMC1_CON0_DRV_DELAYNUM_SHIFT (3U)
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#define CRU_SDMMC1_CON0_DRV_DELAYNUM_MASK (0xFFU << CRU_SDMMC1_CON0_DRV_DELAYNUM_SHIFT) /* 0x000007F8 */
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#define CRU_SDMMC1_CON0_DRV_SEL_SHIFT (11U)
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#define CRU_SDMMC1_CON0_DRV_SEL_MASK (0x1U << CRU_SDMMC1_CON0_DRV_SEL_SHIFT) /* 0x00000800 */
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/* SDMMC1_CON1 */
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#define CRU_SDMMC1_CON1_OFFSET (0x58CU)
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#define CRU_SDMMC1_CON1_SAMPLE_DEGREE_SHIFT (0U)
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#define CRU_SDMMC1_CON1_SAMPLE_DEGREE_MASK (0x3U << CRU_SDMMC1_CON1_SAMPLE_DEGREE_SHIFT) /* 0x00000003 */
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#define CRU_SDMMC1_CON1_SAMPLE_DELAYNUM_SHIFT (2U)
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#define CRU_SDMMC1_CON1_SAMPLE_DELAYNUM_MASK (0xFFU << CRU_SDMMC1_CON1_SAMPLE_DELAYNUM_SHIFT) /* 0x000003FC */
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#define CRU_SDMMC1_CON1_SAMPLE_SEL_SHIFT (10U)
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#define CRU_SDMMC1_CON1_SAMPLE_SEL_MASK (0x1U << CRU_SDMMC1_CON1_SAMPLE_SEL_SHIFT) /* 0x00000400 */
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/* SDMMC2_CON0 */
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#define CRU_SDMMC2_CON0_OFFSET (0x590U)
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#define CRU_SDMMC2_CON0_INIT_STATE_SHIFT (0U)
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#define CRU_SDMMC2_CON0_INIT_STATE_MASK (0x1U << CRU_SDMMC2_CON0_INIT_STATE_SHIFT) /* 0x00000001 */
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#define CRU_SDMMC2_CON0_DRV_DEGREE_SHIFT (1U)
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#define CRU_SDMMC2_CON0_DRV_DEGREE_MASK (0x3U << CRU_SDMMC2_CON0_DRV_DEGREE_SHIFT) /* 0x00000006 */
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#define CRU_SDMMC2_CON0_DRV_DELAYNUM_SHIFT (3U)
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#define CRU_SDMMC2_CON0_DRV_DELAYNUM_MASK (0xFFU << CRU_SDMMC2_CON0_DRV_DELAYNUM_SHIFT) /* 0x000007F8 */
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#define CRU_SDMMC2_CON0_DRV_SEL_SHIFT (11U)
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#define CRU_SDMMC2_CON0_DRV_SEL_MASK (0x1U << CRU_SDMMC2_CON0_DRV_SEL_SHIFT) /* 0x00000800 */
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/* SDMMC2_CON1 */
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#define CRU_SDMMC2_CON1_OFFSET (0x594U)
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#define CRU_SDMMC2_CON1_SAMPLE_DEGREE_SHIFT (0U)
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#define CRU_SDMMC2_CON1_SAMPLE_DEGREE_MASK (0x3U << CRU_SDMMC2_CON1_SAMPLE_DEGREE_SHIFT) /* 0x00000003 */
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#define CRU_SDMMC2_CON1_SAMPLE_DELAYNUM_SHIFT (2U)
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#define CRU_SDMMC2_CON1_SAMPLE_DELAYNUM_MASK (0xFFU << CRU_SDMMC2_CON1_SAMPLE_DELAYNUM_SHIFT) /* 0x000003FC */
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#define CRU_SDMMC2_CON1_SAMPLE_SEL_SHIFT (10U)
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#define CRU_SDMMC2_CON1_SAMPLE_SEL_MASK (0x1U << CRU_SDMMC2_CON1_SAMPLE_SEL_SHIFT) /* 0x00000400 */
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/* EMMC_CON0 */
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#define CRU_EMMC_CON0_OFFSET (0x598U)
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#define CRU_EMMC_CON0_INIT_STATE_SHIFT (0U)
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#define CRU_EMMC_CON0_INIT_STATE_MASK (0x1U << CRU_EMMC_CON0_INIT_STATE_SHIFT) /* 0x00000001 */
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#define CRU_EMMC_CON0_DRV_DEGREE_SHIFT (1U)
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#define CRU_EMMC_CON0_DRV_DEGREE_MASK (0x3U << CRU_EMMC_CON0_DRV_DEGREE_SHIFT) /* 0x00000006 */
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#define CRU_EMMC_CON0_DRV_DELAYNUM_SHIFT (3U)
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#define CRU_EMMC_CON0_DRV_DELAYNUM_MASK (0xFFU << CRU_EMMC_CON0_DRV_DELAYNUM_SHIFT) /* 0x000007F8 */
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#define CRU_EMMC_CON0_DRV_SEL_SHIFT (11U)
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#define CRU_EMMC_CON0_DRV_SEL_MASK (0x1U << CRU_EMMC_CON0_DRV_SEL_SHIFT) /* 0x00000800 */
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/* EMMC_CON1 */
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#define CRU_EMMC_CON1_OFFSET (0x59CU)
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#define CRU_EMMC_CON1_SAMPLE_DEGREE_SHIFT (0U)
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#define CRU_EMMC_CON1_SAMPLE_DEGREE_MASK (0x3U << CRU_EMMC_CON1_SAMPLE_DEGREE_SHIFT) /* 0x00000003 */
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#define CRU_EMMC_CON1_SAMPLE_DELAYNUM_SHIFT (2U)
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#define CRU_EMMC_CON1_SAMPLE_DELAYNUM_MASK (0xFFU << CRU_EMMC_CON1_SAMPLE_DELAYNUM_SHIFT) /* 0x000003FC */
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#define CRU_EMMC_CON1_SAMPLE_SEL_SHIFT (10U)
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#define CRU_EMMC_CON1_SAMPLE_SEL_MASK (0x1U << CRU_EMMC_CON1_SAMPLE_SEL_SHIFT) /* 0x00000400 */
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/******************************************I2C*******************************************/
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/* CON */
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#define I2C_CON_OFFSET (0x0U)
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#define I2C_CON_I2C_EN_SHIFT (0U)
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#define I2C_CON_I2C_EN_MASK (0x1U << I2C_CON_I2C_EN_SHIFT) /* 0x00000001 */
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#define I2C_CON_I2C_MODE_SHIFT (1U)
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#define I2C_CON_I2C_MODE_MASK (0x3U << I2C_CON_I2C_MODE_SHIFT) /* 0x00000006 */
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#define I2C_CON_START_SHIFT (3U)
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#define I2C_CON_START_MASK (0x1U << I2C_CON_START_SHIFT) /* 0x00000008 */
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#define I2C_CON_STOP_SHIFT (4U)
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#define I2C_CON_STOP_MASK (0x1U << I2C_CON_STOP_SHIFT) /* 0x00000010 */
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#define I2C_CON_ACK_SHIFT (5U)
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#define I2C_CON_ACK_MASK (0x1U << I2C_CON_ACK_SHIFT) /* 0x00000020 */
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#define I2C_CON_ACT2NAK_SHIFT (6U)
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#define I2C_CON_ACT2NAK_MASK (0x1U << I2C_CON_ACT2NAK_SHIFT) /* 0x00000040 */
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#define I2C_CON_DATA_UPD_ST_SHIFT (8U)
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#define I2C_CON_DATA_UPD_ST_MASK (0x7U << I2C_CON_DATA_UPD_ST_SHIFT) /* 0x00000700 */
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#define I2C_CON_START_SETUP_SHIFT (12U)
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#define I2C_CON_START_SETUP_MASK (0x3U << I2C_CON_START_SETUP_SHIFT) /* 0x00003000 */
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#define I2C_CON_STOP_SETUP_SHIFT (14U)
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#define I2C_CON_STOP_SETUP_MASK (0x3U << I2C_CON_STOP_SETUP_SHIFT) /* 0x0000C000 */
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#define I2C_CON_VERSION_SHIFT (16U)
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#define I2C_CON_VERSION_MASK (0xFFFFU << I2C_CON_VERSION_SHIFT) /* 0xFFFF0000 */
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/* CLKDIV */
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#define I2C_CLKDIV_OFFSET (0x4U)
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#define I2C_CLKDIV_CLKDIVL_SHIFT (0U)
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#define I2C_CLKDIV_CLKDIVL_MASK (0xFFFFU << I2C_CLKDIV_CLKDIVL_SHIFT) /* 0x0000FFFF */
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#define I2C_CLKDIV_CLKDIVH_SHIFT (16U)
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#define I2C_CLKDIV_CLKDIVH_MASK (0xFFFFU << I2C_CLKDIV_CLKDIVH_SHIFT) /* 0xFFFF0000 */
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/* MRXADDR */
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#define I2C_MRXADDR_OFFSET (0x8U)
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#define I2C_MRXADDR_SADDR_SHIFT (0U)
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#define I2C_MRXADDR_SADDR_MASK (0xFFFFFFU << I2C_MRXADDR_SADDR_SHIFT) /* 0x00FFFFFF */
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#define I2C_MRXADDR_ADDLVLD_SHIFT (24U)
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#define I2C_MRXADDR_ADDLVLD_MASK (0x1U << I2C_MRXADDR_ADDLVLD_SHIFT) /* 0x01000000 */
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#define I2C_MRXADDR_ADDMVLD_SHIFT (25U)
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#define I2C_MRXADDR_ADDMVLD_MASK (0x1U << I2C_MRXADDR_ADDMVLD_SHIFT) /* 0x02000000 */
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#define I2C_MRXADDR_ADDHVLD_SHIFT (26U)
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#define I2C_MRXADDR_ADDHVLD_MASK (0x1U << I2C_MRXADDR_ADDHVLD_SHIFT) /* 0x04000000 */
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/* MRXRADDR */
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#define I2C_MRXRADDR_OFFSET (0xCU)
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#define I2C_MRXRADDR_SRADDR_SHIFT (0U)
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#define I2C_MRXRADDR_SRADDR_MASK (0xFFFFFFU << I2C_MRXRADDR_SRADDR_SHIFT) /* 0x00FFFFFF */
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#define I2C_MRXRADDR_SRADDLVLD_SHIFT (24U)
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#define I2C_MRXRADDR_SRADDLVLD_MASK (0x1U << I2C_MRXRADDR_SRADDLVLD_SHIFT) /* 0x01000000 */
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#define I2C_MRXRADDR_SRADDMVLD_SHIFT (25U)
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#define I2C_MRXRADDR_SRADDMVLD_MASK (0x1U << I2C_MRXRADDR_SRADDMVLD_SHIFT) /* 0x02000000 */
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#define I2C_MRXRADDR_SRADDHVLD_SHIFT (26U)
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#define I2C_MRXRADDR_SRADDHVLD_MASK (0x1U << I2C_MRXRADDR_SRADDHVLD_SHIFT) /* 0x04000000 */
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/* MTXCNT */
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#define I2C_MTXCNT_OFFSET (0x10U)
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#define I2C_MTXCNT_MTXCNT_SHIFT (0U)
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#define I2C_MTXCNT_MTXCNT_MASK (0x3FU << I2C_MTXCNT_MTXCNT_SHIFT) /* 0x0000003F */
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/* MRXCNT */
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#define I2C_MRXCNT_OFFSET (0x14U)
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#define I2C_MRXCNT_MRXCNT_SHIFT (0U)
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#define I2C_MRXCNT_MRXCNT_MASK (0x3FU << I2C_MRXCNT_MRXCNT_SHIFT) /* 0x0000003F */
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/* IEN */
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#define I2C_IEN_OFFSET (0x18U)
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#define I2C_IEN_BTFIEN_SHIFT (0U)
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#define I2C_IEN_BTFIEN_MASK (0x1U << I2C_IEN_BTFIEN_SHIFT) /* 0x00000001 */
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#define I2C_IEN_BRFIEN_SHIFT (1U)
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#define I2C_IEN_BRFIEN_MASK (0x1U << I2C_IEN_BRFIEN_SHIFT) /* 0x00000002 */
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#define I2C_IEN_MBTFIEN_SHIFT (2U)
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#define I2C_IEN_MBTFIEN_MASK (0x1U << I2C_IEN_MBTFIEN_SHIFT) /* 0x00000004 */
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#define I2C_IEN_MBRFIEN_SHIFT (3U)
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#define I2C_IEN_MBRFIEN_MASK (0x1U << I2C_IEN_MBRFIEN_SHIFT) /* 0x00000008 */
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#define I2C_IEN_STARTIEN_SHIFT (4U)
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#define I2C_IEN_STARTIEN_MASK (0x1U << I2C_IEN_STARTIEN_SHIFT) /* 0x00000010 */
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#define I2C_IEN_STOPIEN_SHIFT (5U)
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#define I2C_IEN_STOPIEN_MASK (0x1U << I2C_IEN_STOPIEN_SHIFT) /* 0x00000020 */
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#define I2C_IEN_NAKRCVIEN_SHIFT (6U)
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#define I2C_IEN_NAKRCVIEN_MASK (0x1U << I2C_IEN_NAKRCVIEN_SHIFT) /* 0x00000040 */
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#define I2C_IEN_SLAVEHDSCLEN_SHIFT (7U)
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#define I2C_IEN_SLAVEHDSCLEN_MASK (0x1U << I2C_IEN_SLAVEHDSCLEN_SHIFT) /* 0x00000080 */
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/* IPD */
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#define I2C_IPD_OFFSET (0x1CU)
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#define I2C_IPD_BTFIPD_SHIFT (0U)
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#define I2C_IPD_BTFIPD_MASK (0x1U << I2C_IPD_BTFIPD_SHIFT) /* 0x00000001 */
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#define I2C_IPD_BRFIPD_SHIFT (1U)
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#define I2C_IPD_BRFIPD_MASK (0x1U << I2C_IPD_BRFIPD_SHIFT) /* 0x00000002 */
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#define I2C_IPD_MBTFIPD_SHIFT (2U)
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#define I2C_IPD_MBTFIPD_MASK (0x1U << I2C_IPD_MBTFIPD_SHIFT) /* 0x00000004 */
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#define I2C_IPD_MBRFIPD_SHIFT (3U)
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#define I2C_IPD_MBRFIPD_MASK (0x1U << I2C_IPD_MBRFIPD_SHIFT) /* 0x00000008 */
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#define I2C_IPD_STARTIPD_SHIFT (4U)
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#define I2C_IPD_STARTIPD_MASK (0x1U << I2C_IPD_STARTIPD_SHIFT) /* 0x00000010 */
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#define I2C_IPD_STOPIPD_SHIFT (5U)
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#define I2C_IPD_STOPIPD_MASK (0x1U << I2C_IPD_STOPIPD_SHIFT) /* 0x00000020 */
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#define I2C_IPD_NAKRCVIPD_SHIFT (6U)
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#define I2C_IPD_NAKRCVIPD_MASK (0x1U << I2C_IPD_NAKRCVIPD_SHIFT) /* 0x00000040 */
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#define I2C_IPD_SLAVEHDSCLIPD_SHIFT (7U)
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#define I2C_IPD_SLAVEHDSCLIPD_MASK (0x1U << I2C_IPD_SLAVEHDSCLIPD_SHIFT) /* 0x00000080 */
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/* FCNT */
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#define I2C_FCNT_OFFSET (0x20U)
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#define I2C_FCNT (0x0U)
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#define I2C_FCNT_FCNT_SHIFT (0U)
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#define I2C_FCNT_FCNT_MASK (0x3FU << I2C_FCNT_FCNT_SHIFT) /* 0x0000003F */
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/* SCL_OE_DB */
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#define I2C_SCL_OE_DB_OFFSET (0x24U)
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#define I2C_SCL_OE_DB_SCL_OE_DB_SHIFT (0U)
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#define I2C_SCL_OE_DB_SCL_OE_DB_MASK (0xFFU << I2C_SCL_OE_DB_SCL_OE_DB_SHIFT) /* 0x000000FF */
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/* TXDATA0 */
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#define I2C_TXDATA0_OFFSET (0x100U)
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#define I2C_TXDATA0_TXDATA0_SHIFT (0U)
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#define I2C_TXDATA0_TXDATA0_MASK (0xFFFFFFFFU << I2C_TXDATA0_TXDATA0_SHIFT) /* 0xFFFFFFFF */
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/* TXDATA1 */
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#define I2C_TXDATA1_OFFSET (0x104U)
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#define I2C_TXDATA1_TXDATA1_SHIFT (0U)
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#define I2C_TXDATA1_TXDATA1_MASK (0xFFFFFFFFU << I2C_TXDATA1_TXDATA1_SHIFT) /* 0xFFFFFFFF */
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/* TXDATA2 */
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#define I2C_TXDATA2_OFFSET (0x108U)
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#define I2C_TXDATA2_TXDATA2_SHIFT (0U)
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#define I2C_TXDATA2_TXDATA2_MASK (0xFFFFFFFFU << I2C_TXDATA2_TXDATA2_SHIFT) /* 0xFFFFFFFF */
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/* TXDATA3 */
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#define I2C_TXDATA3_OFFSET (0x10CU)
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#define I2C_TXDATA3_TXDATA3_SHIFT (0U)
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#define I2C_TXDATA3_TXDATA3_MASK (0xFFFFFFFFU << I2C_TXDATA3_TXDATA3_SHIFT) /* 0xFFFFFFFF */
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/* TXDATA4 */
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#define I2C_TXDATA4_OFFSET (0x110U)
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#define I2C_TXDATA4_TXDATA4_SHIFT (0U)
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#define I2C_TXDATA4_TXDATA4_MASK (0xFFFFFFFFU << I2C_TXDATA4_TXDATA4_SHIFT) /* 0xFFFFFFFF */
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/* TXDATA5 */
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#define I2C_TXDATA5_OFFSET (0x114U)
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#define I2C_TXDATA5_TXDATA5_SHIFT (0U)
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#define I2C_TXDATA5_TXDATA5_MASK (0xFFFFFFFFU << I2C_TXDATA5_TXDATA5_SHIFT) /* 0xFFFFFFFF */
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/* TXDATA6 */
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#define I2C_TXDATA6_OFFSET (0x118U)
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#define I2C_TXDATA6_TXDATA6_SHIFT (0U)
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#define I2C_TXDATA6_TXDATA6_MASK (0xFFFFFFFFU << I2C_TXDATA6_TXDATA6_SHIFT) /* 0xFFFFFFFF */
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/* TXDATA7 */
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#define I2C_TXDATA7_OFFSET (0x11CU)
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#define I2C_TXDATA7_TXDATA7_SHIFT (0U)
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#define I2C_TXDATA7_TXDATA7_MASK (0xFFFFFFFFU << I2C_TXDATA7_TXDATA7_SHIFT) /* 0xFFFFFFFF */
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/* RXDATA0 */
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#define I2C_RXDATA0_OFFSET (0x200U)
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#define I2C_RXDATA0 (0x0U)
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#define I2C_RXDATA0_RXDATA0_SHIFT (0U)
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#define I2C_RXDATA0_RXDATA0_MASK (0xFFFFFFFFU << I2C_RXDATA0_RXDATA0_SHIFT) /* 0xFFFFFFFF */
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/* RXDATA1 */
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#define I2C_RXDATA1_OFFSET (0x204U)
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#define I2C_RXDATA1 (0x0U)
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#define I2C_RXDATA1_RXDATA1_SHIFT (0U)
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#define I2C_RXDATA1_RXDATA1_MASK (0xFFFFFFFFU << I2C_RXDATA1_RXDATA1_SHIFT) /* 0xFFFFFFFF */
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/* RXDATA2 */
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#define I2C_RXDATA2_OFFSET (0x208U)
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#define I2C_RXDATA2 (0x0U)
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#define I2C_RXDATA2_RXDATA2_SHIFT (0U)
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#define I2C_RXDATA2_RXDATA2_MASK (0xFFFFFFFFU << I2C_RXDATA2_RXDATA2_SHIFT) /* 0xFFFFFFFF */
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/* RXDATA3 */
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#define I2C_RXDATA3_OFFSET (0x20CU)
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#define I2C_RXDATA3 (0x0U)
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#define I2C_RXDATA3_RXDATA3_SHIFT (0U)
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#define I2C_RXDATA3_RXDATA3_MASK (0xFFFFFFFFU << I2C_RXDATA3_RXDATA3_SHIFT) /* 0xFFFFFFFF */
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/* RXDATA4 */
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#define I2C_RXDATA4_OFFSET (0x210U)
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#define I2C_RXDATA4 (0x0U)
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#define I2C_RXDATA4_RXDATA4_SHIFT (0U)
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#define I2C_RXDATA4_RXDATA4_MASK (0xFFFFFFFFU << I2C_RXDATA4_RXDATA4_SHIFT) /* 0xFFFFFFFF */
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/* RXDATA5 */
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#define I2C_RXDATA5_OFFSET (0x214U)
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#define I2C_RXDATA5 (0x0U)
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#define I2C_RXDATA5_RXDATA5_SHIFT (0U)
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#define I2C_RXDATA5_RXDATA5_MASK (0xFFFFFFFFU << I2C_RXDATA5_RXDATA5_SHIFT) /* 0xFFFFFFFF */
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/* RXDATA6 */
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#define I2C_RXDATA6_OFFSET (0x218U)
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#define I2C_RXDATA6 (0x0U)
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#define I2C_RXDATA6_RXDATA6_SHIFT (0U)
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#define I2C_RXDATA6_RXDATA6_MASK (0xFFFFFFFFU << I2C_RXDATA6_RXDATA6_SHIFT) /* 0xFFFFFFFF */
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/* RXDATA7 */
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#define I2C_RXDATA7_OFFSET (0x21CU)
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#define I2C_RXDATA7 (0x0U)
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#define I2C_RXDATA7_RXDATA7_SHIFT (0U)
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#define I2C_RXDATA7_RXDATA7_MASK (0xFFFFFFFFU << I2C_RXDATA7_RXDATA7_SHIFT) /* 0xFFFFFFFF */
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/* ST */
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#define I2C_ST_OFFSET (0x220U)
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#define I2C_ST (0x0U)
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#define I2C_ST_SDA_ST_SHIFT (0U)
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#define I2C_ST_SDA_ST_MASK (0x1U << I2C_ST_SDA_ST_SHIFT) /* 0x00000001 */
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#define I2C_ST_SCL_ST_SHIFT (1U)
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#define I2C_ST_SCL_ST_MASK (0x1U << I2C_ST_SCL_ST_SHIFT) /* 0x00000002 */
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/* DBGCTRL */
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#define I2C_DBGCTRL_OFFSET (0x224U)
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#define I2C_DBGCTRL_FLT_F_SHIFT (0U)
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#define I2C_DBGCTRL_FLT_F_MASK (0xFU << I2C_DBGCTRL_FLT_F_SHIFT) /* 0x0000000F */
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#define I2C_DBGCTRL_FLT_R_SHIFT (4U)
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#define I2C_DBGCTRL_FLT_R_MASK (0xFU << I2C_DBGCTRL_FLT_R_SHIFT) /* 0x000000F0 */
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#define I2C_DBGCTRL_SLV_HOLD_SCL_TH_SHIFT (8U)
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#define I2C_DBGCTRL_SLV_HOLD_SCL_TH_MASK (0xFU << I2C_DBGCTRL_SLV_HOLD_SCL_TH_SHIFT) /* 0x00000F00 */
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#define I2C_DBGCTRL_FLT_EN_SHIFT (12U)
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#define I2C_DBGCTRL_FLT_EN_MASK (0x1U << I2C_DBGCTRL_FLT_EN_SHIFT) /* 0x00001000 */
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#define I2C_DBGCTRL_NAK_RELEASE_SCL_SHIFT (13U)
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#define I2C_DBGCTRL_NAK_RELEASE_SCL_MASK (0x1U << I2C_DBGCTRL_NAK_RELEASE_SCL_SHIFT) /* 0x00002000 */
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#define I2C_DBGCTRL_H0_CHECK_SCL_SHIFT (14U)
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#define I2C_DBGCTRL_H0_CHECK_SCL_MASK (0x1U << I2C_DBGCTRL_H0_CHECK_SCL_SHIFT) /* 0x00004000 */
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/******************************************UART******************************************/
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/* RBR */
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#define UART_RBR_OFFSET (0x0U)
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#define UART_RBR (0x0U)
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#define UART_RBR_DATA_INPUT_SHIFT (0U)
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#define UART_RBR_DATA_INPUT_MASK (0xFFU << UART_RBR_DATA_INPUT_SHIFT) /* 0x000000FF */
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/* DLL */
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#define UART_DLL_OFFSET (0x0U)
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#define UART_DLL_BAUD_RATE_DIVISOR_L_SHIFT (0U)
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#define UART_DLL_BAUD_RATE_DIVISOR_L_MASK (0xFFU << UART_DLL_BAUD_RATE_DIVISOR_L_SHIFT) /* 0x000000FF */
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/* THR */
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#define UART_THR_OFFSET (0x0U)
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#define UART_THR_DATA_OUTPUT_SHIFT (0U)
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#define UART_THR_DATA_OUTPUT_MASK (0xFFU << UART_THR_DATA_OUTPUT_SHIFT) /* 0x000000FF */
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/* DLH */
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#define UART_DLH_OFFSET (0x4U)
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#define UART_DLH_BAUD_RATE_DIVISOR_H_SHIFT (0U)
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#define UART_DLH_BAUD_RATE_DIVISOR_H_MASK (0xFFU << UART_DLH_BAUD_RATE_DIVISOR_H_SHIFT) /* 0x000000FF */
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/* IER */
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#define UART_IER_OFFSET (0x4U)
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#define UART_IER_RECEIVE_DATA_AVAILABLE_INT_EN_SHIFT (0U)
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#define UART_IER_RECEIVE_DATA_AVAILABLE_INT_EN_MASK (0x1U << UART_IER_RECEIVE_DATA_AVAILABLE_INT_EN_SHIFT) /* 0x00000001 */
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#define UART_IER_TRANS_HOLD_EMPTY_INT_EN_SHIFT (1U)
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#define UART_IER_TRANS_HOLD_EMPTY_INT_EN_MASK (0x1U << UART_IER_TRANS_HOLD_EMPTY_INT_EN_SHIFT) /* 0x00000002 */
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#define UART_IER_RECEIVE_LINE_STATUS_INT_EN_SHIFT (2U)
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#define UART_IER_RECEIVE_LINE_STATUS_INT_EN_MASK (0x1U << UART_IER_RECEIVE_LINE_STATUS_INT_EN_SHIFT) /* 0x00000004 */
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#define UART_IER_MODEM_STATUS_INT_EN_SHIFT (3U)
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#define UART_IER_MODEM_STATUS_INT_EN_MASK (0x1U << UART_IER_MODEM_STATUS_INT_EN_SHIFT) /* 0x00000008 */
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#define UART_IER_PROG_THRE_INT_EN_SHIFT (7U)
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#define UART_IER_PROG_THRE_INT_EN_MASK (0x1U << UART_IER_PROG_THRE_INT_EN_SHIFT) /* 0x00000080 */
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/* FCR */
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#define UART_FCR_OFFSET (0x8U)
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#define UART_FCR_FIFO_EN_SHIFT (0U)
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#define UART_FCR_FIFO_EN_MASK (0x1U << UART_FCR_FIFO_EN_SHIFT) /* 0x00000001 */
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#define UART_FCR_RCVR_FIFO_RESET_SHIFT (1U)
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#define UART_FCR_RCVR_FIFO_RESET_MASK (0x1U << UART_FCR_RCVR_FIFO_RESET_SHIFT) /* 0x00000002 */
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#define UART_FCR_XMIT_FIFO_RESET_SHIFT (2U)
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#define UART_FCR_XMIT_FIFO_RESET_MASK (0x1U << UART_FCR_XMIT_FIFO_RESET_SHIFT) /* 0x00000004 */
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#define UART_FCR_DMA_MODE_SHIFT (3U)
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#define UART_FCR_DMA_MODE_MASK (0x1U << UART_FCR_DMA_MODE_SHIFT) /* 0x00000008 */
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#define UART_FCR_TX_EMPTY_TRIGGER_SHIFT (4U)
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#define UART_FCR_TX_EMPTY_TRIGGER_MASK (0x3U << UART_FCR_TX_EMPTY_TRIGGER_SHIFT) /* 0x00000030 */
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#define UART_FCR_RCVR_TRIGGER_SHIFT (6U)
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#define UART_FCR_RCVR_TRIGGER_MASK (0x3U << UART_FCR_RCVR_TRIGGER_SHIFT) /* 0x000000C0 */
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/* IIR */
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#define UART_IIR_OFFSET (0x8U)
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#define UART_IIR (0x1U)
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#define UART_IIR_INT_ID_SHIFT (0U)
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#define UART_IIR_INT_ID_MASK (0xFU << UART_IIR_INT_ID_SHIFT) /* 0x0000000F */
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#define UART_IIR_FIFOS_EN_SHIFT (6U)
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#define UART_IIR_FIFOS_EN_MASK (0x3U << UART_IIR_FIFOS_EN_SHIFT) /* 0x000000C0 */
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/* LCR */
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#define UART_LCR_OFFSET (0xCU)
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#define UART_LCR_DATA_LENGTH_SEL_SHIFT (0U)
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#define UART_LCR_DATA_LENGTH_SEL_MASK (0x3U << UART_LCR_DATA_LENGTH_SEL_SHIFT) /* 0x00000003 */
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#define UART_LCR_STOP_BITS_NUM_SHIFT (2U)
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#define UART_LCR_STOP_BITS_NUM_MASK (0x1U << UART_LCR_STOP_BITS_NUM_SHIFT) /* 0x00000004 */
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#define UART_LCR_PARITY_EN_SHIFT (3U)
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#define UART_LCR_PARITY_EN_MASK (0x1U << UART_LCR_PARITY_EN_SHIFT) /* 0x00000008 */
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#define UART_LCR_EVEN_PARITY_SEL_SHIFT (4U)
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#define UART_LCR_EVEN_PARITY_SEL_MASK (0x1U << UART_LCR_EVEN_PARITY_SEL_SHIFT) /* 0x00000010 */
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#define UART_LCR_BREAK_CTRL_SHIFT (6U)
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#define UART_LCR_BREAK_CTRL_MASK (0x1U << UART_LCR_BREAK_CTRL_SHIFT) /* 0x00000040 */
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#define UART_LCR_DIV_LAT_ACCESS_SHIFT (7U)
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#define UART_LCR_DIV_LAT_ACCESS_MASK (0x1U << UART_LCR_DIV_LAT_ACCESS_SHIFT) /* 0x00000080 */
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/* MCR */
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#define UART_MCR_OFFSET (0x10U)
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#define UART_MCR_DATA_TERMINAL_READY_SHIFT (0U)
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#define UART_MCR_DATA_TERMINAL_READY_MASK (0x1U << UART_MCR_DATA_TERMINAL_READY_SHIFT) /* 0x00000001 */
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#define UART_MCR_REQ_TO_SEND_SHIFT (1U)
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#define UART_MCR_REQ_TO_SEND_MASK (0x1U << UART_MCR_REQ_TO_SEND_SHIFT) /* 0x00000002 */
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#define UART_MCR_OUT1_SHIFT (2U)
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#define UART_MCR_OUT1_MASK (0x1U << UART_MCR_OUT1_SHIFT) /* 0x00000004 */
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#define UART_MCR_OUT2_SHIFT (3U)
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#define UART_MCR_OUT2_MASK (0x1U << UART_MCR_OUT2_SHIFT) /* 0x00000008 */
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#define UART_MCR_LOOPBACK_SHIFT (4U)
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#define UART_MCR_LOOPBACK_MASK (0x1U << UART_MCR_LOOPBACK_SHIFT) /* 0x00000010 */
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#define UART_MCR_AUTO_FLOW_CTRL_EN_SHIFT (5U)
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#define UART_MCR_AUTO_FLOW_CTRL_EN_MASK (0x1U << UART_MCR_AUTO_FLOW_CTRL_EN_SHIFT) /* 0x00000020 */
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#define UART_MCR_SIR_MODE_EN_SHIFT (6U)
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#define UART_MCR_SIR_MODE_EN_MASK (0x1U << UART_MCR_SIR_MODE_EN_SHIFT) /* 0x00000040 */
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/* LSR */
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#define UART_LSR_OFFSET (0x14U)
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#define UART_LSR (0x60U)
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#define UART_LSR_DATA_READY_SHIFT (0U)
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#define UART_LSR_DATA_READY_MASK (0x1U << UART_LSR_DATA_READY_SHIFT) /* 0x00000001 */
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#define UART_LSR_OVERRUN_ERROR_SHIFT (1U)
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#define UART_LSR_OVERRUN_ERROR_MASK (0x1U << UART_LSR_OVERRUN_ERROR_SHIFT) /* 0x00000002 */
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#define UART_LSR_PARITY_EROR_SHIFT (2U)
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#define UART_LSR_PARITY_EROR_MASK (0x1U << UART_LSR_PARITY_EROR_SHIFT) /* 0x00000004 */
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#define UART_LSR_FRAMING_ERROR_SHIFT (3U)
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#define UART_LSR_FRAMING_ERROR_MASK (0x1U << UART_LSR_FRAMING_ERROR_SHIFT) /* 0x00000008 */
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#define UART_LSR_BREAK_INT_SHIFT (4U)
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#define UART_LSR_BREAK_INT_MASK (0x1U << UART_LSR_BREAK_INT_SHIFT) /* 0x00000010 */
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#define UART_LSR_TRANS_HOLD_REG_EMPTY_SHIFT (5U)
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#define UART_LSR_TRANS_HOLD_REG_EMPTY_MASK (0x1U << UART_LSR_TRANS_HOLD_REG_EMPTY_SHIFT) /* 0x00000020 */
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#define UART_LSR_TRANS_EMPTY_SHIFT (6U)
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#define UART_LSR_TRANS_EMPTY_MASK (0x1U << UART_LSR_TRANS_EMPTY_SHIFT) /* 0x00000040 */
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#define UART_LSR_RECEIVER_FIFO_ERROR_SHIFT (7U)
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#define UART_LSR_RECEIVER_FIFO_ERROR_MASK (0x1U << UART_LSR_RECEIVER_FIFO_ERROR_SHIFT) /* 0x00000080 */
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/* MSR */
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#define UART_MSR_OFFSET (0x18U)
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#define UART_MSR (0x0U)
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#define UART_MSR_DELTA_CLEAR_TO_SEND_SHIFT (0U)
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#define UART_MSR_DELTA_CLEAR_TO_SEND_MASK (0x1U << UART_MSR_DELTA_CLEAR_TO_SEND_SHIFT) /* 0x00000001 */
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#define UART_MSR_DELTA_DATA_SET_READY_SHIFT (1U)
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#define UART_MSR_DELTA_DATA_SET_READY_MASK (0x1U << UART_MSR_DELTA_DATA_SET_READY_SHIFT) /* 0x00000002 */
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#define UART_MSR_TRAILING_EDGE_RING_INDICATOR_SHIFT (2U)
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#define UART_MSR_TRAILING_EDGE_RING_INDICATOR_MASK (0x1U << UART_MSR_TRAILING_EDGE_RING_INDICATOR_SHIFT) /* 0x00000004 */
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#define UART_MSR_DELTA_DATA_CARRIER_DETECT_SHIFT (3U)
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#define UART_MSR_DELTA_DATA_CARRIER_DETECT_MASK (0x1U << UART_MSR_DELTA_DATA_CARRIER_DETECT_SHIFT) /* 0x00000008 */
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#define UART_MSR_CLEAR_TO_SEND_SHIFT (4U)
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#define UART_MSR_CLEAR_TO_SEND_MASK (0x1U << UART_MSR_CLEAR_TO_SEND_SHIFT) /* 0x00000010 */
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#define UART_MSR_DATA_SET_READY_SHIFT (5U)
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#define UART_MSR_DATA_SET_READY_MASK (0x1U << UART_MSR_DATA_SET_READY_SHIFT) /* 0x00000020 */
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#define UART_MSR_RING_INDICATOR_SHIFT (6U)
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#define UART_MSR_RING_INDICATOR_MASK (0x1U << UART_MSR_RING_INDICATOR_SHIFT) /* 0x00000040 */
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#define UART_MSR_DATA_CARRIOR_DETECT_SHIFT (7U)
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#define UART_MSR_DATA_CARRIOR_DETECT_MASK (0x1U << UART_MSR_DATA_CARRIOR_DETECT_SHIFT) /* 0x00000080 */
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/* SCR */
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#define UART_SCR_OFFSET (0x1CU)
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#define UART_SCR_TEMP_STORE_SPACE_SHIFT (0U)
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#define UART_SCR_TEMP_STORE_SPACE_MASK (0xFFU << UART_SCR_TEMP_STORE_SPACE_SHIFT) /* 0x000000FF */
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/* SRBR */
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#define UART_SRBR_OFFSET (0x30U)
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#define UART_SRBR (0x0U)
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#define UART_SRBR_SHADOW_RBR_SHIFT (0U)
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#define UART_SRBR_SHADOW_RBR_MASK (0xFFU << UART_SRBR_SHADOW_RBR_SHIFT) /* 0x000000FF */
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/* STHR */
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#define UART_STHR_OFFSET (0x30U)
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#define UART_STHR_SHADOW_THR_SHIFT (0U)
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#define UART_STHR_SHADOW_THR_MASK (0xFFU << UART_STHR_SHADOW_THR_SHIFT) /* 0x000000FF */
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/* FAR */
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#define UART_FAR_OFFSET (0x70U)
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#define UART_FAR_FIFO_ACCESS_TEST_EN_SHIFT (0U)
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#define UART_FAR_FIFO_ACCESS_TEST_EN_MASK (0x1U << UART_FAR_FIFO_ACCESS_TEST_EN_SHIFT) /* 0x00000001 */
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/* TFR */
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#define UART_TFR_OFFSET (0x74U)
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#define UART_TFR (0x0U)
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#define UART_TFR_TRANS_FIFO_READ_SHIFT (0U)
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#define UART_TFR_TRANS_FIFO_READ_MASK (0xFFU << UART_TFR_TRANS_FIFO_READ_SHIFT) /* 0x000000FF */
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/* RFW */
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#define UART_RFW_OFFSET (0x78U)
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#define UART_RFW_RECEIVE_FIFO_WRITE_SHIFT (0U)
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#define UART_RFW_RECEIVE_FIFO_WRITE_MASK (0xFFU << UART_RFW_RECEIVE_FIFO_WRITE_SHIFT) /* 0x000000FF */
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#define UART_RFW_RECEIVE_FIFO_PARITY_ERROR_SHIFT (8U)
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#define UART_RFW_RECEIVE_FIFO_PARITY_ERROR_MASK (0x1U << UART_RFW_RECEIVE_FIFO_PARITY_ERROR_SHIFT) /* 0x00000100 */
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#define UART_RFW_RECEIVE_FIFO_FRAMING_ERROR_SHIFT (9U)
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#define UART_RFW_RECEIVE_FIFO_FRAMING_ERROR_MASK (0x1U << UART_RFW_RECEIVE_FIFO_FRAMING_ERROR_SHIFT) /* 0x00000200 */
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/* USR */
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#define UART_USR_OFFSET (0x7CU)
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#define UART_USR (0x6U)
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#define UART_USR_UART_BUSY_SHIFT (0U)
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#define UART_USR_UART_BUSY_MASK (0x1U << UART_USR_UART_BUSY_SHIFT) /* 0x00000001 */
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#define UART_USR_TRANS_FIFO_NOT_FULL_SHIFT (1U)
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#define UART_USR_TRANS_FIFO_NOT_FULL_MASK (0x1U << UART_USR_TRANS_FIFO_NOT_FULL_SHIFT) /* 0x00000002 */
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#define UART_USR_TRASN_FIFO_EMPTY_SHIFT (2U)
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#define UART_USR_TRASN_FIFO_EMPTY_MASK (0x1U << UART_USR_TRASN_FIFO_EMPTY_SHIFT) /* 0x00000004 */
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#define UART_USR_RECEIVE_FIFO_NOT_EMPTY_SHIFT (3U)
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#define UART_USR_RECEIVE_FIFO_NOT_EMPTY_MASK (0x1U << UART_USR_RECEIVE_FIFO_NOT_EMPTY_SHIFT) /* 0x00000008 */
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#define UART_USR_RECEIVE_FIFO_FULL_SHIFT (4U)
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#define UART_USR_RECEIVE_FIFO_FULL_MASK (0x1U << UART_USR_RECEIVE_FIFO_FULL_SHIFT) /* 0x00000010 */
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/* TFL */
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#define UART_TFL_OFFSET (0x80U)
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#define UART_TFL (0x0U)
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#define UART_TFL_TRANS_FIFO_LEVEL_SHIFT (0U)
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#define UART_TFL_TRANS_FIFO_LEVEL_MASK (0x3FU << UART_TFL_TRANS_FIFO_LEVEL_SHIFT) /* 0x0000003F */
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/* RFL */
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#define UART_RFL_OFFSET (0x84U)
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#define UART_RFL (0x0U)
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#define UART_RFL_RECEIVE_FIFO_LEVEL_SHIFT (0U)
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#define UART_RFL_RECEIVE_FIFO_LEVEL_MASK (0x3FU << UART_RFL_RECEIVE_FIFO_LEVEL_SHIFT) /* 0x0000003F */
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/* SRR */
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#define UART_SRR_OFFSET (0x88U)
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#define UART_SRR_UART_RESET_SHIFT (0U)
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#define UART_SRR_UART_RESET_MASK (0x1U << UART_SRR_UART_RESET_SHIFT) /* 0x00000001 */
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#define UART_SRR_RCVR_FIFO_RESET_SHIFT (1U)
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#define UART_SRR_RCVR_FIFO_RESET_MASK (0x1U << UART_SRR_RCVR_FIFO_RESET_SHIFT) /* 0x00000002 */
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#define UART_SRR_XMIT_FIFO_RESET_SHIFT (2U)
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#define UART_SRR_XMIT_FIFO_RESET_MASK (0x1U << UART_SRR_XMIT_FIFO_RESET_SHIFT) /* 0x00000004 */
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/* SRTS */
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#define UART_SRTS_OFFSET (0x8CU)
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#define UART_SRTS_SHADOW_REQ_TO_SEND_SHIFT (0U)
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#define UART_SRTS_SHADOW_REQ_TO_SEND_MASK (0x1U << UART_SRTS_SHADOW_REQ_TO_SEND_SHIFT) /* 0x00000001 */
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/* SBCR */
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#define UART_SBCR_OFFSET (0x90U)
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#define UART_SBCR_SHADOW_BREAK_CTRL_SHIFT (0U)
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#define UART_SBCR_SHADOW_BREAK_CTRL_MASK (0x1U << UART_SBCR_SHADOW_BREAK_CTRL_SHIFT) /* 0x00000001 */
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/* SDMAM */
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#define UART_SDMAM_OFFSET (0x94U)
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#define UART_SDMAM_SHADOW_DMA_MODE_SHIFT (0U)
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#define UART_SDMAM_SHADOW_DMA_MODE_MASK (0x1U << UART_SDMAM_SHADOW_DMA_MODE_SHIFT) /* 0x00000001 */
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/* SFE */
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#define UART_SFE_OFFSET (0x98U)
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#define UART_SFE_SHADOW_FIFO_EN_SHIFT (0U)
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#define UART_SFE_SHADOW_FIFO_EN_MASK (0x1U << UART_SFE_SHADOW_FIFO_EN_SHIFT) /* 0x00000001 */
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/* SRT */
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#define UART_SRT_OFFSET (0x9CU)
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#define UART_SRT_SHADOW_RCVR_TRIGGER_SHIFT (0U)
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#define UART_SRT_SHADOW_RCVR_TRIGGER_MASK (0x3U << UART_SRT_SHADOW_RCVR_TRIGGER_SHIFT) /* 0x00000003 */
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/* STET */
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#define UART_STET_OFFSET (0xA0U)
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#define UART_STET_SHADOW_TX_EMPTY_TRIGGER_SHIFT (0U)
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#define UART_STET_SHADOW_TX_EMPTY_TRIGGER_MASK (0x3U << UART_STET_SHADOW_TX_EMPTY_TRIGGER_SHIFT) /* 0x00000003 */
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/* HTX */
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#define UART_HTX_OFFSET (0xA4U)
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#define UART_HTX_HALT_TX_EN_SHIFT (0U)
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#define UART_HTX_HALT_TX_EN_MASK (0x1U << UART_HTX_HALT_TX_EN_SHIFT) /* 0x00000001 */
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/* DMASA */
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#define UART_DMASA_OFFSET (0xA8U)
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#define UART_DMASA_DMA_SOFTWARE_ACK_SHIFT (0U)
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#define UART_DMASA_DMA_SOFTWARE_ACK_MASK (0x1U << UART_DMASA_DMA_SOFTWARE_ACK_SHIFT) /* 0x00000001 */
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/* CPR */
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#define UART_CPR_OFFSET (0xF4U)
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#define UART_CPR (0x0U)
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#define UART_CPR_APB_DATA_WIDTH_SHIFT (0U)
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#define UART_CPR_APB_DATA_WIDTH_MASK (0x3U << UART_CPR_APB_DATA_WIDTH_SHIFT) /* 0x00000003 */
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#define UART_CPR_AFCE_MODE_SHIFT (4U)
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#define UART_CPR_AFCE_MODE_MASK (0x1U << UART_CPR_AFCE_MODE_SHIFT) /* 0x00000010 */
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#define UART_CPR_THRE_MODE_SHIFT (5U)
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#define UART_CPR_THRE_MODE_MASK (0x1U << UART_CPR_THRE_MODE_SHIFT) /* 0x00000020 */
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#define UART_CPR_SIR_MODE_SHIFT (6U)
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#define UART_CPR_SIR_MODE_MASK (0x1U << UART_CPR_SIR_MODE_SHIFT) /* 0x00000040 */
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#define UART_CPR_SIR_LP_MODE_SHIFT (7U)
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#define UART_CPR_SIR_LP_MODE_MASK (0x1U << UART_CPR_SIR_LP_MODE_SHIFT) /* 0x00000080 */
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#define UART_CPR_NEW_FEAT_SHIFT (8U)
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#define UART_CPR_NEW_FEAT_MASK (0x1U << UART_CPR_NEW_FEAT_SHIFT) /* 0x00000100 */
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#define UART_CPR_FIFO_ACCESS_SHIFT (9U)
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#define UART_CPR_FIFO_ACCESS_MASK (0x1U << UART_CPR_FIFO_ACCESS_SHIFT) /* 0x00000200 */
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#define UART_CPR_FIFO_STAT_SHIFT (10U)
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#define UART_CPR_FIFO_STAT_MASK (0x1U << UART_CPR_FIFO_STAT_SHIFT) /* 0x00000400 */
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#define UART_CPR_SHADOW_SHIFT (11U)
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#define UART_CPR_SHADOW_MASK (0x1U << UART_CPR_SHADOW_SHIFT) /* 0x00000800 */
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#define UART_CPR_UART_ADD_ENCODED_PARAMS_SHIFT (12U)
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#define UART_CPR_UART_ADD_ENCODED_PARAMS_MASK (0x1U << UART_CPR_UART_ADD_ENCODED_PARAMS_SHIFT) /* 0x00001000 */
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#define UART_CPR_DMA_EXTRA_SHIFT (13U)
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#define UART_CPR_DMA_EXTRA_MASK (0x1U << UART_CPR_DMA_EXTRA_SHIFT) /* 0x00002000 */
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#define UART_CPR_FIFO_MODE_SHIFT (16U)
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#define UART_CPR_FIFO_MODE_MASK (0xFFU << UART_CPR_FIFO_MODE_SHIFT) /* 0x00FF0000 */
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/* UCV */
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#define UART_UCV_OFFSET (0xF8U)
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#define UART_UCV (0x330372AU)
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#define UART_UCV_VER_SHIFT (0U)
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#define UART_UCV_VER_MASK (0xFFFFFFFFU << UART_UCV_VER_SHIFT) /* 0xFFFFFFFF */
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/* CTR */
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#define UART_CTR_OFFSET (0xFCU)
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#define UART_CTR (0x44570110U)
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#define UART_CTR_PERIPHERAL_ID_SHIFT (0U)
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#define UART_CTR_PERIPHERAL_ID_MASK (0xFFFFFFFFU << UART_CTR_PERIPHERAL_ID_SHIFT) /* 0xFFFFFFFF */
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/******************************************GPIO******************************************/
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/* SWPORT_DR_L */
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#define GPIO_SWPORT_DR_L_OFFSET (0x0U)
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#define GPIO_SWPORT_DR_L_SWPORT_DR_LOW_SHIFT (0U)
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#define GPIO_SWPORT_DR_L_SWPORT_DR_LOW_MASK (0xFFFFU << GPIO_SWPORT_DR_L_SWPORT_DR_LOW_SHIFT) /* 0x0000FFFF */
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/* SWPORT_DR_H */
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#define GPIO_SWPORT_DR_H_OFFSET (0x4U)
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#define GPIO_SWPORT_DR_H_SWPORT_DR_HIGH_SHIFT (0U)
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#define GPIO_SWPORT_DR_H_SWPORT_DR_HIGH_MASK (0xFFFFU << GPIO_SWPORT_DR_H_SWPORT_DR_HIGH_SHIFT) /* 0x0000FFFF */
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/* SWPORT_DDR_L */
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#define GPIO_SWPORT_DDR_L_OFFSET (0x8U)
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#define GPIO_SWPORT_DDR_L_SWPORT_DDR_LOW_SHIFT (0U)
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#define GPIO_SWPORT_DDR_L_SWPORT_DDR_LOW_MASK (0xFFFFU << GPIO_SWPORT_DDR_L_SWPORT_DDR_LOW_SHIFT) /* 0x0000FFFF */
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/* SWPORT_DDR_H */
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#define GPIO_SWPORT_DDR_H_OFFSET (0xCU)
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#define GPIO_SWPORT_DDR_H_SWPORT_DDR_HIGH_SHIFT (0U)
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#define GPIO_SWPORT_DDR_H_SWPORT_DDR_HIGH_MASK (0xFFFFU << GPIO_SWPORT_DDR_H_SWPORT_DDR_HIGH_SHIFT) /* 0x0000FFFF */
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/* INT_EN_L */
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#define GPIO_INT_EN_L_OFFSET (0x10U)
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#define GPIO_INT_EN_L_INT_EN_LOW_SHIFT (0U)
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#define GPIO_INT_EN_L_INT_EN_LOW_MASK (0xFFFFU << GPIO_INT_EN_L_INT_EN_LOW_SHIFT) /* 0x0000FFFF */
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/* INT_EN_H */
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#define GPIO_INT_EN_H_OFFSET (0x14U)
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#define GPIO_INT_EN_H_INT_EN_HIGH_SHIFT (0U)
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#define GPIO_INT_EN_H_INT_EN_HIGH_MASK (0xFFFFU << GPIO_INT_EN_H_INT_EN_HIGH_SHIFT) /* 0x0000FFFF */
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/* INT_MASK_L */
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#define GPIO_INT_MASK_L_OFFSET (0x18U)
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#define GPIO_INT_MASK_L_INT_MASK_LOW_SHIFT (0U)
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#define GPIO_INT_MASK_L_INT_MASK_LOW_MASK (0xFFFFU << GPIO_INT_MASK_L_INT_MASK_LOW_SHIFT) /* 0x0000FFFF */
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/* INT_MASK_H */
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#define GPIO_INT_MASK_H_OFFSET (0x1CU)
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#define GPIO_INT_MASK_H_INT_MASK_HIGH_SHIFT (0U)
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#define GPIO_INT_MASK_H_INT_MASK_HIGH_MASK (0xFFFFU << GPIO_INT_MASK_H_INT_MASK_HIGH_SHIFT) /* 0x0000FFFF */
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/* INT_TYPE_L */
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#define GPIO_INT_TYPE_L_OFFSET (0x20U)
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#define GPIO_INT_TYPE_L_INT_TYPE_LOW_SHIFT (0U)
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#define GPIO_INT_TYPE_L_INT_TYPE_LOW_MASK (0xFFFFU << GPIO_INT_TYPE_L_INT_TYPE_LOW_SHIFT) /* 0x0000FFFF */
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/* INT_TYPE_H */
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#define GPIO_INT_TYPE_H_OFFSET (0x24U)
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#define GPIO_INT_TYPE_H_INT_TYPE_HIGH_SHIFT (0U)
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#define GPIO_INT_TYPE_H_INT_TYPE_HIGH_MASK (0xFFFFU << GPIO_INT_TYPE_H_INT_TYPE_HIGH_SHIFT) /* 0x0000FFFF */
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/* INT_POLARITY_L */
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#define GPIO_INT_POLARITY_L_OFFSET (0x28U)
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#define GPIO_INT_POLARITY_L_INT_POLARITY_LOW_SHIFT (0U)
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#define GPIO_INT_POLARITY_L_INT_POLARITY_LOW_MASK (0xFFFFU << GPIO_INT_POLARITY_L_INT_POLARITY_LOW_SHIFT) /* 0x0000FFFF */
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/* INT_POLARITY_H */
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#define GPIO_INT_POLARITY_H_OFFSET (0x2CU)
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#define GPIO_INT_POLARITY_H_INT_POLARITY_HIGH_SHIFT (0U)
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#define GPIO_INT_POLARITY_H_INT_POLARITY_HIGH_MASK (0xFFFFU << GPIO_INT_POLARITY_H_INT_POLARITY_HIGH_SHIFT) /* 0x0000FFFF */
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/* INT_BOTHEDGE_L */
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#define GPIO_INT_BOTHEDGE_L_OFFSET (0x30U)
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#define GPIO_INT_BOTHEDGE_L_INT_BOTHEDGE_LOW_SHIFT (0U)
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#define GPIO_INT_BOTHEDGE_L_INT_BOTHEDGE_LOW_MASK (0xFFFFU << GPIO_INT_BOTHEDGE_L_INT_BOTHEDGE_LOW_SHIFT) /* 0x0000FFFF */
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/* INT_BOTHEDGE_H */
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#define GPIO_INT_BOTHEDGE_H_OFFSET (0x34U)
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#define GPIO_INT_BOTHEDGE_H_INT_BOTHEDGE_HIGH_SHIFT (0U)
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#define GPIO_INT_BOTHEDGE_H_INT_BOTHEDGE_HIGH_MASK (0xFFFFU << GPIO_INT_BOTHEDGE_H_INT_BOTHEDGE_HIGH_SHIFT) /* 0x0000FFFF */
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/* DEBOUNCE_L */
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#define GPIO_DEBOUNCE_L_OFFSET (0x38U)
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#define GPIO_DEBOUNCE_L_DEBOUNCE_LOW_SHIFT (0U)
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#define GPIO_DEBOUNCE_L_DEBOUNCE_LOW_MASK (0xFFFFU << GPIO_DEBOUNCE_L_DEBOUNCE_LOW_SHIFT) /* 0x0000FFFF */
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/* DEBOUNCE_H */
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#define GPIO_DEBOUNCE_H_OFFSET (0x3CU)
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#define GPIO_DEBOUNCE_H_DEBOUNCE_HIGH_SHIFT (0U)
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#define GPIO_DEBOUNCE_H_DEBOUNCE_HIGH_MASK (0xFFFFU << GPIO_DEBOUNCE_H_DEBOUNCE_HIGH_SHIFT) /* 0x0000FFFF */
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/* DBCLK_DIV_EN_L */
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#define GPIO_DBCLK_DIV_EN_L_OFFSET (0x40U)
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#define GPIO_DBCLK_DIV_EN_L_DBCLK_DIV_EN_LOW_SHIFT (0U)
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#define GPIO_DBCLK_DIV_EN_L_DBCLK_DIV_EN_LOW_MASK (0xFFFFU << GPIO_DBCLK_DIV_EN_L_DBCLK_DIV_EN_LOW_SHIFT) /* 0x0000FFFF */
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/* DBCLK_DIV_EN_H */
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#define GPIO_DBCLK_DIV_EN_H_OFFSET (0x44U)
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#define GPIO_DBCLK_DIV_EN_H_DBCLK_DIV_EN_HIGH_SHIFT (0U)
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#define GPIO_DBCLK_DIV_EN_H_DBCLK_DIV_EN_HIGH_MASK (0xFFFFU << GPIO_DBCLK_DIV_EN_H_DBCLK_DIV_EN_HIGH_SHIFT) /* 0x0000FFFF */
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/* DBCLK_DIV_CON */
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#define GPIO_DBCLK_DIV_CON_OFFSET (0x48U)
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#define GPIO_DBCLK_DIV_CON_DBCLK_DIV_CON_SHIFT (0U)
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#define GPIO_DBCLK_DIV_CON_DBCLK_DIV_CON_MASK (0xFFFFFFU << GPIO_DBCLK_DIV_CON_DBCLK_DIV_CON_SHIFT) /* 0x00FFFFFF */
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/* INT_STATUS */
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#define GPIO_INT_STATUS_OFFSET (0x50U)
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#define GPIO_INT_STATUS (0x0U)
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#define GPIO_INT_STATUS_INT_STATUS_SHIFT (0U)
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#define GPIO_INT_STATUS_INT_STATUS_MASK (0xFFFFFFFFU << GPIO_INT_STATUS_INT_STATUS_SHIFT) /* 0xFFFFFFFF */
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/* INT_RAWSTATUS */
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#define GPIO_INT_RAWSTATUS_OFFSET (0x58U)
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#define GPIO_INT_RAWSTATUS (0x0U)
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#define GPIO_INT_RAWSTATUS_INT_RAWSTATUS_SHIFT (0U)
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#define GPIO_INT_RAWSTATUS_INT_RAWSTATUS_MASK (0xFFFFFFFFU << GPIO_INT_RAWSTATUS_INT_RAWSTATUS_SHIFT) /* 0xFFFFFFFF */
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/* PORT_EOI_L */
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#define GPIO_PORT_EOI_L_OFFSET (0x60U)
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#define GPIO_PORT_EOI_L_PORT_EOI_LOW_SHIFT (0U)
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#define GPIO_PORT_EOI_L_PORT_EOI_LOW_MASK (0xFFFFU << GPIO_PORT_EOI_L_PORT_EOI_LOW_SHIFT) /* 0x0000FFFF */
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/* PORT_EOI_H */
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#define GPIO_PORT_EOI_H_OFFSET (0x64U)
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#define GPIO_PORT_EOI_H_PORT_EOI_HIGH_SHIFT (0U)
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#define GPIO_PORT_EOI_H_PORT_EOI_HIGH_MASK (0xFFFFU << GPIO_PORT_EOI_H_PORT_EOI_HIGH_SHIFT) /* 0x0000FFFF */
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/* EXT_PORT */
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#define GPIO_EXT_PORT_OFFSET (0x70U)
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#define GPIO_EXT_PORT (0x0U)
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#define GPIO_EXT_PORT_EXT_PORT_SHIFT (0U)
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#define GPIO_EXT_PORT_EXT_PORT_MASK (0xFFFFFFFFU << GPIO_EXT_PORT_EXT_PORT_SHIFT) /* 0xFFFFFFFF */
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/* VER_ID */
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#define GPIO_VER_ID_OFFSET (0x78U)
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#define GPIO_VER_ID (0x101157CU)
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#define GPIO_VER_ID_VER_ID_SHIFT (0U)
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#define GPIO_VER_ID_VER_ID_MASK (0xFFFFFFFFU << GPIO_VER_ID_VER_ID_SHIFT) /* 0xFFFFFFFF */
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/******************************************PWM*******************************************/
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/* PWM0_CNT */
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#define PWM_PWM0_CNT_OFFSET (0x0U)
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#define PWM_PWM0_CNT (0x0U)
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#define PWM_PWM0_CNT_CNT_SHIFT (0U)
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#define PWM_PWM0_CNT_CNT_MASK (0xFFFFFFFFU << PWM_PWM0_CNT_CNT_SHIFT) /* 0xFFFFFFFF */
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/* PWM0_PERIOD_HPR */
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#define PWM_PWM0_PERIOD_HPR_OFFSET (0x4U)
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#define PWM_PWM0_PERIOD_HPR_PERIOD_HPR_SHIFT (0U)
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#define PWM_PWM0_PERIOD_HPR_PERIOD_HPR_MASK (0xFFFFFFFFU << PWM_PWM0_PERIOD_HPR_PERIOD_HPR_SHIFT) /* 0xFFFFFFFF */
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/* PWM0_DUTY_LPR */
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#define PWM_PWM0_DUTY_LPR_OFFSET (0x8U)
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#define PWM_PWM0_DUTY_LPR_DUTY_LPR_SHIFT (0U)
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#define PWM_PWM0_DUTY_LPR_DUTY_LPR_MASK (0xFFFFFFFFU << PWM_PWM0_DUTY_LPR_DUTY_LPR_SHIFT) /* 0xFFFFFFFF */
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/* PWM0_CTRL */
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#define PWM_PWM0_CTRL_OFFSET (0xCU)
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#define PWM_PWM0_CTRL_PWM_EN_SHIFT (0U)
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#define PWM_PWM0_CTRL_PWM_EN_MASK (0x1U << PWM_PWM0_CTRL_PWM_EN_SHIFT) /* 0x00000001 */
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#define PWM_PWM0_CTRL_PWM_MODE_SHIFT (1U)
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#define PWM_PWM0_CTRL_PWM_MODE_MASK (0x3U << PWM_PWM0_CTRL_PWM_MODE_SHIFT) /* 0x00000006 */
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#define PWM_PWM0_CTRL_DUTY_POL_SHIFT (3U)
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#define PWM_PWM0_CTRL_DUTY_POL_MASK (0x1U << PWM_PWM0_CTRL_DUTY_POL_SHIFT) /* 0x00000008 */
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#define PWM_PWM0_CTRL_INACTIVE_POL_SHIFT (4U)
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#define PWM_PWM0_CTRL_INACTIVE_POL_MASK (0x1U << PWM_PWM0_CTRL_INACTIVE_POL_SHIFT) /* 0x00000010 */
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#define PWM_PWM0_CTRL_OUTPUT_MODE_SHIFT (5U)
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#define PWM_PWM0_CTRL_OUTPUT_MODE_MASK (0x1U << PWM_PWM0_CTRL_OUTPUT_MODE_SHIFT) /* 0x00000020 */
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#define PWM_PWM0_CTRL_CONLOCK_SHIFT (6U)
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#define PWM_PWM0_CTRL_CONLOCK_MASK (0x1U << PWM_PWM0_CTRL_CONLOCK_SHIFT) /* 0x00000040 */
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#define PWM_PWM0_CTRL_CH_CNT_EN_SHIFT (7U)
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#define PWM_PWM0_CTRL_CH_CNT_EN_MASK (0x1U << PWM_PWM0_CTRL_CH_CNT_EN_SHIFT) /* 0x00000080 */
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#define PWM_PWM0_CTRL_FORCE_CLK_EN_SHIFT (8U)
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#define PWM_PWM0_CTRL_FORCE_CLK_EN_MASK (0x1U << PWM_PWM0_CTRL_FORCE_CLK_EN_SHIFT) /* 0x00000100 */
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#define PWM_PWM0_CTRL_CLK_SEL_SHIFT (9U)
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#define PWM_PWM0_CTRL_CLK_SEL_MASK (0x1U << PWM_PWM0_CTRL_CLK_SEL_SHIFT) /* 0x00000200 */
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#define PWM_PWM0_CTRL_CLK_SRC_SEL_SHIFT (10U)
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#define PWM_PWM0_CTRL_CLK_SRC_SEL_MASK (0x1U << PWM_PWM0_CTRL_CLK_SRC_SEL_SHIFT) /* 0x00000400 */
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#define PWM_PWM0_CTRL_PRESCALE_SHIFT (12U)
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#define PWM_PWM0_CTRL_PRESCALE_MASK (0x7U << PWM_PWM0_CTRL_PRESCALE_SHIFT) /* 0x00007000 */
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#define PWM_PWM0_CTRL_SCALE_SHIFT (16U)
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#define PWM_PWM0_CTRL_SCALE_MASK (0xFFU << PWM_PWM0_CTRL_SCALE_SHIFT) /* 0x00FF0000 */
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#define PWM_PWM0_CTRL_RPT_SHIFT (24U)
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#define PWM_PWM0_CTRL_RPT_MASK (0xFFU << PWM_PWM0_CTRL_RPT_SHIFT) /* 0xFF000000 */
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/* PWM1_CNT */
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#define PWM_PWM1_CNT_OFFSET (0x10U)
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#define PWM_PWM1_CNT (0x0U)
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#define PWM_PWM1_CNT_CNT_SHIFT (0U)
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#define PWM_PWM1_CNT_CNT_MASK (0xFFFFFFFFU << PWM_PWM1_CNT_CNT_SHIFT) /* 0xFFFFFFFF */
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/* PWM1_PERIOD_HPR */
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#define PWM_PWM1_PERIOD_HPR_OFFSET (0x14U)
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#define PWM_PWM1_PERIOD_HPR_PERIOD_HPR_SHIFT (0U)
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#define PWM_PWM1_PERIOD_HPR_PERIOD_HPR_MASK (0xFFFFFFFFU << PWM_PWM1_PERIOD_HPR_PERIOD_HPR_SHIFT) /* 0xFFFFFFFF */
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/* PWM1_DUTY_LPR */
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#define PWM_PWM1_DUTY_LPR_OFFSET (0x18U)
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#define PWM_PWM1_DUTY_LPR_DUTY_LPR_SHIFT (0U)
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#define PWM_PWM1_DUTY_LPR_DUTY_LPR_MASK (0xFFFFFFFFU << PWM_PWM1_DUTY_LPR_DUTY_LPR_SHIFT) /* 0xFFFFFFFF */
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/* PWM1_CTRL */
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#define PWM_PWM1_CTRL_OFFSET (0x1CU)
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#define PWM_PWM1_CTRL_PWM_EN_SHIFT (0U)
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#define PWM_PWM1_CTRL_PWM_EN_MASK (0x1U << PWM_PWM1_CTRL_PWM_EN_SHIFT) /* 0x00000001 */
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#define PWM_PWM1_CTRL_PWM_MODE_SHIFT (1U)
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#define PWM_PWM1_CTRL_PWM_MODE_MASK (0x3U << PWM_PWM1_CTRL_PWM_MODE_SHIFT) /* 0x00000006 */
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#define PWM_PWM1_CTRL_DUTY_POL_SHIFT (3U)
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#define PWM_PWM1_CTRL_DUTY_POL_MASK (0x1U << PWM_PWM1_CTRL_DUTY_POL_SHIFT) /* 0x00000008 */
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#define PWM_PWM1_CTRL_INACTIVE_POL_SHIFT (4U)
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#define PWM_PWM1_CTRL_INACTIVE_POL_MASK (0x1U << PWM_PWM1_CTRL_INACTIVE_POL_SHIFT) /* 0x00000010 */
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#define PWM_PWM1_CTRL_OUTPUT_MODE_SHIFT (5U)
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#define PWM_PWM1_CTRL_OUTPUT_MODE_MASK (0x1U << PWM_PWM1_CTRL_OUTPUT_MODE_SHIFT) /* 0x00000020 */
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#define PWM_PWM1_CTRL_CONLOCK_SHIFT (6U)
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#define PWM_PWM1_CTRL_CONLOCK_MASK (0x1U << PWM_PWM1_CTRL_CONLOCK_SHIFT) /* 0x00000040 */
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#define PWM_PWM1_CTRL_CH_CNT_EN_SHIFT (7U)
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#define PWM_PWM1_CTRL_CH_CNT_EN_MASK (0x1U << PWM_PWM1_CTRL_CH_CNT_EN_SHIFT) /* 0x00000080 */
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#define PWM_PWM1_CTRL_FORCE_CLK_EN_SHIFT (8U)
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#define PWM_PWM1_CTRL_FORCE_CLK_EN_MASK (0x1U << PWM_PWM1_CTRL_FORCE_CLK_EN_SHIFT) /* 0x00000100 */
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#define PWM_PWM1_CTRL_CLK_SEL_SHIFT (9U)
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#define PWM_PWM1_CTRL_CLK_SEL_MASK (0x1U << PWM_PWM1_CTRL_CLK_SEL_SHIFT) /* 0x00000200 */
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#define PWM_PWM1_CTRL_CLK_SRC_SEL_SHIFT (10U)
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#define PWM_PWM1_CTRL_CLK_SRC_SEL_MASK (0x1U << PWM_PWM1_CTRL_CLK_SRC_SEL_SHIFT) /* 0x00000400 */
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#define PWM_PWM1_CTRL_PRESCALE_SHIFT (12U)
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#define PWM_PWM1_CTRL_PRESCALE_MASK (0x7U << PWM_PWM1_CTRL_PRESCALE_SHIFT) /* 0x00007000 */
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#define PWM_PWM1_CTRL_SCALE_SHIFT (16U)
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#define PWM_PWM1_CTRL_SCALE_MASK (0xFFU << PWM_PWM1_CTRL_SCALE_SHIFT) /* 0x00FF0000 */
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#define PWM_PWM1_CTRL_RPT_SHIFT (24U)
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#define PWM_PWM1_CTRL_RPT_MASK (0xFFU << PWM_PWM1_CTRL_RPT_SHIFT) /* 0xFF000000 */
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/* PWM2_CNT */
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#define PWM_PWM2_CNT_OFFSET (0x20U)
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#define PWM_PWM2_CNT (0x0U)
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#define PWM_PWM2_CNT_CNT_SHIFT (0U)
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#define PWM_PWM2_CNT_CNT_MASK (0xFFFFFFFFU << PWM_PWM2_CNT_CNT_SHIFT) /* 0xFFFFFFFF */
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/* PWM2_PERIOD_HPR */
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#define PWM_PWM2_PERIOD_HPR_OFFSET (0x24U)
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#define PWM_PWM2_PERIOD_HPR_PERIOD_HPR_SHIFT (0U)
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#define PWM_PWM2_PERIOD_HPR_PERIOD_HPR_MASK (0xFFFFFFFFU << PWM_PWM2_PERIOD_HPR_PERIOD_HPR_SHIFT) /* 0xFFFFFFFF */
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/* PWM2_DUTY_LPR */
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#define PWM_PWM2_DUTY_LPR_OFFSET (0x28U)
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#define PWM_PWM2_DUTY_LPR_DUTY_LPR_SHIFT (0U)
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#define PWM_PWM2_DUTY_LPR_DUTY_LPR_MASK (0xFFFFFFFFU << PWM_PWM2_DUTY_LPR_DUTY_LPR_SHIFT) /* 0xFFFFFFFF */
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/* PWM2_CTRL */
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#define PWM_PWM2_CTRL_OFFSET (0x2CU)
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#define PWM_PWM2_CTRL_PWM_EN_SHIFT (0U)
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#define PWM_PWM2_CTRL_PWM_EN_MASK (0x1U << PWM_PWM2_CTRL_PWM_EN_SHIFT) /* 0x00000001 */
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#define PWM_PWM2_CTRL_PWM_MODE_SHIFT (1U)
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#define PWM_PWM2_CTRL_PWM_MODE_MASK (0x3U << PWM_PWM2_CTRL_PWM_MODE_SHIFT) /* 0x00000006 */
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#define PWM_PWM2_CTRL_DUTY_POL_SHIFT (3U)
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#define PWM_PWM2_CTRL_DUTY_POL_MASK (0x1U << PWM_PWM2_CTRL_DUTY_POL_SHIFT) /* 0x00000008 */
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#define PWM_PWM2_CTRL_INACTIVE_POL_SHIFT (4U)
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#define PWM_PWM2_CTRL_INACTIVE_POL_MASK (0x1U << PWM_PWM2_CTRL_INACTIVE_POL_SHIFT) /* 0x00000010 */
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#define PWM_PWM2_CTRL_OUTPUT_MODE_SHIFT (5U)
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#define PWM_PWM2_CTRL_OUTPUT_MODE_MASK (0x1U << PWM_PWM2_CTRL_OUTPUT_MODE_SHIFT) /* 0x00000020 */
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#define PWM_PWM2_CTRL_CONLOCK_SHIFT (6U)
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#define PWM_PWM2_CTRL_CONLOCK_MASK (0x1U << PWM_PWM2_CTRL_CONLOCK_SHIFT) /* 0x00000040 */
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#define PWM_PWM2_CTRL_CH_CNT_EN_SHIFT (7U)
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#define PWM_PWM2_CTRL_CH_CNT_EN_MASK (0x1U << PWM_PWM2_CTRL_CH_CNT_EN_SHIFT) /* 0x00000080 */
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#define PWM_PWM2_CTRL_FORCE_CLK_EN_SHIFT (8U)
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#define PWM_PWM2_CTRL_FORCE_CLK_EN_MASK (0x1U << PWM_PWM2_CTRL_FORCE_CLK_EN_SHIFT) /* 0x00000100 */
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#define PWM_PWM2_CTRL_CLK_SEL_SHIFT (9U)
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#define PWM_PWM2_CTRL_CLK_SEL_MASK (0x1U << PWM_PWM2_CTRL_CLK_SEL_SHIFT) /* 0x00000200 */
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#define PWM_PWM2_CTRL_CLK_SRC_SEL_SHIFT (10U)
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#define PWM_PWM2_CTRL_CLK_SRC_SEL_MASK (0x1U << PWM_PWM2_CTRL_CLK_SRC_SEL_SHIFT) /* 0x00000400 */
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#define PWM_PWM2_CTRL_PRESCALE_SHIFT (12U)
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#define PWM_PWM2_CTRL_PRESCALE_MASK (0x7U << PWM_PWM2_CTRL_PRESCALE_SHIFT) /* 0x00007000 */
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#define PWM_PWM2_CTRL_SCALE_SHIFT (16U)
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#define PWM_PWM2_CTRL_SCALE_MASK (0xFFU << PWM_PWM2_CTRL_SCALE_SHIFT) /* 0x00FF0000 */
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#define PWM_PWM2_CTRL_RPT_SHIFT (24U)
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#define PWM_PWM2_CTRL_RPT_MASK (0xFFU << PWM_PWM2_CTRL_RPT_SHIFT) /* 0xFF000000 */
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/* PWM3_CNT */
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#define PWM_PWM3_CNT_OFFSET (0x30U)
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#define PWM_PWM3_CNT (0x0U)
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#define PWM_PWM3_CNT_CNT_SHIFT (0U)
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#define PWM_PWM3_CNT_CNT_MASK (0xFFFFFFFFU << PWM_PWM3_CNT_CNT_SHIFT) /* 0xFFFFFFFF */
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/* PWM3_PERIOD_HPR */
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#define PWM_PWM3_PERIOD_HPR_OFFSET (0x34U)
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#define PWM_PWM3_PERIOD_HPR_PERIOD_HPR_SHIFT (0U)
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#define PWM_PWM3_PERIOD_HPR_PERIOD_HPR_MASK (0xFFFFFFFFU << PWM_PWM3_PERIOD_HPR_PERIOD_HPR_SHIFT) /* 0xFFFFFFFF */
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/* PWM3_DUTY_LPR */
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#define PWM_PWM3_DUTY_LPR_OFFSET (0x38U)
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#define PWM_PWM3_DUTY_LPR_DUTY_LPR_SHIFT (0U)
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#define PWM_PWM3_DUTY_LPR_DUTY_LPR_MASK (0xFFFFFFFFU << PWM_PWM3_DUTY_LPR_DUTY_LPR_SHIFT) /* 0xFFFFFFFF */
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/* PWM3_CTRL */
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#define PWM_PWM3_CTRL_OFFSET (0x3CU)
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#define PWM_PWM3_CTRL_PWM_EN_SHIFT (0U)
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#define PWM_PWM3_CTRL_PWM_EN_MASK (0x1U << PWM_PWM3_CTRL_PWM_EN_SHIFT) /* 0x00000001 */
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#define PWM_PWM3_CTRL_PWM_MODE_SHIFT (1U)
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#define PWM_PWM3_CTRL_PWM_MODE_MASK (0x3U << PWM_PWM3_CTRL_PWM_MODE_SHIFT) /* 0x00000006 */
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#define PWM_PWM3_CTRL_DUTY_POL_SHIFT (3U)
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#define PWM_PWM3_CTRL_DUTY_POL_MASK (0x1U << PWM_PWM3_CTRL_DUTY_POL_SHIFT) /* 0x00000008 */
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#define PWM_PWM3_CTRL_INACTIVE_POL_SHIFT (4U)
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#define PWM_PWM3_CTRL_INACTIVE_POL_MASK (0x1U << PWM_PWM3_CTRL_INACTIVE_POL_SHIFT) /* 0x00000010 */
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#define PWM_PWM3_CTRL_OUTPUT_MODE_SHIFT (5U)
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#define PWM_PWM3_CTRL_OUTPUT_MODE_MASK (0x1U << PWM_PWM3_CTRL_OUTPUT_MODE_SHIFT) /* 0x00000020 */
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#define PWM_PWM3_CTRL_CONLOCK_SHIFT (6U)
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#define PWM_PWM3_CTRL_CONLOCK_MASK (0x1U << PWM_PWM3_CTRL_CONLOCK_SHIFT) /* 0x00000040 */
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#define PWM_PWM3_CTRL_CH_CNT_EN_SHIFT (7U)
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#define PWM_PWM3_CTRL_CH_CNT_EN_MASK (0x1U << PWM_PWM3_CTRL_CH_CNT_EN_SHIFT) /* 0x00000080 */
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#define PWM_PWM3_CTRL_FORCE_CLK_EN_SHIFT (8U)
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#define PWM_PWM3_CTRL_FORCE_CLK_EN_MASK (0x1U << PWM_PWM3_CTRL_FORCE_CLK_EN_SHIFT) /* 0x00000100 */
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#define PWM_PWM3_CTRL_CLK_SEL_SHIFT (9U)
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#define PWM_PWM3_CTRL_CLK_SEL_MASK (0x1U << PWM_PWM3_CTRL_CLK_SEL_SHIFT) /* 0x00000200 */
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#define PWM_PWM3_CTRL_CLK_SRC_SEL_SHIFT (10U)
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#define PWM_PWM3_CTRL_CLK_SRC_SEL_MASK (0x1U << PWM_PWM3_CTRL_CLK_SRC_SEL_SHIFT) /* 0x00000400 */
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#define PWM_PWM3_CTRL_PRESCALE_SHIFT (12U)
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#define PWM_PWM3_CTRL_PRESCALE_MASK (0x7U << PWM_PWM3_CTRL_PRESCALE_SHIFT) /* 0x00007000 */
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#define PWM_PWM3_CTRL_SCALE_SHIFT (16U)
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#define PWM_PWM3_CTRL_SCALE_MASK (0xFFU << PWM_PWM3_CTRL_SCALE_SHIFT) /* 0x00FF0000 */
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#define PWM_PWM3_CTRL_RPT_SHIFT (24U)
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#define PWM_PWM3_CTRL_RPT_MASK (0xFFU << PWM_PWM3_CTRL_RPT_SHIFT) /* 0xFF000000 */
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/* INTSTS */
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#define PWM_INTSTS_OFFSET (0x40U)
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#define PWM_INTSTS_CH0_INTSTS_SHIFT (0U)
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#define PWM_INTSTS_CH0_INTSTS_MASK (0x1U << PWM_INTSTS_CH0_INTSTS_SHIFT) /* 0x00000001 */
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#define PWM_INTSTS_CH1_INTSTS_SHIFT (1U)
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#define PWM_INTSTS_CH1_INTSTS_MASK (0x1U << PWM_INTSTS_CH1_INTSTS_SHIFT) /* 0x00000002 */
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#define PWM_INTSTS_CH2_INTSTS_SHIFT (2U)
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#define PWM_INTSTS_CH2_INTSTS_MASK (0x1U << PWM_INTSTS_CH2_INTSTS_SHIFT) /* 0x00000004 */
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#define PWM_INTSTS_CH3_INTSTS_SHIFT (3U)
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#define PWM_INTSTS_CH3_INTSTS_MASK (0x1U << PWM_INTSTS_CH3_INTSTS_SHIFT) /* 0x00000008 */
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#define PWM_INTSTS_CH0_PWR_INTSTS_SHIFT (4U)
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#define PWM_INTSTS_CH0_PWR_INTSTS_MASK (0x1U << PWM_INTSTS_CH0_PWR_INTSTS_SHIFT) /* 0x00000010 */
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#define PWM_INTSTS_CH1_PWR_INTSTS_SHIFT (5U)
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#define PWM_INTSTS_CH1_PWR_INTSTS_MASK (0x1U << PWM_INTSTS_CH1_PWR_INTSTS_SHIFT) /* 0x00000020 */
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#define PWM_INTSTS_CH2_PWR_INTSTS_SHIFT (6U)
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#define PWM_INTSTS_CH2_PWR_INTSTS_MASK (0x1U << PWM_INTSTS_CH2_PWR_INTSTS_SHIFT) /* 0x00000040 */
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#define PWM_INTSTS_CH3_PWR_INTSTS_SHIFT (7U)
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#define PWM_INTSTS_CH3_PWR_INTSTS_MASK (0x1U << PWM_INTSTS_CH3_PWR_INTSTS_SHIFT) /* 0x00000080 */
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#define PWM_INTSTS_CH0_POL_SHIFT (8U)
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#define PWM_INTSTS_CH0_POL_MASK (0x1U << PWM_INTSTS_CH0_POL_SHIFT) /* 0x00000100 */
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#define PWM_INTSTS_CH1_POL_SHIFT (9U)
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#define PWM_INTSTS_CH1_POL_MASK (0x1U << PWM_INTSTS_CH1_POL_SHIFT) /* 0x00000200 */
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#define PWM_INTSTS_CH2_POL_SHIFT (10U)
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#define PWM_INTSTS_CH2_POL_MASK (0x1U << PWM_INTSTS_CH2_POL_SHIFT) /* 0x00000400 */
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#define PWM_INTSTS_CH3_POL_SHIFT (11U)
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#define PWM_INTSTS_CH3_POL_MASK (0x1U << PWM_INTSTS_CH3_POL_SHIFT) /* 0x00000800 */
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/* INT_EN */
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#define PWM_INT_EN_OFFSET (0x44U)
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#define PWM_INT_EN_CH0_INT_EN_SHIFT (0U)
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#define PWM_INT_EN_CH0_INT_EN_MASK (0x1U << PWM_INT_EN_CH0_INT_EN_SHIFT) /* 0x00000001 */
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#define PWM_INT_EN_CH1_INT_EN_SHIFT (1U)
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#define PWM_INT_EN_CH1_INT_EN_MASK (0x1U << PWM_INT_EN_CH1_INT_EN_SHIFT) /* 0x00000002 */
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#define PWM_INT_EN_CH2_INT_EN_SHIFT (2U)
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#define PWM_INT_EN_CH2_INT_EN_MASK (0x1U << PWM_INT_EN_CH2_INT_EN_SHIFT) /* 0x00000004 */
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#define PWM_INT_EN_CH3_INT_EN_SHIFT (3U)
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#define PWM_INT_EN_CH3_INT_EN_MASK (0x1U << PWM_INT_EN_CH3_INT_EN_SHIFT) /* 0x00000008 */
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#define PWM_INT_EN_CH0_PWR_INT_EN_SHIFT (4U)
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#define PWM_INT_EN_CH0_PWR_INT_EN_MASK (0x1U << PWM_INT_EN_CH0_PWR_INT_EN_SHIFT) /* 0x00000010 */
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#define PWM_INT_EN_CH1_PWR_INT_EN_SHIFT (5U)
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#define PWM_INT_EN_CH1_PWR_INT_EN_MASK (0x1U << PWM_INT_EN_CH1_PWR_INT_EN_SHIFT) /* 0x00000020 */
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#define PWM_INT_EN_CH2_PWR_INT_EN_SHIFT (6U)
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#define PWM_INT_EN_CH2_PWR_INT_EN_MASK (0x1U << PWM_INT_EN_CH2_PWR_INT_EN_SHIFT) /* 0x00000040 */
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#define PWM_INT_EN_CH3_PWR_INT_EN_SHIFT (7U)
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#define PWM_INT_EN_CH3_PWR_INT_EN_MASK (0x1U << PWM_INT_EN_CH3_PWR_INT_EN_SHIFT) /* 0x00000080 */
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/* FIFO_CTRL */
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#define PWM_FIFO_CTRL_OFFSET (0x50U)
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#define PWM_FIFO_CTRL_FIFO_MODE_SEL_SHIFT (0U)
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#define PWM_FIFO_CTRL_FIFO_MODE_SEL_MASK (0x1U << PWM_FIFO_CTRL_FIFO_MODE_SEL_SHIFT) /* 0x00000001 */
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#define PWM_FIFO_CTRL_FULL_INT_EN_SHIFT (1U)
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#define PWM_FIFO_CTRL_FULL_INT_EN_MASK (0x1U << PWM_FIFO_CTRL_FULL_INT_EN_SHIFT) /* 0x00000002 */
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#define PWM_FIFO_CTRL_OVERFLOW_INT_EN_SHIFT (2U)
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#define PWM_FIFO_CTRL_OVERFLOW_INT_EN_MASK (0x1U << PWM_FIFO_CTRL_OVERFLOW_INT_EN_SHIFT) /* 0x00000004 */
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#define PWM_FIFO_CTRL_WATERMARK_INT_EN_SHIFT (3U)
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#define PWM_FIFO_CTRL_WATERMARK_INT_EN_MASK (0x1U << PWM_FIFO_CTRL_WATERMARK_INT_EN_SHIFT) /* 0x00000008 */
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#define PWM_FIFO_CTRL_ALMOST_FULL_WATERMARK_SHIFT (4U)
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#define PWM_FIFO_CTRL_ALMOST_FULL_WATERMARK_MASK (0x7U << PWM_FIFO_CTRL_ALMOST_FULL_WATERMARK_SHIFT) /* 0x00000070 */
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#define PWM_FIFO_CTRL_DMA_MODE_EN_SHIFT (8U)
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#define PWM_FIFO_CTRL_DMA_MODE_EN_MASK (0x1U << PWM_FIFO_CTRL_DMA_MODE_EN_SHIFT) /* 0x00000100 */
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#define PWM_FIFO_CTRL_TIMEOUT_EN_SHIFT (9U)
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#define PWM_FIFO_CTRL_TIMEOUT_EN_MASK (0x1U << PWM_FIFO_CTRL_TIMEOUT_EN_SHIFT) /* 0x00000200 */
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#define PWM_FIFO_CTRL_DMA_CH_SEL_EN_SHIFT (10U)
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#define PWM_FIFO_CTRL_DMA_CH_SEL_EN_MASK (0x1U << PWM_FIFO_CTRL_DMA_CH_SEL_EN_SHIFT) /* 0x00000400 */
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#define PWM_FIFO_CTRL_DMA_CH_SEL_SHIFT (12U)
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#define PWM_FIFO_CTRL_DMA_CH_SEL_MASK (0x3U << PWM_FIFO_CTRL_DMA_CH_SEL_SHIFT) /* 0x00003000 */
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/* FIFO_INTSTS */
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#define PWM_FIFO_INTSTS_OFFSET (0x54U)
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#define PWM_FIFO_INTSTS_FIFO_FULL_INTSTS_SHIFT (0U)
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#define PWM_FIFO_INTSTS_FIFO_FULL_INTSTS_MASK (0x1U << PWM_FIFO_INTSTS_FIFO_FULL_INTSTS_SHIFT) /* 0x00000001 */
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#define PWM_FIFO_INTSTS_FIFO_OVERFLOW_INTSTS_SHIFT (1U)
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#define PWM_FIFO_INTSTS_FIFO_OVERFLOW_INTSTS_MASK (0x1U << PWM_FIFO_INTSTS_FIFO_OVERFLOW_INTSTS_SHIFT) /* 0x00000002 */
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#define PWM_FIFO_INTSTS_FIFO_WATERMARK_FULL_INTSTS_SHIFT (2U)
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#define PWM_FIFO_INTSTS_FIFO_WATERMARK_FULL_INTSTS_MASK (0x1U << PWM_FIFO_INTSTS_FIFO_WATERMARK_FULL_INTSTS_SHIFT) /* 0x00000004 */
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#define PWM_FIFO_INTSTS_TIMIEOUT_INTSTS_SHIFT (3U)
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#define PWM_FIFO_INTSTS_TIMIEOUT_INTSTS_MASK (0x1U << PWM_FIFO_INTSTS_TIMIEOUT_INTSTS_SHIFT) /* 0x00000008 */
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#define PWM_FIFO_INTSTS_FIFO_EMPTY_STATUS_SHIFT (4U)
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#define PWM_FIFO_INTSTS_FIFO_EMPTY_STATUS_MASK (0x1U << PWM_FIFO_INTSTS_FIFO_EMPTY_STATUS_SHIFT) /* 0x00000010 */
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/* FIFO_TOUTTHR */
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#define PWM_FIFO_TOUTTHR_OFFSET (0x58U)
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#define PWM_FIFO_TOUTTHR_TIMEOUT_THRESHOLD_SHIFT (0U)
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#define PWM_FIFO_TOUTTHR_TIMEOUT_THRESHOLD_MASK (0xFFFFFU << PWM_FIFO_TOUTTHR_TIMEOUT_THRESHOLD_SHIFT) /* 0x000FFFFF */
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/* VERSION_ID */
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#define PWM_VERSION_ID_OFFSET (0x5CU)
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#define PWM_VERSION_ID_SVN_VERSION_SHIFT (0U)
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#define PWM_VERSION_ID_SVN_VERSION_MASK (0xFFFFU << PWM_VERSION_ID_SVN_VERSION_SHIFT) /* 0x0000FFFF */
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#define PWM_VERSION_ID_MINOR_VERSION_SHIFT (16U)
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#define PWM_VERSION_ID_MINOR_VERSION_MASK (0xFFU << PWM_VERSION_ID_MINOR_VERSION_SHIFT) /* 0x00FF0000 */
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#define PWM_VERSION_ID_MAIN_VERSION_SHIFT (24U)
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#define PWM_VERSION_ID_MAIN_VERSION_MASK (0xFFU << PWM_VERSION_ID_MAIN_VERSION_SHIFT) /* 0xFF000000 */
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/* FIFO */
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#define PWM_FIFO_OFFSET (0x60U)
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#define PWM_FIFO (0x0U)
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#define PWM_FIFO_CYCLE_CNT_SHIFT (0U)
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#define PWM_FIFO_CYCLE_CNT_MASK (0x7FFFFFFFU << PWM_FIFO_CYCLE_CNT_SHIFT) /* 0x7FFFFFFF */
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#define PWM_FIFO_POL_SHIFT (31U)
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#define PWM_FIFO_POL_MASK (0x1U << PWM_FIFO_POL_SHIFT) /* 0x80000000 */
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/* PWRMATCH_CTRL */
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#define PWM_PWRMATCH_CTRL_OFFSET (0x80U)
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#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_ENABLE_SHIFT (3U)
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#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_ENABLE_MASK (0x1U << PWM_PWRMATCH_CTRL_CH3_PWRKEY_ENABLE_SHIFT) /* 0x00000008 */
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#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_POLARITY_SHIFT (7U)
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#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_POLARITY_MASK (0x1U << PWM_PWRMATCH_CTRL_CH3_PWRKEY_POLARITY_SHIFT) /* 0x00000080 */
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#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_CAPTURE_CTRL_SHIFT (11U)
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#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_CAPTURE_CTRL_MASK (0x1U << PWM_PWRMATCH_CTRL_CH3_PWRKEY_CAPTURE_CTRL_SHIFT) /* 0x00000800 */
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#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_INT_CTRL_SHIFT (15U)
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#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_INT_CTRL_MASK (0x1U << PWM_PWRMATCH_CTRL_CH3_PWRKEY_INT_CTRL_SHIFT) /* 0x00008000 */
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/* PWRMATCH_LPRE */
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#define PWM_PWRMATCH_LPRE_OFFSET (0x84U)
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#define PWM_PWRMATCH_LPRE_CNT_MIN_SHIFT (0U)
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#define PWM_PWRMATCH_LPRE_CNT_MIN_MASK (0xFFFFU << PWM_PWRMATCH_LPRE_CNT_MIN_SHIFT) /* 0x0000FFFF */
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#define PWM_PWRMATCH_LPRE_CNT_MAX_SHIFT (16U)
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#define PWM_PWRMATCH_LPRE_CNT_MAX_MASK (0xFFFFU << PWM_PWRMATCH_LPRE_CNT_MAX_SHIFT) /* 0xFFFF0000 */
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/* PWRMATCH_HPRE */
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#define PWM_PWRMATCH_HPRE_OFFSET (0x88U)
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#define PWM_PWRMATCH_HPRE_CNT_MIN_SHIFT (0U)
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#define PWM_PWRMATCH_HPRE_CNT_MIN_MASK (0xFFFFU << PWM_PWRMATCH_HPRE_CNT_MIN_SHIFT) /* 0x0000FFFF */
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#define PWM_PWRMATCH_HPRE_CNT_MAX_SHIFT (16U)
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#define PWM_PWRMATCH_HPRE_CNT_MAX_MASK (0xFFFFU << PWM_PWRMATCH_HPRE_CNT_MAX_SHIFT) /* 0xFFFF0000 */
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/* PWRMATCH_LD */
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#define PWM_PWRMATCH_LD_OFFSET (0x8CU)
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#define PWM_PWRMATCH_LD_CNT_MIN_SHIFT (0U)
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#define PWM_PWRMATCH_LD_CNT_MIN_MASK (0xFFFFU << PWM_PWRMATCH_LD_CNT_MIN_SHIFT) /* 0x0000FFFF */
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#define PWM_PWRMATCH_LD_CNT_MAX_SHIFT (16U)
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#define PWM_PWRMATCH_LD_CNT_MAX_MASK (0xFFFFU << PWM_PWRMATCH_LD_CNT_MAX_SHIFT) /* 0xFFFF0000 */
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/* PWRMATCH_HD_ZERO */
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#define PWM_PWRMATCH_HD_ZERO_OFFSET (0x90U)
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#define PWM_PWRMATCH_HD_ZERO_CNT_MIN_SHIFT (0U)
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#define PWM_PWRMATCH_HD_ZERO_CNT_MIN_MASK (0xFFFFU << PWM_PWRMATCH_HD_ZERO_CNT_MIN_SHIFT) /* 0x0000FFFF */
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#define PWM_PWRMATCH_HD_ZERO_CNT_MAX_SHIFT (16U)
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#define PWM_PWRMATCH_HD_ZERO_CNT_MAX_MASK (0xFFFFU << PWM_PWRMATCH_HD_ZERO_CNT_MAX_SHIFT) /* 0xFFFF0000 */
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/* PWRMATCH_HD_ONE */
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#define PWM_PWRMATCH_HD_ONE_OFFSET (0x94U)
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#define PWM_PWRMATCH_HD_ONE_CNT_MIN_SHIFT (0U)
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#define PWM_PWRMATCH_HD_ONE_CNT_MIN_MASK (0xFFFFU << PWM_PWRMATCH_HD_ONE_CNT_MIN_SHIFT) /* 0x0000FFFF */
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#define PWM_PWRMATCH_HD_ONE_CNT_MAX_SHIFT (16U)
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#define PWM_PWRMATCH_HD_ONE_CNT_MAX_MASK (0xFFFFU << PWM_PWRMATCH_HD_ONE_CNT_MAX_SHIFT) /* 0xFFFF0000 */
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/* PWRMATCH_VALUE0 */
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#define PWM_PWRMATCH_VALUE0_OFFSET (0x98U)
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#define PWM_PWRMATCH_VALUE0_PWRKEY_MATCH_VALUE_SHIFT (0U)
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#define PWM_PWRMATCH_VALUE0_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE0_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */
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/* PWRMATCH_VALUE1 */
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#define PWM_PWRMATCH_VALUE1_OFFSET (0x9CU)
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#define PWM_PWRMATCH_VALUE1_PWRKEY_MATCH_VALUE_SHIFT (0U)
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#define PWM_PWRMATCH_VALUE1_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE1_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */
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/* PWRMATCH_VALUE2 */
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#define PWM_PWRMATCH_VALUE2_OFFSET (0xA0U)
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#define PWM_PWRMATCH_VALUE2_PWRKEY_MATCH_VALUE_SHIFT (0U)
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#define PWM_PWRMATCH_VALUE2_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE2_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */
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/* PWRMATCH_VALUE3 */
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#define PWM_PWRMATCH_VALUE3_OFFSET (0xA4U)
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#define PWM_PWRMATCH_VALUE3_PWRKEY_MATCH_VALUE_SHIFT (0U)
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#define PWM_PWRMATCH_VALUE3_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE3_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */
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/* PWRMATCH_VALUE4 */
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#define PWM_PWRMATCH_VALUE4_OFFSET (0xA8U)
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#define PWM_PWRMATCH_VALUE4_PWRKEY_MATCH_VALUE_SHIFT (0U)
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#define PWM_PWRMATCH_VALUE4_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE4_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */
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/* PWRMATCH_VALUE5 */
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#define PWM_PWRMATCH_VALUE5_OFFSET (0xACU)
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#define PWM_PWRMATCH_VALUE5_PWRKEY_MATCH_VALUE_SHIFT (0U)
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#define PWM_PWRMATCH_VALUE5_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE5_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */
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/* PWRMATCH_VALUE6 */
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#define PWM_PWRMATCH_VALUE6_OFFSET (0xB0U)
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#define PWM_PWRMATCH_VALUE6_PWRKEY_MATCH_VALUE_SHIFT (0U)
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#define PWM_PWRMATCH_VALUE6_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE6_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */
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/* PWRMATCH_VALUE7 */
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#define PWM_PWRMATCH_VALUE7_OFFSET (0xB4U)
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#define PWM_PWRMATCH_VALUE7_PWRKEY_MATCH_VALUE_SHIFT (0U)
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#define PWM_PWRMATCH_VALUE7_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE7_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */
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/* PWRMATCH_VALUE8 */
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#define PWM_PWRMATCH_VALUE8_OFFSET (0xB8U)
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#define PWM_PWRMATCH_VALUE8_PWRKEY_MATCH_VALUE_SHIFT (0U)
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#define PWM_PWRMATCH_VALUE8_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE8_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */
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/* PWRMATCH_VALUE9 */
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#define PWM_PWRMATCH_VALUE9_OFFSET (0xBCU)
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#define PWM_PWRMATCH_VALUE9_PWRKEY_MATCH_VALUE_SHIFT (0U)
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#define PWM_PWRMATCH_VALUE9_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE9_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */
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/* PWM3_PWRCAPTURE_VALUE */
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#define PWM_PWM3_PWRCAPTURE_VALUE_OFFSET (0xCCU)
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#define PWM_PWM3_PWRCAPTURE_VALUE (0x0U)
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#define PWM_PWM3_PWRCAPTURE_VALUE_PWRKEY_CAPTURE_VALUE_SHIFT (0U)
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#define PWM_PWM3_PWRCAPTURE_VALUE_PWRKEY_CAPTURE_VALUE_MASK (0xFFFFFFFFU << PWM_PWM3_PWRCAPTURE_VALUE_PWRKEY_CAPTURE_VALUE_SHIFT) /* 0xFFFFFFFF */
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/* FILTER_CTRL */
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#define PWM_FILTER_CTRL_OFFSET (0xD0U)
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#define PWM_FILTER_CTRL_CH0_INPUT_FILTER_ENABLE_SHIFT (0U)
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#define PWM_FILTER_CTRL_CH0_INPUT_FILTER_ENABLE_MASK (0x1U << PWM_FILTER_CTRL_CH0_INPUT_FILTER_ENABLE_SHIFT) /* 0x00000001 */
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#define PWM_FILTER_CTRL_CH1_INPUT_FILTER_ENABLE_SHIFT (1U)
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#define PWM_FILTER_CTRL_CH1_INPUT_FILTER_ENABLE_MASK (0x1U << PWM_FILTER_CTRL_CH1_INPUT_FILTER_ENABLE_SHIFT) /* 0x00000002 */
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#define PWM_FILTER_CTRL_CH2_INPUT_FILTER_ENABLE_SHIFT (2U)
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#define PWM_FILTER_CTRL_CH2_INPUT_FILTER_ENABLE_MASK (0x1U << PWM_FILTER_CTRL_CH2_INPUT_FILTER_ENABLE_SHIFT) /* 0x00000004 */
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#define PWM_FILTER_CTRL_CH3_INPUT_FILTER_ENABLE_SHIFT (3U)
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#define PWM_FILTER_CTRL_CH3_INPUT_FILTER_ENABLE_MASK (0x1U << PWM_FILTER_CTRL_CH3_INPUT_FILTER_ENABLE_SHIFT) /* 0x00000008 */
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#define PWM_FILTER_CTRL_FILTER_NUMBER_SHIFT (4U)
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#define PWM_FILTER_CTRL_FILTER_NUMBER_MASK (0x1FFU << PWM_FILTER_CTRL_FILTER_NUMBER_SHIFT) /* 0x00001FF0 */
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#define PWM_FILTER_CTRL_CH0_AND_CH3_SWITCH_EN_SHIFT (16U)
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#define PWM_FILTER_CTRL_CH0_AND_CH3_SWITCH_EN_MASK (0x1U << PWM_FILTER_CTRL_CH0_AND_CH3_SWITCH_EN_SHIFT) /* 0x00010000 */
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#define PWM_FILTER_CTRL_CH1_AND_CH3_SWITCH_EN_SHIFT (17U)
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#define PWM_FILTER_CTRL_CH1_AND_CH3_SWITCH_EN_MASK (0x1U << PWM_FILTER_CTRL_CH1_AND_CH3_SWITCH_EN_SHIFT) /* 0x00020000 */
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#define PWM_FILTER_CTRL_CH2_AND_CH3_SWITCH_EN_SHIFT (18U)
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#define PWM_FILTER_CTRL_CH2_AND_CH3_SWITCH_EN_MASK (0x1U << PWM_FILTER_CTRL_CH2_AND_CH3_SWITCH_EN_SHIFT) /* 0x00040000 */
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/******************************************PMU*******************************************/
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/* VERSION */
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#define PMU_VERSION_OFFSET (0x0U)
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#define PMU_VERSION (0x3003566U)
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#define PMU_VERSION_VERSION_SHIFT (0U)
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#define PMU_VERSION_VERSION_MASK (0xFFFFFFFFU << PMU_VERSION_VERSION_SHIFT) /* 0xFFFFFFFF */
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/* PWR_CON */
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#define PMU_PWR_CON_OFFSET (0x4U)
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#define PMU_PWR_CON_POWERMODE_EN_SHIFT (0U)
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#define PMU_PWR_CON_POWERMODE_EN_MASK (0x1U << PMU_PWR_CON_POWERMODE_EN_SHIFT) /* 0x00000001 */
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#define PMU_PWR_CON_DSU_BYPASS_SHIFT (1U)
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#define PMU_PWR_CON_DSU_BYPASS_MASK (0x1U << PMU_PWR_CON_DSU_BYPASS_SHIFT) /* 0x00000002 */
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#define PMU_PWR_CON_RESERVED_SHIFT (2U)
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#define PMU_PWR_CON_RESERVED_MASK (0x3U << PMU_PWR_CON_RESERVED_SHIFT) /* 0x0000000C */
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#define PMU_PWR_CON_BUS_BYPASS_SHIFT (4U)
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#define PMU_PWR_CON_BUS_BYPASS_MASK (0x1U << PMU_PWR_CON_BUS_BYPASS_SHIFT) /* 0x00000010 */
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#define PMU_PWR_CON_DDR_BYPASS_SHIFT (5U)
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#define PMU_PWR_CON_DDR_BYPASS_MASK (0x1U << PMU_PWR_CON_DDR_BYPASS_SHIFT) /* 0x00000020 */
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#define PMU_PWR_CON_PWRDN_BYPASS_SHIFT (6U)
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#define PMU_PWR_CON_PWRDN_BYPASS_MASK (0x1U << PMU_PWR_CON_PWRDN_BYPASS_SHIFT) /* 0x00000040 */
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#define PMU_PWR_CON_CRU_BYPASS_SHIFT (7U)
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#define PMU_PWR_CON_CRU_BYPASS_MASK (0x1U << PMU_PWR_CON_CRU_BYPASS_SHIFT) /* 0x00000080 */
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#define PMU_PWR_CON_CPU_BYPASS_SHIFT (8U)
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#define PMU_PWR_CON_CPU_BYPASS_MASK (0xFU << PMU_PWR_CON_CPU_BYPASS_SHIFT) /* 0x00000F00 */
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#define PMU_PWR_CON_PMU_SLEEP_POL_SHIFT (15U)
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#define PMU_PWR_CON_PMU_SLEEP_POL_MASK (0x1U << PMU_PWR_CON_PMU_SLEEP_POL_SHIFT) /* 0x00008000 */
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/* MAIN_PWR_STATE */
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#define PMU_MAIN_PWR_STATE_OFFSET (0x8U)
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#define PMU_MAIN_PWR_STATE (0x0U)
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#define PMU_MAIN_PWR_STATE_PMU_POWER_STATE_SHIFT (0U)
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#define PMU_MAIN_PWR_STATE_PMU_POWER_STATE_MASK (0xFU << PMU_MAIN_PWR_STATE_PMU_POWER_STATE_SHIFT) /* 0x0000000F */
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/* INT_MASK_CON */
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#define PMU_INT_MASK_CON_OFFSET (0xCU)
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#define PMU_INT_MASK_CON_GLB_INT_DISABLE_SHIFT (0U)
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#define PMU_INT_MASK_CON_GLB_INT_DISABLE_MASK (0x1U << PMU_INT_MASK_CON_GLB_INT_DISABLE_SHIFT) /* 0x00000001 */
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#define PMU_INT_MASK_CON_WAKEUP_MCU_SFT_SHIFT (15U)
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#define PMU_INT_MASK_CON_WAKEUP_MCU_SFT_MASK (0x1U << PMU_INT_MASK_CON_WAKEUP_MCU_SFT_SHIFT) /* 0x00008000 */
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/* WAKEUP_INT_CON */
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#define PMU_WAKEUP_INT_CON_OFFSET (0x10U)
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#define PMU_WAKEUP_INT_CON_WAKEUP_CPU0_INT_EN_SHIFT (0U)
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#define PMU_WAKEUP_INT_CON_WAKEUP_CPU0_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_CPU0_INT_EN_SHIFT) /* 0x00000001 */
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#define PMU_WAKEUP_INT_CON_WAKEUP_CPU1_INT_EN_SHIFT (1U)
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#define PMU_WAKEUP_INT_CON_WAKEUP_CPU1_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_CPU1_INT_EN_SHIFT) /* 0x00000002 */
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#define PMU_WAKEUP_INT_CON_WAKEUP_CPU2_INT_EN_SHIFT (2U)
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#define PMU_WAKEUP_INT_CON_WAKEUP_CPU2_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_CPU2_INT_EN_SHIFT) /* 0x00000004 */
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#define PMU_WAKEUP_INT_CON_WAKEUP_CPU3_INT_EN_SHIFT (3U)
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#define PMU_WAKEUP_INT_CON_WAKEUP_CPU3_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_CPU3_INT_EN_SHIFT) /* 0x00000008 */
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#define PMU_WAKEUP_INT_CON_WAKEUP_GPIO0_INT_EN_SHIFT (4U)
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#define PMU_WAKEUP_INT_CON_WAKEUP_GPIO0_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_GPIO0_INT_EN_SHIFT) /* 0x00000010 */
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#define PMU_WAKEUP_INT_CON_WAKEUP_UART0_EN_SHIFT (5U)
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#define PMU_WAKEUP_INT_CON_WAKEUP_UART0_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_UART0_EN_SHIFT) /* 0x00000020 */
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#define PMU_WAKEUP_INT_CON_WAKEUP_SDMMC0_EN_SHIFT (6U)
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#define PMU_WAKEUP_INT_CON_WAKEUP_SDMMC0_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_SDMMC0_EN_SHIFT) /* 0x00000040 */
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#define PMU_WAKEUP_INT_CON_WAKEUP_SDMMC1_EN_SHIFT (7U)
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#define PMU_WAKEUP_INT_CON_WAKEUP_SDMMC1_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_SDMMC1_EN_SHIFT) /* 0x00000080 */
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#define PMU_WAKEUP_INT_CON_WAKEUP_SDMMC2_EN_SHIFT (8U)
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#define PMU_WAKEUP_INT_CON_WAKEUP_SDMMC2_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_SDMMC2_EN_SHIFT) /* 0x00000100 */
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#define PMU_WAKEUP_INT_CON_WAKEUP_USB_EN_SHIFT (9U)
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#define PMU_WAKEUP_INT_CON_WAKEUP_USB_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_USB_EN_SHIFT) /* 0x00000200 */
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#define PMU_WAKEUP_INT_CON_WAKEUP_PCIE_EN_SHIFT (10U)
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#define PMU_WAKEUP_INT_CON_WAKEUP_PCIE_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_PCIE_EN_SHIFT) /* 0x00000400 */
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#define PMU_WAKEUP_INT_CON_WAKEUP_VAD_EN_SHIFT (11U)
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#define PMU_WAKEUP_INT_CON_WAKEUP_VAD_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_VAD_EN_SHIFT) /* 0x00000800 */
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#define PMU_WAKEUP_INT_CON_WAKEUP_TIMER_EN_SHIFT (12U)
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#define PMU_WAKEUP_INT_CON_WAKEUP_TIMER_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_TIMER_EN_SHIFT) /* 0x00001000 */
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#define PMU_WAKEUP_INT_CON_WAKEUP_PWM0_EN_SHIFT (13U)
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#define PMU_WAKEUP_INT_CON_WAKEUP_PWM0_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_PWM0_EN_SHIFT) /* 0x00002000 */
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#define PMU_WAKEUP_INT_CON_WAKEUP_TIMEOUT_EN_SHIFT (14U)
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#define PMU_WAKEUP_INT_CON_WAKEUP_TIMEOUT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_TIMEOUT_EN_SHIFT) /* 0x00004000 */
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#define PMU_WAKEUP_INT_CON_WAKEUP_MCU_SFT_EN_SHIFT (15U)
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#define PMU_WAKEUP_INT_CON_WAKEUP_MCU_SFT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_MCU_SFT_EN_SHIFT) /* 0x00008000 */
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/* WAKEUP_INT_ST */
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#define PMU_WAKEUP_INT_ST_OFFSET (0x14U)
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#define PMU_WAKEUP_INT_ST (0x0U)
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#define PMU_WAKEUP_INT_ST_WAKEUP_CPU0_INT_ST_SHIFT (0U)
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#define PMU_WAKEUP_INT_ST_WAKEUP_CPU0_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_CPU0_INT_ST_SHIFT) /* 0x00000001 */
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#define PMU_WAKEUP_INT_ST_WAKEUP_CPU1_INT_ST_SHIFT (1U)
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#define PMU_WAKEUP_INT_ST_WAKEUP_CPU1_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_CPU1_INT_ST_SHIFT) /* 0x00000002 */
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#define PMU_WAKEUP_INT_ST_WAKEUP_CPU2_INT_ST_SHIFT (2U)
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#define PMU_WAKEUP_INT_ST_WAKEUP_CPU2_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_CPU2_INT_ST_SHIFT) /* 0x00000004 */
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#define PMU_WAKEUP_INT_ST_WAKEUP_CPU3_INT_ST_SHIFT (3U)
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#define PMU_WAKEUP_INT_ST_WAKEUP_CPU3_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_CPU3_INT_ST_SHIFT) /* 0x00000008 */
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#define PMU_WAKEUP_INT_ST_WAKEUP_GPIO0_INT_ST_SHIFT (4U)
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#define PMU_WAKEUP_INT_ST_WAKEUP_GPIO0_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_GPIO0_INT_ST_SHIFT) /* 0x00000010 */
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#define PMU_WAKEUP_INT_ST_WAKEUP_UART0_INT_ST_SHIFT (5U)
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#define PMU_WAKEUP_INT_ST_WAKEUP_UART0_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_UART0_INT_ST_SHIFT) /* 0x00000020 */
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#define PMU_WAKEUP_INT_ST_WAKEUP_SDMMC0_INT_ST_SHIFT (6U)
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#define PMU_WAKEUP_INT_ST_WAKEUP_SDMMC0_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_SDMMC0_INT_ST_SHIFT) /* 0x00000040 */
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#define PMU_WAKEUP_INT_ST_WAKEUP_SDMMC1_INT_ST_SHIFT (7U)
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#define PMU_WAKEUP_INT_ST_WAKEUP_SDMMC1_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_SDMMC1_INT_ST_SHIFT) /* 0x00000080 */
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#define PMU_WAKEUP_INT_ST_WAKEUP_SDMMC2_INT_ST_SHIFT (8U)
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#define PMU_WAKEUP_INT_ST_WAKEUP_SDMMC2_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_SDMMC2_INT_ST_SHIFT) /* 0x00000100 */
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#define PMU_WAKEUP_INT_ST_WAKEUP_USB_INT_ST_SHIFT (9U)
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#define PMU_WAKEUP_INT_ST_WAKEUP_USB_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_USB_INT_ST_SHIFT) /* 0x00000200 */
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#define PMU_WAKEUP_INT_ST_WAKEUP_PCIE_INT_ST_SHIFT (10U)
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#define PMU_WAKEUP_INT_ST_WAKEUP_PCIE_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_PCIE_INT_ST_SHIFT) /* 0x00000400 */
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#define PMU_WAKEUP_INT_ST_WAKEUP_VAD_INT_ST_SHIFT (11U)
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#define PMU_WAKEUP_INT_ST_WAKEUP_VAD_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_VAD_INT_ST_SHIFT) /* 0x00000800 */
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#define PMU_WAKEUP_INT_ST_WAKEUP_TIMER_INT_ST_SHIFT (12U)
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#define PMU_WAKEUP_INT_ST_WAKEUP_TIMER_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_TIMER_INT_ST_SHIFT) /* 0x00001000 */
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#define PMU_WAKEUP_INT_ST_WAKEUP_PWM0_INT_ST_SHIFT (13U)
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#define PMU_WAKEUP_INT_ST_WAKEUP_PWM0_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_PWM0_INT_ST_SHIFT) /* 0x00002000 */
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#define PMU_WAKEUP_INT_ST_WAKEUP_TIMEOUT_INT_ST_SHIFT (14U)
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#define PMU_WAKEUP_INT_ST_WAKEUP_TIMEOUT_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_TIMEOUT_INT_ST_SHIFT) /* 0x00004000 */
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#define PMU_WAKEUP_INT_ST_WAKEUP_SYS_INT_ST_SHIFT (15U)
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#define PMU_WAKEUP_INT_ST_WAKEUP_SYS_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_SYS_INT_ST_SHIFT) /* 0x00008000 */
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/* WAKEUP_EDGE_CON */
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#define PMU_WAKEUP_EDGE_CON_OFFSET (0x18U)
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#define PMU_WAKEUP_EDGE_CON_EDGE_WAKEUP_EN_SHIFT (0U)
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#define PMU_WAKEUP_EDGE_CON_EDGE_WAKEUP_EN_MASK (0xFFFFFFFFU << PMU_WAKEUP_EDGE_CON_EDGE_WAKEUP_EN_SHIFT) /* 0xFFFFFFFF */
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/* WAKEUP_EDGE_ST */
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#define PMU_WAKEUP_EDGE_ST_OFFSET (0x1CU)
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#define PMU_WAKEUP_EDGE_ST_EDGE_STATUS_SHIFT (0U)
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#define PMU_WAKEUP_EDGE_ST_EDGE_STATUS_MASK (0xFFFFFFFFU << PMU_WAKEUP_EDGE_ST_EDGE_STATUS_SHIFT) /* 0xFFFFFFFF */
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/* BUS_IDLE_CON0 */
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#define PMU_BUS_IDLE_CON0_OFFSET (0x40U)
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_MSCH_SHIFT (0U)
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_MSCH_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_MSCH_SHIFT) /* 0x00000001 */
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_GPU_SHIFT (1U)
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_GPU_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_GPU_SHIFT) /* 0x00000002 */
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_NPU_SHIFT (2U)
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_NPU_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_NPU_SHIFT) /* 0x00000004 */
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_VI_SHIFT (3U)
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_VI_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_VI_SHIFT) /* 0x00000008 */
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_VO_SHIFT (4U)
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_VO_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_VO_SHIFT) /* 0x00000010 */
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_RGA_SHIFT (5U)
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_RGA_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_RGA_SHIFT) /* 0x00000020 */
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_VPU_SHIFT (6U)
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_VPU_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_VPU_SHIFT) /* 0x00000040 */
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_RKVENC_SHIFT (7U)
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_RKVENC_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_RKVENC_SHIFT) /* 0x00000080 */
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_RKVDEC_SHIFT (8U)
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_RKVDEC_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_RKVDEC_SHIFT) /* 0x00000100 */
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_GIC_AUDIO_SHIFT (9U)
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_GIC_AUDIO_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_GIC_AUDIO_SHIFT) /* 0x00000200 */
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_PHP_SHIFT (10U)
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_PHP_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_PHP_SHIFT) /* 0x00000400 */
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_PIPE_SHIFT (11U)
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_PIPE_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_PIPE_SHIFT) /* 0x00000800 */
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_SECURE_FLASH_SHIFT (12U)
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_SECURE_FLASH_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_SECURE_FLASH_SHIFT) /* 0x00001000 */
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_PERIMID_SHIFT (13U)
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_PERIMID_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_PERIMID_SHIFT) /* 0x00002000 */
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_USB_SHIFT (14U)
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_USB_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_USB_SHIFT) /* 0x00004000 */
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_BUS_SHIFT (15U)
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#define PMU_BUS_IDLE_CON0_IDLE_REQ_BUS_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_BUS_SHIFT) /* 0x00008000 */
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/* BUS_IDLE_CON1 */
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#define PMU_BUS_IDLE_CON1_OFFSET (0x44U)
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#define PMU_BUS_IDLE_CON1_IDLE_REQ_TOP1_SHIFT (0U)
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#define PMU_BUS_IDLE_CON1_IDLE_REQ_TOP1_MASK (0x1U << PMU_BUS_IDLE_CON1_IDLE_REQ_TOP1_SHIFT) /* 0x00000001 */
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#define PMU_BUS_IDLE_CON1_IDLE_REQ_TOP2_SHIFT (1U)
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#define PMU_BUS_IDLE_CON1_IDLE_REQ_TOP2_MASK (0x1U << PMU_BUS_IDLE_CON1_IDLE_REQ_TOP2_SHIFT) /* 0x00000002 */
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#define PMU_BUS_IDLE_CON1_IDLE_REQ_PMU_SHIFT (2U)
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#define PMU_BUS_IDLE_CON1_IDLE_REQ_PMU_MASK (0x1U << PMU_BUS_IDLE_CON1_IDLE_REQ_PMU_SHIFT) /* 0x00000004 */
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/* BUS_IDLE_SFTCON0 */
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#define PMU_BUS_IDLE_SFTCON0_OFFSET (0x50U)
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_MSCH_SHIFT (0U)
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_MSCH_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_MSCH_SHIFT) /* 0x00000001 */
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_GPU_SHIFT (1U)
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_GPU_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_GPU_SHIFT) /* 0x00000002 */
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_NPU_SHIFT (2U)
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_NPU_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_NPU_SHIFT) /* 0x00000004 */
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_VI_SHIFT (3U)
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_VI_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_VI_SHIFT) /* 0x00000008 */
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_VO_SHIFT (4U)
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_VO_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_VO_SHIFT) /* 0x00000010 */
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_RGA_SHIFT (5U)
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_RGA_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_RGA_SHIFT) /* 0x00000020 */
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_VPU_SHIFT (6U)
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_VPU_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_VPU_SHIFT) /* 0x00000040 */
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_RKVENC_SHIFT (7U)
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_RKVENC_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_RKVENC_SHIFT) /* 0x00000080 */
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_RKVDEC_SHIFT (8U)
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_RKVDEC_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_RKVDEC_SHIFT) /* 0x00000100 */
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_GIC_AUDIO_SHIFT (9U)
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_GIC_AUDIO_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_GIC_AUDIO_SHIFT) /* 0x00000200 */
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_PHP_SHIFT (10U)
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_PHP_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_PHP_SHIFT) /* 0x00000400 */
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_PIPE_SHIFT (11U)
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_PIPE_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_PIPE_SHIFT) /* 0x00000800 */
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_SECURE_FLASH_SHIFT (12U)
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_SECURE_FLASH_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_SECURE_FLASH_SHIFT) /* 0x00001000 */
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_PERIMID_SHIFT (13U)
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_PERIMID_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_PERIMID_SHIFT) /* 0x00002000 */
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_USB_SHIFT (14U)
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_USB_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_USB_SHIFT) /* 0x00004000 */
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_BUS_SHIFT (15U)
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#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_BUS_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_BUS_SHIFT) /* 0x00008000 */
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/* BUS_IDLE_SFTCON1 */
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#define PMU_BUS_IDLE_SFTCON1_OFFSET (0x54U)
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#define PMU_BUS_IDLE_SFTCON1_IDLE_REQ_TOP1_SHIFT (0U)
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#define PMU_BUS_IDLE_SFTCON1_IDLE_REQ_TOP1_MASK (0x1U << PMU_BUS_IDLE_SFTCON1_IDLE_REQ_TOP1_SHIFT) /* 0x00000001 */
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#define PMU_BUS_IDLE_SFTCON1_IDLE_REQ_TOP2_SHIFT (1U)
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#define PMU_BUS_IDLE_SFTCON1_IDLE_REQ_TOP2_MASK (0x1U << PMU_BUS_IDLE_SFTCON1_IDLE_REQ_TOP2_SHIFT) /* 0x00000002 */
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#define PMU_BUS_IDLE_SFTCON1_IDLE_REQ_PMU_SHIFT (2U)
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#define PMU_BUS_IDLE_SFTCON1_IDLE_REQ_PMU_MASK (0x1U << PMU_BUS_IDLE_SFTCON1_IDLE_REQ_PMU_SHIFT) /* 0x00000004 */
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/* BUS_IDLE_ACK */
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#define PMU_BUS_IDLE_ACK_OFFSET (0x60U)
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#define PMU_BUS_IDLE_ACK (0x0U)
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_MSCH_SHIFT (0U)
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_MSCH_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_MSCH_SHIFT) /* 0x00000001 */
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_GPU_SHIFT (1U)
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_GPU_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_GPU_SHIFT) /* 0x00000002 */
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_NPU_SHIFT (2U)
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_NPU_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_NPU_SHIFT) /* 0x00000004 */
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_VI_SHIFT (3U)
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_VI_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_VI_SHIFT) /* 0x00000008 */
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_VO_SHIFT (4U)
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_VO_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_VO_SHIFT) /* 0x00000010 */
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_RGA_SHIFT (5U)
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_RGA_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_RGA_SHIFT) /* 0x00000020 */
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_VPU_SHIFT (6U)
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_VPU_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_VPU_SHIFT) /* 0x00000040 */
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_RKVENC_SHIFT (7U)
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_RKVENC_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_RKVENC_SHIFT) /* 0x00000080 */
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_RKVDEC_SHIFT (8U)
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_RKVDEC_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_RKVDEC_SHIFT) /* 0x00000100 */
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_GIC_AUDIO_SHIFT (9U)
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_GIC_AUDIO_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_GIC_AUDIO_SHIFT) /* 0x00000200 */
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_PHP_SHIFT (10U)
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_PHP_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_PHP_SHIFT) /* 0x00000400 */
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_PIPE_SHIFT (11U)
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_PIPE_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_PIPE_SHIFT) /* 0x00000800 */
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_SECURE_FLASH_SHIFT (12U)
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_SECURE_FLASH_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_SECURE_FLASH_SHIFT) /* 0x00001000 */
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_PERIMID_SHIFT (13U)
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_PERIMID_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_PERIMID_SHIFT) /* 0x00002000 */
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_USB_SHIFT (14U)
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_USB_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_USB_SHIFT) /* 0x00004000 */
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_BUS_SHIFT (15U)
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_BUS_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_BUS_SHIFT) /* 0x00008000 */
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_TOP1_SHIFT (16U)
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_TOP1_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_TOP1_SHIFT) /* 0x00010000 */
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_TOP2_SHIFT (17U)
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_TOP2_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_TOP2_SHIFT) /* 0x00020000 */
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_PMU_SHIFT (18U)
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#define PMU_BUS_IDLE_ACK_IDLE_ACK_PMU_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_PMU_SHIFT) /* 0x00040000 */
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/* BUS_IDLE_ST */
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#define PMU_BUS_IDLE_ST_OFFSET (0x68U)
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#define PMU_BUS_IDLE_ST (0x0U)
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#define PMU_BUS_IDLE_ST_IDLE_MSCH_SHIFT (0U)
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#define PMU_BUS_IDLE_ST_IDLE_MSCH_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_MSCH_SHIFT) /* 0x00000001 */
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#define PMU_BUS_IDLE_ST_IDLE_GPU_SHIFT (1U)
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#define PMU_BUS_IDLE_ST_IDLE_GPU_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_GPU_SHIFT) /* 0x00000002 */
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#define PMU_BUS_IDLE_ST_IDLE_NPU_SHIFT (2U)
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#define PMU_BUS_IDLE_ST_IDLE_NPU_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_NPU_SHIFT) /* 0x00000004 */
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#define PMU_BUS_IDLE_ST_IDLE_VI_SHIFT (3U)
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#define PMU_BUS_IDLE_ST_IDLE_VI_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_VI_SHIFT) /* 0x00000008 */
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#define PMU_BUS_IDLE_ST_IDLE_VO_SHIFT (4U)
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#define PMU_BUS_IDLE_ST_IDLE_VO_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_VO_SHIFT) /* 0x00000010 */
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#define PMU_BUS_IDLE_ST_IDLE_RGA_SHIFT (5U)
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#define PMU_BUS_IDLE_ST_IDLE_RGA_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_RGA_SHIFT) /* 0x00000020 */
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#define PMU_BUS_IDLE_ST_IDLE_VPU_SHIFT (6U)
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#define PMU_BUS_IDLE_ST_IDLE_VPU_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_VPU_SHIFT) /* 0x00000040 */
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#define PMU_BUS_IDLE_ST_IDLE_RKVENC_SHIFT (7U)
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#define PMU_BUS_IDLE_ST_IDLE_RKVENC_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_RKVENC_SHIFT) /* 0x00000080 */
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#define PMU_BUS_IDLE_ST_IDLE_RKVDEC_SHIFT (8U)
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#define PMU_BUS_IDLE_ST_IDLE_RKVDEC_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_RKVDEC_SHIFT) /* 0x00000100 */
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#define PMU_BUS_IDLE_ST_IDLE_GIC_AUDIO_SHIFT (9U)
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#define PMU_BUS_IDLE_ST_IDLE_GIC_AUDIO_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_GIC_AUDIO_SHIFT) /* 0x00000200 */
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#define PMU_BUS_IDLE_ST_IDLE_PHP_SHIFT (10U)
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#define PMU_BUS_IDLE_ST_IDLE_PHP_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_PHP_SHIFT) /* 0x00000400 */
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#define PMU_BUS_IDLE_ST_IDLE_PIPE_SHIFT (11U)
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#define PMU_BUS_IDLE_ST_IDLE_PIPE_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_PIPE_SHIFT) /* 0x00000800 */
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#define PMU_BUS_IDLE_ST_IDLE_SECURE_FLASH_SHIFT (12U)
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#define PMU_BUS_IDLE_ST_IDLE_SECURE_FLASH_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_SECURE_FLASH_SHIFT) /* 0x00001000 */
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#define PMU_BUS_IDLE_ST_IDLE_PERIMID_SHIFT (13U)
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#define PMU_BUS_IDLE_ST_IDLE_PERIMID_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_PERIMID_SHIFT) /* 0x00002000 */
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#define PMU_BUS_IDLE_ST_IDLE_USB_SHIFT (14U)
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#define PMU_BUS_IDLE_ST_IDLE_USB_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_USB_SHIFT) /* 0x00004000 */
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#define PMU_BUS_IDLE_ST_IDLE_BUS_SHIFT (15U)
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#define PMU_BUS_IDLE_ST_IDLE_BUS_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_BUS_SHIFT) /* 0x00008000 */
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#define PMU_BUS_IDLE_ST_IDLE_TOP1_SHIFT (16U)
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#define PMU_BUS_IDLE_ST_IDLE_TOP1_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_TOP1_SHIFT) /* 0x00010000 */
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#define PMU_BUS_IDLE_ST_IDLE_TOP2_SHIFT (17U)
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#define PMU_BUS_IDLE_ST_IDLE_TOP2_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_TOP2_SHIFT) /* 0x00020000 */
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#define PMU_BUS_IDLE_ST_IDLE_PMU_SHIFT (18U)
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#define PMU_BUS_IDLE_ST_IDLE_PMU_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_PMU_SHIFT) /* 0x00040000 */
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/* NOC_AUTO_CON0 */
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#define PMU_NOC_AUTO_CON0_OFFSET (0x70U)
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_MSCH_SHIFT (0U)
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_MSCH_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_MSCH_SHIFT) /* 0x00000001 */
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_GPU_SHIFT (1U)
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_GPU_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_GPU_SHIFT) /* 0x00000002 */
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_NPU_SHIFT (2U)
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_NPU_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_NPU_SHIFT) /* 0x00000004 */
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_VI_SHIFT (3U)
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_VI_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_VI_SHIFT) /* 0x00000008 */
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_VO_SHIFT (4U)
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_VO_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_VO_SHIFT) /* 0x00000010 */
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_RGA_SHIFT (5U)
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_RGA_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_RGA_SHIFT) /* 0x00000020 */
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_VPU_SHIFT (6U)
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_VPU_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_VPU_SHIFT) /* 0x00000040 */
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_RKVENC_SHIFT (7U)
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_RKVENC_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_RKVENC_SHIFT) /* 0x00000080 */
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_RKVDEC_SHIFT (8U)
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_RKVDEC_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_RKVDEC_SHIFT) /* 0x00000100 */
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_GIC_AUDIO_SHIFT (9U)
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_GIC_AUDIO_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_GIC_AUDIO_SHIFT) /* 0x00000200 */
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_PHP_SHIFT (10U)
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_PHP_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_PHP_SHIFT) /* 0x00000400 */
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_PIPE_SHIFT (11U)
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_PIPE_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_PIPE_SHIFT) /* 0x00000800 */
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_SECURE_FLASH_SHIFT (12U)
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_SECURE_FLASH_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_SECURE_FLASH_SHIFT) /* 0x00001000 */
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_PERIMID_SHIFT (13U)
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_PERIMID_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_PERIMID_SHIFT) /* 0x00002000 */
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_USB_SHIFT (14U)
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_USB_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_USB_SHIFT) /* 0x00004000 */
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_BUS_SHIFT (15U)
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#define PMU_NOC_AUTO_CON0_AUTO_IDLE_BUS_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_BUS_SHIFT) /* 0x00008000 */
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/* NOC_AUTO_CON1 */
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#define PMU_NOC_AUTO_CON1_OFFSET (0x74U)
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#define PMU_NOC_AUTO_CON1_AUTO_IDLE_TOP1_SHIFT (0U)
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#define PMU_NOC_AUTO_CON1_AUTO_IDLE_TOP1_MASK (0x1U << PMU_NOC_AUTO_CON1_AUTO_IDLE_TOP1_SHIFT) /* 0x00000001 */
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#define PMU_NOC_AUTO_CON1_AUTO_IDLE_TOP2_SHIFT (1U)
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#define PMU_NOC_AUTO_CON1_AUTO_IDLE_TOP2_MASK (0x1U << PMU_NOC_AUTO_CON1_AUTO_IDLE_TOP2_SHIFT) /* 0x00000002 */
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#define PMU_NOC_AUTO_CON1_AUTO_IDLE_PMU_SHIFT (2U)
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#define PMU_NOC_AUTO_CON1_AUTO_IDLE_PMU_MASK (0x1U << PMU_NOC_AUTO_CON1_AUTO_IDLE_PMU_SHIFT) /* 0x00000004 */
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#define PMU_NOC_AUTO_CON1_AUTO_IDLE_CPU_SHIFT (3U)
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#define PMU_NOC_AUTO_CON1_AUTO_IDLE_CPU_MASK (0x1U << PMU_NOC_AUTO_CON1_AUTO_IDLE_CPU_SHIFT) /* 0x00000008 */
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/* DDR_PWR_CON */
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#define PMU_DDR_PWR_CON_OFFSET (0x80U)
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#define PMU_DDR_PWR_CON_DDR_SREF_ENA_SHIFT (0U)
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#define PMU_DDR_PWR_CON_DDR_SREF_ENA_MASK (0x1U << PMU_DDR_PWR_CON_DDR_SREF_ENA_SHIFT) /* 0x00000001 */
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#define PMU_DDR_PWR_CON_DDRIO_RET_ENA_SHIFT (1U)
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#define PMU_DDR_PWR_CON_DDRIO_RET_ENA_MASK (0x1U << PMU_DDR_PWR_CON_DDRIO_RET_ENA_SHIFT) /* 0x00000002 */
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#define PMU_DDR_PWR_CON_DDRPHY_AUTO_GATING_ENA_SHIFT (4U)
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#define PMU_DDR_PWR_CON_DDRPHY_AUTO_GATING_ENA_MASK (0x1U << PMU_DDR_PWR_CON_DDRPHY_AUTO_GATING_ENA_SHIFT) /* 0x00000010 */
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/* DDR_PWR_SFTCON */
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#define PMU_DDR_PWR_SFTCON_OFFSET (0x84U)
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#define PMU_DDR_PWR_SFTCON_SW_DDR_SREF_REQ_SHIFT (0U)
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#define PMU_DDR_PWR_SFTCON_SW_DDR_SREF_REQ_MASK (0x1U << PMU_DDR_PWR_SFTCON_SW_DDR_SREF_REQ_SHIFT) /* 0x00000001 */
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#define PMU_DDR_PWR_SFTCON_SW_DDRIO_RET_REQ_SHIFT (1U)
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#define PMU_DDR_PWR_SFTCON_SW_DDRIO_RET_REQ_MASK (0x1U << PMU_DDR_PWR_SFTCON_SW_DDRIO_RET_REQ_SHIFT) /* 0x00000002 */
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#define PMU_DDR_PWR_SFTCON_SW_DDRIO_RET_EXIT_SHIFT (2U)
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#define PMU_DDR_PWR_SFTCON_SW_DDRIO_RET_EXIT_MASK (0x1U << PMU_DDR_PWR_SFTCON_SW_DDRIO_RET_EXIT_SHIFT) /* 0x00000004 */
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#define PMU_DDR_PWR_SFTCON_DDRCTL_ACTIVE_WAIT_SHIFT (3U)
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#define PMU_DDR_PWR_SFTCON_DDRCTL_ACTIVE_WAIT_MASK (0x1U << PMU_DDR_PWR_SFTCON_DDRCTL_ACTIVE_WAIT_SHIFT) /* 0x00000008 */
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/* DDR_PWR_STATE */
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#define PMU_DDR_PWR_STATE_OFFSET (0x88U)
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#define PMU_DDR_PWR_STATE (0x0U)
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#define PMU_DDR_PWR_STATE_DDR_POWER_STATE_SHIFT (0U)
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#define PMU_DDR_PWR_STATE_DDR_POWER_STATE_MASK (0x7U << PMU_DDR_PWR_STATE_DDR_POWER_STATE_SHIFT) /* 0x00000007 */
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/* DDR_PWR_ST */
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#define PMU_DDR_PWR_ST_OFFSET (0x8CU)
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#define PMU_DDR_PWR_ST (0x2U)
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#define PMU_DDR_PWR_ST_DDRCTL_C_SYSACK_SHIFT (0U)
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#define PMU_DDR_PWR_ST_DDRCTL_C_SYSACK_MASK (0x1U << PMU_DDR_PWR_ST_DDRCTL_C_SYSACK_SHIFT) /* 0x00000001 */
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#define PMU_DDR_PWR_ST_DDRCTL_C_ACTIVE_SHIFT (1U)
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#define PMU_DDR_PWR_ST_DDRCTL_C_ACTIVE_MASK (0x1U << PMU_DDR_PWR_ST_DDRCTL_C_ACTIVE_SHIFT) /* 0x00000002 */
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#define PMU_DDR_PWR_ST_DDRIO_RET_SHIFT (2U)
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#define PMU_DDR_PWR_ST_DDRIO_RET_MASK (0x1U << PMU_DDR_PWR_ST_DDRIO_RET_SHIFT) /* 0x00000004 */
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/* PWR_GATE_CON */
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#define PMU_PWR_GATE_CON_OFFSET (0x90U)
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#define PMU_PWR_GATE_CON_PD_GPU_DWN_ENA_SHIFT (0U)
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#define PMU_PWR_GATE_CON_PD_GPU_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON_PD_GPU_DWN_ENA_SHIFT) /* 0x00000001 */
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#define PMU_PWR_GATE_CON_PD_NPU_DWN_ENA_SHIFT (1U)
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#define PMU_PWR_GATE_CON_PD_NPU_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON_PD_NPU_DWN_ENA_SHIFT) /* 0x00000002 */
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#define PMU_PWR_GATE_CON_PD_VPU_DWN_ENA_SHIFT (2U)
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#define PMU_PWR_GATE_CON_PD_VPU_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON_PD_VPU_DWN_ENA_SHIFT) /* 0x00000004 */
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#define PMU_PWR_GATE_CON_PD_RKVENC_DWN_ENA_SHIFT (3U)
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#define PMU_PWR_GATE_CON_PD_RKVENC_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON_PD_RKVENC_DWN_ENA_SHIFT) /* 0x00000008 */
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#define PMU_PWR_GATE_CON_PD_RKVDEC_DWN_ENA_SHIFT (4U)
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#define PMU_PWR_GATE_CON_PD_RKVDEC_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON_PD_RKVDEC_DWN_ENA_SHIFT) /* 0x00000010 */
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#define PMU_PWR_GATE_CON_PD_RGA_DWN_ENA_SHIFT (5U)
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#define PMU_PWR_GATE_CON_PD_RGA_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON_PD_RGA_DWN_ENA_SHIFT) /* 0x00000020 */
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#define PMU_PWR_GATE_CON_PD_VI_DWN_ENA_SHIFT (6U)
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#define PMU_PWR_GATE_CON_PD_VI_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON_PD_VI_DWN_ENA_SHIFT) /* 0x00000040 */
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#define PMU_PWR_GATE_CON_PD_VO_DWN_ENA_SHIFT (7U)
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#define PMU_PWR_GATE_CON_PD_VO_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON_PD_VO_DWN_ENA_SHIFT) /* 0x00000080 */
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#define PMU_PWR_GATE_CON_PD_PIPE_DWN_ENA_SHIFT (8U)
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#define PMU_PWR_GATE_CON_PD_PIPE_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON_PD_PIPE_DWN_ENA_SHIFT) /* 0x00000100 */
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#define PMU_PWR_GATE_CON_PD_DDR_DWN_ENA_SHIFT (9U)
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#define PMU_PWR_GATE_CON_PD_DDR_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON_PD_DDR_DWN_ENA_SHIFT) /* 0x00000200 */
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/* PWR_GATE_STATE */
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#define PMU_PWR_GATE_STATE_OFFSET (0x94U)
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#define PMU_PWR_GATE_STATE (0x0U)
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#define PMU_PWR_GATE_STATE_POWER_GATE_STATE_SHIFT (0U)
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#define PMU_PWR_GATE_STATE_POWER_GATE_STATE_MASK (0x7U << PMU_PWR_GATE_STATE_POWER_GATE_STATE_SHIFT) /* 0x00000007 */
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/* PWR_DWN_ST */
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#define PMU_PWR_DWN_ST_OFFSET (0x98U)
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#define PMU_PWR_DWN_ST (0x0U)
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#define PMU_PWR_DWN_ST_PD_GPU_DWN_STAT_SHIFT (0U)
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#define PMU_PWR_DWN_ST_PD_GPU_DWN_STAT_MASK (0x1U << PMU_PWR_DWN_ST_PD_GPU_DWN_STAT_SHIFT) /* 0x00000001 */
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#define PMU_PWR_DWN_ST_PD_NPU_DWN_STAT_SHIFT (1U)
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#define PMU_PWR_DWN_ST_PD_NPU_DWN_STAT_MASK (0x1U << PMU_PWR_DWN_ST_PD_NPU_DWN_STAT_SHIFT) /* 0x00000002 */
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#define PMU_PWR_DWN_ST_PD_VPU_DWN_STAT_SHIFT (2U)
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#define PMU_PWR_DWN_ST_PD_VPU_DWN_STAT_MASK (0x1U << PMU_PWR_DWN_ST_PD_VPU_DWN_STAT_SHIFT) /* 0x00000004 */
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#define PMU_PWR_DWN_ST_PD_RKVENC_DWN_STAT_SHIFT (3U)
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#define PMU_PWR_DWN_ST_PD_RKVENC_DWN_STAT_MASK (0x1U << PMU_PWR_DWN_ST_PD_RKVENC_DWN_STAT_SHIFT) /* 0x00000008 */
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#define PMU_PWR_DWN_ST_PD_RKVDEC_DWN_STAT_SHIFT (4U)
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#define PMU_PWR_DWN_ST_PD_RKVDEC_DWN_STAT_MASK (0x1U << PMU_PWR_DWN_ST_PD_RKVDEC_DWN_STAT_SHIFT) /* 0x00000010 */
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#define PMU_PWR_DWN_ST_PD_RGA_DWN_STAT_SHIFT (5U)
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#define PMU_PWR_DWN_ST_PD_RGA_DWN_STAT_MASK (0x1U << PMU_PWR_DWN_ST_PD_RGA_DWN_STAT_SHIFT) /* 0x00000020 */
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#define PMU_PWR_DWN_ST_PD_VI_DWN_STAT_SHIFT (6U)
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#define PMU_PWR_DWN_ST_PD_VI_DWN_STAT_MASK (0x1U << PMU_PWR_DWN_ST_PD_VI_DWN_STAT_SHIFT) /* 0x00000040 */
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#define PMU_PWR_DWN_ST_PD_VO_DWN_STAT_SHIFT (7U)
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#define PMU_PWR_DWN_ST_PD_VO_DWN_STAT_MASK (0x1U << PMU_PWR_DWN_ST_PD_VO_DWN_STAT_SHIFT) /* 0x00000080 */
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#define PMU_PWR_DWN_ST_PD_PIPE_DWN_STAT_SHIFT (8U)
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#define PMU_PWR_DWN_ST_PD_PIPE_DWN_STAT_MASK (0x1U << PMU_PWR_DWN_ST_PD_PIPE_DWN_STAT_SHIFT) /* 0x00000100 */
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#define PMU_PWR_DWN_ST_PD_DDR_DWN_STAT_SHIFT (9U)
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#define PMU_PWR_DWN_ST_PD_DDR_DWN_STAT_MASK (0x1U << PMU_PWR_DWN_ST_PD_DDR_DWN_STAT_SHIFT) /* 0x00000200 */
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/* PWR_GATE_SFTCON */
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#define PMU_PWR_GATE_SFTCON_OFFSET (0xA0U)
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#define PMU_PWR_GATE_SFTCON_PD_GPU_DWN_ENA_SHIFT (0U)
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#define PMU_PWR_GATE_SFTCON_PD_GPU_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_SFTCON_PD_GPU_DWN_ENA_SHIFT) /* 0x00000001 */
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#define PMU_PWR_GATE_SFTCON_PD_NPU_DWN_ENA_SHIFT (1U)
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#define PMU_PWR_GATE_SFTCON_PD_NPU_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_SFTCON_PD_NPU_DWN_ENA_SHIFT) /* 0x00000002 */
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#define PMU_PWR_GATE_SFTCON_PD_VPU_DWN_ENA_SHIFT (2U)
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#define PMU_PWR_GATE_SFTCON_PD_VPU_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_SFTCON_PD_VPU_DWN_ENA_SHIFT) /* 0x00000004 */
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#define PMU_PWR_GATE_SFTCON_PD_RKVENC_DWN_ENA_SHIFT (3U)
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#define PMU_PWR_GATE_SFTCON_PD_RKVENC_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_SFTCON_PD_RKVENC_DWN_ENA_SHIFT) /* 0x00000008 */
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#define PMU_PWR_GATE_SFTCON_PD_RKVDEC_DWN_ENA_SHIFT (4U)
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#define PMU_PWR_GATE_SFTCON_PD_RKVDEC_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_SFTCON_PD_RKVDEC_DWN_ENA_SHIFT) /* 0x00000010 */
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#define PMU_PWR_GATE_SFTCON_PD_RGA_DWN_ENA_SHIFT (5U)
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#define PMU_PWR_GATE_SFTCON_PD_RGA_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_SFTCON_PD_RGA_DWN_ENA_SHIFT) /* 0x00000020 */
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#define PMU_PWR_GATE_SFTCON_PD_VI_DWN_ENA_SHIFT (6U)
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#define PMU_PWR_GATE_SFTCON_PD_VI_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_SFTCON_PD_VI_DWN_ENA_SHIFT) /* 0x00000040 */
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#define PMU_PWR_GATE_SFTCON_PD_VO_DWN_ENA_SHIFT (7U)
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#define PMU_PWR_GATE_SFTCON_PD_VO_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_SFTCON_PD_VO_DWN_ENA_SHIFT) /* 0x00000080 */
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#define PMU_PWR_GATE_SFTCON_PD_PIPE_DWN_ENA_SHIFT (8U)
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#define PMU_PWR_GATE_SFTCON_PD_PIPE_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_SFTCON_PD_PIPE_DWN_ENA_SHIFT) /* 0x00000100 */
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#define PMU_PWR_GATE_SFTCON_PD_DDR_DWN_ENA_SHIFT (9U)
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#define PMU_PWR_GATE_SFTCON_PD_DDR_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_SFTCON_PD_DDR_DWN_ENA_SHIFT) /* 0x00000200 */
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/* VOL_GATE_SFTCON */
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#define PMU_VOL_GATE_SFTCON_OFFSET (0xA8U)
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#define PMU_VOL_GATE_SFTCON_VD_GPU_ENA_SHIFT (0U)
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#define PMU_VOL_GATE_SFTCON_VD_GPU_ENA_MASK (0x1U << PMU_VOL_GATE_SFTCON_VD_GPU_ENA_SHIFT) /* 0x00000001 */
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#define PMU_VOL_GATE_SFTCON_VD_NPU_ENA_SHIFT (1U)
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#define PMU_VOL_GATE_SFTCON_VD_NPU_ENA_MASK (0x1U << PMU_VOL_GATE_SFTCON_VD_NPU_ENA_SHIFT) /* 0x00000002 */
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/* CRU_PWR_CON */
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#define PMU_CRU_PWR_CON_OFFSET (0xB0U)
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#define PMU_CRU_PWR_CON_ALIVE_32K_ENA_SHIFT (0U)
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#define PMU_CRU_PWR_CON_ALIVE_32K_ENA_MASK (0x1U << PMU_CRU_PWR_CON_ALIVE_32K_ENA_SHIFT) /* 0x00000001 */
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#define PMU_CRU_PWR_CON_OSC_DIS_ENA_SHIFT (1U)
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#define PMU_CRU_PWR_CON_OSC_DIS_ENA_MASK (0x1U << PMU_CRU_PWR_CON_OSC_DIS_ENA_SHIFT) /* 0x00000002 */
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#define PMU_CRU_PWR_CON_WAKEUP_RST_ENA_SHIFT (2U)
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#define PMU_CRU_PWR_CON_WAKEUP_RST_ENA_MASK (0x1U << PMU_CRU_PWR_CON_WAKEUP_RST_ENA_SHIFT) /* 0x00000004 */
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#define PMU_CRU_PWR_CON_INPUT_CLAMP_ENA_SHIFT (3U)
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#define PMU_CRU_PWR_CON_INPUT_CLAMP_ENA_MASK (0x1U << PMU_CRU_PWR_CON_INPUT_CLAMP_ENA_SHIFT) /* 0x00000008 */
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#define PMU_CRU_PWR_CON_ALIVE_OSC_ENA_SHIFT (4U)
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#define PMU_CRU_PWR_CON_ALIVE_OSC_ENA_MASK (0x1U << PMU_CRU_PWR_CON_ALIVE_OSC_ENA_SHIFT) /* 0x00000010 */
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#define PMU_CRU_PWR_CON_POWER_OFF_ENA_SHIFT (5U)
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#define PMU_CRU_PWR_CON_POWER_OFF_ENA_MASK (0x1U << PMU_CRU_PWR_CON_POWER_OFF_ENA_SHIFT) /* 0x00000020 */
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#define PMU_CRU_PWR_CON_PWM_SWITCH_ENA_SHIFT (6U)
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#define PMU_CRU_PWR_CON_PWM_SWITCH_ENA_MASK (0x1U << PMU_CRU_PWR_CON_PWM_SWITCH_ENA_SHIFT) /* 0x00000040 */
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#define PMU_CRU_PWR_CON_PWM_GPIO_IOE_ENA_SHIFT (7U)
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#define PMU_CRU_PWR_CON_PWM_GPIO_IOE_ENA_MASK (0x1U << PMU_CRU_PWR_CON_PWM_GPIO_IOE_ENA_SHIFT) /* 0x00000080 */
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#define PMU_CRU_PWR_CON_PWM_SWITCH_IOUT_SHIFT (8U)
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#define PMU_CRU_PWR_CON_PWM_SWITCH_IOUT_MASK (0x1U << PMU_CRU_PWR_CON_PWM_SWITCH_IOUT_SHIFT) /* 0x00000100 */
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#define PMU_CRU_PWR_CON_PD_BUS_CLK_SRC_GATE_ENA_SHIFT (9U)
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#define PMU_CRU_PWR_CON_PD_BUS_CLK_SRC_GATE_ENA_MASK (0x1U << PMU_CRU_PWR_CON_PD_BUS_CLK_SRC_GATE_ENA_SHIFT) /* 0x00000200 */
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#define PMU_CRU_PWR_CON_PD_PERI_CLK_SRC_GATE_ENA_SHIFT (10U)
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#define PMU_CRU_PWR_CON_PD_PERI_CLK_SRC_GATE_ENA_MASK (0x1U << PMU_CRU_PWR_CON_PD_PERI_CLK_SRC_GATE_ENA_SHIFT) /* 0x00000400 */
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#define PMU_CRU_PWR_CON_PD_PMU_CLK_SRC_GATE_ENA_SHIFT (11U)
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#define PMU_CRU_PWR_CON_PD_PMU_CLK_SRC_GATE_ENA_MASK (0x1U << PMU_CRU_PWR_CON_PD_PMU_CLK_SRC_GATE_ENA_SHIFT) /* 0x00000800 */
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#define PMU_CRU_PWR_CON_PMUMEM_CLK_SRC_GATE_ENA_SHIFT (12U)
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#define PMU_CRU_PWR_CON_PMUMEM_CLK_SRC_GATE_ENA_MASK (0x1U << PMU_CRU_PWR_CON_PMUMEM_CLK_SRC_GATE_ENA_SHIFT) /* 0x00001000 */
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/* CRU_PWR_SFTCON */
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#define PMU_CRU_PWR_SFTCON_OFFSET (0xB4U)
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#define PMU_CRU_PWR_SFTCON_ALIVE_32K_ENA_SHIFT (0U)
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#define PMU_CRU_PWR_SFTCON_ALIVE_32K_ENA_MASK (0x1U << PMU_CRU_PWR_SFTCON_ALIVE_32K_ENA_SHIFT) /* 0x00000001 */
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#define PMU_CRU_PWR_SFTCON_OSC_DIS_ENA_SHIFT (1U)
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#define PMU_CRU_PWR_SFTCON_OSC_DIS_ENA_MASK (0x1U << PMU_CRU_PWR_SFTCON_OSC_DIS_ENA_SHIFT) /* 0x00000002 */
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#define PMU_CRU_PWR_SFTCON_WAKEUP_RST_ENA_SHIFT (2U)
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#define PMU_CRU_PWR_SFTCON_WAKEUP_RST_ENA_MASK (0x1U << PMU_CRU_PWR_SFTCON_WAKEUP_RST_ENA_SHIFT) /* 0x00000004 */
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#define PMU_CRU_PWR_SFTCON_INPUT_CLAMP_ENA_SHIFT (3U)
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#define PMU_CRU_PWR_SFTCON_INPUT_CLAMP_ENA_MASK (0x1U << PMU_CRU_PWR_SFTCON_INPUT_CLAMP_ENA_SHIFT) /* 0x00000008 */
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#define PMU_CRU_PWR_SFTCON_ALIVE_OSC_ENA_SHIFT (4U)
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#define PMU_CRU_PWR_SFTCON_ALIVE_OSC_ENA_MASK (0x1U << PMU_CRU_PWR_SFTCON_ALIVE_OSC_ENA_SHIFT) /* 0x00000010 */
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#define PMU_CRU_PWR_SFTCON_POWER_OFF_ENA_SHIFT (5U)
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#define PMU_CRU_PWR_SFTCON_POWER_OFF_ENA_MASK (0x1U << PMU_CRU_PWR_SFTCON_POWER_OFF_ENA_SHIFT) /* 0x00000020 */
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/* CRU_PWR_STATE */
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#define PMU_CRU_PWR_STATE_OFFSET (0xB8U)
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#define PMU_CRU_PWR_STATE (0x0U)
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#define PMU_CRU_PWR_STATE_CRU_POWER_STATE_SHIFT (0U)
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#define PMU_CRU_PWR_STATE_CRU_POWER_STATE_MASK (0xFU << PMU_CRU_PWR_STATE_CRU_POWER_STATE_SHIFT) /* 0x0000000F */
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/* PLLPD_CON */
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#define PMU_PLLPD_CON_OFFSET (0xC0U)
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#define PMU_PLLPD_CON_APLL_PD_ENA_SHIFT (0U)
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#define PMU_PLLPD_CON_APLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON_APLL_PD_ENA_SHIFT) /* 0x00000001 */
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#define PMU_PLLPD_CON_DPLL_PD_ENA_SHIFT (1U)
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#define PMU_PLLPD_CON_DPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON_DPLL_PD_ENA_SHIFT) /* 0x00000002 */
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#define PMU_PLLPD_CON_CPLL_PD_ENA_SHIFT (2U)
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#define PMU_PLLPD_CON_CPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON_CPLL_PD_ENA_SHIFT) /* 0x00000004 */
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#define PMU_PLLPD_CON_GPLL_PD_ENA_SHIFT (3U)
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#define PMU_PLLPD_CON_GPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON_GPLL_PD_ENA_SHIFT) /* 0x00000008 */
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#define PMU_PLLPD_CON_MPLL_PD_ENA_SHIFT (4U)
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#define PMU_PLLPD_CON_MPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON_MPLL_PD_ENA_SHIFT) /* 0x00000010 */
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#define PMU_PLLPD_CON_NPLL_PD_ENA_SHIFT (5U)
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#define PMU_PLLPD_CON_NPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON_NPLL_PD_ENA_SHIFT) /* 0x00000020 */
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#define PMU_PLLPD_CON_HPLL_PD_ENA_SHIFT (6U)
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#define PMU_PLLPD_CON_HPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON_HPLL_PD_ENA_SHIFT) /* 0x00000040 */
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#define PMU_PLLPD_CON_PPLL_PD_ENA_SHIFT (7U)
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#define PMU_PLLPD_CON_PPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON_PPLL_PD_ENA_SHIFT) /* 0x00000080 */
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#define PMU_PLLPD_CON_VPLL_PD_ENA_SHIFT (8U)
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#define PMU_PLLPD_CON_VPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON_VPLL_PD_ENA_SHIFT) /* 0x00000100 */
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/* PLLPD_SFTCON */
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#define PMU_PLLPD_SFTCON_OFFSET (0xC4U)
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#define PMU_PLLPD_SFTCON_APLL_PD_ENA_SHIFT (0U)
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#define PMU_PLLPD_SFTCON_APLL_PD_ENA_MASK (0x1U << PMU_PLLPD_SFTCON_APLL_PD_ENA_SHIFT) /* 0x00000001 */
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#define PMU_PLLPD_SFTCON_DPLL_PD_ENA_SHIFT (1U)
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#define PMU_PLLPD_SFTCON_DPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_SFTCON_DPLL_PD_ENA_SHIFT) /* 0x00000002 */
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#define PMU_PLLPD_SFTCON_CPLL_PD_ENA_SHIFT (2U)
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#define PMU_PLLPD_SFTCON_CPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_SFTCON_CPLL_PD_ENA_SHIFT) /* 0x00000004 */
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#define PMU_PLLPD_SFTCON_GPLL_PD_ENA_SHIFT (3U)
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#define PMU_PLLPD_SFTCON_GPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_SFTCON_GPLL_PD_ENA_SHIFT) /* 0x00000008 */
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#define PMU_PLLPD_SFTCON_MPLL_PD_ENA_SHIFT (4U)
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#define PMU_PLLPD_SFTCON_MPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_SFTCON_MPLL_PD_ENA_SHIFT) /* 0x00000010 */
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#define PMU_PLLPD_SFTCON_NPLL_PD_ENA_SHIFT (5U)
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#define PMU_PLLPD_SFTCON_NPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_SFTCON_NPLL_PD_ENA_SHIFT) /* 0x00000020 */
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#define PMU_PLLPD_SFTCON_HPLL_PD_ENA_SHIFT (6U)
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#define PMU_PLLPD_SFTCON_HPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_SFTCON_HPLL_PD_ENA_SHIFT) /* 0x00000040 */
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#define PMU_PLLPD_SFTCON_PPLL_PD_ENA_SHIFT (7U)
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#define PMU_PLLPD_SFTCON_PPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_SFTCON_PPLL_PD_ENA_SHIFT) /* 0x00000080 */
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#define PMU_PLLPD_SFTCON_VPLL_PD_ENA_SHIFT (8U)
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#define PMU_PLLPD_SFTCON_VPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_SFTCON_VPLL_PD_ENA_SHIFT) /* 0x00000100 */
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/* INFO_TX_CON */
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#define PMU_INFO_TX_CON_OFFSET (0xD0U)
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#define PMU_INFO_TX_CON_INFO_TX_EN_SHIFT (0U)
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#define PMU_INFO_TX_CON_INFO_TX_EN_MASK (0x1U << PMU_INFO_TX_CON_INFO_TX_EN_SHIFT) /* 0x00000001 */
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#define PMU_INFO_TX_CON_INFO_TX_CON_SHIFT (4U)
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#define PMU_INFO_TX_CON_INFO_TX_CON_MASK (0xFU << PMU_INFO_TX_CON_INFO_TX_CON_SHIFT) /* 0x000000F0 */
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#define PMU_INFO_TX_CON_INFO_TX_INTV_TIME_SHIFT (8U)
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#define PMU_INFO_TX_CON_INFO_TX_INTV_TIME_MASK (0xFFU << PMU_INFO_TX_CON_INFO_TX_INTV_TIME_SHIFT) /* 0x0000FF00 */
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/* DSU_STABLE_CNT */
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#define PMU_DSU_STABLE_CNT_OFFSET (0x100U)
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#define PMU_DSU_STABLE_CNT_STABLE_CNT_SHIFT (0U)
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#define PMU_DSU_STABLE_CNT_STABLE_CNT_MASK (0xFFFFFU << PMU_DSU_STABLE_CNT_STABLE_CNT_SHIFT) /* 0x000FFFFF */
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/* PMIC_STABLE_CNT */
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#define PMU_PMIC_STABLE_CNT_OFFSET (0x104U)
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#define PMU_PMIC_STABLE_CNT_STABLE_CNT_SHIFT (0U)
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#define PMU_PMIC_STABLE_CNT_STABLE_CNT_MASK (0xFFFFFU << PMU_PMIC_STABLE_CNT_STABLE_CNT_SHIFT) /* 0x000FFFFF */
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/* OSC_STABLE_CNT */
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#define PMU_OSC_STABLE_CNT_OFFSET (0x108U)
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#define PMU_OSC_STABLE_CNT_STABLE_CNT_SHIFT (0U)
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#define PMU_OSC_STABLE_CNT_STABLE_CNT_MASK (0xFFFFFU << PMU_OSC_STABLE_CNT_STABLE_CNT_SHIFT) /* 0x000FFFFF */
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/* WAKEUP_RSTCLR_CNT */
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#define PMU_WAKEUP_RSTCLR_CNT_OFFSET (0x10CU)
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#define PMU_WAKEUP_RSTCLR_CNT_WAKEUP_RSTCLR_CNT_SHIFT (0U)
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#define PMU_WAKEUP_RSTCLR_CNT_WAKEUP_RSTCLR_CNT_MASK (0xFFFFFU << PMU_WAKEUP_RSTCLR_CNT_WAKEUP_RSTCLR_CNT_SHIFT) /* 0x000FFFFF */
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/* PLL_LOCK_CNT */
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#define PMU_PLL_LOCK_CNT_OFFSET (0x110U)
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#define PMU_PLL_LOCK_CNT_PLL_LOCK_CNT_SHIFT (0U)
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#define PMU_PLL_LOCK_CNT_PLL_LOCK_CNT_MASK (0xFFFFFU << PMU_PLL_LOCK_CNT_PLL_LOCK_CNT_SHIFT) /* 0x000FFFFF */
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/* DSU_PWRUP_CNT */
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#define PMU_DSU_PWRUP_CNT_OFFSET (0x118U)
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#define PMU_DSU_PWRUP_CNT_STABLE_CNT_SHIFT (0U)
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#define PMU_DSU_PWRUP_CNT_STABLE_CNT_MASK (0xFFFFFU << PMU_DSU_PWRUP_CNT_STABLE_CNT_SHIFT) /* 0x000FFFFF */
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/* DSU_PWRDN_CNT */
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#define PMU_DSU_PWRDN_CNT_OFFSET (0x11CU)
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#define PMU_DSU_PWRDN_CNT_STABLE_CNT_SHIFT (0U)
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#define PMU_DSU_PWRDN_CNT_STABLE_CNT_MASK (0xFFFFFU << PMU_DSU_PWRDN_CNT_STABLE_CNT_SHIFT) /* 0x000FFFFF */
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/* GPU_VOLUP_CNT */
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#define PMU_GPU_VOLUP_CNT_OFFSET (0x120U)
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#define PMU_GPU_VOLUP_CNT_STABLE_CNT_SHIFT (0U)
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#define PMU_GPU_VOLUP_CNT_STABLE_CNT_MASK (0xFFFFFU << PMU_GPU_VOLUP_CNT_STABLE_CNT_SHIFT) /* 0x000FFFFF */
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/* GPU_VOLDN_CNT */
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#define PMU_GPU_VOLDN_CNT_OFFSET (0x124U)
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#define PMU_GPU_VOLDN_CNT_STABLE_CNT_SHIFT (0U)
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#define PMU_GPU_VOLDN_CNT_STABLE_CNT_MASK (0xFFFFFU << PMU_GPU_VOLDN_CNT_STABLE_CNT_SHIFT) /* 0x000FFFFF */
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/* WAKEUP_TIMEOUT_CNT */
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#define PMU_WAKEUP_TIMEOUT_CNT_OFFSET (0x128U)
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#define PMU_WAKEUP_TIMEOUT_CNT_WAKEUP_TIMEOUT_CNT_SHIFT (0U)
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#define PMU_WAKEUP_TIMEOUT_CNT_WAKEUP_TIMEOUT_CNT_MASK (0xFFFFFFFFU << PMU_WAKEUP_TIMEOUT_CNT_WAKEUP_TIMEOUT_CNT_SHIFT) /* 0xFFFFFFFF */
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/* PWM_SWITCH_CNT */
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#define PMU_PWM_SWITCH_CNT_OFFSET (0x12CU)
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#define PMU_PWM_SWITCH_CNT_STABLE_CNT_SHIFT (0U)
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#define PMU_PWM_SWITCH_CNT_STABLE_CNT_MASK (0xFFFFFFFFU << PMU_PWM_SWITCH_CNT_STABLE_CNT_SHIFT) /* 0xFFFFFFFF */
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/* DBG_RST_CNT */
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#define PMU_DBG_RST_CNT_OFFSET (0x130U)
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#define PMU_DBG_RST_CNT_DBG_RST_CNT_SHIFT (0U)
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#define PMU_DBG_RST_CNT_DBG_RST_CNT_MASK (0xFFFFFFFFU << PMU_DBG_RST_CNT_DBG_RST_CNT_SHIFT) /* 0xFFFFFFFF */
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/* SYS_REG0 */
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#define PMU_SYS_REG0_OFFSET (0x180U)
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#define PMU_SYS_REG0_PMU_SYS_REG_SHIFT (0U)
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#define PMU_SYS_REG0_PMU_SYS_REG_MASK (0xFFFFFFFFU << PMU_SYS_REG0_PMU_SYS_REG_SHIFT) /* 0xFFFFFFFF */
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/* SYS_REG1 */
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#define PMU_SYS_REG1_OFFSET (0x184U)
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#define PMU_SYS_REG1_PMU_SYS_REG_SHIFT (0U)
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#define PMU_SYS_REG1_PMU_SYS_REG_MASK (0xFFFFFFFFU << PMU_SYS_REG1_PMU_SYS_REG_SHIFT) /* 0xFFFFFFFF */
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/* SYS_REG2 */
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#define PMU_SYS_REG2_OFFSET (0x188U)
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#define PMU_SYS_REG2_PMU_SYS_REG_SHIFT (0U)
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#define PMU_SYS_REG2_PMU_SYS_REG_MASK (0xFFFFFFFFU << PMU_SYS_REG2_PMU_SYS_REG_SHIFT) /* 0xFFFFFFFF */
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/* SYS_REG3 */
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#define PMU_SYS_REG3_OFFSET (0x18CU)
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#define PMU_SYS_REG3_PMU_SYS_REG_SHIFT (0U)
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#define PMU_SYS_REG3_PMU_SYS_REG_MASK (0xFFFFFFFFU << PMU_SYS_REG3_PMU_SYS_REG_SHIFT) /* 0xFFFFFFFF */
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/* SYS_REG4 */
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#define PMU_SYS_REG4_OFFSET (0x190U)
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#define PMU_SYS_REG4_PMU_SYS_REG_SHIFT (0U)
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#define PMU_SYS_REG4_PMU_SYS_REG_MASK (0xFFFFFFFFU << PMU_SYS_REG4_PMU_SYS_REG_SHIFT) /* 0xFFFFFFFF */
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/* SYS_REG5 */
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#define PMU_SYS_REG5_OFFSET (0x194U)
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#define PMU_SYS_REG5_PMU_SYS_REG_SHIFT (0U)
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#define PMU_SYS_REG5_PMU_SYS_REG_MASK (0xFFFFFFFFU << PMU_SYS_REG5_PMU_SYS_REG_SHIFT) /* 0xFFFFFFFF */
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/* SYS_REG6 */
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#define PMU_SYS_REG6_OFFSET (0x198U)
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#define PMU_SYS_REG6_PMU_SYS_REG_SHIFT (0U)
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#define PMU_SYS_REG6_PMU_SYS_REG_MASK (0xFFFFFFFFU << PMU_SYS_REG6_PMU_SYS_REG_SHIFT) /* 0xFFFFFFFF */
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/* SYS_REG7 */
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#define PMU_SYS_REG7_OFFSET (0x19CU)
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#define PMU_SYS_REG7_PMU_SYS_REG_SHIFT (0U)
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#define PMU_SYS_REG7_PMU_SYS_REG_MASK (0xFFFFFFFFU << PMU_SYS_REG7_PMU_SYS_REG_SHIFT) /* 0xFFFFFFFF */
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/* DSU_PWR_CON */
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#define PMU_DSU_PWR_CON_OFFSET (0x300U)
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#define PMU_DSU_PWR_CON_DSU_PWRDN_ENA_SHIFT (2U)
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#define PMU_DSU_PWR_CON_DSU_PWRDN_ENA_MASK (0x1U << PMU_DSU_PWR_CON_DSU_PWRDN_ENA_SHIFT) /* 0x00000004 */
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#define PMU_DSU_PWR_CON_DSU_PWROFF_ENA_SHIFT (3U)
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#define PMU_DSU_PWR_CON_DSU_PWROFF_ENA_MASK (0x1U << PMU_DSU_PWR_CON_DSU_PWROFF_ENA_SHIFT) /* 0x00000008 */
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#define PMU_DSU_PWR_CON_DSU_RET_ENA_SHIFT (6U)
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#define PMU_DSU_PWR_CON_DSU_RET_ENA_MASK (0x1U << PMU_DSU_PWR_CON_DSU_RET_ENA_SHIFT) /* 0x00000040 */
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#define PMU_DSU_PWR_CON_CLUSTER_CLK_SRC_GATE_ENA_SHIFT (7U)
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#define PMU_DSU_PWR_CON_CLUSTER_CLK_SRC_GATE_ENA_MASK (0x1U << PMU_DSU_PWR_CON_CLUSTER_CLK_SRC_GATE_ENA_SHIFT) /* 0x00000080 */
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/* DSU_PWR_SFTCON */
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#define PMU_DSU_PWR_SFTCON_OFFSET (0x304U)
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#define PMU_DSU_PWR_SFTCON_DSU_PWRDN_ENA_SHIFT (0U)
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#define PMU_DSU_PWR_SFTCON_DSU_PWRDN_ENA_MASK (0x1U << PMU_DSU_PWR_SFTCON_DSU_PWRDN_ENA_SHIFT) /* 0x00000001 */
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#define PMU_DSU_PWR_SFTCON_CLUSTER_CLK_SRC_GATE_CFG_SHIFT (7U)
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#define PMU_DSU_PWR_SFTCON_CLUSTER_CLK_SRC_GATE_CFG_MASK (0x1U << PMU_DSU_PWR_SFTCON_CLUSTER_CLK_SRC_GATE_CFG_SHIFT) /* 0x00000080 */
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/* DSU_AUTO_CON */
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#define PMU_DSU_AUTO_CON_OFFSET (0x308U)
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#define PMU_DSU_AUTO_CON_DSU_LP_ENA_SHIFT (0U)
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#define PMU_DSU_AUTO_CON_DSU_LP_ENA_MASK (0x1U << PMU_DSU_AUTO_CON_DSU_LP_ENA_SHIFT) /* 0x00000001 */
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#define PMU_DSU_AUTO_CON_DSU_INT_WAKEUP_CLUSTER_ENA_SHIFT (1U)
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#define PMU_DSU_AUTO_CON_DSU_INT_WAKEUP_CLUSTER_ENA_MASK (0x1U << PMU_DSU_AUTO_CON_DSU_INT_WAKEUP_CLUSTER_ENA_SHIFT) /* 0x00000002 */
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#define PMU_DSU_AUTO_CON_DSU_INT_MASK_ENA_SHIFT (2U)
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#define PMU_DSU_AUTO_CON_DSU_INT_MASK_ENA_MASK (0x1U << PMU_DSU_AUTO_CON_DSU_INT_MASK_ENA_SHIFT) /* 0x00000004 */
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#define PMU_DSU_AUTO_CON_DSU_SFT_WAKEUP_CLUSTER_ENA_SHIFT (3U)
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#define PMU_DSU_AUTO_CON_DSU_SFT_WAKEUP_CLUSTER_ENA_MASK (0x1U << PMU_DSU_AUTO_CON_DSU_SFT_WAKEUP_CLUSTER_ENA_SHIFT) /* 0x00000008 */
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#define PMU_DSU_AUTO_CON_DSU_AUTO_RET_ENA_SHIFT (4U)
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#define PMU_DSU_AUTO_CON_DSU_AUTO_RET_ENA_MASK (0x1U << PMU_DSU_AUTO_CON_DSU_AUTO_RET_ENA_SHIFT) /* 0x00000010 */
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/* DSU_PWR_STATE */
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#define PMU_DSU_PWR_STATE_OFFSET (0x30CU)
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#define PMU_DSU_PWR_STATE (0x0U)
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#define PMU_DSU_PWR_STATE_CPU0_POWER_STATE_SHIFT (0U)
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#define PMU_DSU_PWR_STATE_CPU0_POWER_STATE_MASK (0x7U << PMU_DSU_PWR_STATE_CPU0_POWER_STATE_SHIFT) /* 0x00000007 */
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#define PMU_DSU_PWR_STATE_CPU1_POWER_STATE_SHIFT (4U)
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#define PMU_DSU_PWR_STATE_CPU1_POWER_STATE_MASK (0x7U << PMU_DSU_PWR_STATE_CPU1_POWER_STATE_SHIFT) /* 0x00000070 */
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#define PMU_DSU_PWR_STATE_CPU2_POWER_STATE_SHIFT (8U)
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#define PMU_DSU_PWR_STATE_CPU2_POWER_STATE_MASK (0x7U << PMU_DSU_PWR_STATE_CPU2_POWER_STATE_SHIFT) /* 0x00000700 */
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#define PMU_DSU_PWR_STATE_CPU3_POWER_STATE_SHIFT (12U)
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#define PMU_DSU_PWR_STATE_CPU3_POWER_STATE_MASK (0x7U << PMU_DSU_PWR_STATE_CPU3_POWER_STATE_SHIFT) /* 0x00007000 */
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#define PMU_DSU_PWR_STATE_DSU_POWER_STATE_SHIFT (16U)
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#define PMU_DSU_PWR_STATE_DSU_POWER_STATE_MASK (0x7U << PMU_DSU_PWR_STATE_DSU_POWER_STATE_SHIFT) /* 0x00070000 */
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/* CPU_AUTO_PWR_CON0 */
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#define PMU_CPU_AUTO_PWR_CON0_OFFSET (0x310U)
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#define PMU_CPU_AUTO_PWR_CON0_CPU0_AUTO_PWRDN_ENA_SHIFT (0U)
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#define PMU_CPU_AUTO_PWR_CON0_CPU0_AUTO_PWRDN_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU0_AUTO_PWRDN_ENA_SHIFT) /* 0x00000001 */
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#define PMU_CPU_AUTO_PWR_CON0_CPU0_INT_WAKEUP_ENA_SHIFT (1U)
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#define PMU_CPU_AUTO_PWR_CON0_CPU0_INT_WAKEUP_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU0_INT_WAKEUP_ENA_SHIFT) /* 0x00000002 */
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#define PMU_CPU_AUTO_PWR_CON0_CPU0_INT_MASK_ENA_SHIFT (2U)
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#define PMU_CPU_AUTO_PWR_CON0_CPU0_INT_MASK_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU0_INT_MASK_ENA_SHIFT) /* 0x00000004 */
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#define PMU_CPU_AUTO_PWR_CON0_CPU0_SFT_WAKEUP_PWRDN_ENA_SHIFT (3U)
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#define PMU_CPU_AUTO_PWR_CON0_CPU0_SFT_WAKEUP_PWRDN_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU0_SFT_WAKEUP_PWRDN_ENA_SHIFT) /* 0x00000008 */
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#define PMU_CPU_AUTO_PWR_CON0_CPU0_AUTO_RET_ENA_SHIFT (4U)
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#define PMU_CPU_AUTO_PWR_CON0_CPU0_AUTO_RET_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU0_AUTO_RET_ENA_SHIFT) /* 0x00000010 */
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#define PMU_CPU_AUTO_PWR_CON0_CPU0_SFT_WAKEUP_RET_ENA_SHIFT (5U)
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#define PMU_CPU_AUTO_PWR_CON0_CPU0_SFT_WAKEUP_RET_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU0_SFT_WAKEUP_RET_ENA_SHIFT) /* 0x00000020 */
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#define PMU_CPU_AUTO_PWR_CON0_CPU0_DBG_RECOV_ENA_SHIFT (6U)
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#define PMU_CPU_AUTO_PWR_CON0_CPU0_DBG_RECOV_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU0_DBG_RECOV_ENA_SHIFT) /* 0x00000040 */
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#define PMU_CPU_AUTO_PWR_CON0_CPU0_DBG_RECOV_RSTSRC_SHIFT (7U)
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#define PMU_CPU_AUTO_PWR_CON0_CPU0_DBG_RECOV_RSTSRC_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU0_DBG_RECOV_RSTSRC_SHIFT) /* 0x00000080 */
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#define PMU_CPU_AUTO_PWR_CON0_CPU1_AUTO_PWRDN_ENA_SHIFT (8U)
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#define PMU_CPU_AUTO_PWR_CON0_CPU1_AUTO_PWRDN_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU1_AUTO_PWRDN_ENA_SHIFT) /* 0x00000100 */
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#define PMU_CPU_AUTO_PWR_CON0_CPU1_INT_WAKEUP_ENA_SHIFT (9U)
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#define PMU_CPU_AUTO_PWR_CON0_CPU1_INT_WAKEUP_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU1_INT_WAKEUP_ENA_SHIFT) /* 0x00000200 */
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#define PMU_CPU_AUTO_PWR_CON0_CPU1_INT_MASK_ENA_SHIFT (10U)
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#define PMU_CPU_AUTO_PWR_CON0_CPU1_INT_MASK_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU1_INT_MASK_ENA_SHIFT) /* 0x00000400 */
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#define PMU_CPU_AUTO_PWR_CON0_CPU1_SFT_WAKEUP_PWRDN_ENA_SHIFT (11U)
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#define PMU_CPU_AUTO_PWR_CON0_CPU1_SFT_WAKEUP_PWRDN_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU1_SFT_WAKEUP_PWRDN_ENA_SHIFT) /* 0x00000800 */
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#define PMU_CPU_AUTO_PWR_CON0_CPU1_AUTO_RET_ENA_SHIFT (12U)
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#define PMU_CPU_AUTO_PWR_CON0_CPU1_AUTO_RET_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU1_AUTO_RET_ENA_SHIFT) /* 0x00001000 */
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#define PMU_CPU_AUTO_PWR_CON0_CPU1_SFT_WAKEUP_RET_ENA_SHIFT (13U)
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#define PMU_CPU_AUTO_PWR_CON0_CPU1_SFT_WAKEUP_RET_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU1_SFT_WAKEUP_RET_ENA_SHIFT) /* 0x00002000 */
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#define PMU_CPU_AUTO_PWR_CON0_CPU1_DBG_RECOV_ENA_SHIFT (14U)
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#define PMU_CPU_AUTO_PWR_CON0_CPU1_DBG_RECOV_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU1_DBG_RECOV_ENA_SHIFT) /* 0x00004000 */
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#define PMU_CPU_AUTO_PWR_CON0_CPU1_DBG_RECOV_RSTSRC_SHIFT (15U)
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#define PMU_CPU_AUTO_PWR_CON0_CPU1_DBG_RECOV_RSTSRC_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU1_DBG_RECOV_RSTSRC_SHIFT) /* 0x00008000 */
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/* CPU_AUTO_PWR_CON1 */
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#define PMU_CPU_AUTO_PWR_CON1_OFFSET (0x314U)
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#define PMU_CPU_AUTO_PWR_CON1_CPU2_AUTO_PWRDN_ENA_SHIFT (0U)
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#define PMU_CPU_AUTO_PWR_CON1_CPU2_AUTO_PWRDN_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU2_AUTO_PWRDN_ENA_SHIFT) /* 0x00000001 */
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#define PMU_CPU_AUTO_PWR_CON1_CPU2_INT_WAKEUP_ENA_SHIFT (1U)
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#define PMU_CPU_AUTO_PWR_CON1_CPU2_INT_WAKEUP_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU2_INT_WAKEUP_ENA_SHIFT) /* 0x00000002 */
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#define PMU_CPU_AUTO_PWR_CON1_CPU2_INT_MASK_ENA_SHIFT (2U)
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#define PMU_CPU_AUTO_PWR_CON1_CPU2_INT_MASK_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU2_INT_MASK_ENA_SHIFT) /* 0x00000004 */
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#define PMU_CPU_AUTO_PWR_CON1_CPU2_SFT_WAKEUP_PWRDN_ENA_SHIFT (3U)
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#define PMU_CPU_AUTO_PWR_CON1_CPU2_SFT_WAKEUP_PWRDN_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU2_SFT_WAKEUP_PWRDN_ENA_SHIFT) /* 0x00000008 */
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#define PMU_CPU_AUTO_PWR_CON1_CPU2_AUTO_RET_ENA_SHIFT (4U)
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#define PMU_CPU_AUTO_PWR_CON1_CPU2_AUTO_RET_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU2_AUTO_RET_ENA_SHIFT) /* 0x00000010 */
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#define PMU_CPU_AUTO_PWR_CON1_CPU2_SFT_WAKEUP_RET_ENA_SHIFT (5U)
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#define PMU_CPU_AUTO_PWR_CON1_CPU2_SFT_WAKEUP_RET_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU2_SFT_WAKEUP_RET_ENA_SHIFT) /* 0x00000020 */
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#define PMU_CPU_AUTO_PWR_CON1_CPU2_DBG_RECOV_ENA_SHIFT (6U)
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#define PMU_CPU_AUTO_PWR_CON1_CPU2_DBG_RECOV_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU2_DBG_RECOV_ENA_SHIFT) /* 0x00000040 */
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#define PMU_CPU_AUTO_PWR_CON1_CPU2_DBG_RECOV_RSTSRC_SHIFT (7U)
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#define PMU_CPU_AUTO_PWR_CON1_CPU2_DBG_RECOV_RSTSRC_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU2_DBG_RECOV_RSTSRC_SHIFT) /* 0x00000080 */
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#define PMU_CPU_AUTO_PWR_CON1_CPU3_AUTO_PWRDN_ENA_SHIFT (8U)
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#define PMU_CPU_AUTO_PWR_CON1_CPU3_AUTO_PWRDN_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU3_AUTO_PWRDN_ENA_SHIFT) /* 0x00000100 */
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#define PMU_CPU_AUTO_PWR_CON1_CPU3_INT_WAKEUP_ENA_SHIFT (9U)
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#define PMU_CPU_AUTO_PWR_CON1_CPU3_INT_WAKEUP_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU3_INT_WAKEUP_ENA_SHIFT) /* 0x00000200 */
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#define PMU_CPU_AUTO_PWR_CON1_CPU3_INT_MASK_ENA_SHIFT (10U)
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#define PMU_CPU_AUTO_PWR_CON1_CPU3_INT_MASK_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU3_INT_MASK_ENA_SHIFT) /* 0x00000400 */
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#define PMU_CPU_AUTO_PWR_CON1_CPU3_SFT_WAKEUP_PWRDN_ENA_SHIFT (11U)
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#define PMU_CPU_AUTO_PWR_CON1_CPU3_SFT_WAKEUP_PWRDN_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU3_SFT_WAKEUP_PWRDN_ENA_SHIFT) /* 0x00000800 */
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#define PMU_CPU_AUTO_PWR_CON1_CPU3_AUTO_RET_ENA_SHIFT (12U)
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#define PMU_CPU_AUTO_PWR_CON1_CPU3_AUTO_RET_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU3_AUTO_RET_ENA_SHIFT) /* 0x00001000 */
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#define PMU_CPU_AUTO_PWR_CON1_CPU3_SFT_WAKEUP_RET_ENA_SHIFT (13U)
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#define PMU_CPU_AUTO_PWR_CON1_CPU3_SFT_WAKEUP_RET_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU3_SFT_WAKEUP_RET_ENA_SHIFT) /* 0x00002000 */
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#define PMU_CPU_AUTO_PWR_CON1_CPU3_DBG_RECOV_ENA_SHIFT (14U)
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#define PMU_CPU_AUTO_PWR_CON1_CPU3_DBG_RECOV_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU3_DBG_RECOV_ENA_SHIFT) /* 0x00004000 */
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#define PMU_CPU_AUTO_PWR_CON1_CPU3_DBG_RECOV_RSTSRC_SHIFT (15U)
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#define PMU_CPU_AUTO_PWR_CON1_CPU3_DBG_RECOV_RSTSRC_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU3_DBG_RECOV_RSTSRC_SHIFT) /* 0x00008000 */
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/* CPU_PWR_SFTCON */
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#define PMU_CPU_PWR_SFTCON_OFFSET (0x318U)
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#define PMU_CPU_PWR_SFTCON_CPU0_SFT_PWRDN_ENA_SHIFT (0U)
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#define PMU_CPU_PWR_SFTCON_CPU0_SFT_PWRDN_ENA_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU0_SFT_PWRDN_ENA_SHIFT) /* 0x00000001 */
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#define PMU_CPU_PWR_SFTCON_CPU0_SFT_PREQ_OFF_SHIFT (1U)
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#define PMU_CPU_PWR_SFTCON_CPU0_SFT_PREQ_OFF_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU0_SFT_PREQ_OFF_SHIFT) /* 0x00000002 */
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#define PMU_CPU_PWR_SFTCON_CPU0_SFT_PREQ_ON_SHIFT (2U)
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#define PMU_CPU_PWR_SFTCON_CPU0_SFT_PREQ_ON_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU0_SFT_PREQ_ON_SHIFT) /* 0x00000004 */
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#define PMU_CPU_PWR_SFTCON_CPU0_SFT_PREQ_RET_SHIFT (3U)
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#define PMU_CPU_PWR_SFTCON_CPU0_SFT_PREQ_RET_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU0_SFT_PREQ_RET_SHIFT) /* 0x00000008 */
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#define PMU_CPU_PWR_SFTCON_CPU1_SFT_PWRDN_ENA_SHIFT (4U)
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#define PMU_CPU_PWR_SFTCON_CPU1_SFT_PWRDN_ENA_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU1_SFT_PWRDN_ENA_SHIFT) /* 0x00000010 */
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#define PMU_CPU_PWR_SFTCON_CPU1_SFT_PREQ_OFF_SHIFT (5U)
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#define PMU_CPU_PWR_SFTCON_CPU1_SFT_PREQ_OFF_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU1_SFT_PREQ_OFF_SHIFT) /* 0x00000020 */
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#define PMU_CPU_PWR_SFTCON_CPU1_SFT_PREQ_ON_SHIFT (6U)
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#define PMU_CPU_PWR_SFTCON_CPU1_SFT_PREQ_ON_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU1_SFT_PREQ_ON_SHIFT) /* 0x00000040 */
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#define PMU_CPU_PWR_SFTCON_CPU1_SFT_PREQ_RET_SHIFT (7U)
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#define PMU_CPU_PWR_SFTCON_CPU1_SFT_PREQ_RET_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU1_SFT_PREQ_RET_SHIFT) /* 0x00000080 */
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#define PMU_CPU_PWR_SFTCON_CPU2_SFT_PWRDN_ENA_SHIFT (8U)
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#define PMU_CPU_PWR_SFTCON_CPU2_SFT_PWRDN_ENA_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU2_SFT_PWRDN_ENA_SHIFT) /* 0x00000100 */
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#define PMU_CPU_PWR_SFTCON_CPU2_SFT_PREQ_OFF_SHIFT (9U)
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#define PMU_CPU_PWR_SFTCON_CPU2_SFT_PREQ_OFF_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU2_SFT_PREQ_OFF_SHIFT) /* 0x00000200 */
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#define PMU_CPU_PWR_SFTCON_CPU2_SFT_PREQ_ON_SHIFT (10U)
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#define PMU_CPU_PWR_SFTCON_CPU2_SFT_PREQ_ON_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU2_SFT_PREQ_ON_SHIFT) /* 0x00000400 */
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#define PMU_CPU_PWR_SFTCON_CPU2_SFT_PREQ_RET_SHIFT (11U)
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#define PMU_CPU_PWR_SFTCON_CPU2_SFT_PREQ_RET_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU2_SFT_PREQ_RET_SHIFT) /* 0x00000800 */
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#define PMU_CPU_PWR_SFTCON_CPU3_SFT_PWRDN_ENA_SHIFT (12U)
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#define PMU_CPU_PWR_SFTCON_CPU3_SFT_PWRDN_ENA_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU3_SFT_PWRDN_ENA_SHIFT) /* 0x00001000 */
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#define PMU_CPU_PWR_SFTCON_CPU3_SFT_PREQ_OFF_SHIFT (13U)
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#define PMU_CPU_PWR_SFTCON_CPU3_SFT_PREQ_OFF_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU3_SFT_PREQ_OFF_SHIFT) /* 0x00002000 */
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#define PMU_CPU_PWR_SFTCON_CPU3_SFT_PREQ_ON_SHIFT (14U)
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#define PMU_CPU_PWR_SFTCON_CPU3_SFT_PREQ_ON_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU3_SFT_PREQ_ON_SHIFT) /* 0x00004000 */
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#define PMU_CPU_PWR_SFTCON_CPU3_SFT_PREQ_RET_SHIFT (15U)
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#define PMU_CPU_PWR_SFTCON_CPU3_SFT_PREQ_RET_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU3_SFT_PREQ_RET_SHIFT) /* 0x00008000 */
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/* CLUSTER_PWR_ST */
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#define PMU_CLUSTER_PWR_ST_OFFSET (0x31CU)
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#define PMU_CLUSTER_PWR_ST (0x0U)
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#define PMU_CLUSTER_PWR_ST_CPU0_DWN_STATE_SHIFT (0U)
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#define PMU_CLUSTER_PWR_ST_CPU0_DWN_STATE_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU0_DWN_STATE_SHIFT) /* 0x00000001 */
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#define PMU_CLUSTER_PWR_ST_CPU1_DWN_STATE_SHIFT (1U)
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#define PMU_CLUSTER_PWR_ST_CPU1_DWN_STATE_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU1_DWN_STATE_SHIFT) /* 0x00000002 */
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#define PMU_CLUSTER_PWR_ST_CPU2_DWN_STATE_SHIFT (2U)
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#define PMU_CLUSTER_PWR_ST_CPU2_DWN_STATE_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU2_DWN_STATE_SHIFT) /* 0x00000004 */
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#define PMU_CLUSTER_PWR_ST_CPU3_DWN_STATE_SHIFT (3U)
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#define PMU_CLUSTER_PWR_ST_CPU3_DWN_STATE_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU3_DWN_STATE_SHIFT) /* 0x00000008 */
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#define PMU_CLUSTER_PWR_ST_DSU_DWN_STATE_SHIFT (4U)
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#define PMU_CLUSTER_PWR_ST_DSU_DWN_STATE_MASK (0x1U << PMU_CLUSTER_PWR_ST_DSU_DWN_STATE_SHIFT) /* 0x00000010 */
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#define PMU_CLUSTER_PWR_ST_CLUSTER_PREQ_ACCEPED_SHIFT (7U)
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#define PMU_CLUSTER_PWR_ST_CLUSTER_PREQ_ACCEPED_MASK (0x1U << PMU_CLUSTER_PWR_ST_CLUSTER_PREQ_ACCEPED_SHIFT) /* 0x00000080 */
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#define PMU_CLUSTER_PWR_ST_CLUSTERPACTIVE_BIT_MEMRET_SHIFT (8U)
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#define PMU_CLUSTER_PWR_ST_CLUSTERPACTIVE_BIT_MEMRET_MASK (0x1U << PMU_CLUSTER_PWR_ST_CLUSTERPACTIVE_BIT_MEMRET_SHIFT) /* 0x00000100 */
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#define PMU_CLUSTER_PWR_ST_CLUSTERPACTIVE_BIT_FUNCRET_SHIFT (9U)
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#define PMU_CLUSTER_PWR_ST_CLUSTERPACTIVE_BIT_FUNCRET_MASK (0x1U << PMU_CLUSTER_PWR_ST_CLUSTERPACTIVE_BIT_FUNCRET_SHIFT) /* 0x00000200 */
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#define PMU_CLUSTER_PWR_ST_CLUSTERPACTIVE_BIT_ON_SHIFT (10U)
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#define PMU_CLUSTER_PWR_ST_CLUSTERPACTIVE_BIT_ON_MASK (0x1U << PMU_CLUSTER_PWR_ST_CLUSTERPACTIVE_BIT_ON_SHIFT) /* 0x00000400 */
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#define PMU_CLUSTER_PWR_ST_CLUSTERPACTIVE_BIT_FULL_SHIFT (11U)
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#define PMU_CLUSTER_PWR_ST_CLUSTERPACTIVE_BIT_FULL_MASK (0x1U << PMU_CLUSTER_PWR_ST_CLUSTERPACTIVE_BIT_FULL_SHIFT) /* 0x00000800 */
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#define PMU_CLUSTER_PWR_ST_CPU0_PREQ_ACCEPED_SHIFT (12U)
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#define PMU_CLUSTER_PWR_ST_CPU0_PREQ_ACCEPED_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU0_PREQ_ACCEPED_SHIFT) /* 0x00001000 */
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#define PMU_CLUSTER_PWR_ST_CPU1_PREQ_ACCEPED_SHIFT (13U)
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#define PMU_CLUSTER_PWR_ST_CPU1_PREQ_ACCEPED_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU1_PREQ_ACCEPED_SHIFT) /* 0x00002000 */
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#define PMU_CLUSTER_PWR_ST_CPU2_PREQ_ACCEPED_SHIFT (14U)
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#define PMU_CLUSTER_PWR_ST_CPU2_PREQ_ACCEPED_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU2_PREQ_ACCEPED_SHIFT) /* 0x00004000 */
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#define PMU_CLUSTER_PWR_ST_CPU3_PREQ_ACCEPED_SHIFT (15U)
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#define PMU_CLUSTER_PWR_ST_CPU3_PREQ_ACCEPED_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU3_PREQ_ACCEPED_SHIFT) /* 0x00008000 */
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#define PMU_CLUSTER_PWR_ST_CPU0_BIT_EMUOFF_SHIFT (16U)
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#define PMU_CLUSTER_PWR_ST_CPU0_BIT_EMUOFF_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU0_BIT_EMUOFF_SHIFT) /* 0x00010000 */
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#define PMU_CLUSTER_PWR_ST_CPU0_BIT_FULLRET_SHIFT (17U)
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#define PMU_CLUSTER_PWR_ST_CPU0_BIT_FULLRET_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU0_BIT_FULLRET_SHIFT) /* 0x00020000 */
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#define PMU_CLUSTER_PWR_ST_CPU0_BIT_FUNCRET_SHIFT (18U)
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#define PMU_CLUSTER_PWR_ST_CPU0_BIT_FUNCRET_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU0_BIT_FUNCRET_SHIFT) /* 0x00040000 */
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#define PMU_CLUSTER_PWR_ST_CPU0_BIT_ON_SHIFT (19U)
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#define PMU_CLUSTER_PWR_ST_CPU0_BIT_ON_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU0_BIT_ON_SHIFT) /* 0x00080000 */
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#define PMU_CLUSTER_PWR_ST_CPU1_BIT_EMUOFF_SHIFT (20U)
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#define PMU_CLUSTER_PWR_ST_CPU1_BIT_EMUOFF_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU1_BIT_EMUOFF_SHIFT) /* 0x00100000 */
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#define PMU_CLUSTER_PWR_ST_CPU1_BIT_FULLRET_SHIFT (21U)
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#define PMU_CLUSTER_PWR_ST_CPU1_BIT_FULLRET_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU1_BIT_FULLRET_SHIFT) /* 0x00200000 */
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#define PMU_CLUSTER_PWR_ST_CPU1_BIT_FUNCRET_SHIFT (22U)
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#define PMU_CLUSTER_PWR_ST_CPU1_BIT_FUNCRET_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU1_BIT_FUNCRET_SHIFT) /* 0x00400000 */
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#define PMU_CLUSTER_PWR_ST_CPU1_BIT_ON_SHIFT (23U)
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#define PMU_CLUSTER_PWR_ST_CPU1_BIT_ON_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU1_BIT_ON_SHIFT) /* 0x00800000 */
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#define PMU_CLUSTER_PWR_ST_CPU2_BIT_EMUOFF_SHIFT (24U)
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#define PMU_CLUSTER_PWR_ST_CPU2_BIT_EMUOFF_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU2_BIT_EMUOFF_SHIFT) /* 0x01000000 */
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#define PMU_CLUSTER_PWR_ST_CPU2_BIT_FULLRET_SHIFT (25U)
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#define PMU_CLUSTER_PWR_ST_CPU2_BIT_FULLRET_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU2_BIT_FULLRET_SHIFT) /* 0x02000000 */
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#define PMU_CLUSTER_PWR_ST_CPU2_BIT_FUNCRET_SHIFT (26U)
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#define PMU_CLUSTER_PWR_ST_CPU2_BIT_FUNCRET_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU2_BIT_FUNCRET_SHIFT) /* 0x04000000 */
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#define PMU_CLUSTER_PWR_ST_CPU2_BIT_ON_SHIFT (27U)
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#define PMU_CLUSTER_PWR_ST_CPU2_BIT_ON_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU2_BIT_ON_SHIFT) /* 0x08000000 */
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#define PMU_CLUSTER_PWR_ST_CPU3_BIT_EMUOFF_SHIFT (28U)
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#define PMU_CLUSTER_PWR_ST_CPU3_BIT_EMUOFF_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU3_BIT_EMUOFF_SHIFT) /* 0x10000000 */
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#define PMU_CLUSTER_PWR_ST_CPU3_BIT_FULLRET_SHIFT (29U)
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#define PMU_CLUSTER_PWR_ST_CPU3_BIT_FULLRET_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU3_BIT_FULLRET_SHIFT) /* 0x20000000 */
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#define PMU_CLUSTER_PWR_ST_CPU3_BIT_FUNCRET_SHIFT (30U)
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#define PMU_CLUSTER_PWR_ST_CPU3_BIT_FUNCRET_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU3_BIT_FUNCRET_SHIFT) /* 0x40000000 */
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#define PMU_CLUSTER_PWR_ST_CPU3_BIT_ON_SHIFT (31U)
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#define PMU_CLUSTER_PWR_ST_CPU3_BIT_ON_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU3_BIT_ON_SHIFT) /* 0x80000000 */
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/* CLUSTER_IDLE_CON */
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#define PMU_CLUSTER_IDLE_CON_OFFSET (0x320U)
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#define PMU_CLUSTER_IDLE_CON_IDLE_REQ_CPU_SHIFT (0U)
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#define PMU_CLUSTER_IDLE_CON_IDLE_REQ_CPU_MASK (0x1U << PMU_CLUSTER_IDLE_CON_IDLE_REQ_CPU_SHIFT) /* 0x00000001 */
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#define PMU_CLUSTER_IDLE_CON_DBG_PWRQ_REQ_SHIFT (1U)
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#define PMU_CLUSTER_IDLE_CON_DBG_PWRQ_REQ_MASK (0x1U << PMU_CLUSTER_IDLE_CON_DBG_PWRQ_REQ_SHIFT) /* 0x00000002 */
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#define PMU_CLUSTER_IDLE_CON_CORE2GIC_PWRQ_REQ_SHIFT (2U)
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#define PMU_CLUSTER_IDLE_CON_CORE2GIC_PWRQ_REQ_MASK (0x1U << PMU_CLUSTER_IDLE_CON_CORE2GIC_PWRQ_REQ_SHIFT) /* 0x00000004 */
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#define PMU_CLUSTER_IDLE_CON_GIC2CORE_PWRQ_REQ_SHIFT (3U)
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#define PMU_CLUSTER_IDLE_CON_GIC2CORE_PWRQ_REQ_MASK (0x1U << PMU_CLUSTER_IDLE_CON_GIC2CORE_PWRQ_REQ_SHIFT) /* 0x00000008 */
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/* CLUSTER_IDLE_SFTCON */
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#define PMU_CLUSTER_IDLE_SFTCON_OFFSET (0x324U)
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#define PMU_CLUSTER_IDLE_SFTCON_IDLE_REQ_CPU_SHIFT (0U)
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#define PMU_CLUSTER_IDLE_SFTCON_IDLE_REQ_CPU_MASK (0x1U << PMU_CLUSTER_IDLE_SFTCON_IDLE_REQ_CPU_SHIFT) /* 0x00000001 */
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#define PMU_CLUSTER_IDLE_SFTCON_DBG_PWRQ_REQ_SHIFT (1U)
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#define PMU_CLUSTER_IDLE_SFTCON_DBG_PWRQ_REQ_MASK (0x1U << PMU_CLUSTER_IDLE_SFTCON_DBG_PWRQ_REQ_SHIFT) /* 0x00000002 */
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#define PMU_CLUSTER_IDLE_SFTCON_CORE2GIC_PWRQ_REQ_SHIFT (2U)
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#define PMU_CLUSTER_IDLE_SFTCON_CORE2GIC_PWRQ_REQ_MASK (0x1U << PMU_CLUSTER_IDLE_SFTCON_CORE2GIC_PWRQ_REQ_SHIFT) /* 0x00000004 */
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#define PMU_CLUSTER_IDLE_SFTCON_GIC2CORE_PWRQ_REQ_SHIFT (3U)
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#define PMU_CLUSTER_IDLE_SFTCON_GIC2CORE_PWRQ_REQ_MASK (0x1U << PMU_CLUSTER_IDLE_SFTCON_GIC2CORE_PWRQ_REQ_SHIFT) /* 0x00000008 */
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/* CLUSTER_IDLE_ACK */
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#define PMU_CLUSTER_IDLE_ACK_OFFSET (0x328U)
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#define PMU_CLUSTER_IDLE_ACK (0x0U)
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#define PMU_CLUSTER_IDLE_ACK_IDLE_ACK_CPU_SHIFT (0U)
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#define PMU_CLUSTER_IDLE_ACK_IDLE_ACK_CPU_MASK (0x1U << PMU_CLUSTER_IDLE_ACK_IDLE_ACK_CPU_SHIFT) /* 0x00000001 */
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#define PMU_CLUSTER_IDLE_ACK_DBG_PWRQ_ACCEPT_SHIFT (1U)
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#define PMU_CLUSTER_IDLE_ACK_DBG_PWRQ_ACCEPT_MASK (0x1U << PMU_CLUSTER_IDLE_ACK_DBG_PWRQ_ACCEPT_SHIFT) /* 0x00000002 */
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#define PMU_CLUSTER_IDLE_ACK_CORE2GIC_PWRQ_ACCEPT_SHIFT (2U)
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#define PMU_CLUSTER_IDLE_ACK_CORE2GIC_PWRQ_ACCEPT_MASK (0x1U << PMU_CLUSTER_IDLE_ACK_CORE2GIC_PWRQ_ACCEPT_SHIFT) /* 0x00000004 */
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#define PMU_CLUSTER_IDLE_ACK_GIC2CORE_PWRQ_ACCEPT_SHIFT (3U)
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#define PMU_CLUSTER_IDLE_ACK_GIC2CORE_PWRQ_ACCEPT_MASK (0x1U << PMU_CLUSTER_IDLE_ACK_GIC2CORE_PWRQ_ACCEPT_SHIFT) /* 0x00000008 */
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/* CLUSTER_IDLE_ST */
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#define PMU_CLUSTER_IDLE_ST_OFFSET (0x32CU)
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#define PMU_CLUSTER_IDLE_ST (0x0U)
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#define PMU_CLUSTER_IDLE_ST_IDLE_CPU_SHIFT (0U)
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#define PMU_CLUSTER_IDLE_ST_IDLE_CPU_MASK (0x1U << PMU_CLUSTER_IDLE_ST_IDLE_CPU_SHIFT) /* 0x00000001 */
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#define PMU_CLUSTER_IDLE_ST_DBG_PWRQ_ACTIVE_SHIFT (1U)
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#define PMU_CLUSTER_IDLE_ST_DBG_PWRQ_ACTIVE_MASK (0x1U << PMU_CLUSTER_IDLE_ST_DBG_PWRQ_ACTIVE_SHIFT) /* 0x00000002 */
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#define PMU_CLUSTER_IDLE_ST_CORE2GIC_PWRQ_ACTIVE_SHIFT (2U)
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#define PMU_CLUSTER_IDLE_ST_CORE2GIC_PWRQ_ACTIVE_MASK (0x1U << PMU_CLUSTER_IDLE_ST_CORE2GIC_PWRQ_ACTIVE_SHIFT) /* 0x00000004 */
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#define PMU_CLUSTER_IDLE_ST_GIC2CORE_PWRQ_ACTIVE_SHIFT (3U)
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#define PMU_CLUSTER_IDLE_ST_GIC2CORE_PWRQ_ACTIVE_MASK (0x1U << PMU_CLUSTER_IDLE_ST_GIC2CORE_PWRQ_ACTIVE_SHIFT) /* 0x00000008 */
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/* DBG_PWR_CON */
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#define PMU_DBG_PWR_CON_OFFSET (0x330U)
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#define PMU_DBG_PWR_CON_CPU0_DBG_PWRUP_REQ_ENA_SHIFT (0U)
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#define PMU_DBG_PWR_CON_CPU0_DBG_PWRUP_REQ_ENA_MASK (0x1U << PMU_DBG_PWR_CON_CPU0_DBG_PWRUP_REQ_ENA_SHIFT) /* 0x00000001 */
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#define PMU_DBG_PWR_CON_CPU1_DBG_PWRUP_REQ_ENA_SHIFT (1U)
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#define PMU_DBG_PWR_CON_CPU1_DBG_PWRUP_REQ_ENA_MASK (0x1U << PMU_DBG_PWR_CON_CPU1_DBG_PWRUP_REQ_ENA_SHIFT) /* 0x00000002 */
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#define PMU_DBG_PWR_CON_CPU2_DBG_PWRUP_REQ_ENA_SHIFT (2U)
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#define PMU_DBG_PWR_CON_CPU2_DBG_PWRUP_REQ_ENA_MASK (0x1U << PMU_DBG_PWR_CON_CPU2_DBG_PWRUP_REQ_ENA_SHIFT) /* 0x00000004 */
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#define PMU_DBG_PWR_CON_CPU3_DBG_PWRUP_REQ_ENA_SHIFT (3U)
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#define PMU_DBG_PWR_CON_CPU3_DBG_PWRUP_REQ_ENA_MASK (0x1U << PMU_DBG_PWR_CON_CPU3_DBG_PWRUP_REQ_ENA_SHIFT) /* 0x00000008 */
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#define PMU_DBG_PWR_CON_CLUSTER_DBG_PWRUP_REQ_ENA_SHIFT (4U)
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#define PMU_DBG_PWR_CON_CLUSTER_DBG_PWRUP_REQ_ENA_MASK (0x1U << PMU_DBG_PWR_CON_CLUSTER_DBG_PWRUP_REQ_ENA_SHIFT) /* 0x00000010 */
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/****************************************SPINLOCK****************************************/
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/* STATUS_0 */
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#define SPINLOCK_STATUS_0_OFFSET (0x0U)
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#define SPINLOCK_STATUS_0_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_0_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_0_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_1 */
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#define SPINLOCK_STATUS_1_OFFSET (0x4U)
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#define SPINLOCK_STATUS_1_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_1_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_1_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_2 */
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#define SPINLOCK_STATUS_2_OFFSET (0x8U)
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#define SPINLOCK_STATUS_2_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_2_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_2_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_3 */
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#define SPINLOCK_STATUS_3_OFFSET (0xCU)
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#define SPINLOCK_STATUS_3_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_3_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_3_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_4 */
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#define SPINLOCK_STATUS_4_OFFSET (0x10U)
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#define SPINLOCK_STATUS_4_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_4_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_4_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_5 */
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#define SPINLOCK_STATUS_5_OFFSET (0x14U)
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#define SPINLOCK_STATUS_5_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_5_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_5_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_6 */
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#define SPINLOCK_STATUS_6_OFFSET (0x18U)
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#define SPINLOCK_STATUS_6_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_6_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_6_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_7 */
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#define SPINLOCK_STATUS_7_OFFSET (0x1CU)
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#define SPINLOCK_STATUS_7_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_7_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_7_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_8 */
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#define SPINLOCK_STATUS_8_OFFSET (0x20U)
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#define SPINLOCK_STATUS_8_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_8_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_8_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_9 */
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#define SPINLOCK_STATUS_9_OFFSET (0x24U)
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#define SPINLOCK_STATUS_9_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_9_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_9_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_10 */
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#define SPINLOCK_STATUS_10_OFFSET (0x28U)
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#define SPINLOCK_STATUS_10_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_10_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_10_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_11 */
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#define SPINLOCK_STATUS_11_OFFSET (0x2CU)
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#define SPINLOCK_STATUS_11_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_11_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_11_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_12 */
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#define SPINLOCK_STATUS_12_OFFSET (0x30U)
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#define SPINLOCK_STATUS_12_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_12_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_12_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_13 */
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#define SPINLOCK_STATUS_13_OFFSET (0x34U)
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#define SPINLOCK_STATUS_13_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_13_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_13_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_14 */
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#define SPINLOCK_STATUS_14_OFFSET (0x38U)
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#define SPINLOCK_STATUS_14_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_14_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_14_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_15 */
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#define SPINLOCK_STATUS_15_OFFSET (0x3CU)
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#define SPINLOCK_STATUS_15_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_15_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_15_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_16 */
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#define SPINLOCK_STATUS_16_OFFSET (0x40U)
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#define SPINLOCK_STATUS_16_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_16_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_16_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_17 */
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#define SPINLOCK_STATUS_17_OFFSET (0x44U)
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#define SPINLOCK_STATUS_17_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_17_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_17_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_18 */
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#define SPINLOCK_STATUS_18_OFFSET (0x48U)
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#define SPINLOCK_STATUS_18_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_18_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_18_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_19 */
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#define SPINLOCK_STATUS_19_OFFSET (0x4CU)
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#define SPINLOCK_STATUS_19_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_19_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_19_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_20 */
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#define SPINLOCK_STATUS_20_OFFSET (0x50U)
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#define SPINLOCK_STATUS_20_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_20_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_20_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_21 */
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#define SPINLOCK_STATUS_21_OFFSET (0x54U)
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#define SPINLOCK_STATUS_21_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_21_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_21_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_22 */
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#define SPINLOCK_STATUS_22_OFFSET (0x58U)
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#define SPINLOCK_STATUS_22_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_22_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_22_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_23 */
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#define SPINLOCK_STATUS_23_OFFSET (0x5CU)
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#define SPINLOCK_STATUS_23_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_23_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_23_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_24 */
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#define SPINLOCK_STATUS_24_OFFSET (0x60U)
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#define SPINLOCK_STATUS_24_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_24_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_24_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_25 */
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#define SPINLOCK_STATUS_25_OFFSET (0x64U)
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#define SPINLOCK_STATUS_25_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_25_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_25_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_26 */
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#define SPINLOCK_STATUS_26_OFFSET (0x68U)
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#define SPINLOCK_STATUS_26_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_26_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_26_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_27 */
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#define SPINLOCK_STATUS_27_OFFSET (0x6CU)
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#define SPINLOCK_STATUS_27_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_27_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_27_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_28 */
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#define SPINLOCK_STATUS_28_OFFSET (0x70U)
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#define SPINLOCK_STATUS_28_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_28_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_28_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_29 */
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#define SPINLOCK_STATUS_29_OFFSET (0x74U)
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#define SPINLOCK_STATUS_29_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_29_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_29_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_30 */
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#define SPINLOCK_STATUS_30_OFFSET (0x78U)
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#define SPINLOCK_STATUS_30_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_30_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_30_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_31 */
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#define SPINLOCK_STATUS_31_OFFSET (0x7CU)
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#define SPINLOCK_STATUS_31_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_31_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_31_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_32 */
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#define SPINLOCK_STATUS_32_OFFSET (0x80U)
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#define SPINLOCK_STATUS_32_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_32_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_32_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_33 */
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#define SPINLOCK_STATUS_33_OFFSET (0x84U)
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#define SPINLOCK_STATUS_33_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_33_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_33_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_34 */
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#define SPINLOCK_STATUS_34_OFFSET (0x88U)
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#define SPINLOCK_STATUS_34_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_34_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_34_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_35 */
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#define SPINLOCK_STATUS_35_OFFSET (0x8CU)
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#define SPINLOCK_STATUS_35_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_35_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_35_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_36 */
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#define SPINLOCK_STATUS_36_OFFSET (0x90U)
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#define SPINLOCK_STATUS_36_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_36_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_36_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_37 */
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#define SPINLOCK_STATUS_37_OFFSET (0x94U)
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#define SPINLOCK_STATUS_37_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_37_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_37_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_38 */
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#define SPINLOCK_STATUS_38_OFFSET (0x98U)
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#define SPINLOCK_STATUS_38_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_38_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_38_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_39 */
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#define SPINLOCK_STATUS_39_OFFSET (0x9CU)
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#define SPINLOCK_STATUS_39_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_39_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_39_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_40 */
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#define SPINLOCK_STATUS_40_OFFSET (0xA0U)
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#define SPINLOCK_STATUS_40_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_40_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_40_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_41 */
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#define SPINLOCK_STATUS_41_OFFSET (0xA4U)
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#define SPINLOCK_STATUS_41_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_41_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_41_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_42 */
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#define SPINLOCK_STATUS_42_OFFSET (0xA8U)
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#define SPINLOCK_STATUS_42_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_42_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_42_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_43 */
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#define SPINLOCK_STATUS_43_OFFSET (0xACU)
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#define SPINLOCK_STATUS_43_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_43_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_43_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_44 */
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#define SPINLOCK_STATUS_44_OFFSET (0xB0U)
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#define SPINLOCK_STATUS_44_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_44_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_44_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_45 */
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#define SPINLOCK_STATUS_45_OFFSET (0xB4U)
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#define SPINLOCK_STATUS_45_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_45_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_45_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_46 */
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#define SPINLOCK_STATUS_46_OFFSET (0xB8U)
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#define SPINLOCK_STATUS_46_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_46_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_46_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_47 */
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#define SPINLOCK_STATUS_47_OFFSET (0xBCU)
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#define SPINLOCK_STATUS_47_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_47_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_47_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_48 */
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#define SPINLOCK_STATUS_48_OFFSET (0xC0U)
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#define SPINLOCK_STATUS_48_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_48_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_48_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_49 */
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#define SPINLOCK_STATUS_49_OFFSET (0xC4U)
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#define SPINLOCK_STATUS_49_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_49_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_49_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_50 */
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#define SPINLOCK_STATUS_50_OFFSET (0xC8U)
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#define SPINLOCK_STATUS_50_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_50_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_50_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_51 */
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#define SPINLOCK_STATUS_51_OFFSET (0xCCU)
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#define SPINLOCK_STATUS_51_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_51_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_51_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_52 */
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#define SPINLOCK_STATUS_52_OFFSET (0xD0U)
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#define SPINLOCK_STATUS_52_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_52_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_52_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_53 */
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#define SPINLOCK_STATUS_53_OFFSET (0xD4U)
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#define SPINLOCK_STATUS_53_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_53_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_53_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_54 */
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#define SPINLOCK_STATUS_54_OFFSET (0xD8U)
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#define SPINLOCK_STATUS_54_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_54_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_54_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_55 */
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#define SPINLOCK_STATUS_55_OFFSET (0xDCU)
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#define SPINLOCK_STATUS_55_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_55_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_55_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_56 */
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#define SPINLOCK_STATUS_56_OFFSET (0xE0U)
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#define SPINLOCK_STATUS_56_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_56_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_56_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_57 */
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#define SPINLOCK_STATUS_57_OFFSET (0xE4U)
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#define SPINLOCK_STATUS_57_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_57_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_57_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_58 */
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#define SPINLOCK_STATUS_58_OFFSET (0xE8U)
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#define SPINLOCK_STATUS_58_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_58_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_58_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_59 */
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#define SPINLOCK_STATUS_59_OFFSET (0xECU)
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#define SPINLOCK_STATUS_59_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_59_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_59_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_60 */
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#define SPINLOCK_STATUS_60_OFFSET (0xF0U)
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#define SPINLOCK_STATUS_60_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_60_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_60_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_61 */
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#define SPINLOCK_STATUS_61_OFFSET (0xF4U)
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#define SPINLOCK_STATUS_61_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_61_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_61_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_62 */
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#define SPINLOCK_STATUS_62_OFFSET (0xF8U)
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#define SPINLOCK_STATUS_62_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_62_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_62_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/* STATUS_63 */
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#define SPINLOCK_STATUS_63_OFFSET (0xFCU)
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#define SPINLOCK_STATUS_63_SPINLOCK_STATUS_SHIFT (0U)
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#define SPINLOCK_STATUS_63_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_63_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */
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/******************************************GMAC******************************************/
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/* MAC_CONFIGURATION */
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#define GMAC_MAC_CONFIGURATION_OFFSET (0x0U)
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#define GMAC_MAC_CONFIGURATION_RE_SHIFT (0U)
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#define GMAC_MAC_CONFIGURATION_RE_MASK (0x1U << GMAC_MAC_CONFIGURATION_RE_SHIFT) /* 0x00000001 */
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#define GMAC_MAC_CONFIGURATION_TE_SHIFT (1U)
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#define GMAC_MAC_CONFIGURATION_TE_MASK (0x1U << GMAC_MAC_CONFIGURATION_TE_SHIFT) /* 0x00000002 */
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#define GMAC_MAC_CONFIGURATION_PRELEN_SHIFT (2U)
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#define GMAC_MAC_CONFIGURATION_PRELEN_MASK (0x3U << GMAC_MAC_CONFIGURATION_PRELEN_SHIFT) /* 0x0000000C */
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#define GMAC_MAC_CONFIGURATION_DC_SHIFT (4U)
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#define GMAC_MAC_CONFIGURATION_DC_MASK (0x1U << GMAC_MAC_CONFIGURATION_DC_SHIFT) /* 0x00000010 */
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#define GMAC_MAC_CONFIGURATION_BL_SHIFT (5U)
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#define GMAC_MAC_CONFIGURATION_BL_MASK (0x3U << GMAC_MAC_CONFIGURATION_BL_SHIFT) /* 0x00000060 */
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#define GMAC_MAC_CONFIGURATION_DR_SHIFT (8U)
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#define GMAC_MAC_CONFIGURATION_DR_MASK (0x1U << GMAC_MAC_CONFIGURATION_DR_SHIFT) /* 0x00000100 */
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#define GMAC_MAC_CONFIGURATION_DCRS_SHIFT (9U)
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#define GMAC_MAC_CONFIGURATION_DCRS_MASK (0x1U << GMAC_MAC_CONFIGURATION_DCRS_SHIFT) /* 0x00000200 */
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#define GMAC_MAC_CONFIGURATION_DO_SHIFT (10U)
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#define GMAC_MAC_CONFIGURATION_DO_MASK (0x1U << GMAC_MAC_CONFIGURATION_DO_SHIFT) /* 0x00000400 */
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#define GMAC_MAC_CONFIGURATION_ECRSFD_SHIFT (11U)
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#define GMAC_MAC_CONFIGURATION_ECRSFD_MASK (0x1U << GMAC_MAC_CONFIGURATION_ECRSFD_SHIFT) /* 0x00000800 */
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#define GMAC_MAC_CONFIGURATION_LM_SHIFT (12U)
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#define GMAC_MAC_CONFIGURATION_LM_MASK (0x1U << GMAC_MAC_CONFIGURATION_LM_SHIFT) /* 0x00001000 */
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#define GMAC_MAC_CONFIGURATION_DM_SHIFT (13U)
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#define GMAC_MAC_CONFIGURATION_DM_MASK (0x1U << GMAC_MAC_CONFIGURATION_DM_SHIFT) /* 0x00002000 */
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#define GMAC_MAC_CONFIGURATION_FES_SHIFT (14U)
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#define GMAC_MAC_CONFIGURATION_FES_MASK (0x1U << GMAC_MAC_CONFIGURATION_FES_SHIFT) /* 0x00004000 */
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#define GMAC_MAC_CONFIGURATION_PS_SHIFT (15U)
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#define GMAC_MAC_CONFIGURATION_PS_MASK (0x1U << GMAC_MAC_CONFIGURATION_PS_SHIFT) /* 0x00008000 */
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#define GMAC_MAC_CONFIGURATION_JE_SHIFT (16U)
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#define GMAC_MAC_CONFIGURATION_JE_MASK (0x1U << GMAC_MAC_CONFIGURATION_JE_SHIFT) /* 0x00010000 */
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#define GMAC_MAC_CONFIGURATION_JD_SHIFT (17U)
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#define GMAC_MAC_CONFIGURATION_JD_MASK (0x1U << GMAC_MAC_CONFIGURATION_JD_SHIFT) /* 0x00020000 */
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#define GMAC_MAC_CONFIGURATION_BE_SHIFT (18U)
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#define GMAC_MAC_CONFIGURATION_BE_MASK (0x1U << GMAC_MAC_CONFIGURATION_BE_SHIFT) /* 0x00040000 */
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#define GMAC_MAC_CONFIGURATION_WD_SHIFT (19U)
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#define GMAC_MAC_CONFIGURATION_WD_MASK (0x1U << GMAC_MAC_CONFIGURATION_WD_SHIFT) /* 0x00080000 */
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#define GMAC_MAC_CONFIGURATION_ACS_SHIFT (20U)
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#define GMAC_MAC_CONFIGURATION_ACS_MASK (0x1U << GMAC_MAC_CONFIGURATION_ACS_SHIFT) /* 0x00100000 */
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#define GMAC_MAC_CONFIGURATION_CST_SHIFT (21U)
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#define GMAC_MAC_CONFIGURATION_CST_MASK (0x1U << GMAC_MAC_CONFIGURATION_CST_SHIFT) /* 0x00200000 */
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#define GMAC_MAC_CONFIGURATION_S2KP_SHIFT (22U)
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#define GMAC_MAC_CONFIGURATION_S2KP_MASK (0x1U << GMAC_MAC_CONFIGURATION_S2KP_SHIFT) /* 0x00400000 */
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#define GMAC_MAC_CONFIGURATION_GPSLCE_SHIFT (23U)
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#define GMAC_MAC_CONFIGURATION_GPSLCE_MASK (0x1U << GMAC_MAC_CONFIGURATION_GPSLCE_SHIFT) /* 0x00800000 */
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#define GMAC_MAC_CONFIGURATION_IPG_SHIFT (24U)
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#define GMAC_MAC_CONFIGURATION_IPG_MASK (0x7U << GMAC_MAC_CONFIGURATION_IPG_SHIFT) /* 0x07000000 */
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#define GMAC_MAC_CONFIGURATION_IPC_SHIFT (27U)
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#define GMAC_MAC_CONFIGURATION_IPC_MASK (0x1U << GMAC_MAC_CONFIGURATION_IPC_SHIFT) /* 0x08000000 */
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#define GMAC_MAC_CONFIGURATION_ARPEN_SHIFT (31U)
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#define GMAC_MAC_CONFIGURATION_ARPEN_MASK (0x1U << GMAC_MAC_CONFIGURATION_ARPEN_SHIFT) /* 0x80000000 */
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/* MAC_EXT_CONFIGURATION */
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#define GMAC_MAC_EXT_CONFIGURATION_OFFSET (0x4U)
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#define GMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT (0U)
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#define GMAC_MAC_EXT_CONFIGURATION_GPSL_MASK (0x3FFFU << GMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT) /* 0x00003FFF */
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#define GMAC_MAC_EXT_CONFIGURATION_DCRCC_SHIFT (16U)
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#define GMAC_MAC_EXT_CONFIGURATION_DCRCC_MASK (0x1U << GMAC_MAC_EXT_CONFIGURATION_DCRCC_SHIFT) /* 0x00010000 */
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#define GMAC_MAC_EXT_CONFIGURATION_SPEN_SHIFT (17U)
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#define GMAC_MAC_EXT_CONFIGURATION_SPEN_MASK (0x1U << GMAC_MAC_EXT_CONFIGURATION_SPEN_SHIFT) /* 0x00020000 */
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#define GMAC_MAC_EXT_CONFIGURATION_USP_SHIFT (18U)
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#define GMAC_MAC_EXT_CONFIGURATION_USP_MASK (0x1U << GMAC_MAC_EXT_CONFIGURATION_USP_SHIFT) /* 0x00040000 */
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#define GMAC_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT (24U)
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#define GMAC_MAC_EXT_CONFIGURATION_EIPGEN_MASK (0x1U << GMAC_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT) /* 0x01000000 */
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#define GMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT (25U)
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#define GMAC_MAC_EXT_CONFIGURATION_EIPG_MASK (0x1FU << GMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT) /* 0x3E000000 */
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/* MAC_PACKET_FILTER */
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#define GMAC_MAC_PACKET_FILTER_OFFSET (0x8U)
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#define GMAC_MAC_PACKET_FILTER_PR_SHIFT (0U)
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#define GMAC_MAC_PACKET_FILTER_PR_MASK (0x1U << GMAC_MAC_PACKET_FILTER_PR_SHIFT) /* 0x00000001 */
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#define GMAC_MAC_PACKET_FILTER_HUC_SHIFT (1U)
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#define GMAC_MAC_PACKET_FILTER_HUC_MASK (0x1U << GMAC_MAC_PACKET_FILTER_HUC_SHIFT) /* 0x00000002 */
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#define GMAC_MAC_PACKET_FILTER_HMC_SHIFT (2U)
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#define GMAC_MAC_PACKET_FILTER_HMC_MASK (0x1U << GMAC_MAC_PACKET_FILTER_HMC_SHIFT) /* 0x00000004 */
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#define GMAC_MAC_PACKET_FILTER_DAIF_SHIFT (3U)
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#define GMAC_MAC_PACKET_FILTER_DAIF_MASK (0x1U << GMAC_MAC_PACKET_FILTER_DAIF_SHIFT) /* 0x00000008 */
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#define GMAC_MAC_PACKET_FILTER_PM_SHIFT (4U)
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#define GMAC_MAC_PACKET_FILTER_PM_MASK (0x1U << GMAC_MAC_PACKET_FILTER_PM_SHIFT) /* 0x00000010 */
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#define GMAC_MAC_PACKET_FILTER_DBF_SHIFT (5U)
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#define GMAC_MAC_PACKET_FILTER_DBF_MASK (0x1U << GMAC_MAC_PACKET_FILTER_DBF_SHIFT) /* 0x00000020 */
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#define GMAC_MAC_PACKET_FILTER_PCF_SHIFT (6U)
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#define GMAC_MAC_PACKET_FILTER_PCF_MASK (0x3U << GMAC_MAC_PACKET_FILTER_PCF_SHIFT) /* 0x000000C0 */
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#define GMAC_MAC_PACKET_FILTER_HPF_SHIFT (10U)
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#define GMAC_MAC_PACKET_FILTER_HPF_MASK (0x1U << GMAC_MAC_PACKET_FILTER_HPF_SHIFT) /* 0x00000400 */
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#define GMAC_MAC_PACKET_FILTER_VTFE_SHIFT (16U)
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#define GMAC_MAC_PACKET_FILTER_VTFE_MASK (0x1U << GMAC_MAC_PACKET_FILTER_VTFE_SHIFT) /* 0x00010000 */
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/* MAC_WATCHDOG_TIMEOUT */
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#define GMAC_MAC_WATCHDOG_TIMEOUT_OFFSET (0xCU)
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#define GMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT (0U)
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#define GMAC_MAC_WATCHDOG_TIMEOUT_WTO_MASK (0xFU << GMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT) /* 0x0000000F */
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#define GMAC_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT (8U)
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#define GMAC_MAC_WATCHDOG_TIMEOUT_PWE_MASK (0x1U << GMAC_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT) /* 0x00000100 */
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/* MAC_HASH_TABLE_REG0 */
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#define GMAC_MAC_HASH_TABLE_REG0_OFFSET (0x10U)
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#define GMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT (0U)
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#define GMAC_MAC_HASH_TABLE_REG0_HT31T0_MASK (0xFFFFFFFFU << GMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT) /* 0xFFFFFFFF */
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/* MAC_HASH_TABLE_REG1 */
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#define GMAC_MAC_HASH_TABLE_REG1_OFFSET (0x14U)
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#define GMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT (0U)
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#define GMAC_MAC_HASH_TABLE_REG1_HT63T32_MASK (0xFFFFFFFFU << GMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT) /* 0xFFFFFFFF */
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/* MAC_VLAN_TAG */
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#define GMAC_MAC_VLAN_TAG_OFFSET (0x50U)
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#define GMAC_MAC_VLAN_TAG_VL_SHIFT (0U)
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#define GMAC_MAC_VLAN_TAG_VL_MASK (0xFFFFU << GMAC_MAC_VLAN_TAG_VL_SHIFT) /* 0x0000FFFF */
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#define GMAC_MAC_VLAN_TAG_ETV_SHIFT (16U)
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#define GMAC_MAC_VLAN_TAG_ETV_MASK (0x1U << GMAC_MAC_VLAN_TAG_ETV_SHIFT) /* 0x00010000 */
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#define GMAC_MAC_VLAN_TAG_VTIM_SHIFT (17U)
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#define GMAC_MAC_VLAN_TAG_VTIM_MASK (0x1U << GMAC_MAC_VLAN_TAG_VTIM_SHIFT) /* 0x00020000 */
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#define GMAC_MAC_VLAN_TAG_ESVL_SHIFT (18U)
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#define GMAC_MAC_VLAN_TAG_ESVL_MASK (0x1U << GMAC_MAC_VLAN_TAG_ESVL_SHIFT) /* 0x00040000 */
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#define GMAC_MAC_VLAN_TAG_ERSVLM_SHIFT (19U)
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#define GMAC_MAC_VLAN_TAG_ERSVLM_MASK (0x1U << GMAC_MAC_VLAN_TAG_ERSVLM_SHIFT) /* 0x00080000 */
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#define GMAC_MAC_VLAN_TAG_DOVLTC_SHIFT (20U)
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#define GMAC_MAC_VLAN_TAG_DOVLTC_MASK (0x1U << GMAC_MAC_VLAN_TAG_DOVLTC_SHIFT) /* 0x00100000 */
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#define GMAC_MAC_VLAN_TAG_EVLS_SHIFT (21U)
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#define GMAC_MAC_VLAN_TAG_EVLS_MASK (0x3U << GMAC_MAC_VLAN_TAG_EVLS_SHIFT) /* 0x00600000 */
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#define GMAC_MAC_VLAN_TAG_EVLRXS_SHIFT (24U)
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#define GMAC_MAC_VLAN_TAG_EVLRXS_MASK (0x1U << GMAC_MAC_VLAN_TAG_EVLRXS_SHIFT) /* 0x01000000 */
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/* MAC_Q0_TX_FLOW_CTRL */
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#define GMAC_MAC_Q0_TX_FLOW_CTRL_OFFSET (0x70U)
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#define GMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_SHIFT (0U)
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#define GMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_MASK (0x1U << GMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_SHIFT) /* 0x00000001 */
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#define GMAC_MAC_Q0_TX_FLOW_CTRL_TFE_SHIFT (1U)
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#define GMAC_MAC_Q0_TX_FLOW_CTRL_TFE_MASK (0x1U << GMAC_MAC_Q0_TX_FLOW_CTRL_TFE_SHIFT) /* 0x00000002 */
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#define GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT (4U)
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#define GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_MASK (0x7U << GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT) /* 0x00000070 */
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#define GMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_SHIFT (7U)
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#define GMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_MASK (0x1U << GMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_SHIFT) /* 0x00000080 */
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#define GMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT (16U)
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#define GMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK (0xFFFFU << GMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT) /* 0xFFFF0000 */
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/* MAC_RX_FLOW_CTRL */
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#define GMAC_MAC_RX_FLOW_CTRL_OFFSET (0x90U)
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#define GMAC_MAC_RX_FLOW_CTRL_RFE_SHIFT (0U)
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#define GMAC_MAC_RX_FLOW_CTRL_RFE_MASK (0x1U << GMAC_MAC_RX_FLOW_CTRL_RFE_SHIFT) /* 0x00000001 */
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#define GMAC_MAC_RX_FLOW_CTRL_UP_SHIFT (1U)
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#define GMAC_MAC_RX_FLOW_CTRL_UP_MASK (0x1U << GMAC_MAC_RX_FLOW_CTRL_UP_SHIFT) /* 0x00000002 */
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/* MAC_INTERRUPT_STATUS */
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#define GMAC_MAC_INTERRUPT_STATUS_OFFSET (0xB0U)
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#define GMAC_MAC_INTERRUPT_STATUS (0x0U)
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#define GMAC_MAC_INTERRUPT_STATUS_RGSMIIIS_SHIFT (0U)
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#define GMAC_MAC_INTERRUPT_STATUS_RGSMIIIS_MASK (0x1U << GMAC_MAC_INTERRUPT_STATUS_RGSMIIIS_SHIFT) /* 0x00000001 */
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#define GMAC_MAC_INTERRUPT_STATUS_PHYIS_SHIFT (3U)
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#define GMAC_MAC_INTERRUPT_STATUS_PHYIS_MASK (0x1U << GMAC_MAC_INTERRUPT_STATUS_PHYIS_SHIFT) /* 0x00000008 */
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#define GMAC_MAC_INTERRUPT_STATUS_PMTIS_SHIFT (4U)
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#define GMAC_MAC_INTERRUPT_STATUS_PMTIS_MASK (0x1U << GMAC_MAC_INTERRUPT_STATUS_PMTIS_SHIFT) /* 0x00000010 */
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#define GMAC_MAC_INTERRUPT_STATUS_LPIIS_SHIFT (5U)
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#define GMAC_MAC_INTERRUPT_STATUS_LPIIS_MASK (0x1U << GMAC_MAC_INTERRUPT_STATUS_LPIIS_SHIFT) /* 0x00000020 */
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#define GMAC_MAC_INTERRUPT_STATUS_MMCIS_SHIFT (8U)
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#define GMAC_MAC_INTERRUPT_STATUS_MMCIS_MASK (0x1U << GMAC_MAC_INTERRUPT_STATUS_MMCIS_SHIFT) /* 0x00000100 */
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#define GMAC_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT (9U)
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#define GMAC_MAC_INTERRUPT_STATUS_MMCRXIS_MASK (0x1U << GMAC_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT) /* 0x00000200 */
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#define GMAC_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT (10U)
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#define GMAC_MAC_INTERRUPT_STATUS_MMCTXIS_MASK (0x1U << GMAC_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT) /* 0x00000400 */
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#define GMAC_MAC_INTERRUPT_STATUS_MMCRXIPIS_SHIFT (11U)
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#define GMAC_MAC_INTERRUPT_STATUS_MMCRXIPIS_MASK (0x1U << GMAC_MAC_INTERRUPT_STATUS_MMCRXIPIS_SHIFT) /* 0x00000800 */
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#define GMAC_MAC_INTERRUPT_STATUS_TSIS_SHIFT (12U)
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#define GMAC_MAC_INTERRUPT_STATUS_TSIS_MASK (0x1U << GMAC_MAC_INTERRUPT_STATUS_TSIS_SHIFT) /* 0x00001000 */
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#define GMAC_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT (13U)
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#define GMAC_MAC_INTERRUPT_STATUS_TXSTSIS_MASK (0x1U << GMAC_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT) /* 0x00002000 */
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#define GMAC_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT (14U)
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#define GMAC_MAC_INTERRUPT_STATUS_RXSTSIS_MASK (0x1U << GMAC_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT) /* 0x00004000 */
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#define GMAC_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT (18U)
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#define GMAC_MAC_INTERRUPT_STATUS_MDIOIS_MASK (0x1U << GMAC_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT) /* 0x00040000 */
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/* MAC_INTERRUPT_ENABLE */
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#define GMAC_MAC_INTERRUPT_ENABLE_OFFSET (0xB4U)
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#define GMAC_MAC_INTERRUPT_ENABLE_RGSMIIIE_SHIFT (0U)
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#define GMAC_MAC_INTERRUPT_ENABLE_RGSMIIIE_MASK (0x1U << GMAC_MAC_INTERRUPT_ENABLE_RGSMIIIE_SHIFT) /* 0x00000001 */
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#define GMAC_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT (3U)
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#define GMAC_MAC_INTERRUPT_ENABLE_PHYIE_MASK (0x1U << GMAC_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT) /* 0x00000008 */
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#define GMAC_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT (4U)
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#define GMAC_MAC_INTERRUPT_ENABLE_PMTIE_MASK (0x1U << GMAC_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT) /* 0x00000010 */
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#define GMAC_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT (5U)
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#define GMAC_MAC_INTERRUPT_ENABLE_LPIIE_MASK (0x1U << GMAC_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT) /* 0x00000020 */
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#define GMAC_MAC_INTERRUPT_ENABLE_TSIE_SHIFT (12U)
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#define GMAC_MAC_INTERRUPT_ENABLE_TSIE_MASK (0x1U << GMAC_MAC_INTERRUPT_ENABLE_TSIE_SHIFT) /* 0x00001000 */
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#define GMAC_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT (13U)
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#define GMAC_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK (0x1U << GMAC_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT) /* 0x00002000 */
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#define GMAC_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT (14U)
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#define GMAC_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK (0x1U << GMAC_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT) /* 0x00004000 */
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#define GMAC_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT (18U)
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#define GMAC_MAC_INTERRUPT_ENABLE_MDIOIE_MASK (0x1U << GMAC_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT) /* 0x00040000 */
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/* MAC_RX_TX_STATUS */
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#define GMAC_MAC_RX_TX_STATUS_OFFSET (0xB8U)
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#define GMAC_MAC_RX_TX_STATUS (0x0U)
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#define GMAC_MAC_RX_TX_STATUS_TJT_SHIFT (0U)
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#define GMAC_MAC_RX_TX_STATUS_TJT_MASK (0x1U << GMAC_MAC_RX_TX_STATUS_TJT_SHIFT) /* 0x00000001 */
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#define GMAC_MAC_RX_TX_STATUS_NCARR_SHIFT (1U)
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#define GMAC_MAC_RX_TX_STATUS_NCARR_MASK (0x1U << GMAC_MAC_RX_TX_STATUS_NCARR_SHIFT) /* 0x00000002 */
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#define GMAC_MAC_RX_TX_STATUS_LCARR_SHIFT (2U)
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#define GMAC_MAC_RX_TX_STATUS_LCARR_MASK (0x1U << GMAC_MAC_RX_TX_STATUS_LCARR_SHIFT) /* 0x00000004 */
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#define GMAC_MAC_RX_TX_STATUS_EXDEF_SHIFT (3U)
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#define GMAC_MAC_RX_TX_STATUS_EXDEF_MASK (0x1U << GMAC_MAC_RX_TX_STATUS_EXDEF_SHIFT) /* 0x00000008 */
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#define GMAC_MAC_RX_TX_STATUS_LCOL_SHIFT (4U)
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#define GMAC_MAC_RX_TX_STATUS_LCOL_MASK (0x1U << GMAC_MAC_RX_TX_STATUS_LCOL_SHIFT) /* 0x00000010 */
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#define GMAC_MAC_RX_TX_STATUS_EXCOL_SHIFT (5U)
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#define GMAC_MAC_RX_TX_STATUS_EXCOL_MASK (0x1U << GMAC_MAC_RX_TX_STATUS_EXCOL_SHIFT) /* 0x00000020 */
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#define GMAC_MAC_RX_TX_STATUS_RWT_SHIFT (8U)
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#define GMAC_MAC_RX_TX_STATUS_RWT_MASK (0x1U << GMAC_MAC_RX_TX_STATUS_RWT_SHIFT) /* 0x00000100 */
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/* MAC_PMT_CONTROL_STATUS */
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#define GMAC_MAC_PMT_CONTROL_STATUS_OFFSET (0xC0U)
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#define GMAC_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT (0U)
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#define GMAC_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK (0x1U << GMAC_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT) /* 0x00000001 */
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#define GMAC_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT (1U)
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#define GMAC_MAC_PMT_CONTROL_STATUS_MGKPKTEN_MASK (0x1U << GMAC_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT) /* 0x00000002 */
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#define GMAC_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT (2U)
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#define GMAC_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MASK (0x1U << GMAC_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT) /* 0x00000004 */
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#define GMAC_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT (5U)
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#define GMAC_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MASK (0x1U << GMAC_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT) /* 0x00000020 */
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#define GMAC_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT (6U)
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#define GMAC_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MASK (0x1U << GMAC_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT) /* 0x00000040 */
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#define GMAC_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT (9U)
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#define GMAC_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MASK (0x1U << GMAC_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT) /* 0x00000200 */
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#define GMAC_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT (10U)
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#define GMAC_MAC_PMT_CONTROL_STATUS_RWKPFE_MASK (0x1U << GMAC_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT) /* 0x00000400 */
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#define GMAC_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT (24U)
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#define GMAC_MAC_PMT_CONTROL_STATUS_RWKPTR_MASK (0x1FU << GMAC_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT) /* 0x1F000000 */
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#define GMAC_MAC_PMT_CONTROL_STATUS_RWKFILTRST_SHIFT (31U)
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#define GMAC_MAC_PMT_CONTROL_STATUS_RWKFILTRST_MASK (0x1U << GMAC_MAC_PMT_CONTROL_STATUS_RWKFILTRST_SHIFT) /* 0x80000000 */
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/* RWK_FILTER0_BYTE_MASK */
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#define GMAC_RWK_FILTER0_BYTE_MASK_OFFSET (0xC4U)
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#define GMAC_RWK_FILTER0_BYTE_MASK_FILTER0_BYTE_MASK_SHIFT (0U)
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#define GMAC_RWK_FILTER0_BYTE_MASK_FILTER0_BYTE_MASK_MASK (0xFFFFFFFFU << GMAC_RWK_FILTER0_BYTE_MASK_FILTER0_BYTE_MASK_SHIFT) /* 0xFFFFFFFF */
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/* RWK_FILTER1_BYTE_MASK */
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#define GMAC_RWK_FILTER1_BYTE_MASK_OFFSET (0xC8U)
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#define GMAC_RWK_FILTER1_BYTE_MASK_FILTER1_BYTE_MASK_SHIFT (0U)
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#define GMAC_RWK_FILTER1_BYTE_MASK_FILTER1_BYTE_MASK_MASK (0xFFFFFFFFU << GMAC_RWK_FILTER1_BYTE_MASK_FILTER1_BYTE_MASK_SHIFT) /* 0xFFFFFFFF */
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/* RWK_FILTER2_BYTE_MASK */
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#define GMAC_RWK_FILTER2_BYTE_MASK_OFFSET (0xCCU)
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#define GMAC_RWK_FILTER2_BYTE_MASK_FILTER2_BYTE_MASK_SHIFT (0U)
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#define GMAC_RWK_FILTER2_BYTE_MASK_FILTER2_BYTE_MASK_MASK (0xFFFFFFFFU << GMAC_RWK_FILTER2_BYTE_MASK_FILTER2_BYTE_MASK_SHIFT) /* 0xFFFFFFFF */
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/* RWK_FILTER3_BYTE_MASK */
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#define GMAC_RWK_FILTER3_BYTE_MASK_OFFSET (0xCCU)
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#define GMAC_RWK_FILTER3_BYTE_MASK_FILTER3_BYTE_MASK_SHIFT (0U)
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#define GMAC_RWK_FILTER3_BYTE_MASK_FILTER3_BYTE_MASK_MASK (0xFFFFFFFFU << GMAC_RWK_FILTER3_BYTE_MASK_FILTER3_BYTE_MASK_SHIFT) /* 0xFFFFFFFF */
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/* RWK_FILTER01_CRC */
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#define GMAC_RWK_FILTER01_CRC_OFFSET (0xD0U)
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#define GMAC_RWK_FILTER01_CRC_FILTER0_CRC_SHIFT (0U)
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#define GMAC_RWK_FILTER01_CRC_FILTER0_CRC_MASK (0xFFFFU << GMAC_RWK_FILTER01_CRC_FILTER0_CRC_SHIFT) /* 0x0000FFFF */
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#define GMAC_RWK_FILTER01_CRC_FILTER1_CRC_SHIFT (16U)
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#define GMAC_RWK_FILTER01_CRC_FILTER1_CRC_MASK (0xFFFFU << GMAC_RWK_FILTER01_CRC_FILTER1_CRC_SHIFT) /* 0xFFFF0000 */
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/* RWK_FILTER23_CRC */
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#define GMAC_RWK_FILTER23_CRC_OFFSET (0xD4U)
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#define GMAC_RWK_FILTER23_CRC_FILTER2_CRC_SHIFT (0U)
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#define GMAC_RWK_FILTER23_CRC_FILTER2_CRC_MASK (0xFFFFU << GMAC_RWK_FILTER23_CRC_FILTER2_CRC_SHIFT) /* 0x0000FFFF */
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#define GMAC_RWK_FILTER23_CRC_FILTER3_CRC_SHIFT (16U)
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#define GMAC_RWK_FILTER23_CRC_FILTER3_CRC_MASK (0xFFFFU << GMAC_RWK_FILTER23_CRC_FILTER3_CRC_SHIFT) /* 0xFFFF0000 */
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/* RWK_FILTER_OFFSET */
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#define GMAC_RWK_FILTER_OFFSET_OFFSET (0xD8U)
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#define GMAC_RWK_FILTER_OFFSET_FILTER0_OFFSET_SHIFT (0U)
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#define GMAC_RWK_FILTER_OFFSET_FILTER0_OFFSET_MASK (0xFFU << GMAC_RWK_FILTER_OFFSET_FILTER0_OFFSET_SHIFT) /* 0x000000FF */
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#define GMAC_RWK_FILTER_OFFSET_FILTER1_OFFSET_SHIFT (8U)
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#define GMAC_RWK_FILTER_OFFSET_FILTER1_OFFSET_MASK (0xFFU << GMAC_RWK_FILTER_OFFSET_FILTER1_OFFSET_SHIFT) /* 0x0000FF00 */
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#define GMAC_RWK_FILTER_OFFSET_FILTER2_OFFSET_SHIFT (16U)
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#define GMAC_RWK_FILTER_OFFSET_FILTER2_OFFSET_MASK (0xFFU << GMAC_RWK_FILTER_OFFSET_FILTER2_OFFSET_SHIFT) /* 0x00FF0000 */
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#define GMAC_RWK_FILTER_OFFSET_FILTER3_OFFSET_SHIFT (24U)
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#define GMAC_RWK_FILTER_OFFSET_FILTER3_OFFSET_MASK (0xFFU << GMAC_RWK_FILTER_OFFSET_FILTER3_OFFSET_SHIFT) /* 0xFF000000 */
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/* RWK_FILTER_COMMAND */
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#define GMAC_RWK_FILTER_COMMAND_OFFSET (0xDCU)
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#define GMAC_RWK_FILTER_COMMAND_FILTER0_COMMAND_SHIFT (0U)
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#define GMAC_RWK_FILTER_COMMAND_FILTER0_COMMAND_MASK (0xFU << GMAC_RWK_FILTER_COMMAND_FILTER0_COMMAND_SHIFT) /* 0x0000000F */
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#define GMAC_RWK_FILTER_COMMAND_FILTER1_COMMAND_SHIFT (8U)
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#define GMAC_RWK_FILTER_COMMAND_FILTER1_COMMAND_MASK (0xFU << GMAC_RWK_FILTER_COMMAND_FILTER1_COMMAND_SHIFT) /* 0x00000F00 */
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#define GMAC_RWK_FILTER_COMMAND_FILTER2_COMMAND_SHIFT (16U)
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#define GMAC_RWK_FILTER_COMMAND_FILTER2_COMMAND_MASK (0xFU << GMAC_RWK_FILTER_COMMAND_FILTER2_COMMAND_SHIFT) /* 0x000F0000 */
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#define GMAC_RWK_FILTER_COMMAND_FILTER3_COMMAND_SHIFT (24U)
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#define GMAC_RWK_FILTER_COMMAND_FILTER3_COMMAND_MASK (0xFU << GMAC_RWK_FILTER_COMMAND_FILTER3_COMMAND_SHIFT) /* 0x0F000000 */
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/* MAC_LPI_CONTROL_STATUS */
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#define GMAC_MAC_LPI_CONTROL_STATUS_OFFSET (0xD0U)
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#define GMAC_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT (0U)
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#define GMAC_MAC_LPI_CONTROL_STATUS_TLPIEN_MASK (0x1U << GMAC_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT) /* 0x00000001 */
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#define GMAC_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT (1U)
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#define GMAC_MAC_LPI_CONTROL_STATUS_TLPIEX_MASK (0x1U << GMAC_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT) /* 0x00000002 */
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#define GMAC_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT (2U)
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#define GMAC_MAC_LPI_CONTROL_STATUS_RLPIEN_MASK (0x1U << GMAC_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT) /* 0x00000004 */
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#define GMAC_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT (3U)
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#define GMAC_MAC_LPI_CONTROL_STATUS_RLPIEX_MASK (0x1U << GMAC_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT) /* 0x00000008 */
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#define GMAC_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT (8U)
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#define GMAC_MAC_LPI_CONTROL_STATUS_TLPIST_MASK (0x1U << GMAC_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT) /* 0x00000100 */
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#define GMAC_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT (9U)
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#define GMAC_MAC_LPI_CONTROL_STATUS_RLPIST_MASK (0x1U << GMAC_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT) /* 0x00000200 */
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#define GMAC_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT (16U)
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#define GMAC_MAC_LPI_CONTROL_STATUS_LPIEN_MASK (0x1U << GMAC_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT) /* 0x00010000 */
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#define GMAC_MAC_LPI_CONTROL_STATUS_PLS_SHIFT (17U)
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#define GMAC_MAC_LPI_CONTROL_STATUS_PLS_MASK (0x1U << GMAC_MAC_LPI_CONTROL_STATUS_PLS_SHIFT) /* 0x00020000 */
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#define GMAC_MAC_LPI_CONTROL_STATUS_PLSEN_SHIFT (18U)
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#define GMAC_MAC_LPI_CONTROL_STATUS_PLSEN_MASK (0x1U << GMAC_MAC_LPI_CONTROL_STATUS_PLSEN_SHIFT) /* 0x00040000 */
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#define GMAC_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT (19U)
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#define GMAC_MAC_LPI_CONTROL_STATUS_LPITXA_MASK (0x1U << GMAC_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT) /* 0x00080000 */
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#define GMAC_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT (20U)
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#define GMAC_MAC_LPI_CONTROL_STATUS_LPIATE_MASK (0x1U << GMAC_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT) /* 0x00100000 */
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#define GMAC_MAC_LPI_CONTROL_STATUS_LPITCSE_SHIFT (21U)
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#define GMAC_MAC_LPI_CONTROL_STATUS_LPITCSE_MASK (0x1U << GMAC_MAC_LPI_CONTROL_STATUS_LPITCSE_SHIFT) /* 0x00200000 */
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/* MAC_LPI_TIMERS_CONTROL */
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#define GMAC_MAC_LPI_TIMERS_CONTROL_OFFSET (0xD4U)
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#define GMAC_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT (0U)
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#define GMAC_MAC_LPI_TIMERS_CONTROL_TWT_MASK (0xFFFFU << GMAC_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT) /* 0x0000FFFF */
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#define GMAC_MAC_LPI_TIMERS_CONTROL_LST_SHIFT (16U)
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#define GMAC_MAC_LPI_TIMERS_CONTROL_LST_MASK (0x3FFU << GMAC_MAC_LPI_TIMERS_CONTROL_LST_SHIFT) /* 0x03FF0000 */
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/* MAC_LPI_ENTRY_TIMER */
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#define GMAC_MAC_LPI_ENTRY_TIMER_OFFSET (0xD8U)
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#define GMAC_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT (3U)
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#define GMAC_MAC_LPI_ENTRY_TIMER_LPIET_MASK (0x1FFFFU << GMAC_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT) /* 0x000FFFF8 */
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/* MAC_1US_TIC_COUNTER */
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#define GMAC_MAC_1US_TIC_COUNTER_OFFSET (0xDCU)
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#define GMAC_MAC_1US_TIC_COUNTER_TIC_1US_CNTR_SHIFT (0U)
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#define GMAC_MAC_1US_TIC_COUNTER_TIC_1US_CNTR_MASK (0xFFFU << GMAC_MAC_1US_TIC_COUNTER_TIC_1US_CNTR_SHIFT) /* 0x00000FFF */
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/* MAC_PHYIF_CONTROL_STATUS */
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#define GMAC_MAC_PHYIF_CONTROL_STATUS_OFFSET (0xF8U)
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#define GMAC_MAC_PHYIF_CONTROL_STATUS_TC_SHIFT (0U)
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#define GMAC_MAC_PHYIF_CONTROL_STATUS_TC_MASK (0x1U << GMAC_MAC_PHYIF_CONTROL_STATUS_TC_SHIFT) /* 0x00000001 */
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#define GMAC_MAC_PHYIF_CONTROL_STATUS_LUD_SHIFT (1U)
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#define GMAC_MAC_PHYIF_CONTROL_STATUS_LUD_MASK (0x1U << GMAC_MAC_PHYIF_CONTROL_STATUS_LUD_SHIFT) /* 0x00000002 */
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#define GMAC_MAC_PHYIF_CONTROL_STATUS_LNKMOD_SHIFT (16U)
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#define GMAC_MAC_PHYIF_CONTROL_STATUS_LNKMOD_MASK (0x1U << GMAC_MAC_PHYIF_CONTROL_STATUS_LNKMOD_SHIFT) /* 0x00010000 */
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#define GMAC_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT (17U)
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#define GMAC_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_MASK (0x3U << GMAC_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT) /* 0x00060000 */
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#define GMAC_MAC_PHYIF_CONTROL_STATUS_LNKSTS_SHIFT (19U)
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#define GMAC_MAC_PHYIF_CONTROL_STATUS_LNKSTS_MASK (0x1U << GMAC_MAC_PHYIF_CONTROL_STATUS_LNKSTS_SHIFT) /* 0x00080000 */
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/* MAC_VERSION */
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#define GMAC_MAC_VERSION_OFFSET (0x110U)
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#define GMAC_MAC_VERSION_SNPSVER_SHIFT (0U)
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#define GMAC_MAC_VERSION_SNPSVER_MASK (0xFFU << GMAC_MAC_VERSION_SNPSVER_SHIFT) /* 0x000000FF */
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#define GMAC_MAC_VERSION_USERVER_SHIFT (8U)
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#define GMAC_MAC_VERSION_USERVER_MASK (0xFFU << GMAC_MAC_VERSION_USERVER_SHIFT) /* 0x0000FF00 */
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/* MAC_DEBUG */
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#define GMAC_MAC_DEBUG_OFFSET (0x114U)
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#define GMAC_MAC_DEBUG (0x0U)
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#define GMAC_MAC_DEBUG_RPESTS_SHIFT (0U)
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#define GMAC_MAC_DEBUG_RPESTS_MASK (0x1U << GMAC_MAC_DEBUG_RPESTS_SHIFT) /* 0x00000001 */
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#define GMAC_MAC_DEBUG_RFCFCSTS_SHIFT (1U)
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#define GMAC_MAC_DEBUG_RFCFCSTS_MASK (0x3U << GMAC_MAC_DEBUG_RFCFCSTS_SHIFT) /* 0x00000006 */
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#define GMAC_MAC_DEBUG_TPESTS_SHIFT (16U)
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#define GMAC_MAC_DEBUG_TPESTS_MASK (0x1U << GMAC_MAC_DEBUG_TPESTS_SHIFT) /* 0x00010000 */
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#define GMAC_MAC_DEBUG_TFCSTS_SHIFT (17U)
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#define GMAC_MAC_DEBUG_TFCSTS_MASK (0x3U << GMAC_MAC_DEBUG_TFCSTS_SHIFT) /* 0x00060000 */
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/* MAC_HW_FEATURE0 */
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#define GMAC_MAC_HW_FEATURE0_OFFSET (0x11CU)
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#define GMAC_MAC_HW_FEATURE0 (0x160171E3U)
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#define GMAC_MAC_HW_FEATURE0_MIISEL_SHIFT (0U)
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#define GMAC_MAC_HW_FEATURE0_MIISEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_MIISEL_SHIFT) /* 0x00000001 */
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#define GMAC_MAC_HW_FEATURE0_GMIISEL_SHIFT (1U)
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#define GMAC_MAC_HW_FEATURE0_GMIISEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_GMIISEL_SHIFT) /* 0x00000002 */
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#define GMAC_MAC_HW_FEATURE0_HDSEL_SHIFT (2U)
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#define GMAC_MAC_HW_FEATURE0_HDSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_HDSEL_SHIFT) /* 0x00000004 */
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#define GMAC_MAC_HW_FEATURE0_PCSSEL_SHIFT (3U)
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#define GMAC_MAC_HW_FEATURE0_PCSSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_PCSSEL_SHIFT) /* 0x00000008 */
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#define GMAC_MAC_HW_FEATURE0_VLHASH_SHIFT (4U)
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#define GMAC_MAC_HW_FEATURE0_VLHASH_MASK (0x1U << GMAC_MAC_HW_FEATURE0_VLHASH_SHIFT) /* 0x00000010 */
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#define GMAC_MAC_HW_FEATURE0_SMASEL_SHIFT (5U)
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#define GMAC_MAC_HW_FEATURE0_SMASEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_SMASEL_SHIFT) /* 0x00000020 */
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#define GMAC_MAC_HW_FEATURE0_RWKSEL_SHIFT (6U)
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#define GMAC_MAC_HW_FEATURE0_RWKSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_RWKSEL_SHIFT) /* 0x00000040 */
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#define GMAC_MAC_HW_FEATURE0_MGKSEL_SHIFT (7U)
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#define GMAC_MAC_HW_FEATURE0_MGKSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_MGKSEL_SHIFT) /* 0x00000080 */
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#define GMAC_MAC_HW_FEATURE0_MMCSEL_SHIFT (8U)
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#define GMAC_MAC_HW_FEATURE0_MMCSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_MMCSEL_SHIFT) /* 0x00000100 */
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#define GMAC_MAC_HW_FEATURE0_ARPOFFSEL_SHIFT (9U)
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#define GMAC_MAC_HW_FEATURE0_ARPOFFSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_ARPOFFSEL_SHIFT) /* 0x00000200 */
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#define GMAC_MAC_HW_FEATURE0_TSSEL_SHIFT (12U)
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#define GMAC_MAC_HW_FEATURE0_TSSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_TSSEL_SHIFT) /* 0x00001000 */
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#define GMAC_MAC_HW_FEATURE0_EEESEL_SHIFT (13U)
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#define GMAC_MAC_HW_FEATURE0_EEESEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_EEESEL_SHIFT) /* 0x00002000 */
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#define GMAC_MAC_HW_FEATURE0_TXCOESEL_SHIFT (14U)
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#define GMAC_MAC_HW_FEATURE0_TXCOESEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_TXCOESEL_SHIFT) /* 0x00004000 */
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#define GMAC_MAC_HW_FEATURE0_RXCOESEL_SHIFT (16U)
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#define GMAC_MAC_HW_FEATURE0_RXCOESEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_RXCOESEL_SHIFT) /* 0x00010000 */
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#define GMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT (18U)
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#define GMAC_MAC_HW_FEATURE0_ADDMACADRSEL_MASK (0x1FU << GMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT) /* 0x007C0000 */
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#define GMAC_MAC_HW_FEATURE0_MACADR32SEL_SHIFT (23U)
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#define GMAC_MAC_HW_FEATURE0_MACADR32SEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_MACADR32SEL_SHIFT) /* 0x00800000 */
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#define GMAC_MAC_HW_FEATURE0_MACADR64SEL_SHIFT (24U)
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#define GMAC_MAC_HW_FEATURE0_MACADR64SEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_MACADR64SEL_SHIFT) /* 0x01000000 */
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#define GMAC_MAC_HW_FEATURE0_TSSTSSEL_SHIFT (25U)
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#define GMAC_MAC_HW_FEATURE0_TSSTSSEL_MASK (0x3U << GMAC_MAC_HW_FEATURE0_TSSTSSEL_SHIFT) /* 0x06000000 */
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#define GMAC_MAC_HW_FEATURE0_SAVLANINS_SHIFT (27U)
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#define GMAC_MAC_HW_FEATURE0_SAVLANINS_MASK (0x1U << GMAC_MAC_HW_FEATURE0_SAVLANINS_SHIFT) /* 0x08000000 */
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#define GMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT (28U)
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#define GMAC_MAC_HW_FEATURE0_ACTPHYSEL_MASK (0xFU << GMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT) /* 0xF0000000 */
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/* MAC_HW_FEATURE1 */
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#define GMAC_MAC_HW_FEATURE1_OFFSET (0x120U)
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#define GMAC_MAC_HW_FEATURE1 (0x10C01C8U)
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#define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT (0U)
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#define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK (0x1FU << GMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) /* 0x0000001F */
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#define GMAC_MAC_HW_FEATURE1_SPRAM_SHIFT (5U)
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#define GMAC_MAC_HW_FEATURE1_SPRAM_MASK (0x1U << GMAC_MAC_HW_FEATURE1_SPRAM_SHIFT) /* 0x00000020 */
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#define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT (6U)
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#define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK (0x1FU << GMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) /* 0x000007C0 */
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#define GMAC_MAC_HW_FEATURE1_OSTEN_SHIFT (11U)
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#define GMAC_MAC_HW_FEATURE1_OSTEN_MASK (0x1U << GMAC_MAC_HW_FEATURE1_OSTEN_SHIFT) /* 0x00000800 */
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#define GMAC_MAC_HW_FEATURE1_PTOEN_SHIFT (12U)
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#define GMAC_MAC_HW_FEATURE1_PTOEN_MASK (0x1U << GMAC_MAC_HW_FEATURE1_PTOEN_SHIFT) /* 0x00001000 */
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#define GMAC_MAC_HW_FEATURE1_ADVTHWORD_SHIFT (13U)
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#define GMAC_MAC_HW_FEATURE1_ADVTHWORD_MASK (0x1U << GMAC_MAC_HW_FEATURE1_ADVTHWORD_SHIFT) /* 0x00002000 */
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#define GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT (14U)
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#define GMAC_MAC_HW_FEATURE1_ADDR64_MASK (0x3U << GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT) /* 0x0000C000 */
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#define GMAC_MAC_HW_FEATURE1_DCBEN_SHIFT (16U)
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#define GMAC_MAC_HW_FEATURE1_DCBEN_MASK (0x1U << GMAC_MAC_HW_FEATURE1_DCBEN_SHIFT) /* 0x00010000 */
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#define GMAC_MAC_HW_FEATURE1_SPHEN_SHIFT (17U)
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#define GMAC_MAC_HW_FEATURE1_SPHEN_MASK (0x1U << GMAC_MAC_HW_FEATURE1_SPHEN_SHIFT) /* 0x00020000 */
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#define GMAC_MAC_HW_FEATURE1_TSOEN_SHIFT (18U)
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#define GMAC_MAC_HW_FEATURE1_TSOEN_MASK (0x1U << GMAC_MAC_HW_FEATURE1_TSOEN_SHIFT) /* 0x00040000 */
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#define GMAC_MAC_HW_FEATURE1_DBGMEMA_SHIFT (19U)
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#define GMAC_MAC_HW_FEATURE1_DBGMEMA_MASK (0x1U << GMAC_MAC_HW_FEATURE1_DBGMEMA_SHIFT) /* 0x00080000 */
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#define GMAC_MAC_HW_FEATURE1_AVSEL_SHIFT (20U)
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#define GMAC_MAC_HW_FEATURE1_AVSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE1_AVSEL_SHIFT) /* 0x00100000 */
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#define GMAC_MAC_HW_FEATURE1_RAVSEL_SHIFT (21U)
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#define GMAC_MAC_HW_FEATURE1_RAVSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE1_RAVSEL_SHIFT) /* 0x00200000 */
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#define GMAC_MAC_HW_FEATURE1_POUOST_SHIFT (23U)
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#define GMAC_MAC_HW_FEATURE1_POUOST_MASK (0x1U << GMAC_MAC_HW_FEATURE1_POUOST_SHIFT) /* 0x00800000 */
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#define GMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT (24U)
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#define GMAC_MAC_HW_FEATURE1_HASHTBLSZ_MASK (0x3U << GMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT) /* 0x03000000 */
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#define GMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT (27U)
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#define GMAC_MAC_HW_FEATURE1_L3L4FNUM_MASK (0xFU << GMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT) /* 0x78000000 */
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/* MAC_HW_FEATURE2 */
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#define GMAC_MAC_HW_FEATURE2_OFFSET (0x124U)
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#define GMAC_MAC_HW_FEATURE2 (0x10000000U)
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#define GMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT (0U)
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#define GMAC_MAC_HW_FEATURE2_RXQCNT_MASK (0xFU << GMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT) /* 0x0000000F */
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#define GMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT (6U)
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#define GMAC_MAC_HW_FEATURE2_TXQCNT_MASK (0xFU << GMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT) /* 0x000003C0 */
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#define GMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT (12U)
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#define GMAC_MAC_HW_FEATURE2_RXCHCNT_MASK (0xFU << GMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT) /* 0x0000F000 */
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#define GMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT (18U)
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#define GMAC_MAC_HW_FEATURE2_TXCHCNT_MASK (0xFU << GMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT) /* 0x003C0000 */
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#define GMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT (24U)
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#define GMAC_MAC_HW_FEATURE2_PPSOUTNUM_MASK (0x7U << GMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT) /* 0x07000000 */
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#define GMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT (28U)
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#define GMAC_MAC_HW_FEATURE2_AUXSNAPNUM_MASK (0x7U << GMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT) /* 0x70000000 */
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/* MAC_HW_FEATURE3 */
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#define GMAC_MAC_HW_FEATURE3_OFFSET (0x128U)
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#define GMAC_MAC_HW_FEATURE3_NRVF_SHIFT (0U)
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#define GMAC_MAC_HW_FEATURE3_NRVF_MASK (0x7U << GMAC_MAC_HW_FEATURE3_NRVF_SHIFT) /* 0x00000007 */
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#define GMAC_MAC_HW_FEATURE3_CBTISEL_SHIFT (4U)
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#define GMAC_MAC_HW_FEATURE3_CBTISEL_MASK (0x1U << GMAC_MAC_HW_FEATURE3_CBTISEL_SHIFT) /* 0x00000010 */
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#define GMAC_MAC_HW_FEATURE3_DVLAN_SHIFT (5U)
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#define GMAC_MAC_HW_FEATURE3_DVLAN_MASK (0x1U << GMAC_MAC_HW_FEATURE3_DVLAN_SHIFT) /* 0x00000020 */
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#define GMAC_MAC_HW_FEATURE3_PDUPSEL_SHIFT (9U)
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#define GMAC_MAC_HW_FEATURE3_PDUPSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE3_PDUPSEL_SHIFT) /* 0x00000200 */
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#define GMAC_MAC_HW_FEATURE3_FRPSEL_SHIFT (10U)
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#define GMAC_MAC_HW_FEATURE3_FRPSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE3_FRPSEL_SHIFT) /* 0x00000400 */
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#define GMAC_MAC_HW_FEATURE3_FRPBS_SHIFT (11U)
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#define GMAC_MAC_HW_FEATURE3_FRPBS_MASK (0x3U << GMAC_MAC_HW_FEATURE3_FRPBS_SHIFT) /* 0x00001800 */
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#define GMAC_MAC_HW_FEATURE3_FRPES_SHIFT (13U)
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#define GMAC_MAC_HW_FEATURE3_FRPES_MASK (0x3U << GMAC_MAC_HW_FEATURE3_FRPES_SHIFT) /* 0x00006000 */
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#define GMAC_MAC_HW_FEATURE3_ESTSEL_SHIFT (16U)
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#define GMAC_MAC_HW_FEATURE3_ESTSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE3_ESTSEL_SHIFT) /* 0x00010000 */
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#define GMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT (17U)
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#define GMAC_MAC_HW_FEATURE3_ESTDEP_MASK (0x7U << GMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT) /* 0x000E0000 */
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#define GMAC_MAC_HW_FEATURE3_ESTWID_SHIFT (20U)
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#define GMAC_MAC_HW_FEATURE3_ESTWID_MASK (0x3U << GMAC_MAC_HW_FEATURE3_ESTWID_SHIFT) /* 0x00300000 */
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#define GMAC_MAC_HW_FEATURE3_FPESEL_SHIFT (26U)
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#define GMAC_MAC_HW_FEATURE3_FPESEL_MASK (0x1U << GMAC_MAC_HW_FEATURE3_FPESEL_SHIFT) /* 0x04000000 */
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#define GMAC_MAC_HW_FEATURE3_TBSSEL_SHIFT (27U)
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#define GMAC_MAC_HW_FEATURE3_TBSSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE3_TBSSEL_SHIFT) /* 0x08000000 */
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#define GMAC_MAC_HW_FEATURE3_ASP_SHIFT (28U)
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#define GMAC_MAC_HW_FEATURE3_ASP_MASK (0x3U << GMAC_MAC_HW_FEATURE3_ASP_SHIFT) /* 0x30000000 */
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/* MAC_MDIO_ADDRESS */
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#define GMAC_MAC_MDIO_ADDRESS_OFFSET (0x200U)
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#define GMAC_MAC_MDIO_ADDRESS_GB_SHIFT (0U)
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#define GMAC_MAC_MDIO_ADDRESS_GB_MASK (0x1U << GMAC_MAC_MDIO_ADDRESS_GB_SHIFT) /* 0x00000001 */
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#define GMAC_MAC_MDIO_ADDRESS_C45E_SHIFT (1U)
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#define GMAC_MAC_MDIO_ADDRESS_C45E_MASK (0x1U << GMAC_MAC_MDIO_ADDRESS_C45E_SHIFT) /* 0x00000002 */
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#define GMAC_MAC_MDIO_ADDRESS_GOC_0_SHIFT (2U)
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#define GMAC_MAC_MDIO_ADDRESS_GOC_0_MASK (0x1U << GMAC_MAC_MDIO_ADDRESS_GOC_0_SHIFT) /* 0x00000004 */
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#define GMAC_MAC_MDIO_ADDRESS_GOC_1_SHIFT (3U)
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#define GMAC_MAC_MDIO_ADDRESS_GOC_1_MASK (0x1U << GMAC_MAC_MDIO_ADDRESS_GOC_1_SHIFT) /* 0x00000008 */
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#define GMAC_MAC_MDIO_ADDRESS_SKAP_SHIFT (4U)
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#define GMAC_MAC_MDIO_ADDRESS_SKAP_MASK (0x1U << GMAC_MAC_MDIO_ADDRESS_SKAP_SHIFT) /* 0x00000010 */
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#define GMAC_MAC_MDIO_ADDRESS_CR_SHIFT (8U)
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#define GMAC_MAC_MDIO_ADDRESS_CR_MASK (0xFU << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) /* 0x00000F00 */
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#define GMAC_MAC_MDIO_ADDRESS_NTC_SHIFT (12U)
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#define GMAC_MAC_MDIO_ADDRESS_NTC_MASK (0x7U << GMAC_MAC_MDIO_ADDRESS_NTC_SHIFT) /* 0x00007000 */
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#define GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT (16U)
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#define GMAC_MAC_MDIO_ADDRESS_RDA_MASK (0x1FU << GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) /* 0x001F0000 */
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#define GMAC_MAC_MDIO_ADDRESS_PA_SHIFT (21U)
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#define GMAC_MAC_MDIO_ADDRESS_PA_MASK (0x1FU << GMAC_MAC_MDIO_ADDRESS_PA_SHIFT) /* 0x03E00000 */
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#define GMAC_MAC_MDIO_ADDRESS_BTB_SHIFT (26U)
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#define GMAC_MAC_MDIO_ADDRESS_BTB_MASK (0x1U << GMAC_MAC_MDIO_ADDRESS_BTB_SHIFT) /* 0x04000000 */
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#define GMAC_MAC_MDIO_ADDRESS_PSE_SHIFT (27U)
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#define GMAC_MAC_MDIO_ADDRESS_PSE_MASK (0x1U << GMAC_MAC_MDIO_ADDRESS_PSE_SHIFT) /* 0x08000000 */
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/* MAC_MDIO_DATA */
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#define GMAC_MAC_MDIO_DATA_OFFSET (0x204U)
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#define GMAC_MAC_MDIO_DATA_GD_SHIFT (0U)
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#define GMAC_MAC_MDIO_DATA_GD_MASK (0xFFFFU << GMAC_MAC_MDIO_DATA_GD_SHIFT) /* 0x0000FFFF */
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#define GMAC_MAC_MDIO_DATA_RA_SHIFT (16U)
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#define GMAC_MAC_MDIO_DATA_RA_MASK (0x1U << GMAC_MAC_MDIO_DATA_RA_SHIFT) /* 0x00010000 */
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/* MAC_CSR_SW_CTRL */
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#define GMAC_MAC_CSR_SW_CTRL_OFFSET (0x230U)
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#define GMAC_MAC_CSR_SW_CTRL_RCWE_SHIFT (0U)
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#define GMAC_MAC_CSR_SW_CTRL_RCWE_MASK (0x1U << GMAC_MAC_CSR_SW_CTRL_RCWE_SHIFT) /* 0x00000001 */
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/* MAC_ADDRESS0_HIGH */
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#define GMAC_MAC_ADDRESS0_HIGH_OFFSET (0x300U)
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#define GMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT (0U)
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#define GMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK (0xFFFFU << GMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT) /* 0x0000FFFF */
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#define GMAC_MAC_ADDRESS0_HIGH_AE_SHIFT (31U)
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#define GMAC_MAC_ADDRESS0_HIGH_AE_MASK (0x1U << GMAC_MAC_ADDRESS0_HIGH_AE_SHIFT) /* 0x80000000 */
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/* MAC_ADDRESS0_LOW */
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#define GMAC_MAC_ADDRESS0_LOW_OFFSET (0x304U)
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#define GMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT (0U)
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#define GMAC_MAC_ADDRESS0_LOW_ADDRLO_MASK (0xFFFFFFFFU << GMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT) /* 0xFFFFFFFF */
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/* MMC_CONTROL */
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#define GMAC_MMC_CONTROL_OFFSET (0x700U)
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#define GMAC_MMC_CONTROL_CNTRST_SHIFT (0U)
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#define GMAC_MMC_CONTROL_CNTRST_MASK (0x1U << GMAC_MMC_CONTROL_CNTRST_SHIFT) /* 0x00000001 */
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#define GMAC_MMC_CONTROL_CNTSTOPRO_SHIFT (1U)
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#define GMAC_MMC_CONTROL_CNTSTOPRO_MASK (0x1U << GMAC_MMC_CONTROL_CNTSTOPRO_SHIFT) /* 0x00000002 */
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#define GMAC_MMC_CONTROL_RSTONRD_SHIFT (2U)
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#define GMAC_MMC_CONTROL_RSTONRD_MASK (0x1U << GMAC_MMC_CONTROL_RSTONRD_SHIFT) /* 0x00000004 */
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#define GMAC_MMC_CONTROL_CNTFREEZ_SHIFT (3U)
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#define GMAC_MMC_CONTROL_CNTFREEZ_MASK (0x1U << GMAC_MMC_CONTROL_CNTFREEZ_SHIFT) /* 0x00000008 */
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#define GMAC_MMC_CONTROL_CNTPRST_SHIFT (4U)
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#define GMAC_MMC_CONTROL_CNTPRST_MASK (0x1U << GMAC_MMC_CONTROL_CNTPRST_SHIFT) /* 0x00000010 */
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#define GMAC_MMC_CONTROL_CNTPRSTLVL_SHIFT (5U)
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#define GMAC_MMC_CONTROL_CNTPRSTLVL_MASK (0x1U << GMAC_MMC_CONTROL_CNTPRSTLVL_SHIFT) /* 0x00000020 */
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#define GMAC_MMC_CONTROL_UCDBC_SHIFT (8U)
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#define GMAC_MMC_CONTROL_UCDBC_MASK (0x1U << GMAC_MMC_CONTROL_UCDBC_SHIFT) /* 0x00000100 */
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/* MMC_RX_INTERRUPT */
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#define GMAC_MMC_RX_INTERRUPT_OFFSET (0x704U)
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#define GMAC_MMC_RX_INTERRUPT (0x0U)
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#define GMAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT (0U)
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#define GMAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT) /* 0x00000001 */
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#define GMAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT (1U)
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#define GMAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT) /* 0x00000002 */
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#define GMAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT (2U)
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#define GMAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT) /* 0x00000004 */
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#define GMAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT (4U)
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#define GMAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT) /* 0x00000010 */
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#define GMAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT (5U)
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#define GMAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT) /* 0x00000020 */
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#define GMAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT (18U)
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#define GMAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT) /* 0x00040000 */
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#define GMAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT (21U)
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#define GMAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT) /* 0x00200000 */
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/* MMC_TX_INTERRUPT */
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#define GMAC_MMC_TX_INTERRUPT_OFFSET (0x708U)
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#define GMAC_MMC_TX_INTERRUPT (0x0U)
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#define GMAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT (0U)
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#define GMAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK (0x1U << GMAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT) /* 0x00000001 */
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#define GMAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT (1U)
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#define GMAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK (0x1U << GMAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT) /* 0x00000002 */
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#define GMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT (13U)
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#define GMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK (0x1U << GMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT) /* 0x00002000 */
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#define GMAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT (19U)
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#define GMAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK (0x1U << GMAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT) /* 0x00080000 */
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#define GMAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT (20U)
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#define GMAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK (0x1U << GMAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT) /* 0x00100000 */
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#define GMAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT (21U)
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#define GMAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK (0x1U << GMAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT) /* 0x00200000 */
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/* MMC_RX_INTERRUPT_MASK */
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#define GMAC_MMC_RX_INTERRUPT_MASK_OFFSET (0x70CU)
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#define GMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT (0U)
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#define GMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT) /* 0x00000001 */
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#define GMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT (1U)
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#define GMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT) /* 0x00000002 */
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#define GMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT (2U)
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#define GMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT) /* 0x00000004 */
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#define GMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT (4U)
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#define GMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT) /* 0x00000010 */
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#define GMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT (5U)
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#define GMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT) /* 0x00000020 */
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#define GMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT (18U)
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#define GMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT) /* 0x00040000 */
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#define GMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT (21U)
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#define GMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT) /* 0x00200000 */
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/* MMC_TX_INTERRUPT_MASK */
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#define GMAC_MMC_TX_INTERRUPT_MASK_OFFSET (0x710U)
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#define GMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT (0U)
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#define GMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK (0x1U << GMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT) /* 0x00000001 */
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#define GMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT (1U)
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#define GMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK (0x1U << GMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT) /* 0x00000002 */
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#define GMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT (13U)
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#define GMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK (0x1U << GMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT) /* 0x00002000 */
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#define GMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT (19U)
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#define GMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK (0x1U << GMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT) /* 0x00080000 */
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#define GMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT (20U)
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#define GMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK (0x1U << GMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT) /* 0x00100000 */
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#define GMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT (21U)
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#define GMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK (0x1U << GMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT) /* 0x00200000 */
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/* TX_OCTET_COUNT_GOOD_BAD */
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#define GMAC_TX_OCTET_COUNT_GOOD_BAD_OFFSET (0x714U)
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#define GMAC_TX_OCTET_COUNT_GOOD_BAD (0x0U)
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#define GMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT (0U)
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#define GMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK (0xFFFFFFFFU << GMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT) /* 0xFFFFFFFF */
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/* TX_PACKET_COUNT_GOOD_BAD */
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#define GMAC_TX_PACKET_COUNT_GOOD_BAD_OFFSET (0x718U)
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#define GMAC_TX_PACKET_COUNT_GOOD_BAD (0x0U)
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#define GMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT (0U)
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#define GMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK (0xFFFFFFFFU << GMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT) /* 0xFFFFFFFF */
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/* TX_UNDERFLOW_ERROR_PACKETS */
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#define GMAC_TX_UNDERFLOW_ERROR_PACKETS_OFFSET (0x748U)
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#define GMAC_TX_UNDERFLOW_ERROR_PACKETS (0x0U)
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#define GMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT (0U)
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#define GMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK (0xFFFFFFFFU << GMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT) /* 0xFFFFFFFF */
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/* TX_CARRIER_ERROR_PACKETS */
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#define GMAC_TX_CARRIER_ERROR_PACKETS_OFFSET (0x760U)
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#define GMAC_TX_CARRIER_ERROR_PACKETS (0x0U)
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#define GMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT (0U)
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#define GMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK (0xFFFFFFFFU << GMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT) /* 0xFFFFFFFF */
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/* TX_OCTET_COUNT_GOOD */
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#define GMAC_TX_OCTET_COUNT_GOOD_OFFSET (0x764U)
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#define GMAC_TX_OCTET_COUNT_GOOD (0x0U)
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#define GMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT (0U)
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#define GMAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK (0xFFFFFFFFU << GMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT) /* 0xFFFFFFFF */
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/* TX_PACKET_COUNT_GOOD */
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#define GMAC_TX_PACKET_COUNT_GOOD_OFFSET (0x768U)
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#define GMAC_TX_PACKET_COUNT_GOOD (0x0U)
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#define GMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT (0U)
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#define GMAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK (0xFFFFFFFFU << GMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT) /* 0xFFFFFFFF */
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/* RX_PACKETS_COUNT_GOOD_BAD */
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#define GMAC_RX_PACKETS_COUNT_GOOD_BAD_OFFSET (0x780U)
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#define GMAC_RX_PACKETS_COUNT_GOOD_BAD (0x0U)
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#define GMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT (0U)
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#define GMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK (0xFFFFFFFFU << GMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT) /* 0xFFFFFFFF */
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/* RX_OCTET_COUNT_GOOD_BAD */
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#define GMAC_RX_OCTET_COUNT_GOOD_BAD_OFFSET (0x784U)
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#define GMAC_RX_OCTET_COUNT_GOOD_BAD (0x0U)
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#define GMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT (0U)
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#define GMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK (0xFFFFFFFFU << GMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT) /* 0xFFFFFFFF */
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/* RX_OCTET_COUNT_GOOD */
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#define GMAC_RX_OCTET_COUNT_GOOD_OFFSET (0x788U)
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#define GMAC_RX_OCTET_COUNT_GOOD (0x0U)
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#define GMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT (0U)
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#define GMAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK (0xFFFFFFFFU << GMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT) /* 0xFFFFFFFF */
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/* RX_MULTICAST_PACKETS_GOOD */
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#define GMAC_RX_MULTICAST_PACKETS_GOOD_OFFSET (0x790U)
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#define GMAC_RX_MULTICAST_PACKETS_GOOD (0x0U)
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#define GMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT (0U)
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#define GMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK (0xFFFFFFFFU << GMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT) /* 0xFFFFFFFF */
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/* RX_CRC_ERROR_PACKETS */
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#define GMAC_RX_CRC_ERROR_PACKETS_OFFSET (0x794U)
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#define GMAC_RX_CRC_ERROR_PACKETS (0x0U)
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#define GMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT (0U)
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#define GMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK (0xFFFFFFFFU << GMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT) /* 0xFFFFFFFF */
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/* RX_LENGTH_ERROR_PACKETS */
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#define GMAC_RX_LENGTH_ERROR_PACKETS_OFFSET (0x7C8U)
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#define GMAC_RX_LENGTH_ERROR_PACKETS (0x0U)
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#define GMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT (0U)
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#define GMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK (0xFFFFFFFFU << GMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT) /* 0xFFFFFFFF */
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/* RX_FIFO_OVERFLOW_PACKETS */
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#define GMAC_RX_FIFO_OVERFLOW_PACKETS_OFFSET (0x7D4U)
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#define GMAC_RX_FIFO_OVERFLOW_PACKETS (0x0U)
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#define GMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT (0U)
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#define GMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK (0xFFFFFFFFU << GMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT) /* 0xFFFFFFFF */
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/* MMC_IPC_RX_INTERRUPT_MASK */
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_OFFSET (0x800U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_SHIFT (0U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_SHIFT) /* 0x00000001 */
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_SHIFT (1U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_SHIFT) /* 0x00000002 */
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_SHIFT (5U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_SHIFT) /* 0x00000020 */
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_SHIFT (6U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_SHIFT) /* 0x00000040 */
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_SHIFT (9U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_SHIFT) /* 0x00000200 */
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_SHIFT (11U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_SHIFT) /* 0x00000800 */
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_SHIFT (13U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_SHIFT) /* 0x00002000 */
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_SHIFT (17U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_SHIFT) /* 0x00020000 */
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_SHIFT (22U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_SHIFT) /* 0x00400000 */
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_SHIFT (25U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_SHIFT) /* 0x02000000 */
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_SHIFT (27U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_SHIFT) /* 0x08000000 */
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_SHIFT (29U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_SHIFT) /* 0x20000000 */
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/* MMC_IPC_RX_INTERRUPT */
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#define GMAC_MMC_IPC_RX_INTERRUPT_OFFSET (0x808U)
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#define GMAC_MMC_IPC_RX_INTERRUPT (0x0U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_SHIFT (0U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_SHIFT) /* 0x00000001 */
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#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_SHIFT (1U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_SHIFT) /* 0x00000002 */
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#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_SHIFT (5U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_SHIFT) /* 0x00000020 */
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#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_SHIFT (6U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_SHIFT) /* 0x00000040 */
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#define GMAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_SHIFT (9U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_SHIFT) /* 0x00000200 */
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#define GMAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_SHIFT (11U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_SHIFT) /* 0x00000800 */
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#define GMAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_SHIFT (13U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_SHIFT) /* 0x00002000 */
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#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_SHIFT (17U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_SHIFT) /* 0x00020000 */
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#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_SHIFT (22U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_SHIFT) /* 0x00400000 */
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#define GMAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_SHIFT (25U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_SHIFT) /* 0x02000000 */
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#define GMAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_SHIFT (27U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_SHIFT) /* 0x08000000 */
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#define GMAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_SHIFT (29U)
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#define GMAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_SHIFT) /* 0x20000000 */
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/* RXIPV4_GOOD_PACKETS */
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#define GMAC_RXIPV4_GOOD_PACKETS_OFFSET (0x810U)
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#define GMAC_RXIPV4_GOOD_PACKETS (0x0U)
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#define GMAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_SHIFT (0U)
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#define GMAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_MASK (0xFFFFFFFFU << GMAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_SHIFT) /* 0xFFFFFFFF */
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/* RXIPV4_HEADER_ERROR_PACKETS */
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#define GMAC_RXIPV4_HEADER_ERROR_PACKETS_OFFSET (0x814U)
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#define GMAC_RXIPV4_HEADER_ERROR_PACKETS (0x0U)
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#define GMAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_SHIFT (0U)
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#define GMAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_MASK (0xFFFFFFFFU << GMAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_SHIFT) /* 0xFFFFFFFF */
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/* RXIPV6_GOOD_PACKETS */
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#define GMAC_RXIPV6_GOOD_PACKETS_OFFSET (0x824U)
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#define GMAC_RXIPV6_GOOD_PACKETS (0x0U)
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#define GMAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_SHIFT (0U)
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#define GMAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_MASK (0xFFFFFFFFU << GMAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_SHIFT) /* 0xFFFFFFFF */
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/* RXIPV6_HEADER_ERROR_PACKETS */
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#define GMAC_RXIPV6_HEADER_ERROR_PACKETS_OFFSET (0x828U)
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#define GMAC_RXIPV6_HEADER_ERROR_PACKETS (0x0U)
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#define GMAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_SHIFT (0U)
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#define GMAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_MASK (0xFFFFFFFFU << GMAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_SHIFT) /* 0xFFFFFFFF */
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/* RXUDP_ERROR_PACKETS */
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#define GMAC_RXUDP_ERROR_PACKETS_OFFSET (0x834U)
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#define GMAC_RXUDP_ERROR_PACKETS (0x0U)
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#define GMAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_SHIFT (0U)
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#define GMAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_MASK (0xFFFFFFFFU << GMAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_SHIFT) /* 0xFFFFFFFF */
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/* RXTCP_ERROR_PACKETS */
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#define GMAC_RXTCP_ERROR_PACKETS_OFFSET (0x83CU)
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#define GMAC_RXTCP_ERROR_PACKETS (0x0U)
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#define GMAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_SHIFT (0U)
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#define GMAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_MASK (0xFFFFFFFFU << GMAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_SHIFT) /* 0xFFFFFFFF */
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/* RXICMP_ERROR_PACKETS */
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#define GMAC_RXICMP_ERROR_PACKETS_OFFSET (0x844U)
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#define GMAC_RXICMP_ERROR_PACKETS (0x0U)
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#define GMAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_SHIFT (0U)
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#define GMAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_MASK (0xFFFFFFFFU << GMAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_SHIFT) /* 0xFFFFFFFF */
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/* RXIPV4_HEADER_ERROR_OCTETS */
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#define GMAC_RXIPV4_HEADER_ERROR_OCTETS_OFFSET (0x854U)
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#define GMAC_RXIPV4_HEADER_ERROR_OCTETS (0x0U)
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#define GMAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_SHIFT (0U)
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#define GMAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_MASK (0xFFFFFFFFU << GMAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_SHIFT) /* 0xFFFFFFFF */
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/* RXIPV6_HEADER_ERROR_OCTETS */
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#define GMAC_RXIPV6_HEADER_ERROR_OCTETS_OFFSET (0x868U)
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#define GMAC_RXIPV6_HEADER_ERROR_OCTETS (0x0U)
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#define GMAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_SHIFT (0U)
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#define GMAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_MASK (0xFFFFFFFFU << GMAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_SHIFT) /* 0xFFFFFFFF */
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/* RXUDP_ERROR_OCTETS */
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#define GMAC_RXUDP_ERROR_OCTETS_OFFSET (0x874U)
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#define GMAC_RXUDP_ERROR_OCTETS (0x0U)
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#define GMAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_SHIFT (0U)
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#define GMAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_MASK (0xFFFFFFFFU << GMAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_SHIFT) /* 0xFFFFFFFF */
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/* RXTCP_ERROR_OCTETS */
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#define GMAC_RXTCP_ERROR_OCTETS_OFFSET (0x87CU)
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#define GMAC_RXTCP_ERROR_OCTETS (0x0U)
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#define GMAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_SHIFT (0U)
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#define GMAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_MASK (0xFFFFFFFFU << GMAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_SHIFT) /* 0xFFFFFFFF */
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/* RXICMP_ERROR_OCTETS */
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#define GMAC_RXICMP_ERROR_OCTETS_OFFSET (0x884U)
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#define GMAC_RXICMP_ERROR_OCTETS (0x0U)
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#define GMAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_SHIFT (0U)
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#define GMAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_MASK (0xFFFFFFFFU << GMAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_SHIFT) /* 0xFFFFFFFF */
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/* MAC_TIMESTAMP_CONTROL */
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#define GMAC_MAC_TIMESTAMP_CONTROL_OFFSET (0xB00U)
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT (0U)
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSENA_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT) /* 0x00000001 */
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT (1U)
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT) /* 0x00000002 */
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT (2U)
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSINIT_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT) /* 0x00000004 */
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT (3U)
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT) /* 0x00000008 */
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSTRIG_SHIFT (4U)
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSTRIG_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSTRIG_SHIFT) /* 0x00000010 */
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT (5U)
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT) /* 0x00000020 */
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT (8U)
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSENALL_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT) /* 0x00000100 */
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT (9U)
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT) /* 0x00000200 */
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT (10U)
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT) /* 0x00000400 */
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT (11U)
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT) /* 0x00000800 */
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT (12U)
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT) /* 0x00001000 */
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT (13U)
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT) /* 0x00002000 */
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT (14U)
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT) /* 0x00004000 */
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT (15U)
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT) /* 0x00008000 */
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#define GMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT (16U)
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#define GMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK (0x3U << GMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT) /* 0x00030000 */
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT (18U)
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#define GMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT) /* 0x00040000 */
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#define GMAC_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT (20U)
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#define GMAC_MAC_TIMESTAMP_CONTROL_ESTI_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT) /* 0x00100000 */
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#define GMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT (24U)
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#define GMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT) /* 0x01000000 */
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#define GMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT (28U)
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#define GMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT) /* 0x10000000 */
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/* MAC_SUB_SECOND_INCREMENT */
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#define GMAC_MAC_SUB_SECOND_INCREMENT_OFFSET (0xB04U)
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#define GMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT (16U)
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#define GMAC_MAC_SUB_SECOND_INCREMENT_SSINC_MASK (0xFFU << GMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT) /* 0x00FF0000 */
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/* MAC_SYSTEM_TIME_SECS */
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#define GMAC_MAC_SYSTEM_TIME_SECS_OFFSET (0xB08U)
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#define GMAC_MAC_SYSTEM_TIME_SECS_TSS_SHIFT (0U)
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#define GMAC_MAC_SYSTEM_TIME_SECS_TSS_MASK (0xFFFFFFFFU << GMAC_MAC_SYSTEM_TIME_SECS_TSS_SHIFT) /* 0xFFFFFFFF */
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/* MAC_SYSTEM_TIME_NS */
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#define GMAC_MAC_SYSTEM_TIME_NS_OFFSET (0xB0CU)
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#define GMAC_MAC_SYSTEM_TIME_NS_TSSS_SHIFT (0U)
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#define GMAC_MAC_SYSTEM_TIME_NS_TSSS_MASK (0x7FFFFFFFU << GMAC_MAC_SYSTEM_TIME_NS_TSSS_SHIFT) /* 0x7FFFFFFF */
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/* MAC_SYS_TIME_SECS_UPDATE */
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#define GMAC_MAC_SYS_TIME_SECS_UPDATE_OFFSET (0xB10U)
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#define GMAC_MAC_SYS_TIME_SECS_UPDATE_TSS_SHIFT (0U)
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#define GMAC_MAC_SYS_TIME_SECS_UPDATE_TSS_MASK (0xFFFFFFFFU << GMAC_MAC_SYS_TIME_SECS_UPDATE_TSS_SHIFT) /* 0xFFFFFFFF */
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/* MAC_SYS_TIME_NS_UPDATE */
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#define GMAC_MAC_SYS_TIME_NS_UPDATE_OFFSET (0xB14U)
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#define GMAC_MAC_SYS_TIME_NS_UPDATE_TSSS_SHIFT (0U)
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#define GMAC_MAC_SYS_TIME_NS_UPDATE_TSSS_MASK (0x7FFFFFFFU << GMAC_MAC_SYS_TIME_NS_UPDATE_TSSS_SHIFT) /* 0x7FFFFFFF */
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#define GMAC_MAC_SYS_TIME_NS_UPDATE_ADDSUB_SHIFT (31U)
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#define GMAC_MAC_SYS_TIME_NS_UPDATE_ADDSUB_MASK (0x1U << GMAC_MAC_SYS_TIME_NS_UPDATE_ADDSUB_SHIFT) /* 0x80000000 */
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/* MAC_TIMESTAMP_ADDEND */
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#define GMAC_MAC_TIMESTAMP_ADDEND_OFFSET (0xB18U)
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#define GMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT (0U)
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#define GMAC_MAC_TIMESTAMP_ADDEND_TSAR_MASK (0xFFFFFFFFU << GMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT) /* 0xFFFFFFFF */
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/* MAC_TIMESTAMP_STATUS */
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#define GMAC_MAC_TIMESTAMP_STATUS_OFFSET (0xB20U)
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#define GMAC_MAC_TIMESTAMP_STATUS (0x0U)
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#define GMAC_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT (0U)
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#define GMAC_MAC_TIMESTAMP_STATUS_TSSOVF_MASK (0x1U << GMAC_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT) /* 0x00000001 */
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#define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT (1U)
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#define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK (0x1U << GMAC_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT) /* 0x00000002 */
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#define GMAC_MAC_TIMESTAMP_STATUS_AUXTSTRIG_SHIFT (2U)
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#define GMAC_MAC_TIMESTAMP_STATUS_AUXTSTRIG_MASK (0x1U << GMAC_MAC_TIMESTAMP_STATUS_AUXTSTRIG_SHIFT) /* 0x00000004 */
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#define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT (3U)
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#define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK (0x1U << GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT) /* 0x00000008 */
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#define GMAC_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT (15U)
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#define GMAC_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK (0x1U << GMAC_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT) /* 0x00008000 */
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#define GMAC_MAC_TIMESTAMP_STATUS_ATSSTM_SHIFT (24U)
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#define GMAC_MAC_TIMESTAMP_STATUS_ATSSTM_MASK (0x1U << GMAC_MAC_TIMESTAMP_STATUS_ATSSTM_SHIFT) /* 0x01000000 */
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#define GMAC_MAC_TIMESTAMP_STATUS_ATSNS_SHIFT (25U)
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#define GMAC_MAC_TIMESTAMP_STATUS_ATSNS_MASK (0x1FU << GMAC_MAC_TIMESTAMP_STATUS_ATSNS_SHIFT) /* 0x3E000000 */
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/* MAC_TX_TS_STATUS_NS */
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#define GMAC_MAC_TX_TS_STATUS_NS_OFFSET (0xB30U)
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#define GMAC_MAC_TX_TS_STATUS_NS (0x0U)
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#define GMAC_MAC_TX_TS_STATUS_NS_TXTSSLO_SHIFT (0U)
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#define GMAC_MAC_TX_TS_STATUS_NS_TXTSSLO_MASK (0x7FFFFFFFU << GMAC_MAC_TX_TS_STATUS_NS_TXTSSLO_SHIFT) /* 0x7FFFFFFF */
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#define GMAC_MAC_TX_TS_STATUS_NS_TXTSSMIS_SHIFT (31U)
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#define GMAC_MAC_TX_TS_STATUS_NS_TXTSSMIS_MASK (0x1U << GMAC_MAC_TX_TS_STATUS_NS_TXTSSMIS_SHIFT) /* 0x80000000 */
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/* MAC_TX_TS_STATUS_SECS */
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#define GMAC_MAC_TX_TS_STATUS_SECS_OFFSET (0xB34U)
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#define GMAC_MAC_TX_TS_STATUS_SECS (0x0U)
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#define GMAC_MAC_TX_TS_STATUS_SECS_TXTSSHI_SHIFT (0U)
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#define GMAC_MAC_TX_TS_STATUS_SECS_TXTSSHI_MASK (0xFFFFFFFFU << GMAC_MAC_TX_TS_STATUS_SECS_TXTSSHI_SHIFT) /* 0xFFFFFFFF */
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/* MAC_AUXILIARY_CONTROL */
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#define GMAC_MAC_AUXILIARY_CONTROL_OFFSET (0xB40U)
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#define GMAC_MAC_AUXILIARY_CONTROL_ATSFC_SHIFT (0U)
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#define GMAC_MAC_AUXILIARY_CONTROL_ATSFC_MASK (0x1U << GMAC_MAC_AUXILIARY_CONTROL_ATSFC_SHIFT) /* 0x00000001 */
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/* MAC_AUXILIARY_TS_NS */
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#define GMAC_MAC_AUXILIARY_TS_NS_OFFSET (0xB48U)
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#define GMAC_MAC_AUXILIARY_TS_NS (0x0U)
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#define GMAC_MAC_AUXILIARY_TS_NS_AUXTSLO_SHIFT (0U)
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#define GMAC_MAC_AUXILIARY_TS_NS_AUXTSLO_MASK (0x7FFFFFFFU << GMAC_MAC_AUXILIARY_TS_NS_AUXTSLO_SHIFT) /* 0x7FFFFFFF */
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/* MAC_AUXILIARY_TS_SECS */
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#define GMAC_MAC_AUXILIARY_TS_SECS_OFFSET (0xB4CU)
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#define GMAC_MAC_AUXILIARY_TS_SECS_AUXTSHI_SHIFT (0U)
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#define GMAC_MAC_AUXILIARY_TS_SECS_AUXTSHI_MASK (0xFFFFFFFFU << GMAC_MAC_AUXILIARY_TS_SECS_AUXTSHI_SHIFT) /* 0xFFFFFFFF */
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/* MAC_TS_INGRESS_CORR_NS */
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#define GMAC_MAC_TS_INGRESS_CORR_NS_OFFSET (0xB58U)
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#define GMAC_MAC_TS_INGRESS_CORR_NS_TSIC_SHIFT (0U)
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#define GMAC_MAC_TS_INGRESS_CORR_NS_TSIC_MASK (0xFFFFFFFFU << GMAC_MAC_TS_INGRESS_CORR_NS_TSIC_SHIFT) /* 0xFFFFFFFF */
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/* MAC_TS_EGRESS_CORR_NS */
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#define GMAC_MAC_TS_EGRESS_CORR_NS_OFFSET (0xB5CU)
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#define GMAC_MAC_TS_EGRESS_CORR_NS_TSEC_SHIFT (0U)
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#define GMAC_MAC_TS_EGRESS_CORR_NS_TSEC_MASK (0xFFFFFFFFU << GMAC_MAC_TS_EGRESS_CORR_NS_TSEC_SHIFT) /* 0xFFFFFFFF */
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/* MAC_TS_INGRESS_LATENCY */
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#define GMAC_MAC_TS_INGRESS_LATENCY_OFFSET (0xB68U)
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#define GMAC_MAC_TS_INGRESS_LATENCY (0x0U)
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#define GMAC_MAC_TS_INGRESS_LATENCY_ITLSNS_SHIFT (8U)
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#define GMAC_MAC_TS_INGRESS_LATENCY_ITLSNS_MASK (0xFFU << GMAC_MAC_TS_INGRESS_LATENCY_ITLSNS_SHIFT) /* 0x0000FF00 */
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#define GMAC_MAC_TS_INGRESS_LATENCY_ITLNS_SHIFT (16U)
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#define GMAC_MAC_TS_INGRESS_LATENCY_ITLNS_MASK (0xFFU << GMAC_MAC_TS_INGRESS_LATENCY_ITLNS_SHIFT) /* 0x00FF0000 */
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/* MAC_TS_EGRESS_LATENCY */
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#define GMAC_MAC_TS_EGRESS_LATENCY_OFFSET (0xB6CU)
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#define GMAC_MAC_TS_EGRESS_LATENCY (0x0U)
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#define GMAC_MAC_TS_EGRESS_LATENCY_ETLSNS_SHIFT (8U)
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#define GMAC_MAC_TS_EGRESS_LATENCY_ETLSNS_MASK (0xFFU << GMAC_MAC_TS_EGRESS_LATENCY_ETLSNS_SHIFT) /* 0x0000FF00 */
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#define GMAC_MAC_TS_EGRESS_LATENCY_ETLNS_SHIFT (16U)
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#define GMAC_MAC_TS_EGRESS_LATENCY_ETLNS_MASK (0xFFU << GMAC_MAC_TS_EGRESS_LATENCY_ETLNS_SHIFT) /* 0x00FF0000 */
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/* MAC_PPS_CONTROL */
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#define GMAC_MAC_PPS_CONTROL_OFFSET (0xB70U)
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#define GMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT (0U)
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#define GMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK (0xFU << GMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT) /* 0x0000000F */
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/* MTL_DBG_CTL */
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#define GMAC_MTL_DBG_CTL_OFFSET (0xC08U)
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#define GMAC_MTL_DBG_CTL_FDBGEN_SHIFT (0U)
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#define GMAC_MTL_DBG_CTL_FDBGEN_MASK (0x1U << GMAC_MTL_DBG_CTL_FDBGEN_SHIFT) /* 0x00000001 */
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#define GMAC_MTL_DBG_CTL_DBGMOD_SHIFT (1U)
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#define GMAC_MTL_DBG_CTL_DBGMOD_MASK (0x1U << GMAC_MTL_DBG_CTL_DBGMOD_SHIFT) /* 0x00000002 */
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#define GMAC_MTL_DBG_CTL_BYTEEN_SHIFT (2U)
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#define GMAC_MTL_DBG_CTL_BYTEEN_MASK (0x3U << GMAC_MTL_DBG_CTL_BYTEEN_SHIFT) /* 0x0000000C */
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#define GMAC_MTL_DBG_CTL_PKTSTATE_SHIFT (5U)
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#define GMAC_MTL_DBG_CTL_PKTSTATE_MASK (0x3U << GMAC_MTL_DBG_CTL_PKTSTATE_SHIFT) /* 0x00000060 */
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#define GMAC_MTL_DBG_CTL_RSTALL_SHIFT (8U)
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#define GMAC_MTL_DBG_CTL_RSTALL_MASK (0x1U << GMAC_MTL_DBG_CTL_RSTALL_SHIFT) /* 0x00000100 */
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#define GMAC_MTL_DBG_CTL_RSTSEL_SHIFT (9U)
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#define GMAC_MTL_DBG_CTL_RSTSEL_MASK (0x1U << GMAC_MTL_DBG_CTL_RSTSEL_SHIFT) /* 0x00000200 */
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#define GMAC_MTL_DBG_CTL_FIFORDEN_SHIFT (10U)
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#define GMAC_MTL_DBG_CTL_FIFORDEN_MASK (0x1U << GMAC_MTL_DBG_CTL_FIFORDEN_SHIFT) /* 0x00000400 */
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#define GMAC_MTL_DBG_CTL_FIFOWREN_SHIFT (11U)
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#define GMAC_MTL_DBG_CTL_FIFOWREN_MASK (0x1U << GMAC_MTL_DBG_CTL_FIFOWREN_SHIFT) /* 0x00000800 */
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#define GMAC_MTL_DBG_CTL_FIFOSEL_SHIFT (12U)
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#define GMAC_MTL_DBG_CTL_FIFOSEL_MASK (0x3U << GMAC_MTL_DBG_CTL_FIFOSEL_SHIFT) /* 0x00003000 */
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#define GMAC_MTL_DBG_CTL_PKTIE_SHIFT (14U)
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#define GMAC_MTL_DBG_CTL_PKTIE_MASK (0x1U << GMAC_MTL_DBG_CTL_PKTIE_SHIFT) /* 0x00004000 */
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#define GMAC_MTL_DBG_CTL_STSIE_SHIFT (15U)
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#define GMAC_MTL_DBG_CTL_STSIE_MASK (0x1U << GMAC_MTL_DBG_CTL_STSIE_SHIFT) /* 0x00008000 */
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/* MTL_DBG_STS */
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#define GMAC_MTL_DBG_STS_OFFSET (0xC0CU)
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#define GMAC_MTL_DBG_STS_FIFOBUSY_SHIFT (0U)
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#define GMAC_MTL_DBG_STS_FIFOBUSY_MASK (0x1U << GMAC_MTL_DBG_STS_FIFOBUSY_SHIFT) /* 0x00000001 */
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#define GMAC_MTL_DBG_STS_PKTSTATE_SHIFT (1U)
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#define GMAC_MTL_DBG_STS_PKTSTATE_MASK (0x3U << GMAC_MTL_DBG_STS_PKTSTATE_SHIFT) /* 0x00000006 */
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#define GMAC_MTL_DBG_STS_BYTEEN_SHIFT (3U)
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#define GMAC_MTL_DBG_STS_BYTEEN_MASK (0x3U << GMAC_MTL_DBG_STS_BYTEEN_SHIFT) /* 0x00000018 */
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#define GMAC_MTL_DBG_STS_PKTI_SHIFT (8U)
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#define GMAC_MTL_DBG_STS_PKTI_MASK (0x1U << GMAC_MTL_DBG_STS_PKTI_SHIFT) /* 0x00000100 */
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#define GMAC_MTL_DBG_STS_STSI_SHIFT (9U)
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#define GMAC_MTL_DBG_STS_STSI_MASK (0x1U << GMAC_MTL_DBG_STS_STSI_SHIFT) /* 0x00000200 */
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#define GMAC_MTL_DBG_STS_LOCR_SHIFT (15U)
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#define GMAC_MTL_DBG_STS_LOCR_MASK (0x1U << GMAC_MTL_DBG_STS_LOCR_SHIFT) /* 0x00008000 */
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/* MTL_FIFO_DEBUG_DATA */
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#define GMAC_MTL_FIFO_DEBUG_DATA_OFFSET (0xC10U)
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#define GMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT (0U)
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#define GMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK (0xFFFFFFFFU << GMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT) /* 0xFFFFFFFF */
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/* MTL_INTERRUPT_STATUS */
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#define GMAC_MTL_INTERRUPT_STATUS_OFFSET (0xC20U)
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#define GMAC_MTL_INTERRUPT_STATUS (0x0U)
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#define GMAC_MTL_INTERRUPT_STATUS_Q0IS_SHIFT (0U)
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#define GMAC_MTL_INTERRUPT_STATUS_Q0IS_MASK (0x1U << GMAC_MTL_INTERRUPT_STATUS_Q0IS_SHIFT) /* 0x00000001 */
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#define GMAC_MTL_INTERRUPT_STATUS_DBGIS_SHIFT (17U)
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#define GMAC_MTL_INTERRUPT_STATUS_DBGIS_MASK (0x1U << GMAC_MTL_INTERRUPT_STATUS_DBGIS_SHIFT) /* 0x00020000 */
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/* MTL_TXQ0_OPERATION_MODE */
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#define GMAC_MTL_TXQ0_OPERATION_MODE_OFFSET (0xD00U)
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#define GMAC_MTL_TXQ0_OPERATION_MODE_FTQ_SHIFT (0U)
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#define GMAC_MTL_TXQ0_OPERATION_MODE_FTQ_MASK (0x1U << GMAC_MTL_TXQ0_OPERATION_MODE_FTQ_SHIFT) /* 0x00000001 */
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#define GMAC_MTL_TXQ0_OPERATION_MODE_TSF_SHIFT (1U)
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#define GMAC_MTL_TXQ0_OPERATION_MODE_TSF_MASK (0x1U << GMAC_MTL_TXQ0_OPERATION_MODE_TSF_SHIFT) /* 0x00000002 */
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#define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT (4U)
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#define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_MASK (0x7U << GMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT) /* 0x00000070 */
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/* MTL_TXQ0_UNDERFLOW */
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#define GMAC_MTL_TXQ0_UNDERFLOW_OFFSET (0xD04U)
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#define GMAC_MTL_TXQ0_UNDERFLOW (0x0U)
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#define GMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT (0U)
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#define GMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_MASK (0x7FFU << GMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT) /* 0x000007FF */
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#define GMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_SHIFT (11U)
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#define GMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_MASK (0x1U << GMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_SHIFT) /* 0x00000800 */
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/* MTL_TXQ0_DEBUG */
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#define GMAC_MTL_TXQ0_DEBUG_OFFSET (0xD08U)
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#define GMAC_MTL_TXQ0_DEBUG (0x0U)
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#define GMAC_MTL_TXQ0_DEBUG_TXQPAUSED_SHIFT (0U)
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#define GMAC_MTL_TXQ0_DEBUG_TXQPAUSED_MASK (0x1U << GMAC_MTL_TXQ0_DEBUG_TXQPAUSED_SHIFT) /* 0x00000001 */
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#define GMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT (1U)
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#define GMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK (0x3U << GMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) /* 0x00000006 */
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#define GMAC_MTL_TXQ0_DEBUG_TWCSTS_SHIFT (3U)
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#define GMAC_MTL_TXQ0_DEBUG_TWCSTS_MASK (0x1U << GMAC_MTL_TXQ0_DEBUG_TWCSTS_SHIFT) /* 0x00000008 */
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#define GMAC_MTL_TXQ0_DEBUG_TXQSTS_SHIFT (4U)
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#define GMAC_MTL_TXQ0_DEBUG_TXQSTS_MASK (0x1U << GMAC_MTL_TXQ0_DEBUG_TXQSTS_SHIFT) /* 0x00000010 */
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#define GMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_SHIFT (5U)
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#define GMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_MASK (0x1U << GMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_SHIFT) /* 0x00000020 */
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#define GMAC_MTL_TXQ0_DEBUG_PTXQ_SHIFT (16U)
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#define GMAC_MTL_TXQ0_DEBUG_PTXQ_MASK (0x7U << GMAC_MTL_TXQ0_DEBUG_PTXQ_SHIFT) /* 0x00070000 */
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#define GMAC_MTL_TXQ0_DEBUG_STXSTSF_SHIFT (20U)
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#define GMAC_MTL_TXQ0_DEBUG_STXSTSF_MASK (0x7U << GMAC_MTL_TXQ0_DEBUG_STXSTSF_SHIFT) /* 0x00700000 */
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/* MTL_Q0_INTERRUPT_CTRL_STATUS */
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#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_OFFSET (0xD2CU)
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#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS_SHIFT (0U)
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#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS_MASK (0x1U << GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS_SHIFT) /* 0x00000001 */
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#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUIE_SHIFT (8U)
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#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUIE_MASK (0x1U << GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUIE_SHIFT) /* 0x00000100 */
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#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOVFIS_SHIFT (16U)
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#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOVFIS_MASK (0x1U << GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOVFIS_SHIFT) /* 0x00010000 */
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#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOIE_SHIFT (24U)
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#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOIE_MASK (0x1U << GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOIE_SHIFT) /* 0x01000000 */
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/* MTL_RXQ0_OPERATION_MODE */
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#define GMAC_MTL_RXQ0_OPERATION_MODE_OFFSET (0xD30U)
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#define GMAC_MTL_RXQ0_OPERATION_MODE_RTC_SHIFT (0U)
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#define GMAC_MTL_RXQ0_OPERATION_MODE_RTC_MASK (0x3U << GMAC_MTL_RXQ0_OPERATION_MODE_RTC_SHIFT) /* 0x00000003 */
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#define GMAC_MTL_RXQ0_OPERATION_MODE_FUP_SHIFT (3U)
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#define GMAC_MTL_RXQ0_OPERATION_MODE_FUP_MASK (0x1U << GMAC_MTL_RXQ0_OPERATION_MODE_FUP_SHIFT) /* 0x00000008 */
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#define GMAC_MTL_RXQ0_OPERATION_MODE_FEP_SHIFT (4U)
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#define GMAC_MTL_RXQ0_OPERATION_MODE_FEP_MASK (0x1U << GMAC_MTL_RXQ0_OPERATION_MODE_FEP_SHIFT) /* 0x00000010 */
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#define GMAC_MTL_RXQ0_OPERATION_MODE_RSF_SHIFT (5U)
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#define GMAC_MTL_RXQ0_OPERATION_MODE_RSF_MASK (0x1U << GMAC_MTL_RXQ0_OPERATION_MODE_RSF_SHIFT) /* 0x00000020 */
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#define GMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_SHIFT (6U)
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#define GMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_MASK (0x1U << GMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_SHIFT) /* 0x00000040 */
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#define GMAC_MTL_RXQ0_OPERATION_MODE_EHFC_SHIFT (7U)
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#define GMAC_MTL_RXQ0_OPERATION_MODE_EHFC_MASK (0x1U << GMAC_MTL_RXQ0_OPERATION_MODE_EHFC_SHIFT) /* 0x00000080 */
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#define GMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT (8U)
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#define GMAC_MTL_RXQ0_OPERATION_MODE_RFA_MASK (0x3FU << GMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT) /* 0x00003F00 */
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#define GMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT (14U)
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#define GMAC_MTL_RXQ0_OPERATION_MODE_RFD_MASK (0x3FU << GMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) /* 0x000FC000 */
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/* MTL_RXQ0_MISS_PKT_OVF_CNT */
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#define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_OFFSET (0xD34U)
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#define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT (0x0U)
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#define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_OVFPKTCNT_SHIFT (0U)
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#define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_OVFPKTCNT_MASK (0x7FFU << GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_OVFPKTCNT_SHIFT) /* 0x000007FF */
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#define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_OVFCNTOVF_SHIFT (11U)
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#define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_OVFCNTOVF_MASK (0x1U << GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_OVFCNTOVF_SHIFT) /* 0x00000800 */
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#define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_MISPKTCNT_SHIFT (16U)
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#define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_MISPKTCNT_MASK (0x7FFU << GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_MISPKTCNT_SHIFT) /* 0x07FF0000 */
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#define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_MISCNTOVF_SHIFT (27U)
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#define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_MISCNTOVF_MASK (0x1U << GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_MISCNTOVF_SHIFT) /* 0x08000000 */
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/* MTL_RXQ0_DEBUG */
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#define GMAC_MTL_RXQ0_DEBUG_OFFSET (0xD38U)
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#define GMAC_MTL_RXQ0_DEBUG (0x0U)
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#define GMAC_MTL_RXQ0_DEBUG_RWCSTS_SHIFT (0U)
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#define GMAC_MTL_RXQ0_DEBUG_RWCSTS_MASK (0x1U << GMAC_MTL_RXQ0_DEBUG_RWCSTS_SHIFT) /* 0x00000001 */
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#define GMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT (1U)
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#define GMAC_MTL_RXQ0_DEBUG_RRCSTS_MASK (0x3U << GMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT) /* 0x00000006 */
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#define GMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT (4U)
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#define GMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK (0x3U << GMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) /* 0x00000030 */
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#define GMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT (16U)
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#define GMAC_MTL_RXQ0_DEBUG_PRXQ_MASK (0xFU << GMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT) /* 0x000F0000 */
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/* DMA_MODE */
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#define GMAC_DMA_MODE_OFFSET (0x1000U)
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#define GMAC_DMA_MODE_SWR_SHIFT (0U)
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#define GMAC_DMA_MODE_SWR_MASK (0x1U << GMAC_DMA_MODE_SWR_SHIFT) /* 0x00000001 */
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#define GMAC_DMA_MODE_DSPW_SHIFT (8U)
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#define GMAC_DMA_MODE_DSPW_MASK (0x1U << GMAC_DMA_MODE_DSPW_SHIFT) /* 0x00000100 */
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#define GMAC_DMA_MODE_INTM_SHIFT (16U)
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#define GMAC_DMA_MODE_INTM_MASK (0x3U << GMAC_DMA_MODE_INTM_SHIFT) /* 0x00030000 */
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/* DMA_SYSBUS_MODE */
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#define GMAC_DMA_SYSBUS_MODE_OFFSET (0x1004U)
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#define GMAC_DMA_SYSBUS_MODE_FB_SHIFT (0U)
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#define GMAC_DMA_SYSBUS_MODE_FB_MASK (0x1U << GMAC_DMA_SYSBUS_MODE_FB_SHIFT) /* 0x00000001 */
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#define GMAC_DMA_SYSBUS_MODE_BLEN4_SHIFT (1U)
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#define GMAC_DMA_SYSBUS_MODE_BLEN4_MASK (0x1U << GMAC_DMA_SYSBUS_MODE_BLEN4_SHIFT) /* 0x00000002 */
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#define GMAC_DMA_SYSBUS_MODE_BLEN8_SHIFT (2U)
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#define GMAC_DMA_SYSBUS_MODE_BLEN8_MASK (0x1U << GMAC_DMA_SYSBUS_MODE_BLEN8_SHIFT) /* 0x00000004 */
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#define GMAC_DMA_SYSBUS_MODE_BLEN16_SHIFT (3U)
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#define GMAC_DMA_SYSBUS_MODE_BLEN16_MASK (0x1U << GMAC_DMA_SYSBUS_MODE_BLEN16_SHIFT) /* 0x00000008 */
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#define GMAC_DMA_SYSBUS_MODE_AALE_SHIFT (10U)
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#define GMAC_DMA_SYSBUS_MODE_AALE_MASK (0x1U << GMAC_DMA_SYSBUS_MODE_AALE_SHIFT) /* 0x00000400 */
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#define GMAC_DMA_SYSBUS_MODE_AAL_SHIFT (12U)
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#define GMAC_DMA_SYSBUS_MODE_AAL_MASK (0x1U << GMAC_DMA_SYSBUS_MODE_AAL_SHIFT) /* 0x00001000 */
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#define GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT (16U)
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#define GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK (0x7U << GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) /* 0x00070000 */
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#define GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT (24U)
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#define GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK (0x3U << GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT) /* 0x03000000 */
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#define GMAC_DMA_SYSBUS_MODE_LPI_XIT_PKT_SHIFT (30U)
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#define GMAC_DMA_SYSBUS_MODE_LPI_XIT_PKT_MASK (0x1U << GMAC_DMA_SYSBUS_MODE_LPI_XIT_PKT_SHIFT) /* 0x40000000 */
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#define GMAC_DMA_SYSBUS_MODE_EN_LPI_SHIFT (31U)
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#define GMAC_DMA_SYSBUS_MODE_EN_LPI_MASK (0x1U << GMAC_DMA_SYSBUS_MODE_EN_LPI_SHIFT) /* 0x80000000 */
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/* DMA_INTERRUPT_STATUS */
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#define GMAC_DMA_INTERRUPT_STATUS_OFFSET (0x1008U)
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#define GMAC_DMA_INTERRUPT_STATUS (0x0U)
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#define GMAC_DMA_INTERRUPT_STATUS_DC0IS_SHIFT (0U)
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#define GMAC_DMA_INTERRUPT_STATUS_DC0IS_MASK (0x1U << GMAC_DMA_INTERRUPT_STATUS_DC0IS_SHIFT) /* 0x00000001 */
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#define GMAC_DMA_INTERRUPT_STATUS_MTLIS_SHIFT (16U)
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#define GMAC_DMA_INTERRUPT_STATUS_MTLIS_MASK (0x1U << GMAC_DMA_INTERRUPT_STATUS_MTLIS_SHIFT) /* 0x00010000 */
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#define GMAC_DMA_INTERRUPT_STATUS_MACIS_SHIFT (17U)
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#define GMAC_DMA_INTERRUPT_STATUS_MACIS_MASK (0x1U << GMAC_DMA_INTERRUPT_STATUS_MACIS_SHIFT) /* 0x00020000 */
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/* DMA_DEBUG_STATUS0 */
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#define GMAC_DMA_DEBUG_STATUS0_OFFSET (0x100CU)
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#define GMAC_DMA_DEBUG_STATUS0 (0x0U)
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#define GMAC_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT (0U)
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#define GMAC_DMA_DEBUG_STATUS0_AXWHSTS_MASK (0x1U << GMAC_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT) /* 0x00000001 */
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#define GMAC_DMA_DEBUG_STATUS0_AXRHSTS_SHIFT (1U)
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#define GMAC_DMA_DEBUG_STATUS0_AXRHSTS_MASK (0x1U << GMAC_DMA_DEBUG_STATUS0_AXRHSTS_SHIFT) /* 0x00000002 */
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#define GMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT (8U)
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#define GMAC_DMA_DEBUG_STATUS0_RPS0_MASK (0xFU << GMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT) /* 0x00000F00 */
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#define GMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT (12U)
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#define GMAC_DMA_DEBUG_STATUS0_TPS0_MASK (0xFU << GMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT) /* 0x0000F000 */
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/* AXI_LPI_ENTRY_INTERVAL */
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#define GMAC_AXI_LPI_ENTRY_INTERVAL_OFFSET (0x1040U)
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#define GMAC_AXI_LPI_ENTRY_INTERVAL_LPIEI_SHIFT (0U)
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#define GMAC_AXI_LPI_ENTRY_INTERVAL_LPIEI_MASK (0xFU << GMAC_AXI_LPI_ENTRY_INTERVAL_LPIEI_SHIFT) /* 0x0000000F */
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/* DMA_CH0_CONTROL */
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#define GMAC_DMA_CH0_CONTROL_OFFSET (0x1100U)
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#define GMAC_DMA_CH0_CONTROL_MSS_SHIFT (0U)
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#define GMAC_DMA_CH0_CONTROL_MSS_MASK (0x3FFFU << GMAC_DMA_CH0_CONTROL_MSS_SHIFT) /* 0x00003FFF */
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#define GMAC_DMA_CH0_CONTROL_PBLX8_SHIFT (16U)
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#define GMAC_DMA_CH0_CONTROL_PBLX8_MASK (0x1U << GMAC_DMA_CH0_CONTROL_PBLX8_SHIFT) /* 0x00010000 */
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#define GMAC_DMA_CH0_CONTROL_DSL_SHIFT (18U)
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#define GMAC_DMA_CH0_CONTROL_DSL_MASK (0x7U << GMAC_DMA_CH0_CONTROL_DSL_SHIFT) /* 0x001C0000 */
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/* DMA_CH0_TX_CONTROL */
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#define GMAC_DMA_CH0_TX_CONTROL_OFFSET (0x1104U)
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#define GMAC_DMA_CH0_TX_CONTROL_ST_SHIFT (0U)
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#define GMAC_DMA_CH0_TX_CONTROL_ST_MASK (0x1U << GMAC_DMA_CH0_TX_CONTROL_ST_SHIFT) /* 0x00000001 */
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#define GMAC_DMA_CH0_TX_CONTROL_OSF_SHIFT (4U)
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#define GMAC_DMA_CH0_TX_CONTROL_OSF_MASK (0x1U << GMAC_DMA_CH0_TX_CONTROL_OSF_SHIFT) /* 0x00000010 */
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#define GMAC_DMA_CH0_TX_CONTROL_TSE_SHIFT (12U)
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#define GMAC_DMA_CH0_TX_CONTROL_TSE_MASK (0x1U << GMAC_DMA_CH0_TX_CONTROL_TSE_SHIFT) /* 0x00001000 */
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#define GMAC_DMA_CH0_TX_CONTROL_TSE_MODE_SHIFT (13U)
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#define GMAC_DMA_CH0_TX_CONTROL_TSE_MODE_MASK (0x3U << GMAC_DMA_CH0_TX_CONTROL_TSE_MODE_SHIFT) /* 0x00006000 */
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#define GMAC_DMA_CH0_TX_CONTROL_IPBL_SHIFT (15U)
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#define GMAC_DMA_CH0_TX_CONTROL_IPBL_MASK (0x1U << GMAC_DMA_CH0_TX_CONTROL_IPBL_SHIFT) /* 0x00008000 */
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#define GMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT (16U)
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#define GMAC_DMA_CH0_TX_CONTROL_TXPBL_MASK (0x3FU << GMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT) /* 0x003F0000 */
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/* DMA_CH0_RX_CONTROL */
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#define GMAC_DMA_CH0_RX_CONTROL_OFFSET (0x1108U)
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#define GMAC_DMA_CH0_RX_CONTROL_SR_SHIFT (0U)
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#define GMAC_DMA_CH0_RX_CONTROL_SR_MASK (0x1U << GMAC_DMA_CH0_RX_CONTROL_SR_SHIFT) /* 0x00000001 */
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#define GMAC_DMA_CH0_RX_CONTROL_RBSZ_3_0_SHIFT (1U)
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#define GMAC_DMA_CH0_RX_CONTROL_RBSZ_3_0_MASK (0x7U << GMAC_DMA_CH0_RX_CONTROL_RBSZ_3_0_SHIFT) /* 0x0000000E */
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#define GMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_SHIFT (4U)
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#define GMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_MASK (0x7FFU << GMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_SHIFT) /* 0x00007FF0 */
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#define GMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT (16U)
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#define GMAC_DMA_CH0_RX_CONTROL_RXPBL_MASK (0x3FU << GMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT) /* 0x003F0000 */
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#define GMAC_DMA_CH0_RX_CONTROL_RPF_SHIFT (31U)
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#define GMAC_DMA_CH0_RX_CONTROL_RPF_MASK (0x1U << GMAC_DMA_CH0_RX_CONTROL_RPF_SHIFT) /* 0x80000000 */
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/* DMA_CH0_TXDESC_LIST_ADDRESS */
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#define GMAC_DMA_CH0_TXDESC_LIST_ADDRESS_OFFSET (0x1114U)
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#define GMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT (3U)
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#define GMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_MASK (0x1FFFFFFFU << GMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT) /* 0xFFFFFFF8 */
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/* DMA_CH0_RXDESC_LIST_ADDRESS */
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#define GMAC_DMA_CH0_RXDESC_LIST_ADDRESS_OFFSET (0x111CU)
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#define GMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT (3U)
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#define GMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_MASK (0x1FFFFFFFU << GMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT) /* 0xFFFFFFF8 */
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/* DMA_CH0_TXDESC_TAIL_POINTER */
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#define GMAC_DMA_CH0_TXDESC_TAIL_POINTER_OFFSET (0x1120U)
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#define GMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT (3U)
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#define GMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_MASK (0x1FFFFFFFU << GMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT) /* 0xFFFFFFF8 */
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/* DMA_CH0_RXDESC_TAIL_POINTER */
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#define GMAC_DMA_CH0_RXDESC_TAIL_POINTER_OFFSET (0x1128U)
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#define GMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDRT_SHIFT (3U)
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#define GMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDRT_MASK (0x1FFFFFFFU << GMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDRT_SHIFT) /* 0xFFFFFFF8 */
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/* DMA_CH0_TXDESC_RING_LENGTH */
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#define GMAC_DMA_CH0_TXDESC_RING_LENGTH_OFFSET (0x112CU)
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#define GMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT (0U)
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#define GMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU << GMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT) /* 0x000003FF */
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/* DMA_CH0_RXDESC_RING_LENGTH */
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#define GMAC_DMA_CH0_RXDESC_RING_LENGTH_OFFSET (0x1130U)
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#define GMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT (0U)
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#define GMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU << GMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT) /* 0x000003FF */
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/* DMA_CH0_INTERRUPT_ENABLE */
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_OFFSET (0x1134U)
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_SHIFT (0U)
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_SHIFT) /* 0x00000001 */
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_SHIFT (1U)
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_SHIFT) /* 0x00000002 */
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_SHIFT (2U)
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_SHIFT) /* 0x00000004 */
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_SHIFT (6U)
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_SHIFT) /* 0x00000040 */
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_SHIFT (7U)
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_SHIFT) /* 0x00000080 */
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_SHIFT (8U)
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_SHIFT) /* 0x00000100 */
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_SHIFT (9U)
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_SHIFT) /* 0x00000200 */
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_SHIFT (10U)
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_SHIFT) /* 0x00000400 */
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_SHIFT (11U)
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_SHIFT) /* 0x00000800 */
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_SHIFT (12U)
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_SHIFT) /* 0x00001000 */
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_SHIFT (13U)
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_SHIFT) /* 0x00002000 */
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_SHIFT (14U)
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_SHIFT) /* 0x00004000 */
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_SHIFT (15U)
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#define GMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_SHIFT) /* 0x00008000 */
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/* DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER */
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#define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_OFFSET (0x1138U)
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#define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT (0U)
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#define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK (0xFFU << GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT) /* 0x000000FF */
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#define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT (16U)
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#define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK (0x3U << GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT) /* 0x00030000 */
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/* DMA_CH0_CURRENT_APP_TXDESC */
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#define GMAC_DMA_CH0_CURRENT_APP_TXDESC_OFFSET (0x1144U)
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#define GMAC_DMA_CH0_CURRENT_APP_TXDESC (0x0U)
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#define GMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT (0U)
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#define GMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFFU << GMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT) /* 0xFFFFFFFF */
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/* DMA_CH0_CURRENT_APP_RXDESC */
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#define GMAC_DMA_CH0_CURRENT_APP_RXDESC_OFFSET (0x114CU)
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#define GMAC_DMA_CH0_CURRENT_APP_RXDESC (0x0U)
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#define GMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT (0U)
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#define GMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFFU << GMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT) /* 0xFFFFFFFF */
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/* DMA_CH0_CURRENT_APP_TXBUFFER */
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#define GMAC_DMA_CH0_CURRENT_APP_TXBUFFER_OFFSET (0x1154U)
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#define GMAC_DMA_CH0_CURRENT_APP_TXBUFFER (0x0U)
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#define GMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT (0U)
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#define GMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK (0xFFFFFFFFU << GMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT) /* 0xFFFFFFFF */
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/* DMA_CH0_CURRENT_APP_RXBUFFER */
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#define GMAC_DMA_CH0_CURRENT_APP_RXBUFFER_OFFSET (0x115CU)
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#define GMAC_DMA_CH0_CURRENT_APP_RXBUFFER (0x0U)
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#define GMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT (0U)
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#define GMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK (0xFFFFFFFFU << GMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT) /* 0xFFFFFFFF */
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/* DMA_CH0_STATUS */
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#define GMAC_DMA_CH0_STATUS_OFFSET (0x1160U)
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#define GMAC_DMA_CH0_STATUS_TI_SHIFT (0U)
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#define GMAC_DMA_CH0_STATUS_TI_MASK (0x1U << GMAC_DMA_CH0_STATUS_TI_SHIFT) /* 0x00000001 */
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#define GMAC_DMA_CH0_STATUS_TPS_SHIFT (1U)
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#define GMAC_DMA_CH0_STATUS_TPS_MASK (0x1U << GMAC_DMA_CH0_STATUS_TPS_SHIFT) /* 0x00000002 */
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#define GMAC_DMA_CH0_STATUS_TBU_SHIFT (2U)
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#define GMAC_DMA_CH0_STATUS_TBU_MASK (0x1U << GMAC_DMA_CH0_STATUS_TBU_SHIFT) /* 0x00000004 */
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#define GMAC_DMA_CH0_STATUS_RI_SHIFT (6U)
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#define GMAC_DMA_CH0_STATUS_RI_MASK (0x1U << GMAC_DMA_CH0_STATUS_RI_SHIFT) /* 0x00000040 */
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#define GMAC_DMA_CH0_STATUS_RBU_SHIFT (7U)
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#define GMAC_DMA_CH0_STATUS_RBU_MASK (0x1U << GMAC_DMA_CH0_STATUS_RBU_SHIFT) /* 0x00000080 */
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#define GMAC_DMA_CH0_STATUS_RPS_SHIFT (8U)
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#define GMAC_DMA_CH0_STATUS_RPS_MASK (0x1U << GMAC_DMA_CH0_STATUS_RPS_SHIFT) /* 0x00000100 */
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#define GMAC_DMA_CH0_STATUS_RWT_SHIFT (9U)
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#define GMAC_DMA_CH0_STATUS_RWT_MASK (0x1U << GMAC_DMA_CH0_STATUS_RWT_SHIFT) /* 0x00000200 */
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#define GMAC_DMA_CH0_STATUS_ETI_SHIFT (10U)
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#define GMAC_DMA_CH0_STATUS_ETI_MASK (0x1U << GMAC_DMA_CH0_STATUS_ETI_SHIFT) /* 0x00000400 */
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#define GMAC_DMA_CH0_STATUS_ERI_SHIFT (11U)
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#define GMAC_DMA_CH0_STATUS_ERI_MASK (0x1U << GMAC_DMA_CH0_STATUS_ERI_SHIFT) /* 0x00000800 */
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#define GMAC_DMA_CH0_STATUS_FBE_SHIFT (12U)
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#define GMAC_DMA_CH0_STATUS_FBE_MASK (0x1U << GMAC_DMA_CH0_STATUS_FBE_SHIFT) /* 0x00001000 */
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#define GMAC_DMA_CH0_STATUS_CDE_SHIFT (13U)
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#define GMAC_DMA_CH0_STATUS_CDE_MASK (0x1U << GMAC_DMA_CH0_STATUS_CDE_SHIFT) /* 0x00002000 */
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#define GMAC_DMA_CH0_STATUS_AIS_SHIFT (14U)
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#define GMAC_DMA_CH0_STATUS_AIS_MASK (0x1U << GMAC_DMA_CH0_STATUS_AIS_SHIFT) /* 0x00004000 */
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#define GMAC_DMA_CH0_STATUS_NIS_SHIFT (15U)
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#define GMAC_DMA_CH0_STATUS_NIS_MASK (0x1U << GMAC_DMA_CH0_STATUS_NIS_SHIFT) /* 0x00008000 */
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#define GMAC_DMA_CH0_STATUS_TEB_SHIFT (16U)
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#define GMAC_DMA_CH0_STATUS_TEB_MASK (0x7U << GMAC_DMA_CH0_STATUS_TEB_SHIFT) /* 0x00070000 */
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#define GMAC_DMA_CH0_STATUS_REB_SHIFT (19U)
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#define GMAC_DMA_CH0_STATUS_REB_MASK (0x7U << GMAC_DMA_CH0_STATUS_REB_SHIFT) /* 0x00380000 */
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/* DMA_CH0_MISS_FRAME_CNT */
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#define GMAC_DMA_CH0_MISS_FRAME_CNT_OFFSET (0x1164U)
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#define GMAC_DMA_CH0_MISS_FRAME_CNT (0x0U)
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#define GMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT (0U)
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#define GMAC_DMA_CH0_MISS_FRAME_CNT_MFC_MASK (0x7FFU << GMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT) /* 0x000007FF */
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#define GMAC_DMA_CH0_MISS_FRAME_CNT_MFC0_SHIFT (15U)
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#define GMAC_DMA_CH0_MISS_FRAME_CNT_MFC0_MASK (0x1U << GMAC_DMA_CH0_MISS_FRAME_CNT_MFC0_SHIFT) /* 0x00008000 */
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/* DMA_CH0_RX_ERI_CNT */
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#define GMAC_DMA_CH0_RX_ERI_CNT_OFFSET (0x1168U)
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#define GMAC_DMA_CH0_RX_ERI_CNT (0x0U)
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#define GMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT (0U)
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#define GMAC_DMA_CH0_RX_ERI_CNT_ECNT_MASK (0x1U << GMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT) /* 0x00000001 */
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/******************************************FSPI******************************************/
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/* CTRL0 */
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#define FSPI_CTRL0_OFFSET (0x0U)
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#define FSPI_CTRL0_SPIM_SHIFT (0U)
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#define FSPI_CTRL0_SPIM_MASK (0x1U << FSPI_CTRL0_SPIM_SHIFT) /* 0x00000001 */
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#define FSPI_CTRL0_SHIFTPHASE_SHIFT (1U)
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#define FSPI_CTRL0_SHIFTPHASE_MASK (0x1U << FSPI_CTRL0_SHIFTPHASE_SHIFT) /* 0x00000002 */
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#define FSPI_CTRL0_IDLE_CYCLE_SHIFT (4U)
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#define FSPI_CTRL0_IDLE_CYCLE_MASK (0xFU << FSPI_CTRL0_IDLE_CYCLE_SHIFT) /* 0x000000F0 */
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#define FSPI_CTRL0_CMDB_SHIFT (8U)
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#define FSPI_CTRL0_CMDB_MASK (0x3U << FSPI_CTRL0_CMDB_SHIFT) /* 0x00000300 */
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#define FSPI_CTRL0_ADRB_SHIFT (10U)
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#define FSPI_CTRL0_ADRB_MASK (0x3U << FSPI_CTRL0_ADRB_SHIFT) /* 0x00000C00 */
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#define FSPI_CTRL0_DATB_SHIFT (12U)
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#define FSPI_CTRL0_DATB_MASK (0x3U << FSPI_CTRL0_DATB_SHIFT) /* 0x00003000 */
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/* IMR */
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#define FSPI_IMR_OFFSET (0x4U)
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#define FSPI_IMR_RXFM_SHIFT (0U)
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#define FSPI_IMR_RXFM_MASK (0x1U << FSPI_IMR_RXFM_SHIFT) /* 0x00000001 */
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#define FSPI_IMR_RXUM_SHIFT (1U)
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#define FSPI_IMR_RXUM_MASK (0x1U << FSPI_IMR_RXUM_SHIFT) /* 0x00000002 */
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#define FSPI_IMR_TXOM_SHIFT (2U)
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#define FSPI_IMR_TXOM_MASK (0x1U << FSPI_IMR_TXOM_SHIFT) /* 0x00000004 */
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#define FSPI_IMR_TXEM_SHIFT (3U)
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#define FSPI_IMR_TXEM_MASK (0x1U << FSPI_IMR_TXEM_SHIFT) /* 0x00000008 */
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#define FSPI_IMR_TRANSM_SHIFT (4U)
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#define FSPI_IMR_TRANSM_MASK (0x1U << FSPI_IMR_TRANSM_SHIFT) /* 0x00000010 */
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#define FSPI_IMR_AHBM_SHIFT (5U)
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#define FSPI_IMR_AHBM_MASK (0x1U << FSPI_IMR_AHBM_SHIFT) /* 0x00000020 */
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#define FSPI_IMR_NSPIM_SHIFT (6U)
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#define FSPI_IMR_NSPIM_MASK (0x1U << FSPI_IMR_NSPIM_SHIFT) /* 0x00000040 */
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#define FSPI_IMR_DMAM_SHIFT (7U)
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#define FSPI_IMR_DMAM_MASK (0x1U << FSPI_IMR_DMAM_SHIFT) /* 0x00000080 */
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/* ICLR */
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#define FSPI_ICLR_OFFSET (0x8U)
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#define FSPI_ICLR_RXFC_SHIFT (0U)
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#define FSPI_ICLR_RXFC_MASK (0x1U << FSPI_ICLR_RXFC_SHIFT) /* 0x00000001 */
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#define FSPI_ICLR_RXUC_SHIFT (1U)
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#define FSPI_ICLR_RXUC_MASK (0x1U << FSPI_ICLR_RXUC_SHIFT) /* 0x00000002 */
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#define FSPI_ICLR_TXOC_SHIFT (2U)
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#define FSPI_ICLR_TXOC_MASK (0x1U << FSPI_ICLR_TXOC_SHIFT) /* 0x00000004 */
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#define FSPI_ICLR_TXEC_SHIFT (3U)
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#define FSPI_ICLR_TXEC_MASK (0x1U << FSPI_ICLR_TXEC_SHIFT) /* 0x00000008 */
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#define FSPI_ICLR_TRANSC_SHIFT (4U)
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#define FSPI_ICLR_TRANSC_MASK (0x1U << FSPI_ICLR_TRANSC_SHIFT) /* 0x00000010 */
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#define FSPI_ICLR_AHBC_SHIFT (5U)
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#define FSPI_ICLR_AHBC_MASK (0x1U << FSPI_ICLR_AHBC_SHIFT) /* 0x00000020 */
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#define FSPI_ICLR_NSPIC_SHIFT (6U)
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#define FSPI_ICLR_NSPIC_MASK (0x1U << FSPI_ICLR_NSPIC_SHIFT) /* 0x00000040 */
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#define FSPI_ICLR_DMAC_SHIFT (7U)
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#define FSPI_ICLR_DMAC_MASK (0x1U << FSPI_ICLR_DMAC_SHIFT) /* 0x00000080 */
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/* FTLR */
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#define FSPI_FTLR_OFFSET (0xCU)
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#define FSPI_FTLR_TXFTLR_SHIFT (0U)
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#define FSPI_FTLR_TXFTLR_MASK (0xFFU << FSPI_FTLR_TXFTLR_SHIFT) /* 0x000000FF */
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#define FSPI_FTLR_RXFTLR_SHIFT (8U)
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#define FSPI_FTLR_RXFTLR_MASK (0xFFU << FSPI_FTLR_RXFTLR_SHIFT) /* 0x0000FF00 */
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/* RCVR */
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#define FSPI_RCVR_OFFSET (0x10U)
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#define FSPI_RCVR_RCVR_SHIFT (0U)
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#define FSPI_RCVR_RCVR_MASK (0x1U << FSPI_RCVR_RCVR_SHIFT) /* 0x00000001 */
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/* AX0 */
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#define FSPI_AX0_OFFSET (0x14U)
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#define FSPI_AX0_AX_SHIFT (0U)
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#define FSPI_AX0_AX_MASK (0xFFU << FSPI_AX0_AX_SHIFT) /* 0x000000FF */
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/* ABIT0 */
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#define FSPI_ABIT0_OFFSET (0x18U)
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#define FSPI_ABIT0_ABIT_SHIFT (0U)
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#define FSPI_ABIT0_ABIT_MASK (0x1FU << FSPI_ABIT0_ABIT_SHIFT) /* 0x0000001F */
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/* ISR */
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#define FSPI_ISR_OFFSET (0x1CU)
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#define FSPI_ISR_RXFS_SHIFT (0U)
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#define FSPI_ISR_RXFS_MASK (0x1U << FSPI_ISR_RXFS_SHIFT) /* 0x00000001 */
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#define FSPI_ISR_RXUS_SHIFT (1U)
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#define FSPI_ISR_RXUS_MASK (0x1U << FSPI_ISR_RXUS_SHIFT) /* 0x00000002 */
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#define FSPI_ISR_TXOS_SHIFT (2U)
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#define FSPI_ISR_TXOS_MASK (0x1U << FSPI_ISR_TXOS_SHIFT) /* 0x00000004 */
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#define FSPI_ISR_TXES_SHIFT (3U)
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#define FSPI_ISR_TXES_MASK (0x1U << FSPI_ISR_TXES_SHIFT) /* 0x00000008 */
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#define FSPI_ISR_TRANSS_SHIFT (4U)
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#define FSPI_ISR_TRANSS_MASK (0x1U << FSPI_ISR_TRANSS_SHIFT) /* 0x00000010 */
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#define FSPI_ISR_AHBS_SHIFT (5U)
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#define FSPI_ISR_AHBS_MASK (0x1U << FSPI_ISR_AHBS_SHIFT) /* 0x00000020 */
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#define FSPI_ISR_NSPIS_SHIFT (6U)
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#define FSPI_ISR_NSPIS_MASK (0x1U << FSPI_ISR_NSPIS_SHIFT) /* 0x00000040 */
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#define FSPI_ISR_DMAS_SHIFT (7U)
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#define FSPI_ISR_DMAS_MASK (0x1U << FSPI_ISR_DMAS_SHIFT) /* 0x00000080 */
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/* FSR */
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#define FSPI_FSR_OFFSET (0x20U)
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#define FSPI_FSR_TXFS_SHIFT (0U)
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#define FSPI_FSR_TXFS_MASK (0x1U << FSPI_FSR_TXFS_SHIFT) /* 0x00000001 */
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#define FSPI_FSR_TXES_SHIFT (1U)
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#define FSPI_FSR_TXES_MASK (0x1U << FSPI_FSR_TXES_SHIFT) /* 0x00000002 */
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#define FSPI_FSR_RXES_SHIFT (2U)
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#define FSPI_FSR_RXES_MASK (0x1U << FSPI_FSR_RXES_SHIFT) /* 0x00000004 */
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#define FSPI_FSR_RXFS_SHIFT (3U)
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#define FSPI_FSR_RXFS_MASK (0x1U << FSPI_FSR_RXFS_SHIFT) /* 0x00000008 */
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#define FSPI_FSR_TXWLVL_SHIFT (8U)
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#define FSPI_FSR_TXWLVL_MASK (0x1FU << FSPI_FSR_TXWLVL_SHIFT) /* 0x00001F00 */
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#define FSPI_FSR_RXWLVL_SHIFT (16U)
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#define FSPI_FSR_RXWLVL_MASK (0x1FU << FSPI_FSR_RXWLVL_SHIFT) /* 0x001F0000 */
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/* SR */
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#define FSPI_SR_OFFSET (0x24U)
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#define FSPI_SR (0x0U)
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#define FSPI_SR_SR_SHIFT (0U)
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#define FSPI_SR_SR_MASK (0x1U << FSPI_SR_SR_SHIFT) /* 0x00000001 */
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/* RISR */
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#define FSPI_RISR_OFFSET (0x28U)
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#define FSPI_RISR (0x0U)
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#define FSPI_RISR_RXFS_SHIFT (0U)
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#define FSPI_RISR_RXFS_MASK (0x1U << FSPI_RISR_RXFS_SHIFT) /* 0x00000001 */
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#define FSPI_RISR_RXUS_SHIFT (1U)
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#define FSPI_RISR_RXUS_MASK (0x1U << FSPI_RISR_RXUS_SHIFT) /* 0x00000002 */
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#define FSPI_RISR_TXOS_SHIFT (2U)
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#define FSPI_RISR_TXOS_MASK (0x1U << FSPI_RISR_TXOS_SHIFT) /* 0x00000004 */
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#define FSPI_RISR_TXES_SHIFT (3U)
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#define FSPI_RISR_TXES_MASK (0x1U << FSPI_RISR_TXES_SHIFT) /* 0x00000008 */
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#define FSPI_RISR_TRANSS_SHIFT (4U)
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#define FSPI_RISR_TRANSS_MASK (0x1U << FSPI_RISR_TRANSS_SHIFT) /* 0x00000010 */
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#define FSPI_RISR_AHBS_SHIFT (5U)
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#define FSPI_RISR_AHBS_MASK (0x1U << FSPI_RISR_AHBS_SHIFT) /* 0x00000020 */
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#define FSPI_RISR_NSPIS_SHIFT (6U)
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#define FSPI_RISR_NSPIS_MASK (0x1U << FSPI_RISR_NSPIS_SHIFT) /* 0x00000040 */
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#define FSPI_RISR_DMAS_SHIFT (7U)
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#define FSPI_RISR_DMAS_MASK (0x1U << FSPI_RISR_DMAS_SHIFT) /* 0x00000080 */
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/* VER */
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#define FSPI_VER_OFFSET (0x2CU)
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#define FSPI_VER (0x5U)
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#define FSPI_VER_VER_SHIFT (0U)
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#define FSPI_VER_VER_MASK (0xFFFFU << FSPI_VER_VER_SHIFT) /* 0x0000FFFF */
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/* QOP */
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#define FSPI_QOP_OFFSET (0x30U)
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#define FSPI_QOP_SO123_SHIFT (0U)
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#define FSPI_QOP_SO123_MASK (0x1U << FSPI_QOP_SO123_SHIFT) /* 0x00000001 */
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#define FSPI_QOP_SO123BP_SHIFT (1U)
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#define FSPI_QOP_SO123BP_MASK (0x1U << FSPI_QOP_SO123BP_SHIFT) /* 0x00000002 */
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/* EXT_CTRL */
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#define FSPI_EXT_CTRL_OFFSET (0x34U)
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#define FSPI_EXT_CTRL_CS_DESEL_CTRL_SHIFT (0U)
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#define FSPI_EXT_CTRL_CS_DESEL_CTRL_MASK (0xFU << FSPI_EXT_CTRL_CS_DESEL_CTRL_SHIFT) /* 0x0000000F */
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#define FSPI_EXT_CTRL_SWITCH_IO_DUMM_CNT_SHIFT (4U)
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#define FSPI_EXT_CTRL_SWITCH_IO_DUMM_CNT_MASK (0xFU << FSPI_EXT_CTRL_SWITCH_IO_DUMM_CNT_SHIFT) /* 0x000000F0 */
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#define FSPI_EXT_CTRL_SWITCH_IO_O2I_CNT_SHIFT (8U)
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#define FSPI_EXT_CTRL_SWITCH_IO_O2I_CNT_MASK (0xFU << FSPI_EXT_CTRL_SWITCH_IO_O2I_CNT_SHIFT) /* 0x00000F00 */
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#define FSPI_EXT_CTRL_TRANS_INT_MODE_SHIFT (13U)
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#define FSPI_EXT_CTRL_TRANS_INT_MODE_MASK (0x1U << FSPI_EXT_CTRL_TRANS_INT_MODE_SHIFT) /* 0x00002000 */
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#define FSPI_EXT_CTRL_SR_GEN_MODE_SHIFT (14U)
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#define FSPI_EXT_CTRL_SR_GEN_MODE_MASK (0x1U << FSPI_EXT_CTRL_SR_GEN_MODE_SHIFT) /* 0x00004000 */
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/* DLL_CTRL0 */
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#define FSPI_DLL_CTRL0_OFFSET (0x3CU)
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#define FSPI_DLL_CTRL0_SMP_DLL_CFG_SHIFT (0U)
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#define FSPI_DLL_CTRL0_SMP_DLL_CFG_MASK (0x1FFU << FSPI_DLL_CTRL0_SMP_DLL_CFG_SHIFT) /* 0x000001FF */
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#define FSPI_DLL_CTRL0_SCLK_SMP_SEL_SHIFT (15U)
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#define FSPI_DLL_CTRL0_SCLK_SMP_SEL_MASK (0x1U << FSPI_DLL_CTRL0_SCLK_SMP_SEL_SHIFT) /* 0x00008000 */
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/* EXT_AX */
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#define FSPI_EXT_AX_OFFSET (0x44U)
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#define FSPI_EXT_AX_AX_CANCEL_PAT_SHIFT (0U)
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#define FSPI_EXT_AX_AX_CANCEL_PAT_MASK (0xFFU << FSPI_EXT_AX_AX_CANCEL_PAT_SHIFT) /* 0x000000FF */
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#define FSPI_EXT_AX_AX_SETUP_PAT_SHIFT (8U)
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#define FSPI_EXT_AX_AX_SETUP_PAT_MASK (0xFFU << FSPI_EXT_AX_AX_SETUP_PAT_SHIFT) /* 0x0000FF00 */
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/* SCLK_INATM_CNT */
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#define FSPI_SCLK_INATM_CNT_OFFSET (0x48U)
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#define FSPI_SCLK_INATM_CNT_SCLK_INATM_CNT_SHIFT (0U)
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#define FSPI_SCLK_INATM_CNT_SCLK_INATM_CNT_MASK (0xFFFFFFFFU << FSPI_SCLK_INATM_CNT_SCLK_INATM_CNT_SHIFT) /* 0xFFFFFFFF */
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/* XMMC_WCMD0 */
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#define FSPI_XMMC_WCMD0_OFFSET (0x50U)
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#define FSPI_XMMC_WCMD0_CMD_SHIFT (0U)
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#define FSPI_XMMC_WCMD0_CMD_MASK (0xFFU << FSPI_XMMC_WCMD0_CMD_SHIFT) /* 0x000000FF */
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#define FSPI_XMMC_WCMD0_DUMM_SHIFT (8U)
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#define FSPI_XMMC_WCMD0_DUMM_MASK (0xFU << FSPI_XMMC_WCMD0_DUMM_SHIFT) /* 0x00000F00 */
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#define FSPI_XMMC_WCMD0_CONT_SHIFT (13U)
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#define FSPI_XMMC_WCMD0_CONT_MASK (0x1U << FSPI_XMMC_WCMD0_CONT_SHIFT) /* 0x00002000 */
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#define FSPI_XMMC_WCMD0_ADDRB_SHIFT (14U)
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#define FSPI_XMMC_WCMD0_ADDRB_MASK (0x3U << FSPI_XMMC_WCMD0_ADDRB_SHIFT) /* 0x0000C000 */
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/* XMMC_RCMD0 */
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#define FSPI_XMMC_RCMD0_OFFSET (0x54U)
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#define FSPI_XMMC_RCMD0_CMD_SHIFT (0U)
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#define FSPI_XMMC_RCMD0_CMD_MASK (0xFFU << FSPI_XMMC_RCMD0_CMD_SHIFT) /* 0x000000FF */
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#define FSPI_XMMC_RCMD0_DUMM_SHIFT (8U)
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#define FSPI_XMMC_RCMD0_DUMM_MASK (0xFU << FSPI_XMMC_RCMD0_DUMM_SHIFT) /* 0x00000F00 */
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#define FSPI_XMMC_RCMD0_CONT_SHIFT (13U)
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#define FSPI_XMMC_RCMD0_CONT_MASK (0x1U << FSPI_XMMC_RCMD0_CONT_SHIFT) /* 0x00002000 */
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#define FSPI_XMMC_RCMD0_ADDRB_SHIFT (14U)
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#define FSPI_XMMC_RCMD0_ADDRB_MASK (0x3U << FSPI_XMMC_RCMD0_ADDRB_SHIFT) /* 0x0000C000 */
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/* XMMC_CTRL */
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#define FSPI_XMMC_CTRL_OFFSET (0x58U)
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#define FSPI_XMMC_CTRL_DEV_HWEN_SHIFT (5U)
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#define FSPI_XMMC_CTRL_DEV_HWEN_MASK (0x1U << FSPI_XMMC_CTRL_DEV_HWEN_SHIFT) /* 0x00000020 */
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#define FSPI_XMMC_CTRL_PFT_EN_SHIFT (6U)
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#define FSPI_XMMC_CTRL_PFT_EN_MASK (0x1U << FSPI_XMMC_CTRL_PFT_EN_SHIFT) /* 0x00000040 */
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/* MODE */
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#define FSPI_MODE_OFFSET (0x5CU)
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#define FSPI_MODE_XMMC_MODE_EN_SHIFT (0U)
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#define FSPI_MODE_XMMC_MODE_EN_MASK (0x1U << FSPI_MODE_XMMC_MODE_EN_SHIFT) /* 0x00000001 */
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/* DEVRGN */
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#define FSPI_DEVRGN_OFFSET (0x60U)
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#define FSPI_DEVRGN_RSIZE_SHIFT (0U)
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#define FSPI_DEVRGN_RSIZE_MASK (0x1FU << FSPI_DEVRGN_RSIZE_SHIFT) /* 0x0000001F */
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#define FSPI_DEVRGN_DEC_CTRL_SHIFT (8U)
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#define FSPI_DEVRGN_DEC_CTRL_MASK (0x3U << FSPI_DEVRGN_DEC_CTRL_SHIFT) /* 0x00000300 */
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/* DEVSIZE0 */
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#define FSPI_DEVSIZE0_OFFSET (0x64U)
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#define FSPI_DEVSIZE0_DSIZE_SHIFT (0U)
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#define FSPI_DEVSIZE0_DSIZE_MASK (0x1FU << FSPI_DEVSIZE0_DSIZE_SHIFT) /* 0x0000001F */
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/* TME0 */
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#define FSPI_TME0_OFFSET (0x68U)
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#define FSPI_TME0_SCLK_INATM_EN_SHIFT (1U)
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#define FSPI_TME0_SCLK_INATM_EN_MASK (0x1U << FSPI_TME0_SCLK_INATM_EN_SHIFT) /* 0x00000002 */
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/* XMMC_RX_WTMRK */
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#define FSPI_XMMC_RX_WTMRK_OFFSET (0x70U)
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#define FSPI_XMMC_RX_WTMRK_RX_FULL_WTMRK_SHIFT (0U)
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#define FSPI_XMMC_RX_WTMRK_RX_FULL_WTMRK_MASK (0xFFU << FSPI_XMMC_RX_WTMRK_RX_FULL_WTMRK_SHIFT) /* 0x000000FF */
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/* DMATR */
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#define FSPI_DMATR_OFFSET (0x80U)
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#define FSPI_DMATR_DMATR_SHIFT (0U)
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#define FSPI_DMATR_DMATR_MASK (0x1U << FSPI_DMATR_DMATR_SHIFT) /* 0x00000001 */
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/* DMAADDR */
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#define FSPI_DMAADDR_OFFSET (0x84U)
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#define FSPI_DMAADDR_DMAADDR_SHIFT (0U)
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#define FSPI_DMAADDR_DMAADDR_MASK (0xFFFFFFFFU << FSPI_DMAADDR_DMAADDR_SHIFT) /* 0xFFFFFFFF */
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/* LEN_CTRL */
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#define FSPI_LEN_CTRL_OFFSET (0x88U)
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#define FSPI_LEN_CTRL_TRB_SEL_SHIFT (0U)
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#define FSPI_LEN_CTRL_TRB_SEL_MASK (0x1U << FSPI_LEN_CTRL_TRB_SEL_SHIFT) /* 0x00000001 */
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/* LEN_EXT */
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#define FSPI_LEN_EXT_OFFSET (0x8CU)
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#define FSPI_LEN_EXT_TRB_EXT_SHIFT (0U)
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#define FSPI_LEN_EXT_TRB_EXT_MASK (0xFFFFFFFFU << FSPI_LEN_EXT_TRB_EXT_SHIFT) /* 0xFFFFFFFF */
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/* XMMCSR */
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#define FSPI_XMMCSR_OFFSET (0x94U)
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#define FSPI_XMMCSR_SLOPOVER0_SHIFT (0U)
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#define FSPI_XMMCSR_SLOPOVER0_MASK (0x1U << FSPI_XMMCSR_SLOPOVER0_SHIFT) /* 0x00000001 */
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#define FSPI_XMMCSR_SLOPOVER1_SHIFT (1U)
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#define FSPI_XMMCSR_SLOPOVER1_MASK (0x1U << FSPI_XMMCSR_SLOPOVER1_SHIFT) /* 0x00000002 */
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/* CMD */
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#define FSPI_CMD_OFFSET (0x100U)
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#define FSPI_CMD_CMD_SHIFT (0U)
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#define FSPI_CMD_CMD_MASK (0xFFU << FSPI_CMD_CMD_SHIFT) /* 0x000000FF */
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#define FSPI_CMD_DUMM_SHIFT (8U)
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#define FSPI_CMD_DUMM_MASK (0xFU << FSPI_CMD_DUMM_SHIFT) /* 0x00000F00 */
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#define FSPI_CMD_WR_SHIFT (12U)
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#define FSPI_CMD_WR_MASK (0x1U << FSPI_CMD_WR_SHIFT) /* 0x00001000 */
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#define FSPI_CMD_CONT_SHIFT (13U)
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#define FSPI_CMD_CONT_MASK (0x1U << FSPI_CMD_CONT_SHIFT) /* 0x00002000 */
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#define FSPI_CMD_ADDRB_SHIFT (14U)
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#define FSPI_CMD_ADDRB_MASK (0x3U << FSPI_CMD_ADDRB_SHIFT) /* 0x0000C000 */
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#define FSPI_CMD_TRB_SHIFT (16U)
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#define FSPI_CMD_TRB_MASK (0x3FFFU << FSPI_CMD_TRB_SHIFT) /* 0x3FFF0000 */
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#define FSPI_CMD_CS_SHIFT (30U)
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#define FSPI_CMD_CS_MASK (0x3U << FSPI_CMD_CS_SHIFT) /* 0xC0000000 */
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/* ADDR */
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#define FSPI_ADDR_OFFSET (0x104U)
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#define FSPI_ADDR_ADDR_SHIFT (0U)
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#define FSPI_ADDR_ADDR_MASK (0xFFFFFFFFU << FSPI_ADDR_ADDR_SHIFT) /* 0xFFFFFFFF */
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/* DATA */
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#define FSPI_DATA_OFFSET (0x108U)
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#define FSPI_DATA_DATA_SHIFT (0U)
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#define FSPI_DATA_DATA_MASK (0xFFFFFFFFU << FSPI_DATA_DATA_SHIFT) /* 0xFFFFFFFF */
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/* CTRL1 */
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#define FSPI_CTRL1_OFFSET (0x200U)
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#define FSPI_CTRL1_SPIM_SHIFT (0U)
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#define FSPI_CTRL1_SPIM_MASK (0x1U << FSPI_CTRL1_SPIM_SHIFT) /* 0x00000001 */
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#define FSPI_CTRL1_SHIFTPHASE_SHIFT (1U)
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#define FSPI_CTRL1_SHIFTPHASE_MASK (0x1U << FSPI_CTRL1_SHIFTPHASE_SHIFT) /* 0x00000002 */
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#define FSPI_CTRL1_IDLE_CYCLE_SHIFT (4U)
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#define FSPI_CTRL1_IDLE_CYCLE_MASK (0xFU << FSPI_CTRL1_IDLE_CYCLE_SHIFT) /* 0x000000F0 */
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#define FSPI_CTRL1_CMDB_SHIFT (8U)
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#define FSPI_CTRL1_CMDB_MASK (0x3U << FSPI_CTRL1_CMDB_SHIFT) /* 0x00000300 */
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#define FSPI_CTRL1_ADRB_SHIFT (10U)
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#define FSPI_CTRL1_ADRB_MASK (0x3U << FSPI_CTRL1_ADRB_SHIFT) /* 0x00000C00 */
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#define FSPI_CTRL1_DATB_SHIFT (12U)
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#define FSPI_CTRL1_DATB_MASK (0x3U << FSPI_CTRL1_DATB_SHIFT) /* 0x00003000 */
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/* AX1 */
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#define FSPI_AX1_OFFSET (0x214U)
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#define FSPI_AX1_AX_SHIFT (0U)
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#define FSPI_AX1_AX_MASK (0xFFU << FSPI_AX1_AX_SHIFT) /* 0x000000FF */
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/* ABIT1 */
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#define FSPI_ABIT1_OFFSET (0x218U)
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#define FSPI_ABIT1_ABIT_SHIFT (0U)
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#define FSPI_ABIT1_ABIT_MASK (0x1FU << FSPI_ABIT1_ABIT_SHIFT) /* 0x0000001F */
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/* DLL_CTRL1 */
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#define FSPI_DLL_CTRL1_OFFSET (0x23CU)
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#define FSPI_DLL_CTRL1_SMP_DLL_CFG_SHIFT (0U)
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#define FSPI_DLL_CTRL1_SMP_DLL_CFG_MASK (0x1FFU << FSPI_DLL_CTRL1_SMP_DLL_CFG_SHIFT) /* 0x000001FF */
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#define FSPI_DLL_CTRL1_SCLK_SMP_SEL_SHIFT (15U)
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#define FSPI_DLL_CTRL1_SCLK_SMP_SEL_MASK (0x1U << FSPI_DLL_CTRL1_SCLK_SMP_SEL_SHIFT) /* 0x00008000 */
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/* XMMC_WCMD1 */
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#define FSPI_XMMC_WCMD1_OFFSET (0x250U)
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#define FSPI_XMMC_WCMD1_CMD_SHIFT (0U)
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#define FSPI_XMMC_WCMD1_CMD_MASK (0xFFU << FSPI_XMMC_WCMD1_CMD_SHIFT) /* 0x000000FF */
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#define FSPI_XMMC_WCMD1_DUMM_SHIFT (8U)
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#define FSPI_XMMC_WCMD1_DUMM_MASK (0xFU << FSPI_XMMC_WCMD1_DUMM_SHIFT) /* 0x00000F00 */
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#define FSPI_XMMC_WCMD1_CONT_SHIFT (13U)
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#define FSPI_XMMC_WCMD1_CONT_MASK (0x1U << FSPI_XMMC_WCMD1_CONT_SHIFT) /* 0x00002000 */
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#define FSPI_XMMC_WCMD1_ADDRB_SHIFT (14U)
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#define FSPI_XMMC_WCMD1_ADDRB_MASK (0x3U << FSPI_XMMC_WCMD1_ADDRB_SHIFT) /* 0x0000C000 */
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/* XMMC_RCMD1 */
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#define FSPI_XMMC_RCMD1_OFFSET (0x254U)
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#define FSPI_XMMC_RCMD1_CMD_SHIFT (0U)
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#define FSPI_XMMC_RCMD1_CMD_MASK (0xFFU << FSPI_XMMC_RCMD1_CMD_SHIFT) /* 0x000000FF */
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#define FSPI_XMMC_RCMD1_DUMM_SHIFT (8U)
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#define FSPI_XMMC_RCMD1_DUMM_MASK (0xFU << FSPI_XMMC_RCMD1_DUMM_SHIFT) /* 0x00000F00 */
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#define FSPI_XMMC_RCMD1_CONT_SHIFT (13U)
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#define FSPI_XMMC_RCMD1_CONT_MASK (0x1U << FSPI_XMMC_RCMD1_CONT_SHIFT) /* 0x00002000 */
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#define FSPI_XMMC_RCMD1_ADDRB_SHIFT (14U)
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#define FSPI_XMMC_RCMD1_ADDRB_MASK (0x3U << FSPI_XMMC_RCMD1_ADDRB_SHIFT) /* 0x0000C000 */
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/* DEVSIZE1 */
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#define FSPI_DEVSIZE1_OFFSET (0x264U)
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#define FSPI_DEVSIZE1_DSIZE_SHIFT (0U)
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#define FSPI_DEVSIZE1_DSIZE_MASK (0x1FU << FSPI_DEVSIZE1_DSIZE_SHIFT) /* 0x0000001F */
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/* TME1 */
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#define FSPI_TME1_OFFSET (0x268U)
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#define FSPI_TME1_SCLK_INATM_EN_SHIFT (1U)
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#define FSPI_TME1_SCLK_INATM_EN_MASK (0x1U << FSPI_TME1_SCLK_INATM_EN_SHIFT) /* 0x00000002 */
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/******************************************DMA*******************************************/
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/* DSR */
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#define DMA_DSR_OFFSET (0x0U)
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#define DMA_DSR (0x0U)
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#define DMA_DSR_FIELD0000_SHIFT (0U)
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#define DMA_DSR_FIELD0000_MASK (0xFU << DMA_DSR_FIELD0000_SHIFT) /* 0x0000000F */
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#define DMA_DSR_FIELD0002_SHIFT (4U)
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#define DMA_DSR_FIELD0002_MASK (0x1FU << DMA_DSR_FIELD0002_SHIFT) /* 0x000001F0 */
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#define DMA_DSR_FIELD0001_SHIFT (9U)
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#define DMA_DSR_FIELD0001_MASK (0x1U << DMA_DSR_FIELD0001_SHIFT) /* 0x00000200 */
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/* DPC */
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#define DMA_DPC_OFFSET (0x4U)
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#define DMA_DPC (0x0U)
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#define DMA_DPC_FIELD0000_SHIFT (0U)
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#define DMA_DPC_FIELD0000_MASK (0xFFFFFFFFU << DMA_DPC_FIELD0000_SHIFT) /* 0xFFFFFFFF */
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/* INTEN */
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#define DMA_INTEN_OFFSET (0x20U)
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#define DMA_INTEN_FIELD0000_SHIFT (0U)
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#define DMA_INTEN_FIELD0000_MASK (0xFFFFFFFFU << DMA_INTEN_FIELD0000_SHIFT) /* 0xFFFFFFFF */
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/* EVENT_RIS */
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#define DMA_EVENT_RIS_OFFSET (0x24U)
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#define DMA_EVENT_RIS (0x0U)
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#define DMA_EVENT_RIS_FIELD0000_SHIFT (0U)
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#define DMA_EVENT_RIS_FIELD0000_MASK (0xFFFFFFFFU << DMA_EVENT_RIS_FIELD0000_SHIFT) /* 0xFFFFFFFF */
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/* INTMIS */
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#define DMA_INTMIS_OFFSET (0x28U)
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#define DMA_INTMIS (0x0U)
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#define DMA_INTMIS_FIELD0000_SHIFT (0U)
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#define DMA_INTMIS_FIELD0000_MASK (0xFFFFFFFFU << DMA_INTMIS_FIELD0000_SHIFT) /* 0xFFFFFFFF */
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/* INTCLR */
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#define DMA_INTCLR_OFFSET (0x2CU)
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#define DMA_INTCLR_FIELD0000_SHIFT (0U)
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#define DMA_INTCLR_FIELD0000_MASK (0xFFFFFFFFU << DMA_INTCLR_FIELD0000_SHIFT) /* 0xFFFFFFFF */
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/* FSRD */
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#define DMA_FSRD_OFFSET (0x30U)
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#define DMA_FSRD (0x0U)
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#define DMA_FSRD_FIELD0000_SHIFT (0U)
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#define DMA_FSRD_FIELD0000_MASK (0xFFFFFFFFU << DMA_FSRD_FIELD0000_SHIFT) /* 0xFFFFFFFF */
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/* FSRC */
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#define DMA_FSRC_OFFSET (0x34U)
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#define DMA_FSRC (0x0U)
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#define DMA_FSRC_FIELD0000_SHIFT (0U)
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#define DMA_FSRC_FIELD0000_MASK (0xFFFFFFFFU << DMA_FSRC_FIELD0000_SHIFT) /* 0xFFFFFFFF */
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/* FTRD */
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#define DMA_FTRD_OFFSET (0x38U)
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#define DMA_FTRD_FIELD0000_SHIFT (0U)
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#define DMA_FTRD_FIELD0000_MASK (0x1U << DMA_FTRD_FIELD0000_SHIFT) /* 0x00000001 */
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#define DMA_FTRD_FIELD0005_SHIFT (1U)
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#define DMA_FTRD_FIELD0005_MASK (0x1U << DMA_FTRD_FIELD0005_SHIFT) /* 0x00000002 */
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#define DMA_FTRD_FIELD0004_SHIFT (4U)
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#define DMA_FTRD_FIELD0004_MASK (0x1U << DMA_FTRD_FIELD0004_SHIFT) /* 0x00000010 */
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#define DMA_FTRD_FIELD0003_SHIFT (5U)
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#define DMA_FTRD_FIELD0003_MASK (0x1U << DMA_FTRD_FIELD0003_SHIFT) /* 0x00000020 */
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#define DMA_FTRD_FIELD0002_SHIFT (16U)
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#define DMA_FTRD_FIELD0002_MASK (0x1U << DMA_FTRD_FIELD0002_SHIFT) /* 0x00010000 */
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#define DMA_FTRD_FIELD0001_SHIFT (30U)
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#define DMA_FTRD_FIELD0001_MASK (0x1U << DMA_FTRD_FIELD0001_SHIFT) /* 0x40000000 */
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/* FTR0 */
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#define DMA_FTR0_OFFSET (0x40U)
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#define DMA_FTR0 (0x0U)
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#define DMA_FTR0_FIELD0000_SHIFT (0U)
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#define DMA_FTR0_FIELD0000_MASK (0x1U << DMA_FTR0_FIELD0000_SHIFT) /* 0x00000001 */
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#define DMA_FTR0_FIELD0011_SHIFT (1U)
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#define DMA_FTR0_FIELD0011_MASK (0x1U << DMA_FTR0_FIELD0011_SHIFT) /* 0x00000002 */
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#define DMA_FTR0_FIELD0010_SHIFT (5U)
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#define DMA_FTR0_FIELD0010_MASK (0x1U << DMA_FTR0_FIELD0010_SHIFT) /* 0x00000020 */
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#define DMA_FTR0_FIELD0009_SHIFT (6U)
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#define DMA_FTR0_FIELD0009_MASK (0x1U << DMA_FTR0_FIELD0009_SHIFT) /* 0x00000040 */
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#define DMA_FTR0_FIELD0008_SHIFT (7U)
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#define DMA_FTR0_FIELD0008_MASK (0x1U << DMA_FTR0_FIELD0008_SHIFT) /* 0x00000080 */
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#define DMA_FTR0_FIELD0007_SHIFT (12U)
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#define DMA_FTR0_FIELD0007_MASK (0x1U << DMA_FTR0_FIELD0007_SHIFT) /* 0x00001000 */
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#define DMA_FTR0_FIELD0006_SHIFT (13U)
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#define DMA_FTR0_FIELD0006_MASK (0x1U << DMA_FTR0_FIELD0006_SHIFT) /* 0x00002000 */
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#define DMA_FTR0_FIELD0005_SHIFT (16U)
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#define DMA_FTR0_FIELD0005_MASK (0x1U << DMA_FTR0_FIELD0005_SHIFT) /* 0x00010000 */
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#define DMA_FTR0_FIELD0004_SHIFT (17U)
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#define DMA_FTR0_FIELD0004_MASK (0x1U << DMA_FTR0_FIELD0004_SHIFT) /* 0x00020000 */
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#define DMA_FTR0_FIELD0003_SHIFT (18U)
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#define DMA_FTR0_FIELD0003_MASK (0x1U << DMA_FTR0_FIELD0003_SHIFT) /* 0x00040000 */
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#define DMA_FTR0_FIELD0002_SHIFT (30U)
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#define DMA_FTR0_FIELD0002_MASK (0x1U << DMA_FTR0_FIELD0002_SHIFT) /* 0x40000000 */
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#define DMA_FTR0_FIELD0001_SHIFT (31U)
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#define DMA_FTR0_FIELD0001_MASK (0x1U << DMA_FTR0_FIELD0001_SHIFT) /* 0x80000000 */
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/* FTR1 */
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#define DMA_FTR1_OFFSET (0x44U)
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#define DMA_FTR1 (0x0U)
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#define DMA_FTR1_FIELD0000_SHIFT (0U)
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#define DMA_FTR1_FIELD0000_MASK (0x1U << DMA_FTR1_FIELD0000_SHIFT) /* 0x00000001 */
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#define DMA_FTR1_FIELD0011_SHIFT (1U)
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#define DMA_FTR1_FIELD0011_MASK (0x1U << DMA_FTR1_FIELD0011_SHIFT) /* 0x00000002 */
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#define DMA_FTR1_FIELD0010_SHIFT (5U)
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#define DMA_FTR1_FIELD0010_MASK (0x1U << DMA_FTR1_FIELD0010_SHIFT) /* 0x00000020 */
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#define DMA_FTR1_FIELD0009_SHIFT (6U)
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#define DMA_FTR1_FIELD0009_MASK (0x1U << DMA_FTR1_FIELD0009_SHIFT) /* 0x00000040 */
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#define DMA_FTR1_FIELD0008_SHIFT (7U)
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#define DMA_FTR1_FIELD0008_MASK (0x1U << DMA_FTR1_FIELD0008_SHIFT) /* 0x00000080 */
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#define DMA_FTR1_FIELD0007_SHIFT (12U)
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#define DMA_FTR1_FIELD0007_MASK (0x1U << DMA_FTR1_FIELD0007_SHIFT) /* 0x00001000 */
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#define DMA_FTR1_FIELD0006_SHIFT (13U)
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#define DMA_FTR1_FIELD0006_MASK (0x1U << DMA_FTR1_FIELD0006_SHIFT) /* 0x00002000 */
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#define DMA_FTR1_FIELD0005_SHIFT (16U)
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#define DMA_FTR1_FIELD0005_MASK (0x1U << DMA_FTR1_FIELD0005_SHIFT) /* 0x00010000 */
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#define DMA_FTR1_FIELD0004_SHIFT (17U)
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#define DMA_FTR1_FIELD0004_MASK (0x1U << DMA_FTR1_FIELD0004_SHIFT) /* 0x00020000 */
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#define DMA_FTR1_FIELD0003_SHIFT (18U)
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#define DMA_FTR1_FIELD0003_MASK (0x1U << DMA_FTR1_FIELD0003_SHIFT) /* 0x00040000 */
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#define DMA_FTR1_FIELD0002_SHIFT (30U)
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#define DMA_FTR1_FIELD0002_MASK (0x1U << DMA_FTR1_FIELD0002_SHIFT) /* 0x40000000 */
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#define DMA_FTR1_FIELD0001_SHIFT (31U)
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#define DMA_FTR1_FIELD0001_MASK (0x1U << DMA_FTR1_FIELD0001_SHIFT) /* 0x80000000 */
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/* FTR2 */
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#define DMA_FTR2_OFFSET (0x48U)
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#define DMA_FTR2 (0x0U)
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#define DMA_FTR2_FIELD0000_SHIFT (0U)
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#define DMA_FTR2_FIELD0000_MASK (0x1U << DMA_FTR2_FIELD0000_SHIFT) /* 0x00000001 */
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#define DMA_FTR2_FIELD0011_SHIFT (1U)
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#define DMA_FTR2_FIELD0011_MASK (0x1U << DMA_FTR2_FIELD0011_SHIFT) /* 0x00000002 */
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#define DMA_FTR2_FIELD0010_SHIFT (5U)
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#define DMA_FTR2_FIELD0010_MASK (0x1U << DMA_FTR2_FIELD0010_SHIFT) /* 0x00000020 */
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#define DMA_FTR2_FIELD0009_SHIFT (6U)
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#define DMA_FTR2_FIELD0009_MASK (0x1U << DMA_FTR2_FIELD0009_SHIFT) /* 0x00000040 */
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#define DMA_FTR2_FIELD0008_SHIFT (7U)
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#define DMA_FTR2_FIELD0008_MASK (0x1U << DMA_FTR2_FIELD0008_SHIFT) /* 0x00000080 */
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#define DMA_FTR2_FIELD0007_SHIFT (12U)
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#define DMA_FTR2_FIELD0007_MASK (0x1U << DMA_FTR2_FIELD0007_SHIFT) /* 0x00001000 */
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#define DMA_FTR2_FIELD0006_SHIFT (13U)
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#define DMA_FTR2_FIELD0006_MASK (0x1U << DMA_FTR2_FIELD0006_SHIFT) /* 0x00002000 */
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#define DMA_FTR2_FIELD0005_SHIFT (16U)
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#define DMA_FTR2_FIELD0005_MASK (0x1U << DMA_FTR2_FIELD0005_SHIFT) /* 0x00010000 */
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#define DMA_FTR2_FIELD0004_SHIFT (17U)
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#define DMA_FTR2_FIELD0004_MASK (0x1U << DMA_FTR2_FIELD0004_SHIFT) /* 0x00020000 */
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#define DMA_FTR2_FIELD0003_SHIFT (18U)
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#define DMA_FTR2_FIELD0003_MASK (0x1U << DMA_FTR2_FIELD0003_SHIFT) /* 0x00040000 */
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#define DMA_FTR2_FIELD0002_SHIFT (30U)
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#define DMA_FTR2_FIELD0002_MASK (0x1U << DMA_FTR2_FIELD0002_SHIFT) /* 0x40000000 */
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#define DMA_FTR2_FIELD0001_SHIFT (31U)
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#define DMA_FTR2_FIELD0001_MASK (0x1U << DMA_FTR2_FIELD0001_SHIFT) /* 0x80000000 */
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/* FTR3 */
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#define DMA_FTR3_OFFSET (0x4CU)
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#define DMA_FTR3 (0x0U)
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#define DMA_FTR3_FIELD0000_SHIFT (0U)
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#define DMA_FTR3_FIELD0000_MASK (0x1U << DMA_FTR3_FIELD0000_SHIFT) /* 0x00000001 */
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#define DMA_FTR3_FIELD0011_SHIFT (1U)
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#define DMA_FTR3_FIELD0011_MASK (0x1U << DMA_FTR3_FIELD0011_SHIFT) /* 0x00000002 */
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#define DMA_FTR3_FIELD0010_SHIFT (5U)
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#define DMA_FTR3_FIELD0010_MASK (0x1U << DMA_FTR3_FIELD0010_SHIFT) /* 0x00000020 */
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#define DMA_FTR3_FIELD0009_SHIFT (6U)
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#define DMA_FTR3_FIELD0009_MASK (0x1U << DMA_FTR3_FIELD0009_SHIFT) /* 0x00000040 */
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#define DMA_FTR3_FIELD0008_SHIFT (7U)
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#define DMA_FTR3_FIELD0008_MASK (0x1U << DMA_FTR3_FIELD0008_SHIFT) /* 0x00000080 */
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#define DMA_FTR3_FIELD0007_SHIFT (12U)
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#define DMA_FTR3_FIELD0007_MASK (0x1U << DMA_FTR3_FIELD0007_SHIFT) /* 0x00001000 */
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#define DMA_FTR3_FIELD0006_SHIFT (13U)
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#define DMA_FTR3_FIELD0006_MASK (0x1U << DMA_FTR3_FIELD0006_SHIFT) /* 0x00002000 */
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#define DMA_FTR3_FIELD0005_SHIFT (16U)
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#define DMA_FTR3_FIELD0005_MASK (0x1U << DMA_FTR3_FIELD0005_SHIFT) /* 0x00010000 */
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#define DMA_FTR3_FIELD0004_SHIFT (17U)
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#define DMA_FTR3_FIELD0004_MASK (0x1U << DMA_FTR3_FIELD0004_SHIFT) /* 0x00020000 */
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#define DMA_FTR3_FIELD0003_SHIFT (18U)
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#define DMA_FTR3_FIELD0003_MASK (0x1U << DMA_FTR3_FIELD0003_SHIFT) /* 0x00040000 */
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#define DMA_FTR3_FIELD0002_SHIFT (30U)
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#define DMA_FTR3_FIELD0002_MASK (0x1U << DMA_FTR3_FIELD0002_SHIFT) /* 0x40000000 */
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#define DMA_FTR3_FIELD0001_SHIFT (31U)
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#define DMA_FTR3_FIELD0001_MASK (0x1U << DMA_FTR3_FIELD0001_SHIFT) /* 0x80000000 */
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/* FTR4 */
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#define DMA_FTR4_OFFSET (0x50U)
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#define DMA_FTR4 (0x0U)
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#define DMA_FTR4_FIELD0000_SHIFT (0U)
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#define DMA_FTR4_FIELD0000_MASK (0x1U << DMA_FTR4_FIELD0000_SHIFT) /* 0x00000001 */
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#define DMA_FTR4_FIELD0011_SHIFT (1U)
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#define DMA_FTR4_FIELD0011_MASK (0x1U << DMA_FTR4_FIELD0011_SHIFT) /* 0x00000002 */
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#define DMA_FTR4_FIELD0010_SHIFT (5U)
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#define DMA_FTR4_FIELD0010_MASK (0x1U << DMA_FTR4_FIELD0010_SHIFT) /* 0x00000020 */
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#define DMA_FTR4_FIELD0009_SHIFT (6U)
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#define DMA_FTR4_FIELD0009_MASK (0x1U << DMA_FTR4_FIELD0009_SHIFT) /* 0x00000040 */
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#define DMA_FTR4_FIELD0008_SHIFT (7U)
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#define DMA_FTR4_FIELD0008_MASK (0x1U << DMA_FTR4_FIELD0008_SHIFT) /* 0x00000080 */
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#define DMA_FTR4_FIELD0007_SHIFT (12U)
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#define DMA_FTR4_FIELD0007_MASK (0x1U << DMA_FTR4_FIELD0007_SHIFT) /* 0x00001000 */
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#define DMA_FTR4_FIELD0006_SHIFT (13U)
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#define DMA_FTR4_FIELD0006_MASK (0x1U << DMA_FTR4_FIELD0006_SHIFT) /* 0x00002000 */
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#define DMA_FTR4_FIELD0005_SHIFT (16U)
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#define DMA_FTR4_FIELD0005_MASK (0x1U << DMA_FTR4_FIELD0005_SHIFT) /* 0x00010000 */
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#define DMA_FTR4_FIELD0004_SHIFT (17U)
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#define DMA_FTR4_FIELD0004_MASK (0x1U << DMA_FTR4_FIELD0004_SHIFT) /* 0x00020000 */
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#define DMA_FTR4_FIELD0003_SHIFT (18U)
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#define DMA_FTR4_FIELD0003_MASK (0x1U << DMA_FTR4_FIELD0003_SHIFT) /* 0x00040000 */
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#define DMA_FTR4_FIELD0002_SHIFT (30U)
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#define DMA_FTR4_FIELD0002_MASK (0x1U << DMA_FTR4_FIELD0002_SHIFT) /* 0x40000000 */
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#define DMA_FTR4_FIELD0001_SHIFT (31U)
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#define DMA_FTR4_FIELD0001_MASK (0x1U << DMA_FTR4_FIELD0001_SHIFT) /* 0x80000000 */
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/* FTR5 */
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#define DMA_FTR5_OFFSET (0x54U)
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#define DMA_FTR5 (0x0U)
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#define DMA_FTR5_FIELD0000_SHIFT (0U)
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#define DMA_FTR5_FIELD0000_MASK (0x1U << DMA_FTR5_FIELD0000_SHIFT) /* 0x00000001 */
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#define DMA_FTR5_FIELD0011_SHIFT (1U)
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#define DMA_FTR5_FIELD0011_MASK (0x1U << DMA_FTR5_FIELD0011_SHIFT) /* 0x00000002 */
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#define DMA_FTR5_FIELD0010_SHIFT (5U)
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#define DMA_FTR5_FIELD0010_MASK (0x1U << DMA_FTR5_FIELD0010_SHIFT) /* 0x00000020 */
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#define DMA_FTR5_FIELD0009_SHIFT (6U)
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#define DMA_FTR5_FIELD0009_MASK (0x1U << DMA_FTR5_FIELD0009_SHIFT) /* 0x00000040 */
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#define DMA_FTR5_FIELD0008_SHIFT (7U)
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#define DMA_FTR5_FIELD0008_MASK (0x1U << DMA_FTR5_FIELD0008_SHIFT) /* 0x00000080 */
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#define DMA_FTR5_FIELD0007_SHIFT (12U)
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#define DMA_FTR5_FIELD0007_MASK (0x1U << DMA_FTR5_FIELD0007_SHIFT) /* 0x00001000 */
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#define DMA_FTR5_FIELD0006_SHIFT (13U)
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#define DMA_FTR5_FIELD0006_MASK (0x1U << DMA_FTR5_FIELD0006_SHIFT) /* 0x00002000 */
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#define DMA_FTR5_FIELD0005_SHIFT (16U)
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#define DMA_FTR5_FIELD0005_MASK (0x1U << DMA_FTR5_FIELD0005_SHIFT) /* 0x00010000 */
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#define DMA_FTR5_FIELD0004_SHIFT (17U)
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#define DMA_FTR5_FIELD0004_MASK (0x1U << DMA_FTR5_FIELD0004_SHIFT) /* 0x00020000 */
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#define DMA_FTR5_FIELD0003_SHIFT (18U)
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#define DMA_FTR5_FIELD0003_MASK (0x1U << DMA_FTR5_FIELD0003_SHIFT) /* 0x00040000 */
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#define DMA_FTR5_FIELD0002_SHIFT (30U)
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#define DMA_FTR5_FIELD0002_MASK (0x1U << DMA_FTR5_FIELD0002_SHIFT) /* 0x40000000 */
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#define DMA_FTR5_FIELD0001_SHIFT (31U)
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#define DMA_FTR5_FIELD0001_MASK (0x1U << DMA_FTR5_FIELD0001_SHIFT) /* 0x80000000 */
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/* CSR0 */
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#define DMA_CSR0_OFFSET (0x100U)
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#define DMA_CSR0 (0x0U)
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#define DMA_CSR0_FIELD0000_SHIFT (0U)
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#define DMA_CSR0_FIELD0000_MASK (0xFU << DMA_CSR0_FIELD0000_SHIFT) /* 0x0000000F */
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#define DMA_CSR0_FIELD0004_SHIFT (4U)
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#define DMA_CSR0_FIELD0004_MASK (0x1FU << DMA_CSR0_FIELD0004_SHIFT) /* 0x000001F0 */
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#define DMA_CSR0_FIELD0003_SHIFT (14U)
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#define DMA_CSR0_FIELD0003_MASK (0x1U << DMA_CSR0_FIELD0003_SHIFT) /* 0x00004000 */
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#define DMA_CSR0_FIELD0002_SHIFT (15U)
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#define DMA_CSR0_FIELD0002_MASK (0x1U << DMA_CSR0_FIELD0002_SHIFT) /* 0x00008000 */
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#define DMA_CSR0_FIELD0001_SHIFT (21U)
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#define DMA_CSR0_FIELD0001_MASK (0x1U << DMA_CSR0_FIELD0001_SHIFT) /* 0x00200000 */
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/* CPC0 */
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#define DMA_CPC0_OFFSET (0x104U)
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#define DMA_CPC0 (0x0U)
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#define DMA_CPC0_FIELD0000_SHIFT (0U)
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#define DMA_CPC0_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC0_FIELD0000_SHIFT) /* 0xFFFFFFFF */
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/* CSR1 */
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#define DMA_CSR1_OFFSET (0x108U)
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#define DMA_CSR1 (0x0U)
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#define DMA_CSR1_FIELD0000_SHIFT (0U)
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#define DMA_CSR1_FIELD0000_MASK (0xFU << DMA_CSR1_FIELD0000_SHIFT) /* 0x0000000F */
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#define DMA_CSR1_FIELD0004_SHIFT (4U)
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#define DMA_CSR1_FIELD0004_MASK (0x1FU << DMA_CSR1_FIELD0004_SHIFT) /* 0x000001F0 */
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#define DMA_CSR1_FIELD0003_SHIFT (14U)
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#define DMA_CSR1_FIELD0003_MASK (0x1U << DMA_CSR1_FIELD0003_SHIFT) /* 0x00004000 */
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#define DMA_CSR1_FIELD0002_SHIFT (15U)
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#define DMA_CSR1_FIELD0002_MASK (0x1U << DMA_CSR1_FIELD0002_SHIFT) /* 0x00008000 */
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#define DMA_CSR1_FIELD0001_SHIFT (21U)
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#define DMA_CSR1_FIELD0001_MASK (0x1U << DMA_CSR1_FIELD0001_SHIFT) /* 0x00200000 */
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/* CPC1 */
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#define DMA_CPC1_OFFSET (0x10CU)
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#define DMA_CPC1 (0x0U)
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#define DMA_CPC1_FIELD0000_SHIFT (0U)
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#define DMA_CPC1_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC1_FIELD0000_SHIFT) /* 0xFFFFFFFF */
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/* CSR2 */
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#define DMA_CSR2_OFFSET (0x110U)
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#define DMA_CSR2 (0x0U)
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#define DMA_CSR2_FIELD0000_SHIFT (0U)
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#define DMA_CSR2_FIELD0000_MASK (0xFU << DMA_CSR2_FIELD0000_SHIFT) /* 0x0000000F */
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#define DMA_CSR2_FIELD0004_SHIFT (4U)
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#define DMA_CSR2_FIELD0004_MASK (0x1FU << DMA_CSR2_FIELD0004_SHIFT) /* 0x000001F0 */
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#define DMA_CSR2_FIELD0003_SHIFT (14U)
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#define DMA_CSR2_FIELD0003_MASK (0x1U << DMA_CSR2_FIELD0003_SHIFT) /* 0x00004000 */
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#define DMA_CSR2_FIELD0002_SHIFT (15U)
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#define DMA_CSR2_FIELD0002_MASK (0x1U << DMA_CSR2_FIELD0002_SHIFT) /* 0x00008000 */
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#define DMA_CSR2_FIELD0001_SHIFT (21U)
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#define DMA_CSR2_FIELD0001_MASK (0x1U << DMA_CSR2_FIELD0001_SHIFT) /* 0x00200000 */
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/* CPC2 */
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#define DMA_CPC2_OFFSET (0x114U)
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#define DMA_CPC2 (0x0U)
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#define DMA_CPC2_FIELD0000_SHIFT (0U)
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#define DMA_CPC2_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC2_FIELD0000_SHIFT) /* 0xFFFFFFFF */
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/* CSR3 */
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#define DMA_CSR3_OFFSET (0x118U)
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#define DMA_CSR3 (0x0U)
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#define DMA_CSR3_FIELD0000_SHIFT (0U)
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#define DMA_CSR3_FIELD0000_MASK (0xFU << DMA_CSR3_FIELD0000_SHIFT) /* 0x0000000F */
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#define DMA_CSR3_FIELD0004_SHIFT (4U)
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#define DMA_CSR3_FIELD0004_MASK (0x1FU << DMA_CSR3_FIELD0004_SHIFT) /* 0x000001F0 */
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#define DMA_CSR3_FIELD0003_SHIFT (14U)
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#define DMA_CSR3_FIELD0003_MASK (0x1U << DMA_CSR3_FIELD0003_SHIFT) /* 0x00004000 */
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#define DMA_CSR3_FIELD0002_SHIFT (15U)
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#define DMA_CSR3_FIELD0002_MASK (0x1U << DMA_CSR3_FIELD0002_SHIFT) /* 0x00008000 */
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#define DMA_CSR3_FIELD0001_SHIFT (21U)
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#define DMA_CSR3_FIELD0001_MASK (0x1U << DMA_CSR3_FIELD0001_SHIFT) /* 0x00200000 */
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/* CPC3 */
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#define DMA_CPC3_OFFSET (0x11CU)
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#define DMA_CPC3 (0x0U)
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#define DMA_CPC3_FIELD0000_SHIFT (0U)
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#define DMA_CPC3_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC3_FIELD0000_SHIFT) /* 0xFFFFFFFF */
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/* CSR4 */
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#define DMA_CSR4_OFFSET (0x120U)
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#define DMA_CSR4 (0x0U)
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#define DMA_CSR4_FIELD0000_SHIFT (0U)
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#define DMA_CSR4_FIELD0000_MASK (0xFU << DMA_CSR4_FIELD0000_SHIFT) /* 0x0000000F */
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#define DMA_CSR4_FIELD0004_SHIFT (4U)
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#define DMA_CSR4_FIELD0004_MASK (0x1FU << DMA_CSR4_FIELD0004_SHIFT) /* 0x000001F0 */
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#define DMA_CSR4_FIELD0003_SHIFT (14U)
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#define DMA_CSR4_FIELD0003_MASK (0x1U << DMA_CSR4_FIELD0003_SHIFT) /* 0x00004000 */
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#define DMA_CSR4_FIELD0002_SHIFT (15U)
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#define DMA_CSR4_FIELD0002_MASK (0x1U << DMA_CSR4_FIELD0002_SHIFT) /* 0x00008000 */
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#define DMA_CSR4_FIELD0001_SHIFT (21U)
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#define DMA_CSR4_FIELD0001_MASK (0x1U << DMA_CSR4_FIELD0001_SHIFT) /* 0x00200000 */
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/* CPC4 */
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#define DMA_CPC4_OFFSET (0x124U)
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#define DMA_CPC4 (0x0U)
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#define DMA_CPC4_FIELD0000_SHIFT (0U)
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#define DMA_CPC4_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC4_FIELD0000_SHIFT) /* 0xFFFFFFFF */
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/* CSR5 */
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#define DMA_CSR5_OFFSET (0x128U)
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#define DMA_CSR5 (0x0U)
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#define DMA_CSR5_FIELD0000_SHIFT (0U)
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#define DMA_CSR5_FIELD0000_MASK (0xFU << DMA_CSR5_FIELD0000_SHIFT) /* 0x0000000F */
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#define DMA_CSR5_FIELD0004_SHIFT (4U)
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#define DMA_CSR5_FIELD0004_MASK (0x1FU << DMA_CSR5_FIELD0004_SHIFT) /* 0x000001F0 */
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#define DMA_CSR5_FIELD0003_SHIFT (14U)
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#define DMA_CSR5_FIELD0003_MASK (0x1U << DMA_CSR5_FIELD0003_SHIFT) /* 0x00004000 */
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#define DMA_CSR5_FIELD0002_SHIFT (15U)
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#define DMA_CSR5_FIELD0002_MASK (0x1U << DMA_CSR5_FIELD0002_SHIFT) /* 0x00008000 */
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#define DMA_CSR5_FIELD0001_SHIFT (21U)
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#define DMA_CSR5_FIELD0001_MASK (0x1U << DMA_CSR5_FIELD0001_SHIFT) /* 0x00200000 */
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/* CPC5 */
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#define DMA_CPC5_OFFSET (0x12CU)
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#define DMA_CPC5 (0x0U)
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#define DMA_CPC5_FIELD0000_SHIFT (0U)
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#define DMA_CPC5_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC5_FIELD0000_SHIFT) /* 0xFFFFFFFF */
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/* CSR6 */
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#define DMA_CSR6_OFFSET (0x130U)
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#define DMA_CSR6 (0x0U)
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#define DMA_CSR6_FIELD0000_SHIFT (0U)
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#define DMA_CSR6_FIELD0000_MASK (0xFU << DMA_CSR6_FIELD0000_SHIFT) /* 0x0000000F */
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#define DMA_CSR6_FIELD0004_SHIFT (4U)
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#define DMA_CSR6_FIELD0004_MASK (0x1FU << DMA_CSR6_FIELD0004_SHIFT) /* 0x000001F0 */
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#define DMA_CSR6_FIELD0003_SHIFT (14U)
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#define DMA_CSR6_FIELD0003_MASK (0x1U << DMA_CSR6_FIELD0003_SHIFT) /* 0x00004000 */
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#define DMA_CSR6_FIELD0002_SHIFT (15U)
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#define DMA_CSR6_FIELD0002_MASK (0x1U << DMA_CSR6_FIELD0002_SHIFT) /* 0x00008000 */
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#define DMA_CSR6_FIELD0001_SHIFT (21U)
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#define DMA_CSR6_FIELD0001_MASK (0x1U << DMA_CSR6_FIELD0001_SHIFT) /* 0x00200000 */
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/* CPC6 */
|
#define DMA_CPC6_OFFSET (0x134U)
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#define DMA_CPC6 (0x0U)
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#define DMA_CPC6_FIELD0000_SHIFT (0U)
|
#define DMA_CPC6_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC6_FIELD0000_SHIFT) /* 0xFFFFFFFF */
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/* CSR7 */
|
#define DMA_CSR7_OFFSET (0x138U)
|
#define DMA_CSR7 (0x0U)
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#define DMA_CSR7_FIELD0000_SHIFT (0U)
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#define DMA_CSR7_FIELD0000_MASK (0xFU << DMA_CSR7_FIELD0000_SHIFT) /* 0x0000000F */
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#define DMA_CSR7_FIELD0004_SHIFT (4U)
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#define DMA_CSR7_FIELD0004_MASK (0x1FU << DMA_CSR7_FIELD0004_SHIFT) /* 0x000001F0 */
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#define DMA_CSR7_FIELD0003_SHIFT (14U)
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#define DMA_CSR7_FIELD0003_MASK (0x1U << DMA_CSR7_FIELD0003_SHIFT) /* 0x00004000 */
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#define DMA_CSR7_FIELD0002_SHIFT (15U)
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#define DMA_CSR7_FIELD0002_MASK (0x1U << DMA_CSR7_FIELD0002_SHIFT) /* 0x00008000 */
|
#define DMA_CSR7_FIELD0001_SHIFT (21U)
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#define DMA_CSR7_FIELD0001_MASK (0x1U << DMA_CSR7_FIELD0001_SHIFT) /* 0x00200000 */
|
/* CPC7 */
|
#define DMA_CPC7_OFFSET (0x13CU)
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#define DMA_CPC7 (0x0U)
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#define DMA_CPC7_FIELD0000_SHIFT (0U)
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#define DMA_CPC7_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC7_FIELD0000_SHIFT) /* 0xFFFFFFFF */
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/* SAR0 */
|
#define DMA_SAR0_OFFSET (0x400U)
|
#define DMA_SAR0 (0x0U)
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#define DMA_SAR0_FIELD0000_SHIFT (0U)
|
#define DMA_SAR0_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR0_FIELD0000_SHIFT) /* 0xFFFFFFFF */
|
/* DAR0 */
|
#define DMA_DAR0_OFFSET (0x404U)
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#define DMA_DAR0 (0x0U)
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#define DMA_DAR0_FIELD0000_SHIFT (0U)
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#define DMA_DAR0_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR0_FIELD0000_SHIFT) /* 0xFFFFFFFF */
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/* CCR0 */
|
#define DMA_CCR0_OFFSET (0x408U)
|
#define DMA_CCR0 (0x0U)
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#define DMA_CCR0_FIELD0000_SHIFT (0U)
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#define DMA_CCR0_FIELD0000_MASK (0x1U << DMA_CCR0_FIELD0000_SHIFT) /* 0x00000001 */
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#define DMA_CCR0_FIELD0009_SHIFT (1U)
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#define DMA_CCR0_FIELD0009_MASK (0x7U << DMA_CCR0_FIELD0009_SHIFT) /* 0x0000000E */
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#define DMA_CCR0_FIELD0008_SHIFT (4U)
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#define DMA_CCR0_FIELD0008_MASK (0xFU << DMA_CCR0_FIELD0008_SHIFT) /* 0x000000F0 */
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#define DMA_CCR0_FIELD0007_SHIFT (8U)
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#define DMA_CCR0_FIELD0007_MASK (0x7U << DMA_CCR0_FIELD0007_SHIFT) /* 0x00000700 */
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#define DMA_CCR0_FIELD0006_SHIFT (11U)
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#define DMA_CCR0_FIELD0006_MASK (0x7U << DMA_CCR0_FIELD0006_SHIFT) /* 0x00003800 */
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#define DMA_CCR0_FIELD0005_SHIFT (14U)
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#define DMA_CCR0_FIELD0005_MASK (0x1U << DMA_CCR0_FIELD0005_SHIFT) /* 0x00004000 */
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#define DMA_CCR0_FIELD0004_SHIFT (15U)
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#define DMA_CCR0_FIELD0004_MASK (0x7U << DMA_CCR0_FIELD0004_SHIFT) /* 0x00038000 */
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#define DMA_CCR0_FIELD0003_SHIFT (18U)
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#define DMA_CCR0_FIELD0003_MASK (0xFU << DMA_CCR0_FIELD0003_SHIFT) /* 0x003C0000 */
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#define DMA_CCR0_FIELD0002_SHIFT (22U)
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#define DMA_CCR0_FIELD0002_MASK (0x7U << DMA_CCR0_FIELD0002_SHIFT) /* 0x01C00000 */
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#define DMA_CCR0_FIELD0001_SHIFT (25U)
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#define DMA_CCR0_FIELD0001_MASK (0x7U << DMA_CCR0_FIELD0001_SHIFT) /* 0x0E000000 */
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/* LC0_0 */
|
#define DMA_LC0_0_OFFSET (0x40CU)
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#define DMA_LC0_0 (0x0U)
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#define DMA_LC0_0_FIELD0000_SHIFT (0U)
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#define DMA_LC0_0_FIELD0000_MASK (0xFFU << DMA_LC0_0_FIELD0000_SHIFT) /* 0x000000FF */
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/* LC1_0 */
|
#define DMA_LC1_0_OFFSET (0x410U)
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#define DMA_LC1_0 (0x0U)
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#define DMA_LC1_0_FIELD0000_SHIFT (0U)
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#define DMA_LC1_0_FIELD0000_MASK (0xFFU << DMA_LC1_0_FIELD0000_SHIFT) /* 0x000000FF */
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/* PADDING0 */
|
#define DMA_PADDING0_OFFSET (0x0U)
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/* PADDING1 */
|
#define DMA_PADDING1_OFFSET (0x0U)
|
/* PADDING2 */
|
#define DMA_PADDING2_OFFSET (0x0U)
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/* SAR1 */
|
#define DMA_SAR1_OFFSET (0x420U)
|
#define DMA_SAR1 (0x0U)
|
#define DMA_SAR1_FIELD0000_SHIFT (0U)
|
#define DMA_SAR1_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR1_FIELD0000_SHIFT) /* 0xFFFFFFFF */
|
/* DAR1 */
|
#define DMA_DAR1_OFFSET (0x424U)
|
#define DMA_DAR1 (0x0U)
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#define DMA_DAR1_FIELD0000_SHIFT (0U)
|
#define DMA_DAR1_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR1_FIELD0000_SHIFT) /* 0xFFFFFFFF */
|
/* CCR1 */
|
#define DMA_CCR1_OFFSET (0x428U)
|
#define DMA_CCR1 (0x0U)
|
#define DMA_CCR1_FIELD0000_SHIFT (0U)
|
#define DMA_CCR1_FIELD0000_MASK (0x1U << DMA_CCR1_FIELD0000_SHIFT) /* 0x00000001 */
|
#define DMA_CCR1_FIELD0009_SHIFT (1U)
|
#define DMA_CCR1_FIELD0009_MASK (0x7U << DMA_CCR1_FIELD0009_SHIFT) /* 0x0000000E */
|
#define DMA_CCR1_FIELD0008_SHIFT (4U)
|
#define DMA_CCR1_FIELD0008_MASK (0xFU << DMA_CCR1_FIELD0008_SHIFT) /* 0x000000F0 */
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#define DMA_CCR1_FIELD0007_SHIFT (8U)
|
#define DMA_CCR1_FIELD0007_MASK (0x7U << DMA_CCR1_FIELD0007_SHIFT) /* 0x00000700 */
|
#define DMA_CCR1_FIELD0006_SHIFT (11U)
|
#define DMA_CCR1_FIELD0006_MASK (0x7U << DMA_CCR1_FIELD0006_SHIFT) /* 0x00003800 */
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#define DMA_CCR1_FIELD0005_SHIFT (14U)
|
#define DMA_CCR1_FIELD0005_MASK (0x1U << DMA_CCR1_FIELD0005_SHIFT) /* 0x00004000 */
|
#define DMA_CCR1_FIELD0004_SHIFT (15U)
|
#define DMA_CCR1_FIELD0004_MASK (0x7U << DMA_CCR1_FIELD0004_SHIFT) /* 0x00038000 */
|
#define DMA_CCR1_FIELD0003_SHIFT (18U)
|
#define DMA_CCR1_FIELD0003_MASK (0xFU << DMA_CCR1_FIELD0003_SHIFT) /* 0x003C0000 */
|
#define DMA_CCR1_FIELD0002_SHIFT (22U)
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#define DMA_CCR1_FIELD0002_MASK (0x7U << DMA_CCR1_FIELD0002_SHIFT) /* 0x01C00000 */
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#define DMA_CCR1_FIELD0001_SHIFT (25U)
|
#define DMA_CCR1_FIELD0001_MASK (0x7U << DMA_CCR1_FIELD0001_SHIFT) /* 0x0E000000 */
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/* LC0_1 */
|
#define DMA_LC0_1_OFFSET (0x42CU)
|
#define DMA_LC0_1 (0x0U)
|
#define DMA_LC0_1_FIELD0000_SHIFT (0U)
|
#define DMA_LC0_1_FIELD0000_MASK (0xFFU << DMA_LC0_1_FIELD0000_SHIFT) /* 0x000000FF */
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/* LC1_1 */
|
#define DMA_LC1_1_OFFSET (0x430U)
|
#define DMA_LC1_1 (0x0U)
|
#define DMA_LC1_1_FIELD0000_SHIFT (0U)
|
#define DMA_LC1_1_FIELD0000_MASK (0xFFU << DMA_LC1_1_FIELD0000_SHIFT) /* 0x000000FF */
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/* PADDING0 */
|
#define DMA_PADDING0_OFFSET (0x0U)
|
/* PADDING1 */
|
#define DMA_PADDING1_OFFSET (0x0U)
|
/* PADDING2 */
|
#define DMA_PADDING2_OFFSET (0x0U)
|
/* SAR2 */
|
#define DMA_SAR2_OFFSET (0x440U)
|
#define DMA_SAR2 (0x0U)
|
#define DMA_SAR2_FIELD0000_SHIFT (0U)
|
#define DMA_SAR2_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR2_FIELD0000_SHIFT) /* 0xFFFFFFFF */
|
/* DAR2 */
|
#define DMA_DAR2_OFFSET (0x444U)
|
#define DMA_DAR2 (0x0U)
|
#define DMA_DAR2_FIELD0000_SHIFT (0U)
|
#define DMA_DAR2_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR2_FIELD0000_SHIFT) /* 0xFFFFFFFF */
|
/* CCR2 */
|
#define DMA_CCR2_OFFSET (0x448U)
|
#define DMA_CCR2 (0x0U)
|
#define DMA_CCR2_FIELD0000_SHIFT (0U)
|
#define DMA_CCR2_FIELD0000_MASK (0x1U << DMA_CCR2_FIELD0000_SHIFT) /* 0x00000001 */
|
#define DMA_CCR2_FIELD0009_SHIFT (1U)
|
#define DMA_CCR2_FIELD0009_MASK (0x7U << DMA_CCR2_FIELD0009_SHIFT) /* 0x0000000E */
|
#define DMA_CCR2_FIELD0008_SHIFT (4U)
|
#define DMA_CCR2_FIELD0008_MASK (0xFU << DMA_CCR2_FIELD0008_SHIFT) /* 0x000000F0 */
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#define DMA_CCR2_FIELD0007_SHIFT (8U)
|
#define DMA_CCR2_FIELD0007_MASK (0x7U << DMA_CCR2_FIELD0007_SHIFT) /* 0x00000700 */
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#define DMA_CCR2_FIELD0006_SHIFT (11U)
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#define DMA_CCR2_FIELD0006_MASK (0x7U << DMA_CCR2_FIELD0006_SHIFT) /* 0x00003800 */
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#define DMA_CCR2_FIELD0005_SHIFT (14U)
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#define DMA_CCR2_FIELD0005_MASK (0x1U << DMA_CCR2_FIELD0005_SHIFT) /* 0x00004000 */
|
#define DMA_CCR2_FIELD0004_SHIFT (15U)
|
#define DMA_CCR2_FIELD0004_MASK (0x7U << DMA_CCR2_FIELD0004_SHIFT) /* 0x00038000 */
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#define DMA_CCR2_FIELD0003_SHIFT (18U)
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#define DMA_CCR2_FIELD0003_MASK (0xFU << DMA_CCR2_FIELD0003_SHIFT) /* 0x003C0000 */
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#define DMA_CCR2_FIELD0002_SHIFT (22U)
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#define DMA_CCR2_FIELD0002_MASK (0x7U << DMA_CCR2_FIELD0002_SHIFT) /* 0x01C00000 */
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#define DMA_CCR2_FIELD0001_SHIFT (25U)
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#define DMA_CCR2_FIELD0001_MASK (0x7U << DMA_CCR2_FIELD0001_SHIFT) /* 0x0E000000 */
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/* LC0_2 */
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#define DMA_LC0_2_OFFSET (0x44CU)
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#define DMA_LC0_2 (0x0U)
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#define DMA_LC0_2_FIELD0000_SHIFT (0U)
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#define DMA_LC0_2_FIELD0000_MASK (0xFFU << DMA_LC0_2_FIELD0000_SHIFT) /* 0x000000FF */
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/* LC1_2 */
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#define DMA_LC1_2_OFFSET (0x450U)
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#define DMA_LC1_2 (0x0U)
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#define DMA_LC1_2_FIELD0000_SHIFT (0U)
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#define DMA_LC1_2_FIELD0000_MASK (0xFFU << DMA_LC1_2_FIELD0000_SHIFT) /* 0x000000FF */
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/* PADDING0 */
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#define DMA_PADDING0_OFFSET (0x0U)
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/* PADDING1 */
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#define DMA_PADDING1_OFFSET (0x0U)
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/* PADDING2 */
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#define DMA_PADDING2_OFFSET (0x0U)
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/* SAR3 */
|
#define DMA_SAR3_OFFSET (0x460U)
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#define DMA_SAR3 (0x0U)
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#define DMA_SAR3_FIELD0000_SHIFT (0U)
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#define DMA_SAR3_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR3_FIELD0000_SHIFT) /* 0xFFFFFFFF */
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/* DAR3 */
|
#define DMA_DAR3_OFFSET (0x464U)
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#define DMA_DAR3 (0x0U)
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#define DMA_DAR3_FIELD0000_SHIFT (0U)
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#define DMA_DAR3_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR3_FIELD0000_SHIFT) /* 0xFFFFFFFF */
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/* CCR3 */
|
#define DMA_CCR3_OFFSET (0x468U)
|
#define DMA_CCR3 (0x0U)
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#define DMA_CCR3_FIELD0000_SHIFT (0U)
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#define DMA_CCR3_FIELD0000_MASK (0x1U << DMA_CCR3_FIELD0000_SHIFT) /* 0x00000001 */
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#define DMA_CCR3_FIELD0009_SHIFT (1U)
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#define DMA_CCR3_FIELD0009_MASK (0x7U << DMA_CCR3_FIELD0009_SHIFT) /* 0x0000000E */
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#define DMA_CCR3_FIELD0008_SHIFT (4U)
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#define DMA_CCR3_FIELD0008_MASK (0xFU << DMA_CCR3_FIELD0008_SHIFT) /* 0x000000F0 */
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#define DMA_CCR3_FIELD0007_SHIFT (8U)
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#define DMA_CCR3_FIELD0007_MASK (0x7U << DMA_CCR3_FIELD0007_SHIFT) /* 0x00000700 */
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#define DMA_CCR3_FIELD0006_SHIFT (11U)
|
#define DMA_CCR3_FIELD0006_MASK (0x7U << DMA_CCR3_FIELD0006_SHIFT) /* 0x00003800 */
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#define DMA_CCR3_FIELD0005_SHIFT (14U)
|
#define DMA_CCR3_FIELD0005_MASK (0x1U << DMA_CCR3_FIELD0005_SHIFT) /* 0x00004000 */
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#define DMA_CCR3_FIELD0004_SHIFT (15U)
|
#define DMA_CCR3_FIELD0004_MASK (0x7U << DMA_CCR3_FIELD0004_SHIFT) /* 0x00038000 */
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#define DMA_CCR3_FIELD0003_SHIFT (18U)
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#define DMA_CCR3_FIELD0003_MASK (0xFU << DMA_CCR3_FIELD0003_SHIFT) /* 0x003C0000 */
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#define DMA_CCR3_FIELD0002_SHIFT (22U)
|
#define DMA_CCR3_FIELD0002_MASK (0x7U << DMA_CCR3_FIELD0002_SHIFT) /* 0x01C00000 */
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#define DMA_CCR3_FIELD0001_SHIFT (25U)
|
#define DMA_CCR3_FIELD0001_MASK (0x7U << DMA_CCR3_FIELD0001_SHIFT) /* 0x0E000000 */
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/* LC0_3 */
|
#define DMA_LC0_3_OFFSET (0x46CU)
|
#define DMA_LC0_3 (0x0U)
|
#define DMA_LC0_3_FIELD0000_SHIFT (0U)
|
#define DMA_LC0_3_FIELD0000_MASK (0xFFU << DMA_LC0_3_FIELD0000_SHIFT) /* 0x000000FF */
|
/* LC1_3 */
|
#define DMA_LC1_3_OFFSET (0x470U)
|
#define DMA_LC1_3 (0x0U)
|
#define DMA_LC1_3_FIELD0000_SHIFT (0U)
|
#define DMA_LC1_3_FIELD0000_MASK (0xFFU << DMA_LC1_3_FIELD0000_SHIFT) /* 0x000000FF */
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/* PADDING0 */
|
#define DMA_PADDING0_OFFSET (0x0U)
|
/* PADDING1 */
|
#define DMA_PADDING1_OFFSET (0x0U)
|
/* PADDING2 */
|
#define DMA_PADDING2_OFFSET (0x0U)
|
/* SAR4 */
|
#define DMA_SAR4_OFFSET (0x480U)
|
#define DMA_SAR4 (0x0U)
|
#define DMA_SAR4_FIELD0000_SHIFT (0U)
|
#define DMA_SAR4_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR4_FIELD0000_SHIFT) /* 0xFFFFFFFF */
|
/* DAR4 */
|
#define DMA_DAR4_OFFSET (0x484U)
|
#define DMA_DAR4 (0x0U)
|
#define DMA_DAR4_FIELD0000_SHIFT (0U)
|
#define DMA_DAR4_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR4_FIELD0000_SHIFT) /* 0xFFFFFFFF */
|
/* CCR4 */
|
#define DMA_CCR4_OFFSET (0x488U)
|
#define DMA_CCR4 (0x0U)
|
#define DMA_CCR4_FIELD0000_SHIFT (0U)
|
#define DMA_CCR4_FIELD0000_MASK (0x1U << DMA_CCR4_FIELD0000_SHIFT) /* 0x00000001 */
|
#define DMA_CCR4_FIELD0009_SHIFT (1U)
|
#define DMA_CCR4_FIELD0009_MASK (0x7U << DMA_CCR4_FIELD0009_SHIFT) /* 0x0000000E */
|
#define DMA_CCR4_FIELD0008_SHIFT (4U)
|
#define DMA_CCR4_FIELD0008_MASK (0xFU << DMA_CCR4_FIELD0008_SHIFT) /* 0x000000F0 */
|
#define DMA_CCR4_FIELD0007_SHIFT (8U)
|
#define DMA_CCR4_FIELD0007_MASK (0x7U << DMA_CCR4_FIELD0007_SHIFT) /* 0x00000700 */
|
#define DMA_CCR4_FIELD0006_SHIFT (11U)
|
#define DMA_CCR4_FIELD0006_MASK (0x7U << DMA_CCR4_FIELD0006_SHIFT) /* 0x00003800 */
|
#define DMA_CCR4_FIELD0005_SHIFT (14U)
|
#define DMA_CCR4_FIELD0005_MASK (0x1U << DMA_CCR4_FIELD0005_SHIFT) /* 0x00004000 */
|
#define DMA_CCR4_FIELD0004_SHIFT (15U)
|
#define DMA_CCR4_FIELD0004_MASK (0x7U << DMA_CCR4_FIELD0004_SHIFT) /* 0x00038000 */
|
#define DMA_CCR4_FIELD0003_SHIFT (18U)
|
#define DMA_CCR4_FIELD0003_MASK (0xFU << DMA_CCR4_FIELD0003_SHIFT) /* 0x003C0000 */
|
#define DMA_CCR4_FIELD0002_SHIFT (22U)
|
#define DMA_CCR4_FIELD0002_MASK (0x7U << DMA_CCR4_FIELD0002_SHIFT) /* 0x01C00000 */
|
#define DMA_CCR4_FIELD0001_SHIFT (25U)
|
#define DMA_CCR4_FIELD0001_MASK (0x7U << DMA_CCR4_FIELD0001_SHIFT) /* 0x0E000000 */
|
/* LC0_4 */
|
#define DMA_LC0_4_OFFSET (0x48CU)
|
#define DMA_LC0_4 (0x0U)
|
#define DMA_LC0_4_FIELD0000_SHIFT (0U)
|
#define DMA_LC0_4_FIELD0000_MASK (0xFFU << DMA_LC0_4_FIELD0000_SHIFT) /* 0x000000FF */
|
/* LC1_4 */
|
#define DMA_LC1_4_OFFSET (0x490U)
|
#define DMA_LC1_4 (0x0U)
|
#define DMA_LC1_4_FIELD0000_SHIFT (0U)
|
#define DMA_LC1_4_FIELD0000_MASK (0xFFU << DMA_LC1_4_FIELD0000_SHIFT) /* 0x000000FF */
|
/* PADDING0 */
|
#define DMA_PADDING0_OFFSET (0x0U)
|
/* PADDING1 */
|
#define DMA_PADDING1_OFFSET (0x0U)
|
/* PADDING2 */
|
#define DMA_PADDING2_OFFSET (0x0U)
|
/* SAR5 */
|
#define DMA_SAR5_OFFSET (0x4A0U)
|
#define DMA_SAR5 (0x0U)
|
#define DMA_SAR5_FIELD0000_SHIFT (0U)
|
#define DMA_SAR5_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR5_FIELD0000_SHIFT) /* 0xFFFFFFFF */
|
/* DAR5 */
|
#define DMA_DAR5_OFFSET (0x4A4U)
|
#define DMA_DAR5 (0x0U)
|
#define DMA_DAR5_FIELD0000_SHIFT (0U)
|
#define DMA_DAR5_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR5_FIELD0000_SHIFT) /* 0xFFFFFFFF */
|
/* CCR5 */
|
#define DMA_CCR5_OFFSET (0x4A8U)
|
#define DMA_CCR5 (0x0U)
|
#define DMA_CCR5_FIELD0000_SHIFT (0U)
|
#define DMA_CCR5_FIELD0000_MASK (0x1U << DMA_CCR5_FIELD0000_SHIFT) /* 0x00000001 */
|
#define DMA_CCR5_FIELD0009_SHIFT (1U)
|
#define DMA_CCR5_FIELD0009_MASK (0x7U << DMA_CCR5_FIELD0009_SHIFT) /* 0x0000000E */
|
#define DMA_CCR5_FIELD0008_SHIFT (4U)
|
#define DMA_CCR5_FIELD0008_MASK (0xFU << DMA_CCR5_FIELD0008_SHIFT) /* 0x000000F0 */
|
#define DMA_CCR5_FIELD0007_SHIFT (8U)
|
#define DMA_CCR5_FIELD0007_MASK (0x7U << DMA_CCR5_FIELD0007_SHIFT) /* 0x00000700 */
|
#define DMA_CCR5_FIELD0006_SHIFT (11U)
|
#define DMA_CCR5_FIELD0006_MASK (0x7U << DMA_CCR5_FIELD0006_SHIFT) /* 0x00003800 */
|
#define DMA_CCR5_FIELD0005_SHIFT (14U)
|
#define DMA_CCR5_FIELD0005_MASK (0x1U << DMA_CCR5_FIELD0005_SHIFT) /* 0x00004000 */
|
#define DMA_CCR5_FIELD0004_SHIFT (15U)
|
#define DMA_CCR5_FIELD0004_MASK (0x7U << DMA_CCR5_FIELD0004_SHIFT) /* 0x00038000 */
|
#define DMA_CCR5_FIELD0003_SHIFT (18U)
|
#define DMA_CCR5_FIELD0003_MASK (0xFU << DMA_CCR5_FIELD0003_SHIFT) /* 0x003C0000 */
|
#define DMA_CCR5_FIELD0002_SHIFT (22U)
|
#define DMA_CCR5_FIELD0002_MASK (0x7U << DMA_CCR5_FIELD0002_SHIFT) /* 0x01C00000 */
|
#define DMA_CCR5_FIELD0001_SHIFT (25U)
|
#define DMA_CCR5_FIELD0001_MASK (0x7U << DMA_CCR5_FIELD0001_SHIFT) /* 0x0E000000 */
|
/* LC0_5 */
|
#define DMA_LC0_5_OFFSET (0x4ACU)
|
#define DMA_LC0_5 (0x0U)
|
#define DMA_LC0_5_FIELD0000_SHIFT (0U)
|
#define DMA_LC0_5_FIELD0000_MASK (0xFFU << DMA_LC0_5_FIELD0000_SHIFT) /* 0x000000FF */
|
/* LC1_5 */
|
#define DMA_LC1_5_OFFSET (0x4B0U)
|
#define DMA_LC1_5 (0x0U)
|
#define DMA_LC1_5_FIELD0000_SHIFT (0U)
|
#define DMA_LC1_5_FIELD0000_MASK (0xFFU << DMA_LC1_5_FIELD0000_SHIFT) /* 0x000000FF */
|
/* PADDING0 */
|
#define DMA_PADDING0_OFFSET (0x0U)
|
/* PADDING1 */
|
#define DMA_PADDING1_OFFSET (0x0U)
|
/* PADDING2 */
|
#define DMA_PADDING2_OFFSET (0x0U)
|
/* SAR6 */
|
#define DMA_SAR6_OFFSET (0x4C0U)
|
#define DMA_SAR6 (0x0U)
|
#define DMA_SAR6_FIELD0000_SHIFT (0U)
|
#define DMA_SAR6_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR6_FIELD0000_SHIFT) /* 0xFFFFFFFF */
|
/* DAR6 */
|
#define DMA_DAR6_OFFSET (0x4C4U)
|
#define DMA_DAR6 (0x0U)
|
#define DMA_DAR6_FIELD0000_SHIFT (0U)
|
#define DMA_DAR6_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR6_FIELD0000_SHIFT) /* 0xFFFFFFFF */
|
/* CCR6 */
|
#define DMA_CCR6_OFFSET (0x4C8U)
|
#define DMA_CCR6 (0x0U)
|
#define DMA_CCR6_FIELD0000_SHIFT (0U)
|
#define DMA_CCR6_FIELD0000_MASK (0x1U << DMA_CCR6_FIELD0000_SHIFT) /* 0x00000001 */
|
#define DMA_CCR6_FIELD0009_SHIFT (1U)
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#define DMA_CCR6_FIELD0009_MASK (0x7U << DMA_CCR6_FIELD0009_SHIFT) /* 0x0000000E */
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#define DMA_CCR6_FIELD0008_SHIFT (4U)
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#define DMA_CCR6_FIELD0008_MASK (0xFU << DMA_CCR6_FIELD0008_SHIFT) /* 0x000000F0 */
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#define DMA_CCR6_FIELD0007_SHIFT (8U)
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#define DMA_CCR6_FIELD0007_MASK (0x7U << DMA_CCR6_FIELD0007_SHIFT) /* 0x00000700 */
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#define DMA_CCR6_FIELD0006_SHIFT (11U)
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#define DMA_CCR6_FIELD0006_MASK (0x7U << DMA_CCR6_FIELD0006_SHIFT) /* 0x00003800 */
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#define DMA_CCR6_FIELD0005_SHIFT (14U)
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#define DMA_CCR6_FIELD0005_MASK (0x1U << DMA_CCR6_FIELD0005_SHIFT) /* 0x00004000 */
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#define DMA_CCR6_FIELD0004_SHIFT (15U)
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#define DMA_CCR6_FIELD0004_MASK (0x7U << DMA_CCR6_FIELD0004_SHIFT) /* 0x00038000 */
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#define DMA_CCR6_FIELD0003_SHIFT (18U)
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#define DMA_CCR6_FIELD0003_MASK (0xFU << DMA_CCR6_FIELD0003_SHIFT) /* 0x003C0000 */
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#define DMA_CCR6_FIELD0002_SHIFT (22U)
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#define DMA_CCR6_FIELD0002_MASK (0x7U << DMA_CCR6_FIELD0002_SHIFT) /* 0x01C00000 */
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#define DMA_CCR6_FIELD0001_SHIFT (25U)
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#define DMA_CCR6_FIELD0001_MASK (0x7U << DMA_CCR6_FIELD0001_SHIFT) /* 0x0E000000 */
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/* LC0_6 */
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#define DMA_LC0_6_OFFSET (0x4CCU)
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#define DMA_LC0_6 (0x0U)
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#define DMA_LC0_6_FIELD0000_SHIFT (0U)
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#define DMA_LC0_6_FIELD0000_MASK (0xFFU << DMA_LC0_6_FIELD0000_SHIFT) /* 0x000000FF */
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/* LC1_6 */
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#define DMA_LC1_6_OFFSET (0x4D0U)
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#define DMA_LC1_6 (0x0U)
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#define DMA_LC1_6_FIELD0000_SHIFT (0U)
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#define DMA_LC1_6_FIELD0000_MASK (0xFFU << DMA_LC1_6_FIELD0000_SHIFT) /* 0x000000FF */
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/* PADDING0 */
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#define DMA_PADDING0_OFFSET (0x0U)
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/* PADDING1 */
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#define DMA_PADDING1_OFFSET (0x0U)
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/* PADDING2 */
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#define DMA_PADDING2_OFFSET (0x0U)
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/* SAR7 */
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#define DMA_SAR7_OFFSET (0x4E0U)
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#define DMA_SAR7 (0x0U)
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#define DMA_SAR7_FIELD0000_SHIFT (0U)
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#define DMA_SAR7_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR7_FIELD0000_SHIFT) /* 0xFFFFFFFF */
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/* DAR7 */
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#define DMA_DAR7_OFFSET (0x4E4U)
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#define DMA_DAR7 (0x0U)
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#define DMA_DAR7_FIELD0000_SHIFT (0U)
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#define DMA_DAR7_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR7_FIELD0000_SHIFT) /* 0xFFFFFFFF */
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/* CCR7 */
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#define DMA_CCR7_OFFSET (0x4E8U)
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#define DMA_CCR7 (0x0U)
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#define DMA_CCR7_FIELD0000_SHIFT (0U)
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#define DMA_CCR7_FIELD0000_MASK (0x1U << DMA_CCR7_FIELD0000_SHIFT) /* 0x00000001 */
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#define DMA_CCR7_FIELD0009_SHIFT (1U)
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#define DMA_CCR7_FIELD0009_MASK (0x7U << DMA_CCR7_FIELD0009_SHIFT) /* 0x0000000E */
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#define DMA_CCR7_FIELD0008_SHIFT (4U)
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#define DMA_CCR7_FIELD0008_MASK (0xFU << DMA_CCR7_FIELD0008_SHIFT) /* 0x000000F0 */
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#define DMA_CCR7_FIELD0007_SHIFT (8U)
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#define DMA_CCR7_FIELD0007_MASK (0x7U << DMA_CCR7_FIELD0007_SHIFT) /* 0x00000700 */
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#define DMA_CCR7_FIELD0006_SHIFT (11U)
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#define DMA_CCR7_FIELD0006_MASK (0x7U << DMA_CCR7_FIELD0006_SHIFT) /* 0x00003800 */
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#define DMA_CCR7_FIELD0005_SHIFT (14U)
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#define DMA_CCR7_FIELD0005_MASK (0x1U << DMA_CCR7_FIELD0005_SHIFT) /* 0x00004000 */
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#define DMA_CCR7_FIELD0004_SHIFT (15U)
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#define DMA_CCR7_FIELD0004_MASK (0x7U << DMA_CCR7_FIELD0004_SHIFT) /* 0x00038000 */
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#define DMA_CCR7_FIELD0003_SHIFT (18U)
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#define DMA_CCR7_FIELD0003_MASK (0xFU << DMA_CCR7_FIELD0003_SHIFT) /* 0x003C0000 */
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#define DMA_CCR7_FIELD0002_SHIFT (22U)
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#define DMA_CCR7_FIELD0002_MASK (0x7U << DMA_CCR7_FIELD0002_SHIFT) /* 0x01C00000 */
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#define DMA_CCR7_FIELD0001_SHIFT (25U)
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#define DMA_CCR7_FIELD0001_MASK (0x7U << DMA_CCR7_FIELD0001_SHIFT) /* 0x0E000000 */
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/* LC0_7 */
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#define DMA_LC0_7_OFFSET (0x4ECU)
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#define DMA_LC0_7 (0x0U)
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#define DMA_LC0_7_FIELD0000_SHIFT (0U)
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#define DMA_LC0_7_FIELD0000_MASK (0xFFU << DMA_LC0_7_FIELD0000_SHIFT) /* 0x000000FF */
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/* LC1_7 */
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#define DMA_LC1_7_OFFSET (0x4F0U)
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#define DMA_LC1_7 (0x0U)
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#define DMA_LC1_7_FIELD0000_SHIFT (0U)
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#define DMA_LC1_7_FIELD0000_MASK (0xFFU << DMA_LC1_7_FIELD0000_SHIFT) /* 0x000000FF */
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/* PADDING0 */
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#define DMA_PADDING0_OFFSET (0x0U)
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/* PADDING1 */
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#define DMA_PADDING1_OFFSET (0x0U)
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/* PADDING2 */
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#define DMA_PADDING2_OFFSET (0x0U)
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/* DBGSTATUS */
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#define DMA_DBGSTATUS_OFFSET (0xD00U)
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#define DMA_DBGSTATUS (0x0U)
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#define DMA_DBGSTATUS_FIELD0000_SHIFT (0U)
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#define DMA_DBGSTATUS_FIELD0000_MASK (0x3U << DMA_DBGSTATUS_FIELD0000_SHIFT) /* 0x00000003 */
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/* DBGCMD */
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#define DMA_DBGCMD_OFFSET (0xD04U)
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#define DMA_DBGCMD_FIELD0000_SHIFT (0U)
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#define DMA_DBGCMD_FIELD0000_MASK (0x3U << DMA_DBGCMD_FIELD0000_SHIFT) /* 0x00000003 */
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/* DBGINST0 */
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#define DMA_DBGINST0_OFFSET (0xD08U)
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#define DMA_DBGINST0_FIELD0000_SHIFT (0U)
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#define DMA_DBGINST0_FIELD0000_MASK (0x1U << DMA_DBGINST0_FIELD0000_SHIFT) /* 0x00000001 */
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#define DMA_DBGINST0_FIELD0003_SHIFT (8U)
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#define DMA_DBGINST0_FIELD0003_MASK (0x7U << DMA_DBGINST0_FIELD0003_SHIFT) /* 0x00000700 */
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#define DMA_DBGINST0_FIELD0002_SHIFT (16U)
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#define DMA_DBGINST0_FIELD0002_MASK (0xFFU << DMA_DBGINST0_FIELD0002_SHIFT) /* 0x00FF0000 */
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#define DMA_DBGINST0_FIELD0001_SHIFT (24U)
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#define DMA_DBGINST0_FIELD0001_MASK (0xFFU << DMA_DBGINST0_FIELD0001_SHIFT) /* 0xFF000000 */
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/* DBGINST1 */
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#define DMA_DBGINST1_OFFSET (0xD0CU)
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#define DMA_DBGINST1_FIELD0000_SHIFT (0U)
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#define DMA_DBGINST1_FIELD0000_MASK (0xFFU << DMA_DBGINST1_FIELD0000_SHIFT) /* 0x000000FF */
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#define DMA_DBGINST1_FIELD0003_SHIFT (8U)
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#define DMA_DBGINST1_FIELD0003_MASK (0xFFU << DMA_DBGINST1_FIELD0003_SHIFT) /* 0x0000FF00 */
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#define DMA_DBGINST1_FIELD0002_SHIFT (16U)
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#define DMA_DBGINST1_FIELD0002_MASK (0xFFU << DMA_DBGINST1_FIELD0002_SHIFT) /* 0x00FF0000 */
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#define DMA_DBGINST1_FIELD0001_SHIFT (24U)
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#define DMA_DBGINST1_FIELD0001_MASK (0xFFU << DMA_DBGINST1_FIELD0001_SHIFT) /* 0xFF000000 */
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/* CR0 */
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#define DMA_CR0_OFFSET (0xE00U)
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#define DMA_CR0 (0x47051U)
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#define DMA_CR0_FIELD0000_SHIFT (0U)
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#define DMA_CR0_FIELD0000_MASK (0x1U << DMA_CR0_FIELD0000_SHIFT) /* 0x00000001 */
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#define DMA_CR0_FIELD0005_SHIFT (1U)
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#define DMA_CR0_FIELD0005_MASK (0x1U << DMA_CR0_FIELD0005_SHIFT) /* 0x00000002 */
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#define DMA_CR0_FIELD0004_SHIFT (2U)
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#define DMA_CR0_FIELD0004_MASK (0x1U << DMA_CR0_FIELD0004_SHIFT) /* 0x00000004 */
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#define DMA_CR0_FIELD0003_SHIFT (4U)
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#define DMA_CR0_FIELD0003_MASK (0x7U << DMA_CR0_FIELD0003_SHIFT) /* 0x00000070 */
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#define DMA_CR0_FIELD0002_SHIFT (12U)
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#define DMA_CR0_FIELD0002_MASK (0x1FU << DMA_CR0_FIELD0002_SHIFT) /* 0x0001F000 */
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#define DMA_CR0_FIELD0001_SHIFT (17U)
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#define DMA_CR0_FIELD0001_MASK (0x1FU << DMA_CR0_FIELD0001_SHIFT) /* 0x003E0000 */
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/* CR1 */
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#define DMA_CR1_OFFSET (0xE04U)
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#define DMA_CR1 (0x57U)
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#define DMA_CR1_FIELD0000_SHIFT (0U)
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#define DMA_CR1_FIELD0000_MASK (0x7U << DMA_CR1_FIELD0000_SHIFT) /* 0x00000007 */
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#define DMA_CR1_FIELD0001_SHIFT (4U)
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#define DMA_CR1_FIELD0001_MASK (0xFU << DMA_CR1_FIELD0001_SHIFT) /* 0x000000F0 */
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/* CR2 */
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#define DMA_CR2_OFFSET (0xE08U)
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#define DMA_CR2 (0x0U)
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#define DMA_CR2_FIELD0000_SHIFT (0U)
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#define DMA_CR2_FIELD0000_MASK (0xFFFFFFFFU << DMA_CR2_FIELD0000_SHIFT) /* 0xFFFFFFFF */
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/* CR3 */
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#define DMA_CR3_OFFSET (0xE0CU)
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#define DMA_CR3 (0x0U)
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#define DMA_CR3_FIELD0000_SHIFT (0U)
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#define DMA_CR3_FIELD0000_MASK (0xFFFFFFFFU << DMA_CR3_FIELD0000_SHIFT) /* 0xFFFFFFFF */
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/* CR4 */
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#define DMA_CR4_OFFSET (0xE10U)
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#define DMA_CR4 (0x6U)
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#define DMA_CR4_FIELD0000_SHIFT (0U)
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#define DMA_CR4_FIELD0000_MASK (0xFFFFFFFFU << DMA_CR4_FIELD0000_SHIFT) /* 0xFFFFFFFF */
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/* CRDN */
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#define DMA_CRDN_OFFSET (0xE14U)
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#define DMA_CRDN (0x2094733U)
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#define DMA_CRDN_FIELD0000_SHIFT (0U)
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#define DMA_CRDN_FIELD0000_MASK (0x7U << DMA_CRDN_FIELD0000_SHIFT) /* 0x00000007 */
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#define DMA_CRDN_FIELD0005_SHIFT (4U)
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#define DMA_CRDN_FIELD0005_MASK (0x7U << DMA_CRDN_FIELD0005_SHIFT) /* 0x00000070 */
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#define DMA_CRDN_FIELD0004_SHIFT (8U)
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#define DMA_CRDN_FIELD0004_MASK (0xFU << DMA_CRDN_FIELD0004_SHIFT) /* 0x00000F00 */
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#define DMA_CRDN_FIELD0003_SHIFT (12U)
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#define DMA_CRDN_FIELD0003_MASK (0x7U << DMA_CRDN_FIELD0003_SHIFT) /* 0x00007000 */
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#define DMA_CRDN_FIELD0002_SHIFT (16U)
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#define DMA_CRDN_FIELD0002_MASK (0xFU << DMA_CRDN_FIELD0002_SHIFT) /* 0x000F0000 */
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#define DMA_CRDN_FIELD0001_SHIFT (20U)
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#define DMA_CRDN_FIELD0001_MASK (0x3FFU << DMA_CRDN_FIELD0001_SHIFT) /* 0x3FF00000 */
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/* WD */
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#define DMA_WD_OFFSET (0xE80U)
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#define DMA_WD_FIELD0000_SHIFT (0U)
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#define DMA_WD_FIELD0000_MASK (0x1U << DMA_WD_FIELD0000_SHIFT) /* 0x00000001 */
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/******************************************CAN*******************************************/
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/* MODE */
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#define CAN_MODE_OFFSET (0x0U)
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#define CAN_MODE_WORK_MODE_SHIFT (0U)
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#define CAN_MODE_WORK_MODE_MASK (0x1U << CAN_MODE_WORK_MODE_SHIFT) /* 0x00000001 */
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#define CAN_MODE_SLEEP_MODE_SHIFT (1U)
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#define CAN_MODE_SLEEP_MODE_MASK (0x1U << CAN_MODE_SLEEP_MODE_SHIFT) /* 0x00000002 */
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#define CAN_MODE_SELF_TEST_SHIFT (2U)
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#define CAN_MODE_SELF_TEST_MASK (0x1U << CAN_MODE_SELF_TEST_SHIFT) /* 0x00000004 */
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#define CAN_MODE_SILENT_MODE_SHIFT (3U)
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#define CAN_MODE_SILENT_MODE_MASK (0x1U << CAN_MODE_SILENT_MODE_SHIFT) /* 0x00000008 */
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#define CAN_MODE_LBACK_MODE_SHIFT (4U)
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#define CAN_MODE_LBACK_MODE_MASK (0x1U << CAN_MODE_LBACK_MODE_SHIFT) /* 0x00000010 */
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#define CAN_MODE_RXSTX_MODE_SHIFT (5U)
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#define CAN_MODE_RXSTX_MODE_MASK (0x1U << CAN_MODE_RXSTX_MODE_SHIFT) /* 0x00000020 */
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#define CAN_MODE_TXORDER_MODE_SHIFT (6U)
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#define CAN_MODE_TXORDER_MODE_MASK (0x1U << CAN_MODE_TXORDER_MODE_SHIFT) /* 0x00000040 */
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#define CAN_MODE_RXSORT_MODE_SHIFT (7U)
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#define CAN_MODE_RXSORT_MODE_MASK (0x1U << CAN_MODE_RXSORT_MODE_SHIFT) /* 0x00000080 */
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#define CAN_MODE_COVER_MODE_SHIFT (8U)
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#define CAN_MODE_COVER_MODE_MASK (0x1U << CAN_MODE_COVER_MODE_SHIFT) /* 0x00000100 */
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#define CAN_MODE_OVLD_MODE_SHIFT (9U)
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#define CAN_MODE_OVLD_MODE_MASK (0x1U << CAN_MODE_OVLD_MODE_SHIFT) /* 0x00000200 */
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#define CAN_MODE_AUTO_RETX_MODE_SHIFT (10U)
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#define CAN_MODE_AUTO_RETX_MODE_MASK (0x1U << CAN_MODE_AUTO_RETX_MODE_SHIFT) /* 0x00000400 */
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#define CAN_MODE_AUTO_BUS_ON_SHIFT (11U)
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#define CAN_MODE_AUTO_BUS_ON_MASK (0x1U << CAN_MODE_AUTO_BUS_ON_SHIFT) /* 0x00000800 */
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#define CAN_MODE_SPACE_RX_MODE_SHIFT (12U)
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#define CAN_MODE_SPACE_RX_MODE_MASK (0x1U << CAN_MODE_SPACE_RX_MODE_SHIFT) /* 0x00001000 */
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#define CAN_MODE_BRSD_SHIFT (13U)
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#define CAN_MODE_BRSD_MASK (0x1U << CAN_MODE_BRSD_SHIFT) /* 0x00002000 */
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#define CAN_MODE_DPEE_SHIFT (14U)
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#define CAN_MODE_DPEE_MASK (0x1U << CAN_MODE_DPEE_SHIFT) /* 0x00004000 */
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#define CAN_MODE_CAN_FD_MODE_ENABLE_SHIFT (15U)
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#define CAN_MODE_CAN_FD_MODE_ENABLE_MASK (0x1U << CAN_MODE_CAN_FD_MODE_ENABLE_SHIFT) /* 0x00008000 */
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/* CMD */
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#define CAN_CMD_OFFSET (0x4U)
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#define CAN_CMD_TX0_REQ_SHIFT (0U)
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#define CAN_CMD_TX0_REQ_MASK (0x1U << CAN_CMD_TX0_REQ_SHIFT) /* 0x00000001 */
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#define CAN_CMD_TX1_REQ_SHIFT (1U)
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#define CAN_CMD_TX1_REQ_MASK (0x1U << CAN_CMD_TX1_REQ_SHIFT) /* 0x00000002 */
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/* STATE */
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#define CAN_STATE_OFFSET (0x8U)
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#define CAN_STATE (0x0U)
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#define CAN_STATE_RX_BUFFER_FULL_SHIFT (0U)
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#define CAN_STATE_RX_BUFFER_FULL_MASK (0x1U << CAN_STATE_RX_BUFFER_FULL_SHIFT) /* 0x00000001 */
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#define CAN_STATE_TX_BUFFER_FULL_SHIFT (1U)
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#define CAN_STATE_TX_BUFFER_FULL_MASK (0x1U << CAN_STATE_TX_BUFFER_FULL_SHIFT) /* 0x00000002 */
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#define CAN_STATE_RX_PERIOD_SHIFT (2U)
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#define CAN_STATE_RX_PERIOD_MASK (0x1U << CAN_STATE_RX_PERIOD_SHIFT) /* 0x00000004 */
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#define CAN_STATE_TX_PERIOD_SHIFT (3U)
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#define CAN_STATE_TX_PERIOD_MASK (0x1U << CAN_STATE_TX_PERIOD_SHIFT) /* 0x00000008 */
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#define CAN_STATE_ERROR_WARNING_STATE_SHIFT (4U)
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#define CAN_STATE_ERROR_WARNING_STATE_MASK (0x1U << CAN_STATE_ERROR_WARNING_STATE_SHIFT) /* 0x00000010 */
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#define CAN_STATE_BUS_OFF_STATE_SHIFT (5U)
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#define CAN_STATE_BUS_OFF_STATE_MASK (0x1U << CAN_STATE_BUS_OFF_STATE_SHIFT) /* 0x00000020 */
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#define CAN_STATE_SLEEP_STATE_SHIFT (6U)
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#define CAN_STATE_SLEEP_STATE_MASK (0x1U << CAN_STATE_SLEEP_STATE_SHIFT) /* 0x00000040 */
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/* INT */
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#define CAN_INT_OFFSET (0xCU)
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#define CAN_INT_RX_FINISH_INT_SHIFT (0U)
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#define CAN_INT_RX_FINISH_INT_MASK (0x1U << CAN_INT_RX_FINISH_INT_SHIFT) /* 0x00000001 */
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#define CAN_INT_TX_FINISH_INT_SHIFT (1U)
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#define CAN_INT_TX_FINISH_INT_MASK (0x1U << CAN_INT_TX_FINISH_INT_SHIFT) /* 0x00000002 */
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#define CAN_INT_ERROR_WARNING_INT_SHIFT (2U)
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#define CAN_INT_ERROR_WARNING_INT_MASK (0x1U << CAN_INT_ERROR_WARNING_INT_SHIFT) /* 0x00000004 */
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#define CAN_INT_OVERLOAD_INT_SHIFT (3U)
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#define CAN_INT_OVERLOAD_INT_MASK (0x1U << CAN_INT_OVERLOAD_INT_SHIFT) /* 0x00000008 */
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#define CAN_INT_PASSIVE_ERROR_INT_SHIFT (4U)
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#define CAN_INT_PASSIVE_ERROR_INT_MASK (0x1U << CAN_INT_PASSIVE_ERROR_INT_SHIFT) /* 0x00000010 */
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#define CAN_INT_TX_ARBIT_FAIL_INT_SHIFT (5U)
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#define CAN_INT_TX_ARBIT_FAIL_INT_MASK (0x1U << CAN_INT_TX_ARBIT_FAIL_INT_SHIFT) /* 0x00000020 */
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#define CAN_INT_ERROR_INT_SHIFT (6U)
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#define CAN_INT_ERROR_INT_MASK (0x1U << CAN_INT_ERROR_INT_SHIFT) /* 0x00000040 */
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#define CAN_INT_RX_FIFO_FULL_INT_SHIFT (7U)
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#define CAN_INT_RX_FIFO_FULL_INT_MASK (0x1U << CAN_INT_RX_FIFO_FULL_INT_SHIFT) /* 0x00000080 */
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#define CAN_INT_RX_FIFO_OVERFLOW_INT_SHIFT (8U)
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#define CAN_INT_RX_FIFO_OVERFLOW_INT_MASK (0x1U << CAN_INT_RX_FIFO_OVERFLOW_INT_SHIFT) /* 0x00000100 */
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#define CAN_INT_BUS_OFF_INT_SHIFT (9U)
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#define CAN_INT_BUS_OFF_INT_MASK (0x1U << CAN_INT_BUS_OFF_INT_SHIFT) /* 0x00000200 */
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#define CAN_INT_BUS_OFF_RECOVERY_INT_SHIFT (10U)
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#define CAN_INT_BUS_OFF_RECOVERY_INT_MASK (0x1U << CAN_INT_BUS_OFF_RECOVERY_INT_SHIFT) /* 0x00000400 */
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#define CAN_INT_TIMESTAMP_COUNTER_OVERFLOW_INT_SHIFT (11U)
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#define CAN_INT_TIMESTAMP_COUNTER_OVERFLOW_INT_MASK (0x1U << CAN_INT_TIMESTAMP_COUNTER_OVERFLOW_INT_SHIFT) /* 0x00000800 */
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#define CAN_INT_TX_EVENT_FIFO_OVERFLOW_INT_SHIFT (12U)
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#define CAN_INT_TX_EVENT_FIFO_OVERFLOW_INT_MASK (0x1U << CAN_INT_TX_EVENT_FIFO_OVERFLOW_INT_SHIFT) /* 0x00001000 */
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#define CAN_INT_TX_EVENT_FIFO_FULL_INT_SHIFT (13U)
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#define CAN_INT_TX_EVENT_FIFO_FULL_INT_MASK (0x1U << CAN_INT_TX_EVENT_FIFO_FULL_INT_SHIFT) /* 0x00002000 */
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#define CAN_INT_WAKEUP_INT_SHIFT (14U)
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#define CAN_INT_WAKEUP_INT_MASK (0x1U << CAN_INT_WAKEUP_INT_SHIFT) /* 0x00004000 */
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/* INT_MASK */
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#define CAN_INT_MASK_OFFSET (0x10U)
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#define CAN_INT_MASK_RX_FINISH_INT_MASK_SHIFT (0U)
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#define CAN_INT_MASK_RX_FINISH_INT_MASK_MASK (0x1U << CAN_INT_MASK_RX_FINISH_INT_MASK_SHIFT) /* 0x00000001 */
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#define CAN_INT_MASK_TX_FINISH_INT_MASK_SHIFT (1U)
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#define CAN_INT_MASK_TX_FINISH_INT_MASK_MASK (0x1U << CAN_INT_MASK_TX_FINISH_INT_MASK_SHIFT) /* 0x00000002 */
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#define CAN_INT_MASK_ERROR_WARNING_INT_MASK_SHIFT (2U)
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#define CAN_INT_MASK_ERROR_WARNING_INT_MASK_MASK (0x1U << CAN_INT_MASK_ERROR_WARNING_INT_MASK_SHIFT) /* 0x00000004 */
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#define CAN_INT_MASK_RX_BUFFER_OVERFLOW_INT_MASK_SHIFT (3U)
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#define CAN_INT_MASK_RX_BUFFER_OVERFLOW_INT_MASK_MASK (0x1U << CAN_INT_MASK_RX_BUFFER_OVERFLOW_INT_MASK_SHIFT) /* 0x00000008 */
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#define CAN_INT_MASK_PASSIVE_ERROR_INT_MASK_SHIFT (4U)
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#define CAN_INT_MASK_PASSIVE_ERROR_INT_MASK_MASK (0x1U << CAN_INT_MASK_PASSIVE_ERROR_INT_MASK_SHIFT) /* 0x00000010 */
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#define CAN_INT_MASK_TX_ARBIT_FAIL_INT_MASK_SHIFT (5U)
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#define CAN_INT_MASK_TX_ARBIT_FAIL_INT_MASK_MASK (0x1U << CAN_INT_MASK_TX_ARBIT_FAIL_INT_MASK_SHIFT) /* 0x00000020 */
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#define CAN_INT_MASK_ERROR_INT_MASK_SHIFT (6U)
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#define CAN_INT_MASK_ERROR_INT_MASK_MASK (0x1U << CAN_INT_MASK_ERROR_INT_MASK_SHIFT) /* 0x00000040 */
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#define CAN_INT_MASK_RX_FIFO_FULL_INT_MASK_SHIFT (7U)
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#define CAN_INT_MASK_RX_FIFO_FULL_INT_MASK_MASK (0x1U << CAN_INT_MASK_RX_FIFO_FULL_INT_MASK_SHIFT) /* 0x00000080 */
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#define CAN_INT_MASK_RX_FIFO_OVERFLOW_INT_MASK_SHIFT (8U)
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#define CAN_INT_MASK_RX_FIFO_OVERFLOW_INT_MASK_MASK (0x1U << CAN_INT_MASK_RX_FIFO_OVERFLOW_INT_MASK_SHIFT) /* 0x00000100 */
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#define CAN_INT_MASK_BUS_OFF_INT_MASK_SHIFT (9U)
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#define CAN_INT_MASK_BUS_OFF_INT_MASK_MASK (0x1U << CAN_INT_MASK_BUS_OFF_INT_MASK_SHIFT) /* 0x00000200 */
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#define CAN_INT_MASK_BUS_OFF_RECOVERY_INT_MASK_SHIFT (10U)
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#define CAN_INT_MASK_BUS_OFF_RECOVERY_INT_MASK_MASK (0x1U << CAN_INT_MASK_BUS_OFF_RECOVERY_INT_MASK_SHIFT) /* 0x00000400 */
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#define CAN_INT_MASK_TIMESTAMP_COUNTER_OVERFLOW_INT_MASK_SHIFT (11U)
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#define CAN_INT_MASK_TIMESTAMP_COUNTER_OVERFLOW_INT_MASK_MASK (0x1U << CAN_INT_MASK_TIMESTAMP_COUNTER_OVERFLOW_INT_MASK_SHIFT) /* 0x00000800 */
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#define CAN_INT_MASK_TX_EVENT_FIFO_OVERFLOW_INT_MASK_SHIFT (12U)
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#define CAN_INT_MASK_TX_EVENT_FIFO_OVERFLOW_INT_MASK_MASK (0x1U << CAN_INT_MASK_TX_EVENT_FIFO_OVERFLOW_INT_MASK_SHIFT) /* 0x00001000 */
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#define CAN_INT_MASK_TX_EVENT_FIFO_FULL_INT_MASK_SHIFT (13U)
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#define CAN_INT_MASK_TX_EVENT_FIFO_FULL_INT_MASK_MASK (0x1U << CAN_INT_MASK_TX_EVENT_FIFO_FULL_INT_MASK_SHIFT) /* 0x00002000 */
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#define CAN_INT_MASK_WAKEUP_INT_MASK_SHIFT (14U)
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#define CAN_INT_MASK_WAKEUP_INT_MASK_MASK (0x1U << CAN_INT_MASK_WAKEUP_INT_MASK_SHIFT) /* 0x00004000 */
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/* DMA_CTRL */
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#define CAN_DMA_CTRL_OFFSET (0x14U)
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#define CAN_DMA_CTRL_DMA_TX_MODE_SHIFT (0U)
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#define CAN_DMA_CTRL_DMA_TX_MODE_MASK (0x1U << CAN_DMA_CTRL_DMA_TX_MODE_SHIFT) /* 0x00000001 */
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#define CAN_DMA_CTRL_DMA_RX_MODE_SHIFT (1U)
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#define CAN_DMA_CTRL_DMA_RX_MODE_MASK (0x1U << CAN_DMA_CTRL_DMA_RX_MODE_SHIFT) /* 0x00000002 */
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/* BITTIMING */
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#define CAN_BITTIMING_OFFSET (0x18U)
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#define CAN_BITTIMING_TSEG1_SHIFT (0U)
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#define CAN_BITTIMING_TSEG1_MASK (0xFU << CAN_BITTIMING_TSEG1_SHIFT) /* 0x0000000F */
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#define CAN_BITTIMING_TSEG2_SHIFT (4U)
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#define CAN_BITTIMING_TSEG2_MASK (0x7U << CAN_BITTIMING_TSEG2_SHIFT) /* 0x00000070 */
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#define CAN_BITTIMING_BRP_SHIFT (8U)
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#define CAN_BITTIMING_BRP_MASK (0x3FU << CAN_BITTIMING_BRP_SHIFT) /* 0x00003F00 */
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#define CAN_BITTIMING_SJW_SHIFT (14U)
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#define CAN_BITTIMING_SJW_MASK (0x3U << CAN_BITTIMING_SJW_SHIFT) /* 0x0000C000 */
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#define CAN_BITTIMING_SAMPLE_MODE_SHIFT (16U)
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#define CAN_BITTIMING_SAMPLE_MODE_MASK (0x1U << CAN_BITTIMING_SAMPLE_MODE_SHIFT) /* 0x00010000 */
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/* ARBITFAIL */
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#define CAN_ARBITFAIL_OFFSET (0x28U)
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#define CAN_ARBITFAIL (0x0U)
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#define CAN_ARBITFAIL_ARBIT_FAIL_CODE_SHIFT (0U)
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#define CAN_ARBITFAIL_ARBIT_FAIL_CODE_MASK (0x7FU << CAN_ARBITFAIL_ARBIT_FAIL_CODE_SHIFT) /* 0x0000007F */
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/* ERROR_CODE */
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#define CAN_ERROR_CODE_OFFSET (0x2CU)
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#define CAN_ERROR_CODE_RX_ERROR_POSITION_SHIFT (0U)
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#define CAN_ERROR_CODE_RX_ERROR_POSITION_MASK (0xFFFFU << CAN_ERROR_CODE_RX_ERROR_POSITION_SHIFT) /* 0x0000FFFF */
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#define CAN_ERROR_CODE_TX_ERROR_POSITION_SHIFT (16U)
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#define CAN_ERROR_CODE_TX_ERROR_POSITION_MASK (0x1FFU << CAN_ERROR_CODE_TX_ERROR_POSITION_SHIFT) /* 0x01FF0000 */
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#define CAN_ERROR_CODE_ERROR_DIRECTION_SHIFT (25U)
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#define CAN_ERROR_CODE_ERROR_DIRECTION_MASK (0x1U << CAN_ERROR_CODE_ERROR_DIRECTION_SHIFT) /* 0x02000000 */
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#define CAN_ERROR_CODE_ERROR_TYPE_SHIFT (26U)
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#define CAN_ERROR_CODE_ERROR_TYPE_MASK (0x7U << CAN_ERROR_CODE_ERROR_TYPE_SHIFT) /* 0x1C000000 */
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#define CAN_ERROR_CODE_ERROR_PHASE_SHIFT (29U)
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#define CAN_ERROR_CODE_ERROR_PHASE_MASK (0x1U << CAN_ERROR_CODE_ERROR_PHASE_SHIFT) /* 0x20000000 */
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/* RXERRORCNT */
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#define CAN_RXERRORCNT_OFFSET (0x34U)
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#define CAN_RXERRORCNT (0x0U)
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#define CAN_RXERRORCNT_RX_ERR_CNT_SHIFT (0U)
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#define CAN_RXERRORCNT_RX_ERR_CNT_MASK (0xFFU << CAN_RXERRORCNT_RX_ERR_CNT_SHIFT) /* 0x000000FF */
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/* TXERRORCNT */
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#define CAN_TXERRORCNT_OFFSET (0x38U)
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#define CAN_TXERRORCNT (0x0U)
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#define CAN_TXERRORCNT_TX_ERR_CNT_SHIFT (0U)
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#define CAN_TXERRORCNT_TX_ERR_CNT_MASK (0x1FFU << CAN_TXERRORCNT_TX_ERR_CNT_SHIFT) /* 0x000001FF */
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/* IDCODE */
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#define CAN_IDCODE_OFFSET (0x3CU)
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#define CAN_IDCODE_ID_CODE_SHIFT (0U)
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#define CAN_IDCODE_ID_CODE_MASK (0x1FFFFFFFU << CAN_IDCODE_ID_CODE_SHIFT) /* 0x1FFFFFFF */
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/* IDMASK */
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#define CAN_IDMASK_OFFSET (0x40U)
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#define CAN_IDMASK_ID_MASK_SHIFT (0U)
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#define CAN_IDMASK_ID_MASK_MASK (0x1FFFFFFFU << CAN_IDMASK_ID_MASK_SHIFT) /* 0x1FFFFFFF */
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/* TXFRAMEINFO */
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#define CAN_TXFRAMEINFO_OFFSET (0x50U)
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#define CAN_TXFRAMEINFO_TXDATA_LENGTH_SHIFT (0U)
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#define CAN_TXFRAMEINFO_TXDATA_LENGTH_MASK (0xFU << CAN_TXFRAMEINFO_TXDATA_LENGTH_SHIFT) /* 0x0000000F */
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#define CAN_TXFRAMEINFO_TX_RTR_SHIFT (6U)
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#define CAN_TXFRAMEINFO_TX_RTR_MASK (0x1U << CAN_TXFRAMEINFO_TX_RTR_SHIFT) /* 0x00000040 */
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#define CAN_TXFRAMEINFO_TXFRAME_FORMAT_SHIFT (7U)
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#define CAN_TXFRAMEINFO_TXFRAME_FORMAT_MASK (0x1U << CAN_TXFRAMEINFO_TXFRAME_FORMAT_SHIFT) /* 0x00000080 */
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/* TXID */
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#define CAN_TXID_OFFSET (0x54U)
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#define CAN_TXID_TX_ID_SHIFT (0U)
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#define CAN_TXID_TX_ID_MASK (0x1FFFFFFFU << CAN_TXID_TX_ID_SHIFT) /* 0x1FFFFFFF */
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/* TXDATA0 */
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#define CAN_TXDATA0_OFFSET (0x58U)
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#define CAN_TXDATA0_TX_DATA0_SHIFT (0U)
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#define CAN_TXDATA0_TX_DATA0_MASK (0xFFFFFFFFU << CAN_TXDATA0_TX_DATA0_SHIFT) /* 0xFFFFFFFF */
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/* TXDATA1 */
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#define CAN_TXDATA1_OFFSET (0x5CU)
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#define CAN_TXDATA1_TX_DATA1_SHIFT (0U)
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#define CAN_TXDATA1_TX_DATA1_MASK (0xFFFFFFFFU << CAN_TXDATA1_TX_DATA1_SHIFT) /* 0xFFFFFFFF */
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/* RXFRAMEINFO */
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#define CAN_RXFRAMEINFO_OFFSET (0x60U)
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#define CAN_RXFRAMEINFO (0x0U)
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#define CAN_RXFRAMEINFO_RXDATA_LENGTH_SHIFT (0U)
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#define CAN_RXFRAMEINFO_RXDATA_LENGTH_MASK (0xFU << CAN_RXFRAMEINFO_RXDATA_LENGTH_SHIFT) /* 0x0000000F */
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#define CAN_RXFRAMEINFO_RX_RTR_SHIFT (6U)
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#define CAN_RXFRAMEINFO_RX_RTR_MASK (0x1U << CAN_RXFRAMEINFO_RX_RTR_SHIFT) /* 0x00000040 */
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#define CAN_RXFRAMEINFO_RXFRAME_FORMAT_SHIFT (7U)
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#define CAN_RXFRAMEINFO_RXFRAME_FORMAT_MASK (0x1U << CAN_RXFRAMEINFO_RXFRAME_FORMAT_SHIFT) /* 0x00000080 */
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/* RXID */
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#define CAN_RXID_OFFSET (0x64U)
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#define CAN_RXID (0x0U)
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#define CAN_RXID_RX_ID_SHIFT (0U)
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#define CAN_RXID_RX_ID_MASK (0x1FFFFFFFU << CAN_RXID_RX_ID_SHIFT) /* 0x1FFFFFFF */
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/* RXDATA0 */
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#define CAN_RXDATA0_OFFSET (0x68U)
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#define CAN_RXDATA0 (0x0U)
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#define CAN_RXDATA0_RX_DATA0_SHIFT (0U)
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#define CAN_RXDATA0_RX_DATA0_MASK (0xFFFFFFFFU << CAN_RXDATA0_RX_DATA0_SHIFT) /* 0xFFFFFFFF */
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/* RXDATA1 */
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#define CAN_RXDATA1_OFFSET (0x6CU)
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#define CAN_RXDATA1 (0x0U)
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#define CAN_RXDATA1_RX_DATA1_SHIFT (0U)
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#define CAN_RXDATA1_RX_DATA1_MASK (0xFFFFFFFFU << CAN_RXDATA1_RX_DATA1_SHIFT) /* 0xFFFFFFFF */
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/* RTL_VERSION */
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#define CAN_RTL_VERSION_OFFSET (0x70U)
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#define CAN_RTL_VERSION (0x21U)
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#define CAN_RTL_VERSION_VERSION_SHIFT (0U)
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#define CAN_RTL_VERSION_VERSION_MASK (0xFFFFFFFFU << CAN_RTL_VERSION_VERSION_SHIFT) /* 0xFFFFFFFF */
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/* FD_NOMINAL_BITTIMING */
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#define CAN_FD_NOMINAL_BITTIMING_OFFSET (0x100U)
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#define CAN_FD_NOMINAL_BITTIMING_TSEG1_SHIFT (0U)
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#define CAN_FD_NOMINAL_BITTIMING_TSEG1_MASK (0xFFU << CAN_FD_NOMINAL_BITTIMING_TSEG1_SHIFT) /* 0x000000FF */
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#define CAN_FD_NOMINAL_BITTIMING_TSEG2_SHIFT (8U)
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#define CAN_FD_NOMINAL_BITTIMING_TSEG2_MASK (0x7FU << CAN_FD_NOMINAL_BITTIMING_TSEG2_SHIFT) /* 0x00007F00 */
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#define CAN_FD_NOMINAL_BITTIMING_BRQ_SHIFT (16U)
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#define CAN_FD_NOMINAL_BITTIMING_BRQ_MASK (0xFFU << CAN_FD_NOMINAL_BITTIMING_BRQ_SHIFT) /* 0x00FF0000 */
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#define CAN_FD_NOMINAL_BITTIMING_SJW_SHIFT (24U)
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#define CAN_FD_NOMINAL_BITTIMING_SJW_MASK (0x7FU << CAN_FD_NOMINAL_BITTIMING_SJW_SHIFT) /* 0x7F000000 */
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#define CAN_FD_NOMINAL_BITTIMING_SAMPLE_MODE_SHIFT (31U)
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#define CAN_FD_NOMINAL_BITTIMING_SAMPLE_MODE_MASK (0x1U << CAN_FD_NOMINAL_BITTIMING_SAMPLE_MODE_SHIFT) /* 0x80000000 */
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/* FD_DATA_BITTIMING */
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#define CAN_FD_DATA_BITTIMING_OFFSET (0x104U)
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#define CAN_FD_DATA_BITTIMING_TSEG1_SHIFT (0U)
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#define CAN_FD_DATA_BITTIMING_TSEG1_MASK (0x1FU << CAN_FD_DATA_BITTIMING_TSEG1_SHIFT) /* 0x0000001F */
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#define CAN_FD_DATA_BITTIMING_TSEG2_SHIFT (5U)
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#define CAN_FD_DATA_BITTIMING_TSEG2_MASK (0xFU << CAN_FD_DATA_BITTIMING_TSEG2_SHIFT) /* 0x000001E0 */
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#define CAN_FD_DATA_BITTIMING_BRQ_SHIFT (9U)
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#define CAN_FD_DATA_BITTIMING_BRQ_MASK (0xFFU << CAN_FD_DATA_BITTIMING_BRQ_SHIFT) /* 0x0001FE00 */
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#define CAN_FD_DATA_BITTIMING_SJW_SHIFT (17U)
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#define CAN_FD_DATA_BITTIMING_SJW_MASK (0xFU << CAN_FD_DATA_BITTIMING_SJW_SHIFT) /* 0x001E0000 */
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#define CAN_FD_DATA_BITTIMING_SAMPLE_MODE_SHIFT (21U)
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#define CAN_FD_DATA_BITTIMING_SAMPLE_MODE_MASK (0x1U << CAN_FD_DATA_BITTIMING_SAMPLE_MODE_SHIFT) /* 0x00200000 */
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/* TRANSMIT_DELAY_COMPENSATION */
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#define CAN_TRANSMIT_DELAY_COMPENSATION_OFFSET (0x108U)
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#define CAN_TRANSMIT_DELAY_COMPENSATION_TDC_ENABLE_SHIFT (0U)
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#define CAN_TRANSMIT_DELAY_COMPENSATION_TDC_ENABLE_MASK (0x1U << CAN_TRANSMIT_DELAY_COMPENSATION_TDC_ENABLE_SHIFT) /* 0x00000001 */
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#define CAN_TRANSMIT_DELAY_COMPENSATION_TDC_OFFSET_SHIFT (1U)
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#define CAN_TRANSMIT_DELAY_COMPENSATION_TDC_OFFSET_MASK (0x3FU << CAN_TRANSMIT_DELAY_COMPENSATION_TDC_OFFSET_SHIFT) /* 0x0000007E */
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/* TIMESTAMP_CTRL */
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#define CAN_TIMESTAMP_CTRL_OFFSET (0x10CU)
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#define CAN_TIMESTAMP_CTRL_TIME_BASE_COUNTER_ENABLE_SHIFT (0U)
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#define CAN_TIMESTAMP_CTRL_TIME_BASE_COUNTER_ENABLE_MASK (0x1U << CAN_TIMESTAMP_CTRL_TIME_BASE_COUNTER_ENABLE_SHIFT) /* 0x00000001 */
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#define CAN_TIMESTAMP_CTRL_TIME_BASE_COUNTER_PRESCALE_SHIFT (1U)
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#define CAN_TIMESTAMP_CTRL_TIME_BASE_COUNTER_PRESCALE_MASK (0x3FU << CAN_TIMESTAMP_CTRL_TIME_BASE_COUNTER_PRESCALE_SHIFT) /* 0x0000007E */
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/* TIMESTAMP */
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#define CAN_TIMESTAMP_OFFSET (0x110U)
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#define CAN_TIMESTAMP_TIME_BASE_COUNTER_SHIFT (0U)
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#define CAN_TIMESTAMP_TIME_BASE_COUNTER_MASK (0xFFFFFFFFU << CAN_TIMESTAMP_TIME_BASE_COUNTER_SHIFT) /* 0xFFFFFFFF */
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/* TXEVENT_FIFO_CTRL */
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#define CAN_TXEVENT_FIFO_CTRL_OFFSET (0x114U)
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#define CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_ENABLE_SHIFT (0U)
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#define CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_ENABLE_MASK (0x1U << CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_ENABLE_SHIFT) /* 0x00000001 */
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#define CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_WATERMARK_SHIFT (1U)
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#define CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_WATERMARK_MASK (0xFU << CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_WATERMARK_SHIFT) /* 0x0000001E */
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#define CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_CNT_SHIFT (5U)
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#define CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_CNT_MASK (0xFU << CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_CNT_SHIFT) /* 0x000001E0 */
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/* RX_FIFO_CTRL */
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#define CAN_RX_FIFO_CTRL_OFFSET (0x118U)
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#define CAN_RX_FIFO_CTRL_RX_FIFO_ENABLE_SHIFT (0U)
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#define CAN_RX_FIFO_CTRL_RX_FIFO_ENABLE_MASK (0x1U << CAN_RX_FIFO_CTRL_RX_FIFO_ENABLE_SHIFT) /* 0x00000001 */
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#define CAN_RX_FIFO_CTRL_RX_FIFO_FULL_WATERMARK_SHIFT (1U)
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#define CAN_RX_FIFO_CTRL_RX_FIFO_FULL_WATERMARK_MASK (0x7U << CAN_RX_FIFO_CTRL_RX_FIFO_FULL_WATERMARK_SHIFT) /* 0x0000000E */
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#define CAN_RX_FIFO_CTRL_RX_FIFO_CNT_SHIFT (4U)
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#define CAN_RX_FIFO_CTRL_RX_FIFO_CNT_MASK (0x7U << CAN_RX_FIFO_CTRL_RX_FIFO_CNT_SHIFT) /* 0x00000070 */
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/* AFR_CTRL */
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#define CAN_AFR_CTRL_OFFSET (0x11CU)
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#define CAN_AFR_CTRL_UAF1_SHIFT (0U)
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#define CAN_AFR_CTRL_UAF1_MASK (0x1U << CAN_AFR_CTRL_UAF1_SHIFT) /* 0x00000001 */
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#define CAN_AFR_CTRL_UAF2_SHIFT (1U)
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#define CAN_AFR_CTRL_UAF2_MASK (0x1U << CAN_AFR_CTRL_UAF2_SHIFT) /* 0x00000002 */
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#define CAN_AFR_CTRL_UAF3_SHIFT (2U)
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#define CAN_AFR_CTRL_UAF3_MASK (0x1U << CAN_AFR_CTRL_UAF3_SHIFT) /* 0x00000004 */
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#define CAN_AFR_CTRL_UAF4_SHIFT (3U)
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#define CAN_AFR_CTRL_UAF4_MASK (0x1U << CAN_AFR_CTRL_UAF4_SHIFT) /* 0x00000008 */
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#define CAN_AFR_CTRL_UAF5_SHIFT (4U)
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#define CAN_AFR_CTRL_UAF5_MASK (0x1U << CAN_AFR_CTRL_UAF5_SHIFT) /* 0x00000010 */
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/* IDCODE0 */
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#define CAN_IDCODE0_OFFSET (0x120U)
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#define CAN_IDCODE0_ID_CODE_SHIFT (0U)
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#define CAN_IDCODE0_ID_CODE_MASK (0x1FFFFFFFU << CAN_IDCODE0_ID_CODE_SHIFT) /* 0x1FFFFFFF */
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/* IDMASK0 */
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#define CAN_IDMASK0_OFFSET (0x124U)
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#define CAN_IDMASK0_ID_MASK_SHIFT (0U)
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#define CAN_IDMASK0_ID_MASK_MASK (0x1FFFFFFFU << CAN_IDMASK0_ID_MASK_SHIFT) /* 0x1FFFFFFF */
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/* IDCODE1 */
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#define CAN_IDCODE1_OFFSET (0x128U)
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#define CAN_IDCODE1_ID_CODE_SHIFT (0U)
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#define CAN_IDCODE1_ID_CODE_MASK (0x1FFFFFFFU << CAN_IDCODE1_ID_CODE_SHIFT) /* 0x1FFFFFFF */
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/* IDMASK1 */
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#define CAN_IDMASK1_OFFSET (0x12CU)
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#define CAN_IDMASK1_ID_MASK_SHIFT (0U)
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#define CAN_IDMASK1_ID_MASK_MASK (0x1FFFFFFFU << CAN_IDMASK1_ID_MASK_SHIFT) /* 0x1FFFFFFF */
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/* IDCODE2 */
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#define CAN_IDCODE2_OFFSET (0x130U)
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#define CAN_IDCODE2_ID_CODE_SHIFT (0U)
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#define CAN_IDCODE2_ID_CODE_MASK (0x1FFFFFFFU << CAN_IDCODE2_ID_CODE_SHIFT) /* 0x1FFFFFFF */
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/* IDMASK2 */
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#define CAN_IDMASK2_OFFSET (0x134U)
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#define CAN_IDMASK2_ID_MASK_SHIFT (0U)
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#define CAN_IDMASK2_ID_MASK_MASK (0x1FFFFFFFU << CAN_IDMASK2_ID_MASK_SHIFT) /* 0x1FFFFFFF */
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/* IDCODE3 */
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#define CAN_IDCODE3_OFFSET (0x138U)
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#define CAN_IDCODE3_ID_CODE_SHIFT (0U)
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#define CAN_IDCODE3_ID_CODE_MASK (0x1FFFFFFFU << CAN_IDCODE3_ID_CODE_SHIFT) /* 0x1FFFFFFF */
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/* IDMASK3 */
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#define CAN_IDMASK3_OFFSET (0x13CU)
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#define CAN_IDMASK3_ID_MASK_SHIFT (0U)
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#define CAN_IDMASK3_ID_MASK_MASK (0x1FFFFFFFU << CAN_IDMASK3_ID_MASK_SHIFT) /* 0x1FFFFFFF */
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/* IDCODE4 */
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#define CAN_IDCODE4_OFFSET (0x140U)
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#define CAN_IDCODE4_ID_CODE_SHIFT (0U)
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#define CAN_IDCODE4_ID_CODE_MASK (0x1FFFFFFFU << CAN_IDCODE4_ID_CODE_SHIFT) /* 0x1FFFFFFF */
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/* IDMASK4 */
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#define CAN_IDMASK4_OFFSET (0x144U)
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#define CAN_IDMASK4_ID_MASK_SHIFT (0U)
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#define CAN_IDMASK4_ID_MASK_MASK (0x1FFFFFFFU << CAN_IDMASK4_ID_MASK_SHIFT) /* 0x1FFFFFFF */
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/* FD_TXFRAMEINFO */
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#define CAN_FD_TXFRAMEINFO_OFFSET (0x200U)
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#define CAN_FD_TXFRAMEINFO_TXDATA_LENGTH_SHIFT (0U)
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#define CAN_FD_TXFRAMEINFO_TXDATA_LENGTH_MASK (0xFU << CAN_FD_TXFRAMEINFO_TXDATA_LENGTH_SHIFT) /* 0x0000000F */
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#define CAN_FD_TXFRAMEINFO_TX_BRS_SHIFT (4U)
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#define CAN_FD_TXFRAMEINFO_TX_BRS_MASK (0x1U << CAN_FD_TXFRAMEINFO_TX_BRS_SHIFT) /* 0x00000010 */
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#define CAN_FD_TXFRAMEINFO_TX_FDF_SHIFT (5U)
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#define CAN_FD_TXFRAMEINFO_TX_FDF_MASK (0x1U << CAN_FD_TXFRAMEINFO_TX_FDF_SHIFT) /* 0x00000020 */
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#define CAN_FD_TXFRAMEINFO_TX_RTR_SHIFT (6U)
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#define CAN_FD_TXFRAMEINFO_TX_RTR_MASK (0x1U << CAN_FD_TXFRAMEINFO_TX_RTR_SHIFT) /* 0x00000040 */
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#define CAN_FD_TXFRAMEINFO_TXFRAME_FORMAT_SHIFT (7U)
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#define CAN_FD_TXFRAMEINFO_TXFRAME_FORMAT_MASK (0x1U << CAN_FD_TXFRAMEINFO_TXFRAME_FORMAT_SHIFT) /* 0x00000080 */
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/* FD_TXID */
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#define CAN_FD_TXID_OFFSET (0x204U)
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#define CAN_FD_TXID_TX_ID_SHIFT (0U)
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#define CAN_FD_TXID_TX_ID_MASK (0x1FFFFFFFU << CAN_FD_TXID_TX_ID_SHIFT) /* 0x1FFFFFFF */
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/* FD_TXDATA0 */
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#define CAN_FD_TXDATA0_OFFSET (0x208U)
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#define CAN_FD_TXDATA0_TX_DATA0_SHIFT (0U)
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#define CAN_FD_TXDATA0_TX_DATA0_MASK (0xFFFFFFFFU << CAN_FD_TXDATA0_TX_DATA0_SHIFT) /* 0xFFFFFFFF */
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/* FD_TXDATA1 */
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#define CAN_FD_TXDATA1_OFFSET (0x20CU)
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#define CAN_FD_TXDATA1_TX_DATA1_SHIFT (0U)
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#define CAN_FD_TXDATA1_TX_DATA1_MASK (0xFFFFFFFFU << CAN_FD_TXDATA1_TX_DATA1_SHIFT) /* 0xFFFFFFFF */
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/* FD_TXDATA2 */
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#define CAN_FD_TXDATA2_OFFSET (0x210U)
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#define CAN_FD_TXDATA2_TX_DATA2_SHIFT (0U)
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#define CAN_FD_TXDATA2_TX_DATA2_MASK (0xFFFFFFFFU << CAN_FD_TXDATA2_TX_DATA2_SHIFT) /* 0xFFFFFFFF */
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/* FD_TXDATA3 */
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#define CAN_FD_TXDATA3_OFFSET (0x214U)
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#define CAN_FD_TXDATA3_TX_DATA3_SHIFT (0U)
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#define CAN_FD_TXDATA3_TX_DATA3_MASK (0xFFFFFFFFU << CAN_FD_TXDATA3_TX_DATA3_SHIFT) /* 0xFFFFFFFF */
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/* FD_TXDATA4 */
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#define CAN_FD_TXDATA4_OFFSET (0x218U)
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#define CAN_FD_TXDATA4_TX_DATA4_SHIFT (0U)
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#define CAN_FD_TXDATA4_TX_DATA4_MASK (0xFFFFFFFFU << CAN_FD_TXDATA4_TX_DATA4_SHIFT) /* 0xFFFFFFFF */
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/* FD_TXDATA5 */
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#define CAN_FD_TXDATA5_OFFSET (0x21CU)
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#define CAN_FD_TXDATA5_TX_DATA5_SHIFT (0U)
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#define CAN_FD_TXDATA5_TX_DATA5_MASK (0xFFFFFFFFU << CAN_FD_TXDATA5_TX_DATA5_SHIFT) /* 0xFFFFFFFF */
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/* FD_TXDATA6 */
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#define CAN_FD_TXDATA6_OFFSET (0x220U)
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#define CAN_FD_TXDATA6_TX_DATA6_SHIFT (0U)
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#define CAN_FD_TXDATA6_TX_DATA6_MASK (0xFFFFFFFFU << CAN_FD_TXDATA6_TX_DATA6_SHIFT) /* 0xFFFFFFFF */
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/* FD_TXDATA7 */
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#define CAN_FD_TXDATA7_OFFSET (0x224U)
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#define CAN_FD_TXDATA7_TX_DATA7_SHIFT (0U)
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#define CAN_FD_TXDATA7_TX_DATA7_MASK (0xFFFFFFFFU << CAN_FD_TXDATA7_TX_DATA7_SHIFT) /* 0xFFFFFFFF */
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/* FD_TXDATA8 */
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#define CAN_FD_TXDATA8_OFFSET (0x228U)
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#define CAN_FD_TXDATA8_TX_DATA8_SHIFT (0U)
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#define CAN_FD_TXDATA8_TX_DATA8_MASK (0xFFFFFFFFU << CAN_FD_TXDATA8_TX_DATA8_SHIFT) /* 0xFFFFFFFF */
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/* FD_TXDATA9 */
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#define CAN_FD_TXDATA9_OFFSET (0x22CU)
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#define CAN_FD_TXDATA9_TX_DATA9_SHIFT (0U)
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#define CAN_FD_TXDATA9_TX_DATA9_MASK (0xFFFFFFFFU << CAN_FD_TXDATA9_TX_DATA9_SHIFT) /* 0xFFFFFFFF */
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/* FD_TXDATA10 */
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#define CAN_FD_TXDATA10_OFFSET (0x230U)
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#define CAN_FD_TXDATA10_TX_DATA10_SHIFT (0U)
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#define CAN_FD_TXDATA10_TX_DATA10_MASK (0xFFFFFFFFU << CAN_FD_TXDATA10_TX_DATA10_SHIFT) /* 0xFFFFFFFF */
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/* FD_TXDATA11 */
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#define CAN_FD_TXDATA11_OFFSET (0x234U)
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#define CAN_FD_TXDATA11_TX_DATA11_SHIFT (0U)
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#define CAN_FD_TXDATA11_TX_DATA11_MASK (0xFFFFFFFFU << CAN_FD_TXDATA11_TX_DATA11_SHIFT) /* 0xFFFFFFFF */
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/* FD_TXDATA12 */
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#define CAN_FD_TXDATA12_OFFSET (0x238U)
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#define CAN_FD_TXDATA12_TX_DATA12_SHIFT (0U)
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#define CAN_FD_TXDATA12_TX_DATA12_MASK (0xFFFFFFFFU << CAN_FD_TXDATA12_TX_DATA12_SHIFT) /* 0xFFFFFFFF */
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/* FD_TXDATA13 */
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#define CAN_FD_TXDATA13_OFFSET (0x23CU)
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#define CAN_FD_TXDATA13_TX_DATA13_SHIFT (0U)
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#define CAN_FD_TXDATA13_TX_DATA13_MASK (0xFFFFFFFFU << CAN_FD_TXDATA13_TX_DATA13_SHIFT) /* 0xFFFFFFFF */
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/* FD_TXDATA14 */
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#define CAN_FD_TXDATA14_OFFSET (0x240U)
|
#define CAN_FD_TXDATA14_TX_DATA14_SHIFT (0U)
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#define CAN_FD_TXDATA14_TX_DATA14_MASK (0xFFFFFFFFU << CAN_FD_TXDATA14_TX_DATA14_SHIFT) /* 0xFFFFFFFF */
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/* FD_TXDATA15 */
|
#define CAN_FD_TXDATA15_OFFSET (0x244U)
|
#define CAN_FD_TXDATA15_TX_DATA15_SHIFT (0U)
|
#define CAN_FD_TXDATA15_TX_DATA15_MASK (0xFFFFFFFFU << CAN_FD_TXDATA15_TX_DATA15_SHIFT) /* 0xFFFFFFFF */
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/* FD_RXFRAMEINFO */
|
#define CAN_FD_RXFRAMEINFO_OFFSET (0x300U)
|
#define CAN_FD_RXFRAMEINFO_RXDATA_LENGTH_SHIFT (0U)
|
#define CAN_FD_RXFRAMEINFO_RXDATA_LENGTH_MASK (0xFU << CAN_FD_RXFRAMEINFO_RXDATA_LENGTH_SHIFT) /* 0x0000000F */
|
#define CAN_FD_RXFRAMEINFO_RX_BRS_SHIFT (4U)
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#define CAN_FD_RXFRAMEINFO_RX_BRS_MASK (0x1U << CAN_FD_RXFRAMEINFO_RX_BRS_SHIFT) /* 0x00000010 */
|
#define CAN_FD_RXFRAMEINFO_RX_FDF_SHIFT (5U)
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#define CAN_FD_RXFRAMEINFO_RX_FDF_MASK (0x1U << CAN_FD_RXFRAMEINFO_RX_FDF_SHIFT) /* 0x00000020 */
|
#define CAN_FD_RXFRAMEINFO_RX_RTR_SHIFT (6U)
|
#define CAN_FD_RXFRAMEINFO_RX_RTR_MASK (0x1U << CAN_FD_RXFRAMEINFO_RX_RTR_SHIFT) /* 0x00000040 */
|
#define CAN_FD_RXFRAMEINFO_RXFRAME_FORMAT_SHIFT (7U)
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#define CAN_FD_RXFRAMEINFO_RXFRAME_FORMAT_MASK (0x1U << CAN_FD_RXFRAMEINFO_RXFRAME_FORMAT_SHIFT) /* 0x00000080 */
|
/* FD_RXID */
|
#define CAN_FD_RXID_OFFSET (0x304U)
|
#define CAN_FD_RXID (0x0U)
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#define CAN_FD_RXID_RX_ID_SHIFT (0U)
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#define CAN_FD_RXID_RX_ID_MASK (0x1FFFFFFFU << CAN_FD_RXID_RX_ID_SHIFT) /* 0x1FFFFFFF */
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/* FD_RXTIMESTAMP */
|
#define CAN_FD_RXTIMESTAMP_OFFSET (0x308U)
|
#define CAN_FD_RXTIMESTAMP (0x0U)
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#define CAN_FD_RXTIMESTAMP_TIMESTAMP_SHIFT (0U)
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#define CAN_FD_RXTIMESTAMP_TIMESTAMP_MASK (0xFFFFFFFFU << CAN_FD_RXTIMESTAMP_TIMESTAMP_SHIFT) /* 0xFFFFFFFF */
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/* FD_RXDATA0 */
|
#define CAN_FD_RXDATA0_OFFSET (0x30CU)
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#define CAN_FD_RXDATA0 (0x0U)
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#define CAN_FD_RXDATA0_RX_DATA0_SHIFT (0U)
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#define CAN_FD_RXDATA0_RX_DATA0_MASK (0xFFFFFFFFU << CAN_FD_RXDATA0_RX_DATA0_SHIFT) /* 0xFFFFFFFF */
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/* FD_RXDATA1 */
|
#define CAN_FD_RXDATA1_OFFSET (0x310U)
|
#define CAN_FD_RXDATA1 (0x0U)
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#define CAN_FD_RXDATA1_RX_DATA1_SHIFT (0U)
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#define CAN_FD_RXDATA1_RX_DATA1_MASK (0xFFFFFFFFU << CAN_FD_RXDATA1_RX_DATA1_SHIFT) /* 0xFFFFFFFF */
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/* FD_RXDATA2 */
|
#define CAN_FD_RXDATA2_OFFSET (0x314U)
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#define CAN_FD_RXDATA2 (0x0U)
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#define CAN_FD_RXDATA2_RX_DATA2_SHIFT (0U)
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#define CAN_FD_RXDATA2_RX_DATA2_MASK (0xFFFFFFFFU << CAN_FD_RXDATA2_RX_DATA2_SHIFT) /* 0xFFFFFFFF */
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/* FD_RXDATA3 */
|
#define CAN_FD_RXDATA3_OFFSET (0x318U)
|
#define CAN_FD_RXDATA3 (0x0U)
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#define CAN_FD_RXDATA3_RX_DATA3_SHIFT (0U)
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#define CAN_FD_RXDATA3_RX_DATA3_MASK (0xFFFFFFFFU << CAN_FD_RXDATA3_RX_DATA3_SHIFT) /* 0xFFFFFFFF */
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/* FD_RXDATA4 */
|
#define CAN_FD_RXDATA4_OFFSET (0x31CU)
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#define CAN_FD_RXDATA4 (0x0U)
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#define CAN_FD_RXDATA4_RX_DATA4_SHIFT (0U)
|
#define CAN_FD_RXDATA4_RX_DATA4_MASK (0xFFFFFFFFU << CAN_FD_RXDATA4_RX_DATA4_SHIFT) /* 0xFFFFFFFF */
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/* FD_RXDATA5 */
|
#define CAN_FD_RXDATA5_OFFSET (0x320U)
|
#define CAN_FD_RXDATA5 (0x0U)
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#define CAN_FD_RXDATA5_RX_DATA5_SHIFT (0U)
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#define CAN_FD_RXDATA5_RX_DATA5_MASK (0xFFFFFFFFU << CAN_FD_RXDATA5_RX_DATA5_SHIFT) /* 0xFFFFFFFF */
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/* FD_RXDATA6 */
|
#define CAN_FD_RXDATA6_OFFSET (0x324U)
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#define CAN_FD_RXDATA6 (0x0U)
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#define CAN_FD_RXDATA6_RX_DATA6_SHIFT (0U)
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#define CAN_FD_RXDATA6_RX_DATA6_MASK (0xFFFFFFFFU << CAN_FD_RXDATA6_RX_DATA6_SHIFT) /* 0xFFFFFFFF */
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/* FD_RXDATA7 */
|
#define CAN_FD_RXDATA7_OFFSET (0x328U)
|
#define CAN_FD_RXDATA7 (0x0U)
|
#define CAN_FD_RXDATA7_RX_DATA7_SHIFT (0U)
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#define CAN_FD_RXDATA7_RX_DATA7_MASK (0xFFFFFFFFU << CAN_FD_RXDATA7_RX_DATA7_SHIFT) /* 0xFFFFFFFF */
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/* FD_RXDATA8 */
|
#define CAN_FD_RXDATA8_OFFSET (0x32CU)
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#define CAN_FD_RXDATA8 (0x0U)
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#define CAN_FD_RXDATA8_RX_DATA8_SHIFT (0U)
|
#define CAN_FD_RXDATA8_RX_DATA8_MASK (0xFFFFFFFFU << CAN_FD_RXDATA8_RX_DATA8_SHIFT) /* 0xFFFFFFFF */
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/* FD_RXDATA9 */
|
#define CAN_FD_RXDATA9_OFFSET (0x330U)
|
#define CAN_FD_RXDATA9 (0x0U)
|
#define CAN_FD_RXDATA9_RX_DATA9_SHIFT (0U)
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#define CAN_FD_RXDATA9_RX_DATA9_MASK (0xFFFFFFFFU << CAN_FD_RXDATA9_RX_DATA9_SHIFT) /* 0xFFFFFFFF */
|
/* FD_RXDATA10 */
|
#define CAN_FD_RXDATA10_OFFSET (0x334U)
|
#define CAN_FD_RXDATA10 (0x0U)
|
#define CAN_FD_RXDATA10_RX_DATA10_SHIFT (0U)
|
#define CAN_FD_RXDATA10_RX_DATA10_MASK (0xFFFFFFFFU << CAN_FD_RXDATA10_RX_DATA10_SHIFT) /* 0xFFFFFFFF */
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/* FD_RXDATA11 */
|
#define CAN_FD_RXDATA11_OFFSET (0x338U)
|
#define CAN_FD_RXDATA11 (0x0U)
|
#define CAN_FD_RXDATA11_RX_DATA11_SHIFT (0U)
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#define CAN_FD_RXDATA11_RX_DATA11_MASK (0xFFFFFFFFU << CAN_FD_RXDATA11_RX_DATA11_SHIFT) /* 0xFFFFFFFF */
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/* FD_RXDATA12 */
|
#define CAN_FD_RXDATA12_OFFSET (0x33CU)
|
#define CAN_FD_RXDATA12 (0x0U)
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#define CAN_FD_RXDATA12_RX_DATA12_SHIFT (0U)
|
#define CAN_FD_RXDATA12_RX_DATA12_MASK (0xFFFFFFFFU << CAN_FD_RXDATA12_RX_DATA12_SHIFT) /* 0xFFFFFFFF */
|
/* FD_RXDATA13 */
|
#define CAN_FD_RXDATA13_OFFSET (0x340U)
|
#define CAN_FD_RXDATA13 (0x0U)
|
#define CAN_FD_RXDATA13_RX_DATA13_SHIFT (0U)
|
#define CAN_FD_RXDATA13_RX_DATA13_MASK (0xFFFFFFFFU << CAN_FD_RXDATA13_RX_DATA13_SHIFT) /* 0xFFFFFFFF */
|
/* FD_RXDATA14 */
|
#define CAN_FD_RXDATA14_OFFSET (0x344U)
|
#define CAN_FD_RXDATA14 (0x0U)
|
#define CAN_FD_RXDATA14_RX_DATA14_SHIFT (0U)
|
#define CAN_FD_RXDATA14_RX_DATA14_MASK (0xFFFFFFFFU << CAN_FD_RXDATA14_RX_DATA14_SHIFT) /* 0xFFFFFFFF */
|
/* FD_RXDATA15 */
|
#define CAN_FD_RXDATA15_OFFSET (0x348U)
|
#define CAN_FD_RXDATA15 (0x0U)
|
#define CAN_FD_RXDATA15_RX_DATA15_SHIFT (0U)
|
#define CAN_FD_RXDATA15_RX_DATA15_MASK (0xFFFFFFFFU << CAN_FD_RXDATA15_RX_DATA15_SHIFT) /* 0xFFFFFFFF */
|
/* RX_FIFO_RDATA */
|
#define CAN_RX_FIFO_RDATA_OFFSET (0x400U)
|
#define CAN_RX_FIFO_RDATA (0x0U)
|
#define CAN_RX_FIFO_RDATA_RX_FIFO_RDATA_SHIFT (0U)
|
#define CAN_RX_FIFO_RDATA_RX_FIFO_RDATA_MASK (0xFFFFFFFFU << CAN_RX_FIFO_RDATA_RX_FIFO_RDATA_SHIFT) /* 0xFFFFFFFF */
|
/* TXE_FIFO_RDATA */
|
#define CAN_TXE_FIFO_RDATA_OFFSET (0x500U)
|
#define CAN_TXE_FIFO_RDATA (0x0U)
|
#define CAN_TXE_FIFO_RDATA_TXE_FIFO_RDATA_SHIFT (0U)
|
#define CAN_TXE_FIFO_RDATA_TXE_FIFO_RDATA_MASK (0xFFFFFFFFU << CAN_TXE_FIFO_RDATA_TXE_FIFO_RDATA_SHIFT) /* 0xFFFFFFFF */
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/******************************************WDT*******************************************/
|
/* CR */
|
#define WDT_CR_OFFSET (0x0U)
|
#define WDT_CR_WDT_EN_SHIFT (0U)
|
#define WDT_CR_WDT_EN_MASK (0x1U << WDT_CR_WDT_EN_SHIFT) /* 0x00000001 */
|
#define WDT_CR_RESP_MODE_SHIFT (1U)
|
#define WDT_CR_RESP_MODE_MASK (0x1U << WDT_CR_RESP_MODE_SHIFT) /* 0x00000002 */
|
#define WDT_CR_RST_PLUSE_LENGTH_SHIFT (2U)
|
#define WDT_CR_RST_PLUSE_LENGTH_MASK (0x7U << WDT_CR_RST_PLUSE_LENGTH_SHIFT) /* 0x0000001C */
|
/* TORR */
|
#define WDT_TORR_OFFSET (0x4U)
|
#define WDT_TORR_TIMEOUT_PERIOD_SHIFT (0U)
|
#define WDT_TORR_TIMEOUT_PERIOD_MASK (0xFU << WDT_TORR_TIMEOUT_PERIOD_SHIFT) /* 0x0000000F */
|
/* CCVR */
|
#define WDT_CCVR_OFFSET (0x8U)
|
#define WDT_CCVR (0xFFFFU)
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#define WDT_CCVR_CUR_CNT_SHIFT (0U)
|
#define WDT_CCVR_CUR_CNT_MASK (0xFFFFFFFFU << WDT_CCVR_CUR_CNT_SHIFT) /* 0xFFFFFFFF */
|
/* CRR */
|
#define WDT_CRR_OFFSET (0xCU)
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#define WDT_CRR_CNT_RESTART_SHIFT (0U)
|
#define WDT_CRR_CNT_RESTART_MASK (0xFFU << WDT_CRR_CNT_RESTART_SHIFT) /* 0x000000FF */
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/* STAT */
|
#define WDT_STAT_OFFSET (0x10U)
|
#define WDT_STAT (0x0U)
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#define WDT_STAT_WDT_STATUS_SHIFT (0U)
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#define WDT_STAT_WDT_STATUS_MASK (0x1U << WDT_STAT_WDT_STATUS_SHIFT) /* 0x00000001 */
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/* EOI */
|
#define WDT_EOI_OFFSET (0x14U)
|
#define WDT_EOI (0x0U)
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#define WDT_EOI_WDT_INT_CLR_SHIFT (0U)
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#define WDT_EOI_WDT_INT_CLR_MASK (0x1U << WDT_EOI_WDT_INT_CLR_SHIFT) /* 0x00000001 */
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/******************************************SPI*******************************************/
|
/* CTRLR0 */
|
#define SPI_CTRLR0_OFFSET (0x0U)
|
#define SPI_CTRLR0_DFS_SHIFT (0U)
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#define SPI_CTRLR0_DFS_MASK (0x3U << SPI_CTRLR0_DFS_SHIFT) /* 0x00000003 */
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#define SPI_CTRLR0_CFS_SHIFT (2U)
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#define SPI_CTRLR0_CFS_MASK (0xFU << SPI_CTRLR0_CFS_SHIFT) /* 0x0000003C */
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#define SPI_CTRLR0_SCPH_SHIFT (6U)
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#define SPI_CTRLR0_SCPH_MASK (0x1U << SPI_CTRLR0_SCPH_SHIFT) /* 0x00000040 */
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#define SPI_CTRLR0_SCPOL_SHIFT (7U)
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#define SPI_CTRLR0_SCPOL_MASK (0x1U << SPI_CTRLR0_SCPOL_SHIFT) /* 0x00000080 */
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#define SPI_CTRLR0_CSM_SHIFT (8U)
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#define SPI_CTRLR0_CSM_MASK (0x3U << SPI_CTRLR0_CSM_SHIFT) /* 0x00000300 */
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#define SPI_CTRLR0_SSD_SHIFT (10U)
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#define SPI_CTRLR0_SSD_MASK (0x1U << SPI_CTRLR0_SSD_SHIFT) /* 0x00000400 */
|
#define SPI_CTRLR0_EM_SHIFT (11U)
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#define SPI_CTRLR0_EM_MASK (0x1U << SPI_CTRLR0_EM_SHIFT) /* 0x00000800 */
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#define SPI_CTRLR0_FBM_SHIFT (12U)
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#define SPI_CTRLR0_FBM_MASK (0x1U << SPI_CTRLR0_FBM_SHIFT) /* 0x00001000 */
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#define SPI_CTRLR0_BHT_SHIFT (13U)
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#define SPI_CTRLR0_BHT_MASK (0x1U << SPI_CTRLR0_BHT_SHIFT) /* 0x00002000 */
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#define SPI_CTRLR0_RSD_SHIFT (14U)
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#define SPI_CTRLR0_RSD_MASK (0x3U << SPI_CTRLR0_RSD_SHIFT) /* 0x0000C000 */
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#define SPI_CTRLR0_FRF_SHIFT (16U)
|
#define SPI_CTRLR0_FRF_MASK (0x3U << SPI_CTRLR0_FRF_SHIFT) /* 0x00030000 */
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#define SPI_CTRLR0_XFM_SHIFT (18U)
|
#define SPI_CTRLR0_XFM_MASK (0x3U << SPI_CTRLR0_XFM_SHIFT) /* 0x000C0000 */
|
#define SPI_CTRLR0_OPM_SHIFT (20U)
|
#define SPI_CTRLR0_OPM_MASK (0x1U << SPI_CTRLR0_OPM_SHIFT) /* 0x00100000 */
|
#define SPI_CTRLR0_MTM_SHIFT (21U)
|
#define SPI_CTRLR0_MTM_MASK (0x1U << SPI_CTRLR0_MTM_SHIFT) /* 0x00200000 */
|
#define SPI_CTRLR0_SM_SHIFT (22U)
|
#define SPI_CTRLR0_SM_MASK (0x1U << SPI_CTRLR0_SM_SHIFT) /* 0x00400000 */
|
#define SPI_CTRLR0_SOI_SHIFT (23U)
|
#define SPI_CTRLR0_SOI_MASK (0x3U << SPI_CTRLR0_SOI_SHIFT) /* 0x01800000 */
|
#define SPI_CTRLR0_LBK_SHIFT (25U)
|
#define SPI_CTRLR0_LBK_MASK (0x1U << SPI_CTRLR0_LBK_SHIFT) /* 0x02000000 */
|
/* CTRLR1 */
|
#define SPI_CTRLR1_OFFSET (0x4U)
|
#define SPI_CTRLR1_NDM_SHIFT (0U)
|
#define SPI_CTRLR1_NDM_MASK (0xFFFFFFFFU << SPI_CTRLR1_NDM_SHIFT) /* 0xFFFFFFFF */
|
/* ENR */
|
#define SPI_ENR_OFFSET (0x8U)
|
#define SPI_ENR_ENR_SHIFT (0U)
|
#define SPI_ENR_ENR_MASK (0x1U << SPI_ENR_ENR_SHIFT) /* 0x00000001 */
|
/* SER */
|
#define SPI_SER_OFFSET (0xCU)
|
#define SPI_SER_SER_SHIFT (0U)
|
#define SPI_SER_SER_MASK (0x3U << SPI_SER_SER_SHIFT) /* 0x00000003 */
|
/* BAUDR */
|
#define SPI_BAUDR_OFFSET (0x10U)
|
#define SPI_BAUDR_BAUDR_SHIFT (0U)
|
#define SPI_BAUDR_BAUDR_MASK (0xFFFFU << SPI_BAUDR_BAUDR_SHIFT) /* 0x0000FFFF */
|
/* TXFTLR */
|
#define SPI_TXFTLR_OFFSET (0x14U)
|
#define SPI_TXFTLR_XFTLR_SHIFT (0U)
|
#define SPI_TXFTLR_XFTLR_MASK (0x3FU << SPI_TXFTLR_XFTLR_SHIFT) /* 0x0000003F */
|
/* RXFTLR */
|
#define SPI_RXFTLR_OFFSET (0x18U)
|
#define SPI_RXFTLR_RXFTLR_SHIFT (0U)
|
#define SPI_RXFTLR_RXFTLR_MASK (0x3FU << SPI_RXFTLR_RXFTLR_SHIFT) /* 0x0000003F */
|
/* TXFLR */
|
#define SPI_TXFLR_OFFSET (0x1CU)
|
#define SPI_TXFLR (0x0U)
|
#define SPI_TXFLR_TXFLR_SHIFT (0U)
|
#define SPI_TXFLR_TXFLR_MASK (0x7FU << SPI_TXFLR_TXFLR_SHIFT) /* 0x0000007F */
|
/* RXFLR */
|
#define SPI_RXFLR_OFFSET (0x20U)
|
#define SPI_RXFLR (0x0U)
|
#define SPI_RXFLR_RXFLR_SHIFT (0U)
|
#define SPI_RXFLR_RXFLR_MASK (0x7FU << SPI_RXFLR_RXFLR_SHIFT) /* 0x0000007F */
|
/* SR */
|
#define SPI_SR_OFFSET (0x24U)
|
#define SPI_SR (0x4CU)
|
#define SPI_SR_BSF_SHIFT (0U)
|
#define SPI_SR_BSF_MASK (0x1U << SPI_SR_BSF_SHIFT) /* 0x00000001 */
|
#define SPI_SR_TFF_SHIFT (1U)
|
#define SPI_SR_TFF_MASK (0x1U << SPI_SR_TFF_SHIFT) /* 0x00000002 */
|
#define SPI_SR_TFE_SHIFT (2U)
|
#define SPI_SR_TFE_MASK (0x1U << SPI_SR_TFE_SHIFT) /* 0x00000004 */
|
#define SPI_SR_RFE_SHIFT (3U)
|
#define SPI_SR_RFE_MASK (0x1U << SPI_SR_RFE_SHIFT) /* 0x00000008 */
|
#define SPI_SR_RFF_SHIFT (4U)
|
#define SPI_SR_RFF_MASK (0x1U << SPI_SR_RFF_SHIFT) /* 0x00000010 */
|
#define SPI_SR_STB_SHIFT (5U)
|
#define SPI_SR_STB_MASK (0x1U << SPI_SR_STB_SHIFT) /* 0x00000020 */
|
#define SPI_SR_SSI_SHIFT (6U)
|
#define SPI_SR_SSI_MASK (0x1U << SPI_SR_SSI_SHIFT) /* 0x00000040 */
|
/* IPR */
|
#define SPI_IPR_OFFSET (0x28U)
|
#define SPI_IPR_IPR_SHIFT (0U)
|
#define SPI_IPR_IPR_MASK (0x1U << SPI_IPR_IPR_SHIFT) /* 0x00000001 */
|
/* IMR */
|
#define SPI_IMR_OFFSET (0x2CU)
|
#define SPI_IMR_TFEIM_SHIFT (0U)
|
#define SPI_IMR_TFEIM_MASK (0x1U << SPI_IMR_TFEIM_SHIFT) /* 0x00000001 */
|
#define SPI_IMR_TFOIM_SHIFT (1U)
|
#define SPI_IMR_TFOIM_MASK (0x1U << SPI_IMR_TFOIM_SHIFT) /* 0x00000002 */
|
#define SPI_IMR_RFUIM_SHIFT (2U)
|
#define SPI_IMR_RFUIM_MASK (0x1U << SPI_IMR_RFUIM_SHIFT) /* 0x00000004 */
|
#define SPI_IMR_RFOIM_SHIFT (3U)
|
#define SPI_IMR_RFOIM_MASK (0x1U << SPI_IMR_RFOIM_SHIFT) /* 0x00000008 */
|
#define SPI_IMR_RFFIM_SHIFT (4U)
|
#define SPI_IMR_RFFIM_MASK (0x1U << SPI_IMR_RFFIM_SHIFT) /* 0x00000010 */
|
#define SPI_IMR_TOIM_SHIFT (5U)
|
#define SPI_IMR_TOIM_MASK (0x1U << SPI_IMR_TOIM_SHIFT) /* 0x00000020 */
|
#define SPI_IMR_SSPIM_SHIFT (6U)
|
#define SPI_IMR_SSPIM_MASK (0x1U << SPI_IMR_SSPIM_SHIFT) /* 0x00000040 */
|
#define SPI_IMR_TXFIM_SHIFT (7U)
|
#define SPI_IMR_TXFIM_MASK (0x1U << SPI_IMR_TXFIM_SHIFT) /* 0x00000080 */
|
/* ISR */
|
#define SPI_ISR_OFFSET (0x30U)
|
#define SPI_ISR_TFEIS_SHIFT (0U)
|
#define SPI_ISR_TFEIS_MASK (0x1U << SPI_ISR_TFEIS_SHIFT) /* 0x00000001 */
|
#define SPI_ISR_TFOIS_SHIFT (1U)
|
#define SPI_ISR_TFOIS_MASK (0x1U << SPI_ISR_TFOIS_SHIFT) /* 0x00000002 */
|
#define SPI_ISR_RFUIS_SHIFT (2U)
|
#define SPI_ISR_RFUIS_MASK (0x1U << SPI_ISR_RFUIS_SHIFT) /* 0x00000004 */
|
#define SPI_ISR_RFOIS_SHIFT (3U)
|
#define SPI_ISR_RFOIS_MASK (0x1U << SPI_ISR_RFOIS_SHIFT) /* 0x00000008 */
|
#define SPI_ISR_RFFIS_SHIFT (4U)
|
#define SPI_ISR_RFFIS_MASK (0x1U << SPI_ISR_RFFIS_SHIFT) /* 0x00000010 */
|
#define SPI_ISR_TOIS_SHIFT (5U)
|
#define SPI_ISR_TOIS_MASK (0x1U << SPI_ISR_TOIS_SHIFT) /* 0x00000020 */
|
#define SPI_ISR_SSPIS_SHIFT (6U)
|
#define SPI_ISR_SSPIS_MASK (0x1U << SPI_ISR_SSPIS_SHIFT) /* 0x00000040 */
|
#define SPI_ISR_TXFIS_SHIFT (7U)
|
#define SPI_ISR_TXFIS_MASK (0x1U << SPI_ISR_TXFIS_SHIFT) /* 0x00000080 */
|
/* RISR */
|
#define SPI_RISR_OFFSET (0x34U)
|
#define SPI_RISR_TFERIS_SHIFT (0U)
|
#define SPI_RISR_TFERIS_MASK (0x1U << SPI_RISR_TFERIS_SHIFT) /* 0x00000001 */
|
#define SPI_RISR_TFORIS_SHIFT (1U)
|
#define SPI_RISR_TFORIS_MASK (0x1U << SPI_RISR_TFORIS_SHIFT) /* 0x00000002 */
|
#define SPI_RISR_RFURIS_SHIFT (2U)
|
#define SPI_RISR_RFURIS_MASK (0x1U << SPI_RISR_RFURIS_SHIFT) /* 0x00000004 */
|
#define SPI_RISR_RFORIS_SHIFT (3U)
|
#define SPI_RISR_RFORIS_MASK (0x1U << SPI_RISR_RFORIS_SHIFT) /* 0x00000008 */
|
#define SPI_RISR_RFFRIS_SHIFT (4U)
|
#define SPI_RISR_RFFRIS_MASK (0x1U << SPI_RISR_RFFRIS_SHIFT) /* 0x00000010 */
|
#define SPI_RISR_TORIS_SHIFT (5U)
|
#define SPI_RISR_TORIS_MASK (0x1U << SPI_RISR_TORIS_SHIFT) /* 0x00000020 */
|
#define SPI_RISR_SSPRIS_SHIFT (6U)
|
#define SPI_RISR_SSPRIS_MASK (0x1U << SPI_RISR_SSPRIS_SHIFT) /* 0x00000040 */
|
#define SPI_RISR_TXFRIS_SHIFT (7U)
|
#define SPI_RISR_TXFRIS_MASK (0x1U << SPI_RISR_TXFRIS_SHIFT) /* 0x00000080 */
|
/* ICR */
|
#define SPI_ICR_OFFSET (0x38U)
|
#define SPI_ICR_CCI_SHIFT (0U)
|
#define SPI_ICR_CCI_MASK (0x1U << SPI_ICR_CCI_SHIFT) /* 0x00000001 */
|
#define SPI_ICR_CRFUI_SHIFT (1U)
|
#define SPI_ICR_CRFUI_MASK (0x1U << SPI_ICR_CRFUI_SHIFT) /* 0x00000002 */
|
#define SPI_ICR_CRFOI_SHIFT (2U)
|
#define SPI_ICR_CRFOI_MASK (0x1U << SPI_ICR_CRFOI_SHIFT) /* 0x00000004 */
|
#define SPI_ICR_CTFOI_SHIFT (3U)
|
#define SPI_ICR_CTFOI_MASK (0x1U << SPI_ICR_CTFOI_SHIFT) /* 0x00000008 */
|
#define SPI_ICR_CTOI_SHIFT (4U)
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#define SPI_ICR_CTOI_MASK (0x1U << SPI_ICR_CTOI_SHIFT) /* 0x00000010 */
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#define SPI_ICR_CSSPI_SHIFT (5U)
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#define SPI_ICR_CSSPI_MASK (0x1U << SPI_ICR_CSSPI_SHIFT) /* 0x00000020 */
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#define SPI_ICR_CTXFI_SHIFT (6U)
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#define SPI_ICR_CTXFI_MASK (0x1U << SPI_ICR_CTXFI_SHIFT) /* 0x00000040 */
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/* DMACR */
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#define SPI_DMACR_OFFSET (0x3CU)
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#define SPI_DMACR_RDE_SHIFT (0U)
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#define SPI_DMACR_RDE_MASK (0x1U << SPI_DMACR_RDE_SHIFT) /* 0x00000001 */
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#define SPI_DMACR_TDE_SHIFT (1U)
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#define SPI_DMACR_TDE_MASK (0x1U << SPI_DMACR_TDE_SHIFT) /* 0x00000002 */
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/* DMATDLR */
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#define SPI_DMATDLR_OFFSET (0x40U)
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#define SPI_DMATDLR_TDL_SHIFT (0U)
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#define SPI_DMATDLR_TDL_MASK (0x3FU << SPI_DMATDLR_TDL_SHIFT) /* 0x0000003F */
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/* DMARDLR */
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#define SPI_DMARDLR_OFFSET (0x44U)
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#define SPI_DMARDLR_RDL_SHIFT (0U)
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#define SPI_DMARDLR_RDL_MASK (0x3FU << SPI_DMARDLR_RDL_SHIFT) /* 0x0000003F */
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/* TIMEOUT */
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#define SPI_TIMEOUT_OFFSET (0x4CU)
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#define SPI_TIMEOUT_TOV_SHIFT (0U)
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#define SPI_TIMEOUT_TOV_MASK (0xFFFFU << SPI_TIMEOUT_TOV_SHIFT) /* 0x0000FFFF */
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#define SPI_TIMEOUT_TOE_SHIFT (16U)
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#define SPI_TIMEOUT_TOE_MASK (0x1U << SPI_TIMEOUT_TOE_SHIFT) /* 0x00010000 */
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/* BYPASS */
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#define SPI_BYPASS_OFFSET (0x50U)
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#define SPI_BYPASS_BYEN_SHIFT (0U)
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#define SPI_BYPASS_BYEN_MASK (0x1U << SPI_BYPASS_BYEN_SHIFT) /* 0x00000001 */
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#define SPI_BYPASS_FBM_SHIFT (1U)
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#define SPI_BYPASS_FBM_MASK (0x1U << SPI_BYPASS_FBM_SHIFT) /* 0x00000002 */
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#define SPI_BYPASS_END_SHIFT (2U)
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#define SPI_BYPASS_END_MASK (0x1U << SPI_BYPASS_END_SHIFT) /* 0x00000004 */
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#define SPI_BYPASS_RXCP_SHIFT (3U)
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#define SPI_BYPASS_RXCP_MASK (0x1U << SPI_BYPASS_RXCP_SHIFT) /* 0x00000008 */
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#define SPI_BYPASS_TXCP_SHIFT (4U)
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#define SPI_BYPASS_TXCP_MASK (0x1U << SPI_BYPASS_TXCP_SHIFT) /* 0x00000010 */
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/* TXDR */
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#define SPI_TXDR_OFFSET (0x400U)
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#define SPI_TXDR_TXDR_SHIFT (0U)
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#define SPI_TXDR_TXDR_MASK (0xFFFFU << SPI_TXDR_TXDR_SHIFT) /* 0x0000FFFF */
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/* RXDR */
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#define SPI_RXDR_OFFSET (0x800U)
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#define SPI_RXDR (0x0U)
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#define SPI_RXDR_RXDR_SHIFT (0U)
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#define SPI_RXDR_RXDR_MASK (0xFFFFU << SPI_RXDR_RXDR_SHIFT) /* 0x0000FFFF */
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/*****************************************TSADC******************************************/
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/* USER_CON */
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#define TSADC_USER_CON_OFFSET (0x0U)
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#define TSADC_USER_CON_ADC_INPUT_SRC_SEL_SHIFT (0U)
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#define TSADC_USER_CON_ADC_INPUT_SRC_SEL_MASK (0x7U << TSADC_USER_CON_ADC_INPUT_SRC_SEL_SHIFT) /* 0x00000007 */
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#define TSADC_USER_CON_ADC_POWER_CTRL_SHIFT (3U)
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#define TSADC_USER_CON_ADC_POWER_CTRL_MASK (0x1U << TSADC_USER_CON_ADC_POWER_CTRL_SHIFT) /* 0x00000008 */
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#define TSADC_USER_CON_START_MODE_SHIFT (4U)
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#define TSADC_USER_CON_START_MODE_MASK (0x1U << TSADC_USER_CON_START_MODE_SHIFT) /* 0x00000010 */
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#define TSADC_USER_CON_START_SHIFT (5U)
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#define TSADC_USER_CON_START_MASK (0x1U << TSADC_USER_CON_START_SHIFT) /* 0x00000020 */
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#define TSADC_USER_CON_INTER_PD_SOC_SHIFT (6U)
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#define TSADC_USER_CON_INTER_PD_SOC_MASK (0x1FFU << TSADC_USER_CON_INTER_PD_SOC_SHIFT) /* 0x00007FC0 */
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#define TSADC_USER_CON_ADC_STATUS_SHIFT (15U)
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#define TSADC_USER_CON_ADC_STATUS_MASK (0x1U << TSADC_USER_CON_ADC_STATUS_SHIFT) /* 0x00008000 */
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/* AUTO_CON */
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#define TSADC_AUTO_CON_OFFSET (0x4U)
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#define TSADC_AUTO_CON_AUTO_EN_SHIFT (0U)
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#define TSADC_AUTO_CON_AUTO_EN_MASK (0x1U << TSADC_AUTO_CON_AUTO_EN_SHIFT) /* 0x00000001 */
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#define TSADC_AUTO_CON_TSADC_Q_SEL_SHIFT (1U)
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#define TSADC_AUTO_CON_TSADC_Q_SEL_MASK (0x1U << TSADC_AUTO_CON_TSADC_Q_SEL_SHIFT) /* 0x00000002 */
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#define TSADC_AUTO_CON_SRC0_EN_SHIFT (4U)
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#define TSADC_AUTO_CON_SRC0_EN_MASK (0x1U << TSADC_AUTO_CON_SRC0_EN_SHIFT) /* 0x00000010 */
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#define TSADC_AUTO_CON_SRC1_EN_SHIFT (5U)
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#define TSADC_AUTO_CON_SRC1_EN_MASK (0x1U << TSADC_AUTO_CON_SRC1_EN_SHIFT) /* 0x00000020 */
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#define TSADC_AUTO_CON_TSHUT_PROLARITY_SHIFT (8U)
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#define TSADC_AUTO_CON_TSHUT_PROLARITY_MASK (0x1U << TSADC_AUTO_CON_TSHUT_PROLARITY_SHIFT) /* 0x00000100 */
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#define TSADC_AUTO_CON_SRC0_LT_EN_SHIFT (12U)
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#define TSADC_AUTO_CON_SRC0_LT_EN_MASK (0x1U << TSADC_AUTO_CON_SRC0_LT_EN_SHIFT) /* 0x00001000 */
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#define TSADC_AUTO_CON_SRC1_LT_EN_SHIFT (13U)
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#define TSADC_AUTO_CON_SRC1_LT_EN_MASK (0x1U << TSADC_AUTO_CON_SRC1_LT_EN_SHIFT) /* 0x00002000 */
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#define TSADC_AUTO_CON_AUTO_STATUS_SHIFT (16U)
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#define TSADC_AUTO_CON_AUTO_STATUS_MASK (0x1U << TSADC_AUTO_CON_AUTO_STATUS_SHIFT) /* 0x00010000 */
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#define TSADC_AUTO_CON_SAMPLE_DLY_SEL_SHIFT (17U)
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#define TSADC_AUTO_CON_SAMPLE_DLY_SEL_MASK (0x1U << TSADC_AUTO_CON_SAMPLE_DLY_SEL_SHIFT) /* 0x00020000 */
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#define TSADC_AUTO_CON_LAST_TSHUT_2GPIO_SHIFT (24U)
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#define TSADC_AUTO_CON_LAST_TSHUT_2GPIO_MASK (0x1U << TSADC_AUTO_CON_LAST_TSHUT_2GPIO_SHIFT) /* 0x01000000 */
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#define TSADC_AUTO_CON_LAST_TSHUT_2CRU_SHIFT (25U)
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#define TSADC_AUTO_CON_LAST_TSHUT_2CRU_MASK (0x1U << TSADC_AUTO_CON_LAST_TSHUT_2CRU_SHIFT) /* 0x02000000 */
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/* INT_EN */
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#define TSADC_INT_EN_OFFSET (0x8U)
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#define TSADC_INT_EN_HT_INTEN_SRC0_SHIFT (0U)
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#define TSADC_INT_EN_HT_INTEN_SRC0_MASK (0x1U << TSADC_INT_EN_HT_INTEN_SRC0_SHIFT) /* 0x00000001 */
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#define TSADC_INT_EN_HT_INTEN_SRC1_SHIFT (1U)
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#define TSADC_INT_EN_HT_INTEN_SRC1_MASK (0x1U << TSADC_INT_EN_HT_INTEN_SRC1_SHIFT) /* 0x00000002 */
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#define TSADC_INT_EN_TSHUT_2GPIO_EN_SRC0_SHIFT (4U)
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#define TSADC_INT_EN_TSHUT_2GPIO_EN_SRC0_MASK (0x1U << TSADC_INT_EN_TSHUT_2GPIO_EN_SRC0_SHIFT) /* 0x00000010 */
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#define TSADC_INT_EN_TSHUT_2GPIO_EN_SRC1_SHIFT (5U)
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#define TSADC_INT_EN_TSHUT_2GPIO_EN_SRC1_MASK (0x1U << TSADC_INT_EN_TSHUT_2GPIO_EN_SRC1_SHIFT) /* 0x00000020 */
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#define TSADC_INT_EN_TSHUT_2CRU_EN_SRC0_SHIFT (8U)
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#define TSADC_INT_EN_TSHUT_2CRU_EN_SRC0_MASK (0x1U << TSADC_INT_EN_TSHUT_2CRU_EN_SRC0_SHIFT) /* 0x00000100 */
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#define TSADC_INT_EN_TSHUT_2CRU_EN_SRC1_SHIFT (9U)
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#define TSADC_INT_EN_TSHUT_2CRU_EN_SRC1_MASK (0x1U << TSADC_INT_EN_TSHUT_2CRU_EN_SRC1_SHIFT) /* 0x00000200 */
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#define TSADC_INT_EN_LT_INTEN_SRC0_SHIFT (12U)
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#define TSADC_INT_EN_LT_INTEN_SRC0_MASK (0x1U << TSADC_INT_EN_LT_INTEN_SRC0_SHIFT) /* 0x00001000 */
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#define TSADC_INT_EN_LT_INTEN_SRC1_SHIFT (13U)
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#define TSADC_INT_EN_LT_INTEN_SRC1_MASK (0x1U << TSADC_INT_EN_LT_INTEN_SRC1_SHIFT) /* 0x00002000 */
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#define TSADC_INT_EN_EOC_INT_EN_SHIFT (16U)
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#define TSADC_INT_EN_EOC_INT_EN_MASK (0x1U << TSADC_INT_EN_EOC_INT_EN_SHIFT) /* 0x00010000 */
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/* INT_PD */
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#define TSADC_INT_PD_OFFSET (0xCU)
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#define TSADC_INT_PD_HT_IRQ_SRC0_SHIFT (0U)
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#define TSADC_INT_PD_HT_IRQ_SRC0_MASK (0x1U << TSADC_INT_PD_HT_IRQ_SRC0_SHIFT) /* 0x00000001 */
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#define TSADC_INT_PD_HT_IRQ_SRC1_SHIFT (1U)
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#define TSADC_INT_PD_HT_IRQ_SRC1_MASK (0x1U << TSADC_INT_PD_HT_IRQ_SRC1_SHIFT) /* 0x00000002 */
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#define TSADC_INT_PD_TSHUT_O_SRC0_SHIFT (4U)
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#define TSADC_INT_PD_TSHUT_O_SRC0_MASK (0x1U << TSADC_INT_PD_TSHUT_O_SRC0_SHIFT) /* 0x00000010 */
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#define TSADC_INT_PD_TSHUT_O_SRC1_SHIFT (5U)
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#define TSADC_INT_PD_TSHUT_O_SRC1_MASK (0x1U << TSADC_INT_PD_TSHUT_O_SRC1_SHIFT) /* 0x00000020 */
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#define TSADC_INT_PD_LT_IRQ_SRC0_SHIFT (12U)
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#define TSADC_INT_PD_LT_IRQ_SRC0_MASK (0x1U << TSADC_INT_PD_LT_IRQ_SRC0_SHIFT) /* 0x00001000 */
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#define TSADC_INT_PD_LT_IRQ_SRC1_SHIFT (13U)
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#define TSADC_INT_PD_LT_IRQ_SRC1_MASK (0x1U << TSADC_INT_PD_LT_IRQ_SRC1_SHIFT) /* 0x00002000 */
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#define TSADC_INT_PD_EOC_INT_PD_SHIFT (16U)
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#define TSADC_INT_PD_EOC_INT_PD_MASK (0x1U << TSADC_INT_PD_EOC_INT_PD_SHIFT) /* 0x00010000 */
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/* DATA0 */
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#define TSADC_DATA0_OFFSET (0x20U)
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#define TSADC_DATA0 (0x0U)
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#define TSADC_DATA0_ADC_DATA_SHIFT (0U)
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#define TSADC_DATA0_ADC_DATA_MASK (0xFFFU << TSADC_DATA0_ADC_DATA_SHIFT) /* 0x00000FFF */
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/* DATA1 */
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#define TSADC_DATA1_OFFSET (0x24U)
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#define TSADC_DATA1 (0x0U)
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#define TSADC_DATA1_ADC_DATA_SHIFT (0U)
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#define TSADC_DATA1_ADC_DATA_MASK (0xFFFU << TSADC_DATA1_ADC_DATA_SHIFT) /* 0x00000FFF */
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/* COMP0_INT */
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#define TSADC_COMP0_INT_OFFSET (0x30U)
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#define TSADC_COMP0_INT_TSADC_COMP_SRC0_SHIFT (0U)
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#define TSADC_COMP0_INT_TSADC_COMP_SRC0_MASK (0xFFFU << TSADC_COMP0_INT_TSADC_COMP_SRC0_SHIFT) /* 0x00000FFF */
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/* COMP1_INT */
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#define TSADC_COMP1_INT_OFFSET (0x34U)
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#define TSADC_COMP1_INT_TSADC_COMP_SRC1_SHIFT (0U)
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#define TSADC_COMP1_INT_TSADC_COMP_SRC1_MASK (0xFFFU << TSADC_COMP1_INT_TSADC_COMP_SRC1_SHIFT) /* 0x00000FFF */
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/* COMP0_SHUT */
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#define TSADC_COMP0_SHUT_OFFSET (0x40U)
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#define TSADC_COMP0_SHUT_TSADC_COMP_SRC0_SHIFT (0U)
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#define TSADC_COMP0_SHUT_TSADC_COMP_SRC0_MASK (0xFFFU << TSADC_COMP0_SHUT_TSADC_COMP_SRC0_SHIFT) /* 0x00000FFF */
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/* COMP1_SHUT */
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#define TSADC_COMP1_SHUT_OFFSET (0x44U)
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#define TSADC_COMP1_SHUT_TSADC_COMP_SRC1_SHIFT (0U)
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#define TSADC_COMP1_SHUT_TSADC_COMP_SRC1_MASK (0xFFFU << TSADC_COMP1_SHUT_TSADC_COMP_SRC1_SHIFT) /* 0x00000FFF */
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/* HIGHT_INT_DEBOUNCE */
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#define TSADC_HIGHT_INT_DEBOUNCE_OFFSET (0x60U)
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#define TSADC_HIGHT_INT_DEBOUNCE_DEBOUNCE_SHIFT (0U)
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#define TSADC_HIGHT_INT_DEBOUNCE_DEBOUNCE_MASK (0xFFU << TSADC_HIGHT_INT_DEBOUNCE_DEBOUNCE_SHIFT) /* 0x000000FF */
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/* HIGHT_TSHUT_DEBOUNCE */
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#define TSADC_HIGHT_TSHUT_DEBOUNCE_OFFSET (0x64U)
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#define TSADC_HIGHT_TSHUT_DEBOUNCE_DEBOUNCE_SHIFT (0U)
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#define TSADC_HIGHT_TSHUT_DEBOUNCE_DEBOUNCE_MASK (0xFFU << TSADC_HIGHT_TSHUT_DEBOUNCE_DEBOUNCE_SHIFT) /* 0x000000FF */
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/* AUTO_PERIOD */
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#define TSADC_AUTO_PERIOD_OFFSET (0x68U)
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#define TSADC_AUTO_PERIOD_AUTO_PERIOD_SHIFT (0U)
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#define TSADC_AUTO_PERIOD_AUTO_PERIOD_MASK (0xFFFFFFFFU << TSADC_AUTO_PERIOD_AUTO_PERIOD_SHIFT) /* 0xFFFFFFFF */
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/* AUTO_PERIOD_HT */
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#define TSADC_AUTO_PERIOD_HT_OFFSET (0x6CU)
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#define TSADC_AUTO_PERIOD_HT_AUTO_PERIOD_SHIFT (0U)
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#define TSADC_AUTO_PERIOD_HT_AUTO_PERIOD_MASK (0xFFFFFFFFU << TSADC_AUTO_PERIOD_HT_AUTO_PERIOD_SHIFT) /* 0xFFFFFFFF */
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/* COMP0_LOW_INT */
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#define TSADC_COMP0_LOW_INT_OFFSET (0x80U)
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#define TSADC_COMP0_LOW_INT_TSADC_COMP_SRC0_SHIFT (0U)
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#define TSADC_COMP0_LOW_INT_TSADC_COMP_SRC0_MASK (0xFFFU << TSADC_COMP0_LOW_INT_TSADC_COMP_SRC0_SHIFT) /* 0x00000FFF */
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/* COMP1_LOW_INT */
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#define TSADC_COMP1_LOW_INT_OFFSET (0x84U)
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#define TSADC_COMP1_LOW_INT_TSADC_COMP_SRC1_SHIFT (0U)
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#define TSADC_COMP1_LOW_INT_TSADC_COMP_SRC1_MASK (0xFFFU << TSADC_COMP1_LOW_INT_TSADC_COMP_SRC1_SHIFT) /* 0x00000FFF */
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/******************************************MBOX******************************************/
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/* A2B_INTEN */
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#define MBOX_A2B_INTEN_OFFSET (0x0U)
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#define MBOX_A2B_INTEN_INT0_SHIFT (0U)
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#define MBOX_A2B_INTEN_INT0_MASK (0x1U << MBOX_A2B_INTEN_INT0_SHIFT) /* 0x00000001 */
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#define MBOX_A2B_INTEN_INT1_SHIFT (1U)
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#define MBOX_A2B_INTEN_INT1_MASK (0x1U << MBOX_A2B_INTEN_INT1_SHIFT) /* 0x00000002 */
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#define MBOX_A2B_INTEN_INT2_SHIFT (2U)
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#define MBOX_A2B_INTEN_INT2_MASK (0x1U << MBOX_A2B_INTEN_INT2_SHIFT) /* 0x00000004 */
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#define MBOX_A2B_INTEN_INT3_SHIFT (3U)
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#define MBOX_A2B_INTEN_INT3_MASK (0x1U << MBOX_A2B_INTEN_INT3_SHIFT) /* 0x00000008 */
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/* A2B_STATUS */
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#define MBOX_A2B_STATUS_OFFSET (0x4U)
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#define MBOX_A2B_STATUS_INT0_SHIFT (0U)
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#define MBOX_A2B_STATUS_INT0_MASK (0x1U << MBOX_A2B_STATUS_INT0_SHIFT) /* 0x00000001 */
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#define MBOX_A2B_STATUS_INT1_SHIFT (1U)
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#define MBOX_A2B_STATUS_INT1_MASK (0x1U << MBOX_A2B_STATUS_INT1_SHIFT) /* 0x00000002 */
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#define MBOX_A2B_STATUS_INT2_SHIFT (2U)
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#define MBOX_A2B_STATUS_INT2_MASK (0x1U << MBOX_A2B_STATUS_INT2_SHIFT) /* 0x00000004 */
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#define MBOX_A2B_STATUS_INT3_SHIFT (3U)
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#define MBOX_A2B_STATUS_INT3_MASK (0x1U << MBOX_A2B_STATUS_INT3_SHIFT) /* 0x00000008 */
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/* A2B_CMD_0 */
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#define MBOX_A2B_CMD_0_OFFSET (0x8U)
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#define MBOX_A2B_CMD_0_COMMAND_SHIFT (0U)
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#define MBOX_A2B_CMD_0_COMMAND_MASK (0xFFFFFFFFU << MBOX_A2B_CMD_0_COMMAND_SHIFT) /* 0xFFFFFFFF */
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/* A2B_DAT_0 */
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#define MBOX_A2B_DAT_0_OFFSET (0xCU)
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#define MBOX_A2B_DAT_0_DATA_SHIFT (0U)
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#define MBOX_A2B_DAT_0_DATA_MASK (0xFFFFFFFFU << MBOX_A2B_DAT_0_DATA_SHIFT) /* 0xFFFFFFFF */
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/* A2B_CMD_1 */
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#define MBOX_A2B_CMD_1_OFFSET (0x10U)
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#define MBOX_A2B_CMD_1_COMMAND_SHIFT (0U)
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#define MBOX_A2B_CMD_1_COMMAND_MASK (0xFFFFFFFFU << MBOX_A2B_CMD_1_COMMAND_SHIFT) /* 0xFFFFFFFF */
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/* A2B_DAT_1 */
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#define MBOX_A2B_DAT_1_OFFSET (0x14U)
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#define MBOX_A2B_DAT_1_DATA_SHIFT (0U)
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#define MBOX_A2B_DAT_1_DATA_MASK (0xFFFFFFFFU << MBOX_A2B_DAT_1_DATA_SHIFT) /* 0xFFFFFFFF */
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/* A2B_CMD_2 */
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#define MBOX_A2B_CMD_2_OFFSET (0x18U)
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#define MBOX_A2B_CMD_2_COMMAND_SHIFT (0U)
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#define MBOX_A2B_CMD_2_COMMAND_MASK (0xFFFFFFFFU << MBOX_A2B_CMD_2_COMMAND_SHIFT) /* 0xFFFFFFFF */
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/* A2B_DAT_2 */
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#define MBOX_A2B_DAT_2_OFFSET (0x1CU)
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#define MBOX_A2B_DAT_2_DATA_SHIFT (0U)
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#define MBOX_A2B_DAT_2_DATA_MASK (0xFFFFFFFFU << MBOX_A2B_DAT_2_DATA_SHIFT) /* 0xFFFFFFFF */
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/* A2B_CMD_3 */
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#define MBOX_A2B_CMD_3_OFFSET (0x20U)
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#define MBOX_A2B_CMD_3_COMMAND_SHIFT (0U)
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#define MBOX_A2B_CMD_3_COMMAND_MASK (0xFFFFFFFFU << MBOX_A2B_CMD_3_COMMAND_SHIFT) /* 0xFFFFFFFF */
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/* A2B_DAT_3 */
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#define MBOX_A2B_DAT_3_OFFSET (0x24U)
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#define MBOX_A2B_DAT_3_DATA_SHIFT (0U)
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#define MBOX_A2B_DAT_3_DATA_MASK (0xFFFFFFFFU << MBOX_A2B_DAT_3_DATA_SHIFT) /* 0xFFFFFFFF */
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/* B2A_INTEN */
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#define MBOX_B2A_INTEN_OFFSET (0x28U)
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#define MBOX_B2A_INTEN_INT0_SHIFT (0U)
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#define MBOX_B2A_INTEN_INT0_MASK (0x1U << MBOX_B2A_INTEN_INT0_SHIFT) /* 0x00000001 */
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#define MBOX_B2A_INTEN_INT1_SHIFT (1U)
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#define MBOX_B2A_INTEN_INT1_MASK (0x1U << MBOX_B2A_INTEN_INT1_SHIFT) /* 0x00000002 */
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#define MBOX_B2A_INTEN_INT2_SHIFT (2U)
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#define MBOX_B2A_INTEN_INT2_MASK (0x1U << MBOX_B2A_INTEN_INT2_SHIFT) /* 0x00000004 */
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#define MBOX_B2A_INTEN_INT3_SHIFT (3U)
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#define MBOX_B2A_INTEN_INT3_MASK (0x1U << MBOX_B2A_INTEN_INT3_SHIFT) /* 0x00000008 */
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/* B2A_STATUS */
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#define MBOX_B2A_STATUS_OFFSET (0x2CU)
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#define MBOX_B2A_STATUS_INT0_SHIFT (0U)
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#define MBOX_B2A_STATUS_INT0_MASK (0x1U << MBOX_B2A_STATUS_INT0_SHIFT) /* 0x00000001 */
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#define MBOX_B2A_STATUS_INT1_SHIFT (1U)
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#define MBOX_B2A_STATUS_INT1_MASK (0x1U << MBOX_B2A_STATUS_INT1_SHIFT) /* 0x00000002 */
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#define MBOX_B2A_STATUS_INT2_SHIFT (2U)
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#define MBOX_B2A_STATUS_INT2_MASK (0x1U << MBOX_B2A_STATUS_INT2_SHIFT) /* 0x00000004 */
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#define MBOX_B2A_STATUS_INT3_SHIFT (3U)
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#define MBOX_B2A_STATUS_INT3_MASK (0x1U << MBOX_B2A_STATUS_INT3_SHIFT) /* 0x00000008 */
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/* B2A_CMD_0 */
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#define MBOX_B2A_CMD_0_OFFSET (0x30U)
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#define MBOX_B2A_CMD_0_COMMAND_SHIFT (0U)
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#define MBOX_B2A_CMD_0_COMMAND_MASK (0xFFFFFFFFU << MBOX_B2A_CMD_0_COMMAND_SHIFT) /* 0xFFFFFFFF */
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/* B2A_DAT_0 */
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#define MBOX_B2A_DAT_0_OFFSET (0x34U)
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#define MBOX_B2A_DAT_0_DATA_SHIFT (0U)
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#define MBOX_B2A_DAT_0_DATA_MASK (0xFFFFFFFFU << MBOX_B2A_DAT_0_DATA_SHIFT) /* 0xFFFFFFFF */
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/* B2A_CMD_1 */
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#define MBOX_B2A_CMD_1_OFFSET (0x38U)
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#define MBOX_B2A_CMD_1_COMMAND_SHIFT (0U)
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#define MBOX_B2A_CMD_1_COMMAND_MASK (0xFFFFFFFFU << MBOX_B2A_CMD_1_COMMAND_SHIFT) /* 0xFFFFFFFF */
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/* B2A_DAT_1 */
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#define MBOX_B2A_DAT_1_OFFSET (0x3CU)
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#define MBOX_B2A_DAT_1_DATA_SHIFT (0U)
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#define MBOX_B2A_DAT_1_DATA_MASK (0xFFFFFFFFU << MBOX_B2A_DAT_1_DATA_SHIFT) /* 0xFFFFFFFF */
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/* B2A_CMD_2 */
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#define MBOX_B2A_CMD_2_OFFSET (0x40U)
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#define MBOX_B2A_CMD_2_COMMAND_SHIFT (0U)
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#define MBOX_B2A_CMD_2_COMMAND_MASK (0xFFFFFFFFU << MBOX_B2A_CMD_2_COMMAND_SHIFT) /* 0xFFFFFFFF */
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/* B2A_DAT_2 */
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#define MBOX_B2A_DAT_2_OFFSET (0x44U)
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#define MBOX_B2A_DAT_2_DATA_SHIFT (0U)
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#define MBOX_B2A_DAT_2_DATA_MASK (0xFFFFFFFFU << MBOX_B2A_DAT_2_DATA_SHIFT) /* 0xFFFFFFFF */
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/* B2A_CMD_3 */
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#define MBOX_B2A_CMD_3_OFFSET (0x48U)
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#define MBOX_B2A_CMD_3_COMMAND_SHIFT (0U)
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#define MBOX_B2A_CMD_3_COMMAND_MASK (0xFFFFFFFFU << MBOX_B2A_CMD_3_COMMAND_SHIFT) /* 0xFFFFFFFF */
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/* B2A_DAT_3 */
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#define MBOX_B2A_DAT_3_OFFSET (0x4CU)
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#define MBOX_B2A_DAT_3_DATA_SHIFT (0U)
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#define MBOX_B2A_DAT_3_DATA_MASK (0xFFFFFFFFU << MBOX_B2A_DAT_3_DATA_SHIFT) /* 0xFFFFFFFF */
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/* ATOMIC_LOCK_00 */
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#define MBOX_ATOMIC_LOCK_00_OFFSET (0x100U)
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#define MBOX_ATOMIC_LOCK_00_ATOMIC_LOCK_00_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_00_ATOMIC_LOCK_00_MASK (0x1U << MBOX_ATOMIC_LOCK_00_ATOMIC_LOCK_00_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_01 */
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#define MBOX_ATOMIC_LOCK_01_OFFSET (0x104U)
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#define MBOX_ATOMIC_LOCK_01_ATOMIC_LOCK_01_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_01_ATOMIC_LOCK_01_MASK (0x1U << MBOX_ATOMIC_LOCK_01_ATOMIC_LOCK_01_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_02 */
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#define MBOX_ATOMIC_LOCK_02_OFFSET (0x108U)
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#define MBOX_ATOMIC_LOCK_02_ATOMIC_LOCK_02_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_02_ATOMIC_LOCK_02_MASK (0x1U << MBOX_ATOMIC_LOCK_02_ATOMIC_LOCK_02_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_03 */
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#define MBOX_ATOMIC_LOCK_03_OFFSET (0x10CU)
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#define MBOX_ATOMIC_LOCK_03_ATOMIC_LOCK_03_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_03_ATOMIC_LOCK_03_MASK (0x1U << MBOX_ATOMIC_LOCK_03_ATOMIC_LOCK_03_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_04 */
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#define MBOX_ATOMIC_LOCK_04_OFFSET (0x110U)
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#define MBOX_ATOMIC_LOCK_04_ATOMIC_LOCK_04_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_04_ATOMIC_LOCK_04_MASK (0x1U << MBOX_ATOMIC_LOCK_04_ATOMIC_LOCK_04_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_05 */
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#define MBOX_ATOMIC_LOCK_05_OFFSET (0x114U)
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#define MBOX_ATOMIC_LOCK_05_ATOMIC_LOCK_05_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_05_ATOMIC_LOCK_05_MASK (0x1U << MBOX_ATOMIC_LOCK_05_ATOMIC_LOCK_05_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_06 */
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#define MBOX_ATOMIC_LOCK_06_OFFSET (0x118U)
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#define MBOX_ATOMIC_LOCK_06_ATOMIC_LOCK_06_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_06_ATOMIC_LOCK_06_MASK (0x1U << MBOX_ATOMIC_LOCK_06_ATOMIC_LOCK_06_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_07 */
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#define MBOX_ATOMIC_LOCK_07_OFFSET (0x11CU)
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#define MBOX_ATOMIC_LOCK_07_ATOMIC_LOCK_07_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_07_ATOMIC_LOCK_07_MASK (0x1U << MBOX_ATOMIC_LOCK_07_ATOMIC_LOCK_07_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_08 */
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#define MBOX_ATOMIC_LOCK_08_OFFSET (0x120U)
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#define MBOX_ATOMIC_LOCK_08_ATOMIC_LOCK_08_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_08_ATOMIC_LOCK_08_MASK (0x1U << MBOX_ATOMIC_LOCK_08_ATOMIC_LOCK_08_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_09 */
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#define MBOX_ATOMIC_LOCK_09_OFFSET (0x124U)
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#define MBOX_ATOMIC_LOCK_09_ATOMIC_LOCK_09_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_09_ATOMIC_LOCK_09_MASK (0x1U << MBOX_ATOMIC_LOCK_09_ATOMIC_LOCK_09_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_10 */
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#define MBOX_ATOMIC_LOCK_10_OFFSET (0x128U)
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#define MBOX_ATOMIC_LOCK_10_ATOMIC_LOCK_10_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_10_ATOMIC_LOCK_10_MASK (0x1U << MBOX_ATOMIC_LOCK_10_ATOMIC_LOCK_10_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_11 */
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#define MBOX_ATOMIC_LOCK_11_OFFSET (0x12CU)
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#define MBOX_ATOMIC_LOCK_11_ATOMIC_LOCK_11_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_11_ATOMIC_LOCK_11_MASK (0x1U << MBOX_ATOMIC_LOCK_11_ATOMIC_LOCK_11_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_12 */
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#define MBOX_ATOMIC_LOCK_12_OFFSET (0x130U)
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#define MBOX_ATOMIC_LOCK_12_ATOMIC_LOCK_12_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_12_ATOMIC_LOCK_12_MASK (0x1U << MBOX_ATOMIC_LOCK_12_ATOMIC_LOCK_12_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_13 */
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#define MBOX_ATOMIC_LOCK_13_OFFSET (0x134U)
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#define MBOX_ATOMIC_LOCK_13_ATOMIC_LOCK_13_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_13_ATOMIC_LOCK_13_MASK (0x1U << MBOX_ATOMIC_LOCK_13_ATOMIC_LOCK_13_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_14 */
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#define MBOX_ATOMIC_LOCK_14_OFFSET (0x138U)
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#define MBOX_ATOMIC_LOCK_14_ATOMIC_LOCK_14_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_14_ATOMIC_LOCK_14_MASK (0x1U << MBOX_ATOMIC_LOCK_14_ATOMIC_LOCK_14_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_15 */
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#define MBOX_ATOMIC_LOCK_15_OFFSET (0x13CU)
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#define MBOX_ATOMIC_LOCK_15_ATOMIC_LOCK_15_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_15_ATOMIC_LOCK_15_MASK (0x1U << MBOX_ATOMIC_LOCK_15_ATOMIC_LOCK_15_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_16 */
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#define MBOX_ATOMIC_LOCK_16_OFFSET (0x140U)
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#define MBOX_ATOMIC_LOCK_16_ATOMIC_LOCK_16_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_16_ATOMIC_LOCK_16_MASK (0x1U << MBOX_ATOMIC_LOCK_16_ATOMIC_LOCK_16_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_17 */
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#define MBOX_ATOMIC_LOCK_17_OFFSET (0x144U)
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#define MBOX_ATOMIC_LOCK_17_ATOMIC_LOCK_17_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_17_ATOMIC_LOCK_17_MASK (0x1U << MBOX_ATOMIC_LOCK_17_ATOMIC_LOCK_17_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_18 */
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#define MBOX_ATOMIC_LOCK_18_OFFSET (0x148U)
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#define MBOX_ATOMIC_LOCK_18_ATOMIC_LOCK_18_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_18_ATOMIC_LOCK_18_MASK (0x1U << MBOX_ATOMIC_LOCK_18_ATOMIC_LOCK_18_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_19 */
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#define MBOX_ATOMIC_LOCK_19_OFFSET (0x14CU)
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#define MBOX_ATOMIC_LOCK_19_ATOMIC_LOCK_19_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_19_ATOMIC_LOCK_19_MASK (0x1U << MBOX_ATOMIC_LOCK_19_ATOMIC_LOCK_19_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_20 */
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#define MBOX_ATOMIC_LOCK_20_OFFSET (0x150U)
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#define MBOX_ATOMIC_LOCK_20_ATOMIC_LOCK_20_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_20_ATOMIC_LOCK_20_MASK (0x1U << MBOX_ATOMIC_LOCK_20_ATOMIC_LOCK_20_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_21 */
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#define MBOX_ATOMIC_LOCK_21_OFFSET (0x154U)
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#define MBOX_ATOMIC_LOCK_21_ATOMIC_LOCK_21_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_21_ATOMIC_LOCK_21_MASK (0x1U << MBOX_ATOMIC_LOCK_21_ATOMIC_LOCK_21_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_22 */
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#define MBOX_ATOMIC_LOCK_22_OFFSET (0x158U)
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#define MBOX_ATOMIC_LOCK_22_ATOMIC_LOCK_22_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_22_ATOMIC_LOCK_22_MASK (0x1U << MBOX_ATOMIC_LOCK_22_ATOMIC_LOCK_22_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_23 */
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#define MBOX_ATOMIC_LOCK_23_OFFSET (0x15CU)
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#define MBOX_ATOMIC_LOCK_23_ATOMIC_LOCK_23_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_23_ATOMIC_LOCK_23_MASK (0x1U << MBOX_ATOMIC_LOCK_23_ATOMIC_LOCK_23_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_24 */
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#define MBOX_ATOMIC_LOCK_24_OFFSET (0x160U)
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#define MBOX_ATOMIC_LOCK_24_ATOMIC_LOCK_24_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_24_ATOMIC_LOCK_24_MASK (0x1U << MBOX_ATOMIC_LOCK_24_ATOMIC_LOCK_24_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_25 */
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#define MBOX_ATOMIC_LOCK_25_OFFSET (0x164U)
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#define MBOX_ATOMIC_LOCK_25_ATOMIC_LOCK_25_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_25_ATOMIC_LOCK_25_MASK (0x1U << MBOX_ATOMIC_LOCK_25_ATOMIC_LOCK_25_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_26 */
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#define MBOX_ATOMIC_LOCK_26_OFFSET (0x168U)
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#define MBOX_ATOMIC_LOCK_26_ATOMIC_LOCK_26_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_26_ATOMIC_LOCK_26_MASK (0x1U << MBOX_ATOMIC_LOCK_26_ATOMIC_LOCK_26_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_27 */
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#define MBOX_ATOMIC_LOCK_27_OFFSET (0x16CU)
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#define MBOX_ATOMIC_LOCK_27_ATOMIC_LOCK_27_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_27_ATOMIC_LOCK_27_MASK (0x1U << MBOX_ATOMIC_LOCK_27_ATOMIC_LOCK_27_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_28 */
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#define MBOX_ATOMIC_LOCK_28_OFFSET (0x170U)
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#define MBOX_ATOMIC_LOCK_28_ATOMIC_LOCK_28_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_28_ATOMIC_LOCK_28_MASK (0x1U << MBOX_ATOMIC_LOCK_28_ATOMIC_LOCK_28_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_29 */
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#define MBOX_ATOMIC_LOCK_29_OFFSET (0x174U)
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#define MBOX_ATOMIC_LOCK_29_ATOMIC_LOCK_29_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_29_ATOMIC_LOCK_29_MASK (0x1U << MBOX_ATOMIC_LOCK_29_ATOMIC_LOCK_29_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_30 */
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#define MBOX_ATOMIC_LOCK_30_OFFSET (0x178U)
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#define MBOX_ATOMIC_LOCK_30_ATOMIC_LOCK_30_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_30_ATOMIC_LOCK_30_MASK (0x1U << MBOX_ATOMIC_LOCK_30_ATOMIC_LOCK_30_SHIFT) /* 0x00000001 */
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/* ATOMIC_LOCK_31 */
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#define MBOX_ATOMIC_LOCK_31_OFFSET (0x17CU)
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#define MBOX_ATOMIC_LOCK_31_ATOMIC_LOCK_31_SHIFT (0U)
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#define MBOX_ATOMIC_LOCK_31_ATOMIC_LOCK_31_MASK (0x1U << MBOX_ATOMIC_LOCK_31_ATOMIC_LOCK_31_SHIFT) /* 0x00000001 */
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/********Name=SOFTRST_CON00,Offset=0x400********/
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#define SRST_NCORERESET0 0U
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#define SRST_NCORERESET1 1U
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#define SRST_NCORERESET2 2U
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#define SRST_NCORERESET3 3U
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#define SRST_NCPUPORESET0 4U
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#define SRST_NCPUPORESET1 5U
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#define SRST_NCPUPORESET2 6U
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#define SRST_NCPUPORESET3 7U
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#define SRST_NSRESET 8U
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#define SRST_NSPORESET 9U
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#define SRST_NATRESET 10U
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#define SRST_NGICRESET 11U
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#define SRST_NPRESET 12U
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#define SRST_NPERIPHRESET 13U
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/********Name=SOFTRST_CON01,Offset=0x404********/
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#define SRST_A_CORE_NIU2DDR 16U
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#define SRST_A_CORE_NIU2BUS 17U
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#define SRST_P_DBG_NIU 18U
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#define SRST_P_DBG 19U
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#define SRST_P_DBG_DAPLITE 20U
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#define SRST_DAP 21U
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#define SRST_A_ADB400_CORE2GIC 22U
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#define SRST_A_ADB400_GIC2CORE 23U
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#define SRST_P_CORE_GRF 24U
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#define SRST_P_CORE_PVTM 25U
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#define SRST_CORE_PVTM 26U
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#define SRST_CORE_PVTPLL 27U
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/********Name=SOFTRST_CON02,Offset=0x408********/
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#define SRST_GPU 32U
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#define SRST_A_GPU_NIU 33U
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#define SRST_P_GPU_NIU 34U
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#define SRST_P_GPU_PVTM 35U
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#define SRST_GPU_PVTM 36U
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#define SRST_GPU_PVTPLL 37U
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#define SRST_A_NPU_NIU 40U
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#define SRST_H_NPU_NIU 41U
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#define SRST_P_NPU_NIU 42U
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#define SRST_A_RKNN 43U
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#define SRST_H_RKNN 44U
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#define SRST_P_NPU_PVTM 45U
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#define SRST_NPU_PVTM 46U
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#define SRST_NPU_PVTPLL 47U
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/********Name=SOFTRST_CON03,Offset=0x40C********/
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#define SRST_A_MSCH 51U
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#define SRST_HWFFC_CTRL 52U
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#define SRST_DDR_ALWAYSON 53U
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#define SRST_A_DDRSPLIT 54U
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#define SRST_DDRDFI_CTL 55U
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#define SRST_A_DMA2DDR 57U
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/********Name=SOFTRST_CON04,Offset=0x410********/
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#define SRST_A_PERIMID_NIU 64U
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#define SRST_H_PERIMID_NIU 65U
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#define SRST_A_GIC_AUDIO_NIU 66U
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#define SRST_H_GIC_AUDIO_NIU 67U
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#define SRST_A_GIC600 68U
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#define SRST_A_GIC600_DEBUG 69U
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#define SRST_A_GICADB_CORE2GIC 70U
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#define SRST_A_GICADB_GIC2CORE 71U
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#define SRST_A_SPINLOCK 72U
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#define SRST_H_SDMMC_BUFFER 73U
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#define SRST_D_SDMMC_BUFFER 74U
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#define SRST_H_I2S0_8CH 75U
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#define SRST_H_I2S1_8CH 76U
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#define SRST_H_I2S2_2CH 77U
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#define SRST_H_I2S3_2CH 78U
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/********Name=SOFTRST_CON05,Offset=0x414********/
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#define SRST_M_I2S0_8CH_TX 80U
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#define SRST_M_I2S0_8CH_RX 81U
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#define SRST_M_I2S1_8CH_TX 82U
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#define SRST_M_I2S1_8CH_RX 83U
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#define SRST_M_I2S2_2CH 84U
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#define SRST_M_I2S3_2CH_TX 85U
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#define SRST_M_I2S3_2CH_RX 86U
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#define SRST_H_PDM 87U
|
#define SRST_M_PDM 88U
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#define SRST_H_VAD 89U
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#define SRST_H_SPDIF_8CH 90U
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#define SRST_M_SPDIF_8CH 91U
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#define SRST_H_AUDPWM 92U
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#define SRST_S_AUDPWM 93U
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#define SRST_H_ACDCDIG 94U
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#define SRST_ACDCDIG 95U
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/********Name=SOFTRST_CON06,Offset=0x418********/
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#define SRST_A_SECURE_FLASH_NIU 96U
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#define SRST_H_SECURE_FLASH_NIU 97U
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#define SRST_A_CRYPTO_NS 103U
|
#define SRST_H_CRYPTO_NS 104U
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#define SRST_CRYPTO_NS_CORE 105U
|
#define SRST_CRYPTO_NS_PKA 106U
|
#define SRST_CRYPTO_NS_RNG 107U
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#define SRST_H_TRNG_NS 108U
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#define SRST_TRNG_NS 109U
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/********Name=SOFTRST_CON07,Offset=0x41C********/
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#define SRST_H_NANDC 112U
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#define SRST_N_NANDC 113U
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#define SRST_H_SFC 114U
|
#define SRST_H_SFC_XIP 115U
|
#define SRST_S_SFC 116U
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#define SRST_A_EMMC 117U
|
#define SRST_H_EMMC 118U
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#define SRST_B_EMMC 119U
|
#define SRST_C_EMMC 120U
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#define SRST_T_EMMC 121U
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/********Name=SOFTRST_CON08,Offset=0x420********/
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#define SRST_A_PIPE_NIU 128U
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#define SRST_P_PIPE_NIU 130U
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#define SRST_P_PIPE_GRF 133U
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#define SRST_A_SATA0 134U
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#define SRST_SATA0_PIPE 135U
|
#define SRST_SATA0_PMALIVE 136U
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#define SRST_SATA0_RXOOB 137U
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#define SRST_A_SATA1 138U
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#define SRST_SATA1_PIPE 139U
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#define SRST_SATA1_PMALIVE 140U
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#define SRST_SATA1_RXOOB 141U
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/********Name=SOFTRST_CON09,Offset=0x424********/
|
#define SRST_A_SATA2 144U
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#define SRST_SATA2_PIPE 145U
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#define SRST_SATA2_PMALIVE 146U
|
#define SRST_SATA2_RXOOB 147U
|
#define SRST_USB3OTG0 148U
|
#define SRST_USB3OTG1 149U
|
#define SRST_XPCS 150U
|
#define SRST_XPCS_TX_DIV10 151U
|
#define SRST_XPCS_RX_DIV10 152U
|
#define SRST_XPCS_XGXS_RX 153U
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/********Name=SOFTRST_CON10,Offset=0x428********/
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#define SRST_P_PCIE20 160U
|
#define SRST_PCIE20_POWERUP 161U
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#define SRST_MSTR_ARESET_PCIE20 162U
|
#define SRST_SLV_ARESET_PCIE20 163U
|
#define SRST_DBI_ARESET_PCIE20 164U
|
#define SRST_BRESET_PCIE20 165U
|
#define SRST_PERST_PCIE20 166U
|
#define SRST_CORE_RST_PCIE20 167U
|
#define SRST_NSTICKY_RST_PCIE20 168U
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#define SRST_STICKY_RST_PCIE20 169U
|
#define SRST_PWR_RST_PCIE20 170U
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/********Name=SOFTRST_CON11,Offset=0x42C********/
|
#define SRST_P_PCIE30X1 176U
|
#define SRST_PCIE30X1_POWERUP 177U
|
#define SRST_MSTR_ARESET_PCIE30X1 178U
|
#define SRST_SLV_ARESET_PCIE30X1 179U
|
#define SRST_DBI_ARESET_PCIE30X1 180U
|
#define SRST_BRESET_PCIE30X1 181U
|
#define SRST_PERST_PCIE30X1 182U
|
#define SRST_CORE_RST_PCIE30X1 183U
|
#define SRST_NSTICKY_RST_PCIE30X1 184U
|
#define SRST_STICKY_RST_PCIE30X1 185U
|
#define SRST_PWR_RST_PCIE30X1 186U
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/********Name=SOFTRST_CON12,Offset=0x430********/
|
#define SRST_P_PCIE30X2 192U
|
#define SRST_PCIE30X2_POWERUP 193U
|
#define SRST_MSTR_ARESET_PCIE30X2 194U
|
#define SRST_SLV_ARESET_PCIE30X2 195U
|
#define SRST_DBI_ARESET_PCIE30X2 196U
|
#define SRST_BRESET_PCIE30X2 197U
|
#define SRST_PERST_PCIE30X2 198U
|
#define SRST_CORE_RST_PCIE30X2 199U
|
#define SRST_NSTICKY_RST_PCIE30X2 200U
|
#define SRST_STICKY_RST_PCIE30X2 201U
|
#define SRST_PWR_RST_PCIE30X2 202U
|
/********Name=SOFTRST_CON13,Offset=0x434********/
|
#define SRST_A_PHP_NIU 208U
|
#define SRST_H_PHP_NIU 209U
|
#define SRST_P_PHP_NIU 210U
|
#define SRST_H_SDMMC0 211U
|
#define SRST_SDMMC0 212U
|
#define SRST_H_SDMMC1 213U
|
#define SRST_SDMMC1 214U
|
#define SRST_A_GMAC0 215U
|
#define SRST_GMAC0_TIMESTAMP 216U
|
/********Name=SOFTRST_CON14,Offset=0x438********/
|
#define SRST_A_USB_NIU 224U
|
#define SRST_H_USB_NIU 225U
|
#define SRST_P_USB_NIU 226U
|
#define SRST_P_USB_GRF 227U
|
#define SRST_H_USB2HOST0 228U
|
#define SRST_H_USB2HOST0_ARB 229U
|
#define SRST_USB2HOST0_UTMI 230U
|
#define SRST_H_USB2HOST1 231U
|
#define SRST_H_USB2HOST1_ARB 232U
|
#define SRST_USB2HOST1_UTMI 233U
|
#define SRST_H_SDMMC2 234U
|
#define SRST_SDMMC2 235U
|
#define SRST_A_GMAC1 236U
|
#define SRST_GMAC1_TIMESTAMP 237U
|
/********Name=SOFTRST_CON15,Offset=0x43C********/
|
#define SRST_A_VI_NIU 240U
|
#define SRST_H_VI_NIU 241U
|
#define SRST_P_VI_NIU 242U
|
#define SRST_A_VICAP1 247U
|
#define SRST_H_VICAP1 248U
|
#define SRST_D_VICAP1 249U
|
#define SRST_I_VICAP1 250U
|
#define SRST_P_VICAP1 251U
|
#define SRST_H_ISP 252U
|
#define SRST_ISP 253U
|
#define SRST_P_CSI2HOST1 255U
|
/********Name=SOFTRST_CON16,Offset=0x440********/
|
#define SRST_A_VO_NIU 256U
|
#define SRST_H_VO_NIU 257U
|
#define SRST_P_VO_NIU 258U
|
#define SRST_A_VOP_NIU 259U
|
#define SRST_A_VOP 260U
|
#define SRST_H_VOP 261U
|
#define SRST_D0_VOP 262U
|
#define SRST_D1_VOP 263U
|
#define SRST_D2_VOP 264U
|
#define SRST_VOP_PWM 265U
|
#define SRST_A_HDCP 266U
|
#define SRST_H_HDCP 267U
|
#define SRST_P_HDCP 268U
|
#define SRST_P_HDMI_HOST 270U
|
#define SRST_HDMI_HOST 271U
|
/********Name=SOFTRST_CON17,Offset=0x444********/
|
#define SRST_P_DSITX_0 272U
|
#define SRST_P_DSITX_1 273U
|
#define SRST_P_EDP_CTRL 274U
|
#define SRST_EDP_24M 275U
|
#define SRST_A_VPU_NIU 280U
|
#define SRST_H_VPU_NIU 281U
|
#define SRST_A_VPU 282U
|
#define SRST_H_VPU 283U
|
#define SRST_H_EINK 286U
|
#define SRST_P_EINK 287U
|
/********Name=SOFTRST_CON18,Offset=0x448********/
|
#define SRST_A_RGA_NIU 288U
|
#define SRST_H_RGA_NIU 289U
|
#define SRST_P_RGA_NIU 290U
|
#define SRST_A_RGA 292U
|
#define SRST_H_RGA 293U
|
#define SRST_RGA_CORE 294U
|
#define SRST_A_IEP 295U
|
#define SRST_H_IEP 296U
|
#define SRST_IEP_CORE 297U
|
#define SRST_H_EBC 298U
|
#define SRST_D_EBC 299U
|
#define SRST_A_JDEC 300U
|
#define SRST_H_JDEC 301U
|
#define SRST_A_JENC 302U
|
#define SRST_H_JENC 303U
|
/********Name=SOFTRST_CON19,Offset=0x44C********/
|
#define SRST_A_VENC_NIU 304U
|
#define SRST_H_VENC_NIU 305U
|
#define SRST_A_RKVENC 307U
|
#define SRST_H_RKVENC 308U
|
#define SRST_RKVENC_CORE 309U
|
/********Name=SOFTRST_CON20,Offset=0x450********/
|
#define SRST_A_RKVDEC_NIU 320U
|
#define SRST_H_RKVDEC_NIU 321U
|
#define SRST_A_RKVDEC 322U
|
#define SRST_H_RKVDEC 323U
|
#define SRST_RKVDEC_CA 324U
|
#define SRST_RKVDEC_CORE 325U
|
#define SRST_RKVDEC_HEVC_CA 326U
|
/********Name=SOFTRST_CON21,Offset=0x454********/
|
#define SRST_A_BUS_NIU 336U
|
#define SRST_P_BUS_NIU 338U
|
#define SRST_P_CAN0 340U
|
#define SRST_CAN0 341U
|
#define SRST_P_CAN1 342U
|
#define SRST_CAN1 343U
|
#define SRST_P_CAN2 344U
|
#define SRST_CAN2 345U
|
#define SRST_P_GPIO1 346U
|
#define SRST_DB_GPIO1 347U
|
#define SRST_P_GPIO2 348U
|
#define SRST_DB_GPIO2 349U
|
#define SRST_P_GPIO3 350U
|
#define SRST_DB_GPIO3 351U
|
/********Name=SOFTRST_CON22,Offset=0x458********/
|
#define SRST_P_GPIO4 352U
|
#define SRST_DB_GPIO4 353U
|
#define SRST_P_I2C1 354U
|
#define SRST_I2C1 355U
|
#define SRST_P_I2C2 356U
|
#define SRST_I2C2 357U
|
#define SRST_P_I2C3 358U
|
#define SRST_I2C3 359U
|
#define SRST_P_I2C4 360U
|
#define SRST_I2C4 361U
|
#define SRST_P_I2C5 362U
|
#define SRST_I2C5 363U
|
#define SRST_P_OTPC_NS 364U
|
#define SRST_OTPC_NS_SBPI 365U
|
#define SRST_OTPC_NS_USR 366U
|
/********Name=SOFTRST_CON23,Offset=0x45C********/
|
#define SRST_P_PWM1 368U
|
#define SRST_PWM1 369U
|
#define SRST_P_PWM2 370U
|
#define SRST_PWM2 371U
|
#define SRST_P_PWM3 372U
|
#define SRST_PWM3 373U
|
#define SRST_P_SPI0 374U
|
#define SRST_SPI0 375U
|
#define SRST_P_SPI1 376U
|
#define SRST_SPI1 377U
|
#define SRST_P_SPI2 378U
|
#define SRST_SPI2 379U
|
#define SRST_P_SPI3 380U
|
#define SRST_SPI3 381U
|
/********Name=SOFTRST_CON24,Offset=0x460********/
|
#define SRST_P_SARADC 384U
|
#define SRST_P_TSADC 385U
|
#define SRST_TSADC 386U
|
#define SRST_P_TIMER 387U
|
#define SRST_TIMER0 388U
|
#define SRST_TIMER1 389U
|
#define SRST_TIMER2 390U
|
#define SRST_TIMER3 391U
|
#define SRST_TIMER4 392U
|
#define SRST_TIMER5 393U
|
#define SRST_P_UART1 394U
|
#define SRST_S_UART1 395U
|
/********Name=SOFTRST_CON25,Offset=0x464********/
|
#define SRST_P_UART2 400U
|
#define SRST_S_UART2 401U
|
#define SRST_P_UART3 402U
|
#define SRST_S_UART3 403U
|
#define SRST_P_UART4 404U
|
#define SRST_S_UART4 405U
|
#define SRST_P_UART5 406U
|
#define SRST_S_UART5 407U
|
#define SRST_P_UART6 408U
|
#define SRST_S_UART6 409U
|
#define SRST_P_UART7 410U
|
#define SRST_S_UART7 411U
|
#define SRST_P_UART8 412U
|
#define SRST_S_UART8 413U
|
#define SRST_P_UART9 414U
|
#define SRST_S_UART9 415U
|
/********Name=SOFTRST_CON26,Offset=0x468********/
|
#define SRST_P_GRF 416U
|
#define SRST_P_GRF_VCCIO12 417U
|
#define SRST_P_GRF_VCCIO34 418U
|
#define SRST_P_GRF_VCCIO567 419U
|
#define SRST_P_SCR 420U
|
#define SRST_P_WDT_NS 421U
|
#define SRST_T_WDT_NS 422U
|
#define SRST_P_DFT2APB 423U
|
#define SRST_A_MCU 426U
|
#define SRST_P_INTMUX 427U
|
#define SRST_P_MAILBOX 428U
|
/********Name=SOFTRST_CON27,Offset=0x46C********/
|
#define SRST_A_TOP_HIGH_NIU 432U
|
#define SRST_A_TOP_LOW_NIU 433U
|
#define SRST_H_TOP_NIU 434U
|
#define SRST_P_TOP_NIU 435U
|
#define SRST_P_TOP_CRU 438U
|
#define SRST_P_DDRPHY 439U
|
#define SRST_DDRPHY 440U
|
#define SRST_P_MIPICSIPHY 442U
|
#define SRST_P_MIPIDSIPHY0 443U
|
#define SRST_P_MIPIDSIPHY1 444U
|
#define SRST_P_PCIE30PHY 445U
|
#define SRST_PCIE30PHY 446U
|
#define SRST_P_PCIE30PHY_GRF 447U
|
/********Name=SOFTRST_CON28,Offset=0x470********/
|
#define SRST_P_APB2ASB_CHIP_LEFT 448U
|
#define SRST_P_APB2ASB_CHIP_BOTTOM 449U
|
#define SRST_P_ASB2APB_CHIP_LEFT 450U
|
#define SRST_P_ASB2APB_CHIP_BOTTOM 451U
|
#define SRST_P_PIPEPHY0 452U
|
#define SRST_PIPEPHY0 453U
|
#define SRST_P_PIPEPHY1 454U
|
#define SRST_PIPEPHY1 455U
|
#define SRST_P_PIPEPHY2 456U
|
#define SRST_PIPEPHY2 457U
|
#define SRST_P_USB2PHY0_GRF 458U
|
#define SRST_P_USB2PHY1_GRF 459U
|
#define SRST_P_CPU_BOOST 460U
|
#define SRST_CPU_BOOST 461U
|
#define SRST_P_OTPPHY 462U
|
#define SRST_OTPPHY 463U
|
/********Name=SOFTRST_CON29,Offset=0x474********/
|
#define SRST_USB2PHY0_POR 464U
|
#define SRST_USB2PHY0_USB3OTG0 465U
|
#define SRST_USB2PHY0_USB3OTG1 466U
|
#define SRST_USB2PHY1_POR 467U
|
#define SRST_USB2PHY1_USB2HOST0 468U
|
#define SRST_USB2PHY1_USB2HOST1 469U
|
#define SRST_P_EDPPHY_GRF 470U
|
#define SRST_TSADCPHY 471U
|
#define SRST_GMAC0_DELAYLINE 472U
|
#define SRST_GMAC1_DELAYLINE 473U
|
#define SRST_OTPC_ARB 474U
|
#define SRST_P_PIPEPHY0_GRF 475U
|
#define SRST_P_PIPEPHY1_GRF 476U
|
#define SRST_P_PIPEPHY2_GRF 477U
|
/********Name=PMUSOFTRST_CON00,Offset=0x200********/
|
#define SRST_P_PDPMU_NIU 480U
|
#define SRST_P_PMUCRU 481U
|
#define SRST_P_PMUGRF 482U
|
#define SRST_P_I2C0 483U
|
#define SRST_I2C0 484U
|
#define SRST_P_UART0 485U
|
#define SRST_S_UART0 486U
|
#define SRST_P_PWM0 487U
|
#define SRST_PWM0 488U
|
#define SRST_P_GPIO0 489U
|
#define SRST_DB_GPIO0 490U
|
#define SRST_P_PMUPVTM 491U
|
#define SRST_PMUPVTM 492U
|
|
/********Name=GATE_CON00,Offset=0x300********/
|
#define CLK_CORE_GATE 0U
|
#define CLK_CORE0_GATE 1U
|
#define CLK_CORE1_GATE 2U
|
#define CLK_CORE2_GATE 3U
|
#define CLK_CORE3_GATE 4U
|
#define SCLK_CORE_SRC_GATE 5U
|
#define CLK_NPLL_CORE_GATE 6U
|
#define SCLK_CORE_GATE 7U
|
#define ATCLK_CORE_GATE 8U
|
#define GICCLK_CORE_GATE 9U
|
#define PCLK_CORE_PRE_GATE 10U
|
#define PERIPHCLK_CORE_PRE_GATE 11U
|
#define PCLK_CORE_GATE 12U
|
#define PERIPHCLK_CORE_GATE 13U
|
#define TSCLK_CORE_GATE 14U
|
#define CNTCLK_CORE_GATE 15U
|
/********Name=GATE_CON01,Offset=0x304********/
|
#define ACLK_CORE_GATE 16U
|
#define ACLK_CORE_NIU2DDR_GATE 17U
|
#define ACLK_CORE_NIU2BUS_GATE 18U
|
#define PCLK_DBG_NIU_GATE 19U
|
#define PCLK_DBG_GATE 20U
|
#define PCLK_DBG_DAPLITE_GATE 21U
|
#define ACLK_ADB400_CORE2GIC_GATE 22U
|
#define ACLK_ADB400_GIC2CORE_GATE 23U
|
#define PCLK_CORE_GRF_GATE 24U
|
#define PCLK_CORE_PVTM_GATE 25U
|
#define CLK_CORE_PVTM_GATE 26U
|
#define CLK_CORE_PVTM_CORE_GATE 27U
|
#define CLK_CORE_PVTPLL_GATE 28U
|
#define CLK_CORE_DIV2_GATE 29U
|
#define CLK_APLL_CORE_GATE 30U
|
#define CLK_JTAG_GATE 31U
|
/********Name=GATE_CON02,Offset=0x308********/
|
#define CLK_GPU_SRC_GATE 32U
|
#define PCLK_GPU_PRE_GATE 34U
|
#define ACLK_GPU_GATE 35U
|
#define ACLK_GPU_NIU_GATE 36U
|
#define PCLK_GPU_NIU_GATE 37U
|
#define PCLK_GPU_PVTM_GATE 38U
|
#define CLK_GPU_PVTM_GATE 39U
|
#define CLK_GPU_PVTM_CORE_GATE 40U
|
#define CLK_GPU_PVTPLL_GATE 41U
|
#define CLK_GPU_DIV2_GATE 42U
|
#define ACLK_GPU_PRE_GATE 43U
|
/********Name=GATE_CON03,Offset=0x30C********/
|
#define CLK_NPU_SRC_GATE 48U
|
#define CLK_NPU_NP5_GATE 49U
|
#define HCLK_NPU_PRE_GATE 50U
|
#define PCLK_NPU_PRE_GATE 51U
|
#define ACLK_NPU_NIU_GATE 52U
|
#define HCLK_NPU_NIU_GATE 53U
|
#define PCLK_NPU_NIU_GATE 54U
|
#define ACLK_RKNN_GATE 55U
|
#define HCLK_RKNN_GATE 56U
|
#define PCLK_NPU_PVTM_GATE 57U
|
#define CLK_NPU_PVTM_GATE 58U
|
#define CLK_NPU_PVTM_CORE_GATE 59U
|
#define CLK_NPU_PVTPLL_GATE 60U
|
#define CLK_NPU_DIV2_GATE 61U
|
/********Name=GATE_CON04,Offset=0x310********/
|
#define CLK_DDRPHY1X_GATE 64U
|
#define CLK_DPLL_DDR_GATE 65U
|
#define ACLK_MSCH_DIV2_GATE 66U
|
#define CLK_HWFFC_CTRL_GATE 67U
|
#define ACLK_DDRSCRAMBLE_GATE 68U
|
#define ACLK_MSCH_GATE 69U
|
#define CLK_DDR_ALWAYSON_GATE 70U
|
#define ACLK_DDRSPLIT_GATE 72U
|
#define CLK_DDRDFI_CTL_GATE 73U
|
#define ACLK_DMA2DDR_GATE 75U
|
#define CLK_DDRMON_GATE 77U
|
#define CLK24_DDRMON_GATE 79U
|
/********Name=GATE_CON05,Offset=0x314********/
|
#define ACLK_GIC_AUDIO_GATE 80U
|
#define HCLK_GIC_AUDIO_GATE 81U
|
#define ACLK_GIC_AUDIO_NIU_GATE 82U
|
#define HCLK_GIC_AUDIO_NIU_GATE 83U
|
#define ACLK_GIC600_GATE 84U
|
#define ACLK_GICADB_CORE2GIC_GATE 85U
|
#define ACLK_GICADB_GIC2CORE_GATE 86U
|
#define ACLK_SPINLOCK_GATE 87U
|
#define HCLK_SDMMC_BUFFER_GATE 88U
|
#define DCLK_SDMMC_BUFFER_GATE 89U
|
#define HCLK_I2S0_8CH_GATE 90U
|
#define HCLK_I2S1_8CH_GATE 91U
|
#define HCLK_I2S2_2CH_GATE 92U
|
#define HCLK_I2S3_2CH_GATE 93U
|
#define HCLK_PDM_GATE 94U
|
#define MCLK_PDM_GATE 95U
|
/********Name=GATE_CON06,Offset=0x318********/
|
#define CLK_I2S0_8CH_TX_SRC_GATE 96U
|
#define CLK_I2S0_8CH_TX_FRAC_GATE 97U
|
#define MCLK_I2S0_8CH_TX_GATE 98U
|
#define I2S0_MCLKOUT_TX_GATE 99U
|
#define CLK_I2S0_8CH_RX_SRC_GATE 100U
|
#define CLK_I2S0_8CH_RX_FRAC_GATE 101U
|
#define MCLK_I2S0_8CH_RX_GATE 102U
|
#define I2S0_MCLKOUT_RX_GATE 103U
|
#define CLK_I2S1_8CH_TX_SRC_GATE 104U
|
#define CLK_I2S1_8CH_TX_FRAC_GATE 105U
|
#define MCLK_I2S1_8CH_TX_GATE 106U
|
#define I2S1_MCLKOUT_TX_GATE 107U
|
#define CLK_I2S1_8CH_RX_SRC_GATE 108U
|
#define CLK_I2S1_8CH_RX_FRAC_GATE 109U
|
#define MCLK_I2S1_8CH_RX_GATE 110U
|
#define I2S1_MCLKOUT_RX_GATE 111U
|
/********Name=GATE_CON07,Offset=0x31C********/
|
#define CLK_I2S2_2CH_SRC_GATE 112U
|
#define CLK_I2S2_2CH_FRAC_GATE 113U
|
#define MCLK_I2S2_2CH_GATE 114U
|
#define I2S2_MCLKOUT_GATE 115U
|
#define CLK_I2S3_2CH_TX_SRC_GATE 116U
|
#define CLK_I2S3_2CH_TX_FRAC_GATE 117U
|
#define MCLK_I2S3_2CH_TX_GATE 118U
|
#define I2S3_MCLKOUT_TX_GATE 119U
|
#define CLK_I2S3_2CH_RX_SRC_GATE 120U
|
#define CLK_I2S3_2CH_RX_FRAC_GATE 121U
|
#define MCLK_I2S3_2CH_RX_GATE 122U
|
#define I2S3_MCLKOUT_RX_GATE 123U
|
#define HCLK_VAD_GATE 124U
|
#define HCLK_SPDIF_8CH_GATE 125U
|
#define MCLK_SPDIF_8CH_SRC_GATE 126U
|
#define MCLK_SPDIF_8CH_FRAC_GATE 127U
|
/********Name=GATE_CON08,Offset=0x320********/
|
#define HCLK_AUDPWM_GATE 128U
|
#define SCLK_AUDPWM_SRC_GATE 129U
|
#define SCLK_AUDPWM_FRAC_GATE 130U
|
#define HCLK_ACDCDIG_GATE 131U
|
#define CLK_ACDCDIG_I2C_GATE 132U
|
#define CLK_ACDCDIG_DAC_GATE 133U
|
#define CLK_ACDCDIG_ADC_GATE 134U
|
#define ACLK_SECURE_FLASH_GATE 135U
|
#define HCLK_SECURE_FLASH_GATE 136U
|
#define ACLK_SECURE_FLASH_NIU_GATE 137U
|
#define HCLK_SECURE_FLASH_NIU_GATE 138U
|
#define ACLK_CRYPTO_NS_GATE 139U
|
#define HCLK_CRYPTO_NS_GATE 140U
|
#define CLK_CRYPTO_NS_CORE_GATE 141U
|
#define CLK_CRYPTO_NS_PKA_GATE 142U
|
#define CLK_CRYPTO_NS_RNG_GATE 143U
|
/********Name=GATE_CON09,Offset=0x324********/
|
#define HCLK_NANDC_GATE 144U
|
#define NCLK_NANDC_GATE 145U
|
#define HCLK_SFC_GATE 146U
|
#define HCLK_SFC_XIP_GATE 147U
|
#define SCLK_SFC_GATE 148U
|
#define ACLK_EMMC_GATE 149U
|
#define HCLK_EMMC_GATE 150U
|
#define BCLK_EMMC_GATE 151U
|
#define CCLK_EMMC_GATE 152U
|
#define TCLK_EMMC_GATE 153U
|
#define HCLK_TRNG_NS_GATE 154U
|
#define CLK_TRNG_NS_GATE 155U
|
/********Name=GATE_CON10,Offset=0x328********/
|
#define ACLK_PIPE_GATE 160U
|
#define PCLK_PIPE_GATE 161U
|
#define ACLK_PIPE_NIU_GATE 162U
|
#define PCLK_PIPE_NIU_GATE 163U
|
#define CLK_XPCS_EEE_GATE 164U
|
#define CLK_XPCS_RX_DIV10_GATE 165U
|
#define CLK_XPCS_TX_DIV10_GATE 166U
|
#define PCLK_PIPE_GRF_GATE 167U
|
#define ACLK_USB3OTG0_GATE 168U
|
#define CLK_USB3OTG0_REF_GATE 169U
|
#define CLK_USB3OTG0_SUSPEND_GATE 170U
|
#define CLK_USB3OTG0_PIPE_GATE 171U
|
#define ACLK_USB3OTG1_GATE 172U
|
#define CLK_USB3OTG1_REF_GATE 173U
|
#define CLK_USB3OTG1_SUSPEND_GATE 174U
|
#define CLK_USB3OTG1_PIPE_GATE 175U
|
/********Name=GATE_CON11,Offset=0x32C********/
|
#define ACLK_SATA0_GATE 176U
|
#define CLK_SATA0_PMALIVE_GATE 177U
|
#define CLK_SATA0_RXOOB_GATE 178U
|
#define CLK_SATA0_PIPE_GATE 179U
|
#define ACLK_SATA1_GATE 180U
|
#define CLK_SATA1_PMALIVE_GATE 181U
|
#define CLK_SATA1_RXOOB_GATE 182U
|
#define CLK_SATA1_PIPE_GATE 183U
|
#define ACLK_SATA2_GATE 184U
|
#define CLK_SATA2_PMALIVE_GATE 185U
|
#define CLK_SATA2_RXOOB_GATE 186U
|
#define CLK_SATA2_PIPE_GATE 187U
|
/********Name=GATE_CON12,Offset=0x330********/
|
#define ACLK_PCIE20_MST_GATE 192U
|
#define ACLK_PCIE20_SLV_GATE 193U
|
#define ACLK_PCIE20_DBI_GATE 194U
|
#define PCLK_PCIE20_GATE 195U
|
#define CLK_PCIE20_AUX_GATE 196U
|
#define CLK_PCIE20_PIPE_GATE 197U
|
#define ACLK_PCIE30X1_MST_GATE 200U
|
#define ACLK_PCIE30X1_SLV_GATE 201U
|
#define ACLK_PCIE30X1_DBI_GATE 202U
|
#define PCLK_PCIE30X1_GATE 203U
|
#define CLK_PCIE30X1_AUX_GATE 204U
|
#define CLK_PCIE30X1_PIPE_GATE 205U
|
/********Name=GATE_CON13,Offset=0x334********/
|
#define ACLK_PCIE30X2_MST_GATE 208U
|
#define ACLK_PCIE30X2_SLV_GATE 209U
|
#define ACLK_PCIE30X2_DBI_GATE 210U
|
#define PCLK_PCIE30X2_GATE 211U
|
#define CLK_PCIE30X2_AUX_GATE 212U
|
#define CLK_PCIE30X2_PIPE_GATE 213U
|
#define PCLK_XPCS_GATE 214U
|
#define CLK_XPCS_QSGMII_TX_GATE 215U
|
#define CLK_XPCS_QSGMII_RX_GATE 216U
|
#define CLK_XPCS_XGXS_TX_GATE 217U
|
#define CLK_XPCS_XGXS_RX_GATE 219U
|
#define CLK_XPCS_MII0_TX_GATE 220U
|
#define CLK_XPCS_MII0_RX_GATE 221U
|
#define CLK_XPCS_MII1_TX_GATE 222U
|
#define CLK_XPCS_MII1_RX_GATE 223U
|
/********Name=GATE_CON14,Offset=0x338********/
|
#define ACLK_PERIMID_GATE 224U
|
#define HCLK_PERIMID_GATE 225U
|
#define ACLK_PERIMID_NIU_GATE 226U
|
#define HCLK_PERIMID_NIU_GATE 227U
|
#define ACLK_PHP_GATE 232U
|
#define HCLK_PHP_GATE 233U
|
#define PCLK_PHP_GATE 234U
|
#define ACLK_PHP_NIU_GATE 235U
|
#define HCLK_PHP_NIU_GATE 236U
|
#define PCLK_PHP_NIU_GATE 237U
|
/********Name=GATE_CON15,Offset=0x33C********/
|
#define HCLK_SDMMC0_GATE 240U
|
#define CLK_SDMMC0_GATE 241U
|
#define HCLK_SDMMC1_GATE 242U
|
#define CLK_SDMMC1_GATE 243U
|
#define CLK_GMAC0_PTP_REF_GATE 244U
|
#define ACLK_GMAC0_GATE 245U
|
#define PCLK_GMAC0_GATE 246U
|
#define CLK_MAC0_2TOP_GATE 247U
|
#define CLK_MAC0_OUT_GATE 248U
|
#define CLK_MAC0_REFOUT_GATE 252U
|
/********Name=GATE_CON16,Offset=0x340********/
|
#define ACLK_USB_GATE 256U
|
#define HCLK_USB_GATE 257U
|
#define PCLK_USB_GATE 258U
|
#define ACLK_USB_NIU_GATE 259U
|
#define HCLK_USB_NIU_GATE 260U
|
#define PCLK_USB_NIU_GATE 261U
|
#define PCLK_USB_GRF_GATE 262U
|
#define HCLK_USB2HOST0_GATE 268U
|
#define HCLK_USB2HOST0_ARB_GATE 269U
|
#define HCLK_USB2HOST1_GATE 270U
|
#define HCLK_USB2HOST1_ARB_GATE 271U
|
/********Name=GATE_CON17,Offset=0x344********/
|
#define HCLK_SDMMC2_GATE 272U
|
#define CLK_SDMMC2_GATE 273U
|
#define CLK_GMAC1_PTP_REF_GATE 274U
|
#define ACLK_GMAC1_GATE 275U
|
#define PCLK_GMAC1_GATE 276U
|
#define CLK_MAC1_2TOP_GATE 277U
|
#define CLK_MAC1_OUT_GATE 278U
|
#define CLK_MAC1_REFOUT_GATE 282U
|
/********Name=GATE_CON18,Offset=0x348********/
|
#define ACLK_VI_GATE 288U
|
#define HCLK_VI_GATE 289U
|
#define PCLK_VI_GATE 290U
|
#define ACLK_VI_NIU_GATE 291U
|
#define HCLK_VI_NIU_GATE 292U
|
#define PCLK_VI_NIU_GATE 293U
|
#define ACLK_VICAP1_GATE 297U
|
#define HCLK_VICAP1_GATE 298U
|
#define DCLK_VICAP1_GATE 299U
|
/********Name=GATE_CON19,Offset=0x34C********/
|
#define ACLK_ISP_GATE 304U
|
#define HCLK_ISP_GATE 305U
|
#define CLK_ISP_GATE 306U
|
#define PCLK_CSI2HOST1_GATE 308U
|
#define CLK_CIF_OUT_GATE 312U
|
#define CLK_CAM0_OUT_GATE 313U
|
#define CLK_CAM1_OUT_GATE 314U
|
/********Name=GATE_CON20,Offset=0x350********/
|
#define HCLK_VO_GATE 321U
|
#define PCLK_VO_GATE 322U
|
#define ACLK_VO_NIU_GATE 323U
|
#define HCLK_VO_NIU_GATE 324U
|
#define PCLK_VO_NIU_GATE 325U
|
#define ACLK_VOP_PRE_GATE 326U
|
#define ACLK_VOP_NIU_GATE 327U
|
#define ACLK_VOP_GATE 328U
|
#define HCLK_VOP_GATE 329U
|
#define DCLK0_VOP_GATE 330U
|
#define DCLK1_VOP_GATE 331U
|
#define DCLK2_VOP_GATE 332U
|
#define CLK_VOP_PWM_GATE 333U
|
/********Name=GATE_CON21,Offset=0x354********/
|
#define ACLK_HDCP_GATE 336U
|
#define HCLK_HDCP_GATE 337U
|
#define PCLK_HDCP_GATE 338U
|
#define PCLK_HDMI_HOST_GATE 339U
|
#define CLK_HDMI_SFR_GATE 340U
|
#define CLK_HDMI_CEC_GATE 341U
|
#define PCLK_DSITX_0_GATE 342U
|
#define PCLK_DSITX_1_GATE 343U
|
#define PCLK_EDP_CTRL_GATE 344U
|
#define CLK_EDP_200M_GATE 345U
|
/********Name=GATE_CON22,Offset=0x358********/
|
#define ACLK_VPU_PRE_GATE 352U
|
#define HCLK_VPU_PRE_GATE 353U
|
#define ACLK_VPU_NIU_GATE 354U
|
#define HCLK_VPU_NIU_GATE 355U
|
#define ACLK_VPU_GATE 356U
|
#define HCLK_VPU_GATE 357U
|
#define PCLK_RGA_PRE_GATE 364U
|
#define PCLK_RGA_NIU_GATE 365U
|
#define PCLK_EINK_GATE 366U
|
#define HCLK_EINK_GATE 367U
|
/********Name=GATE_CON23,Offset=0x35C********/
|
#define ACLK_RGA_PRE_GATE 368U
|
#define HCLK_RGA_PRE_GATE 369U
|
#define ACLK_RGA_NIU_GATE 370U
|
#define HCLK_RGA_NIU_GATE 371U
|
#define ACLK_RGA_GATE 372U
|
#define HCLK_RGA_GATE 373U
|
#define CLK_RGA_CORE_GATE 374U
|
#define ACLK_IEP_GATE 375U
|
#define HCLK_IEP_GATE 376U
|
#define CLK_IEP_CORE_GATE 377U
|
#define HCLK_EBC_GATE 378U
|
#define DCLK_EBC_GATE 379U
|
#define ACLK_JDEC_GATE 380U
|
#define HCLK_JDEC_GATE 381U
|
#define ACLK_JENC_GATE 382U
|
#define HCLK_JENC_GATE 383U
|
/********Name=GATE_CON24,Offset=0x360********/
|
#define ACLK_RKVENC_PRE_GATE 384U
|
#define HCLK_RKVENC_PRE_GATE 385U
|
#define ACLK_RKVENC_NIU_GATE 387U
|
#define HCLK_RKVENC_NIU_GATE 388U
|
#define ACLK_RKVENC_GATE 390U
|
#define HCLK_RKVENC_GATE 391U
|
#define CLK_RKVENC_CORE_GATE 392U
|
/********Name=GATE_CON25,Offset=0x364********/
|
#define ACLK_RKVDEC_PRE_GATE 400U
|
#define HCLK_RKVDEC_PRE_GATE 401U
|
#define ACLK_RKVDEC_NIU_GATE 402U
|
#define HCLK_RKVDEC_NIU_GATE 403U
|
#define ACLK_RKVDEC_GATE 404U
|
#define HCLK_RKVDEC_GATE 405U
|
#define CLK_RKVDEC_CA_GATE 406U
|
#define CLK_RKVDEC_CORE_GATE 407U
|
#define CLK_RKVDEC_HEVC_CA_GATE 408U
|
/********Name=GATE_CON26,Offset=0x368********/
|
#define ACLK_BUS_GATE 416U
|
#define PCLK_BUS_GATE 417U
|
#define ACLK_BUS_NIU_GATE 418U
|
#define PCLK_BUS_NIU_GATE 419U
|
#define PCLK_TSADC_GATE 420U
|
#define CLK_TSADC_TSEN_GATE 421U
|
#define CLK_TSADC_GATE 422U
|
#define PCLK_SARADC_GATE 423U
|
#define CLK_SARADC_GATE 424U
|
#define PCLK_OTPC_NS_GATE 425U
|
#define CLK_OTPC_NS_SBPI_GATE 426U
|
#define CLK_OTPC_NS_USR_GATE 427U
|
#define PCLK_SCR_GATE 428U
|
#define PCLK_WDT_NS_GATE 429U
|
#define TCLK_WDT_NS_GATE 430U
|
/********Name=GATE_CON27,Offset=0x36C********/
|
#define PCLK_GRF_GATE 432U
|
#define PCLK_GRF_VCCIO12_GATE 433U
|
#define PCLK_GRF_VCCIO34_GATE 434U
|
#define PCLK_GRF_VCCIO567_GATE 435U
|
#define PCLK_DFT2APB_GATE 436U
|
#define PCLK_CAN0_GATE 437U
|
#define CLK_CAN0_GATE 438U
|
#define PCLK_CAN1_GATE 439U
|
#define CLK_CAN1_GATE 440U
|
#define PCLK_CAN2_GATE 441U
|
#define CLK_CAN2_GATE 442U
|
#define PCLK_UART1_GATE 444U
|
#define CLK_UART1_GATE 445U
|
#define CLK_UART1_FRAC_GATE 446U
|
#define SCLK_UART1_GATE 447U
|
/********Name=GATE_CON28,Offset=0x370********/
|
#define PCLK_UART2_GATE 448U
|
#define CLK_UART2_GATE 449U
|
#define CLK_UART2_FRAC_GATE 450U
|
#define SCLK_UART2_GATE 451U
|
#define PCLK_UART3_GATE 452U
|
#define CLK_UART3_GATE 453U
|
#define CLK_UART3_FRAC_GATE 454U
|
#define SCLK_UART3_GATE 455U
|
#define PCLK_UART4_GATE 456U
|
#define CLK_UART4_GATE 457U
|
#define CLK_UART4_FRAC_GATE 458U
|
#define SCLK_UART4_GATE 459U
|
#define PCLK_UART5_GATE 460U
|
#define CLK_UART5_GATE 461U
|
#define CLK_UART5_FRAC_GATE 462U
|
#define SCLK_UART5_GATE 463U
|
/********Name=GATE_CON29,Offset=0x374********/
|
#define PCLK_UART6_GATE 464U
|
#define CLK_UART6_GATE 465U
|
#define CLK_UART6_FRAC_GATE 466U
|
#define SCLK_UART6_GATE 467U
|
#define PCLK_UART7_GATE 468U
|
#define CLK_UART7_GATE 469U
|
#define CLK_UART7_FRAC_GATE 470U
|
#define SCLK_UART7_GATE 471U
|
#define PCLK_UART8_GATE 472U
|
#define CLK_UART8_GATE 473U
|
#define CLK_UART8_FRAC_GATE 474U
|
#define SCLK_UART8_GATE 475U
|
#define PCLK_UART9_GATE 476U
|
#define CLK_UART9_GATE 477U
|
#define CLK_UART9_FRAC_GATE 478U
|
#define SCLK_UART9_GATE 479U
|
/********Name=GATE_CON30,Offset=0x378********/
|
#define PCLK_I2C1_GATE 480U
|
#define CLK_I2C1_GATE 481U
|
#define PCLK_I2C2_GATE 482U
|
#define CLK_I2C2_GATE 483U
|
#define PCLK_I2C3_GATE 484U
|
#define CLK_I2C3_GATE 485U
|
#define PCLK_I2C4_GATE 486U
|
#define CLK_I2C4_GATE 487U
|
#define PCLK_I2C5_GATE 488U
|
#define CLK_I2C5_GATE 489U
|
#define PCLK_SPI0_GATE 490U
|
#define CLK_SPI0_GATE 491U
|
#define PCLK_SPI1_GATE 492U
|
#define CLK_SPI1_GATE 493U
|
#define PCLK_SPI2_GATE 494U
|
#define CLK_SPI2_GATE 495U
|
/********Name=GATE_CON31,Offset=0x37C********/
|
#define PCLK_SPI3_GATE 496U
|
#define CLK_SPI3_GATE 497U
|
#define PCLK_GPIO1_GATE 498U
|
#define DBCLK_GPIO1_GATE 499U
|
#define PCLK_GPIO2_GATE 500U
|
#define DBCLK_GPIO2_GATE 501U
|
#define PCLK_GPIO3_GATE 502U
|
#define DBCLK_GPIO3_GATE 503U
|
#define PCLK_GPIO4_GATE 504U
|
#define DBCLK_GPIO4_GATE 505U
|
#define PCLK_PWM1_GATE 506U
|
#define CLK_PWM1_GATE 507U
|
#define CLK_PWM1_CAPTURE_GATE 508U
|
#define PCLK_PWM2_GATE 509U
|
#define CLK_PWM2_GATE 510U
|
#define CLK_PWM2_CAPTURE_GATE 511U
|
/********Name=GATE_CON32,Offset=0x380********/
|
#define PCLK_PWM3_GATE 512U
|
#define CLK_PWM3_GATE 513U
|
#define CLK_PWM3_CAPTURE_GATE 514U
|
#define PCLK_TIMER_GATE 515U
|
#define CLK_TIMER0_GATE 516U
|
#define CLK_TIMER1_GATE 517U
|
#define CLK_TIMER2_GATE 518U
|
#define CLK_TIMER3_GATE 519U
|
#define CLK_TIMER4_GATE 520U
|
#define CLK_TIMER5_GATE 521U
|
#define CLK_I2C_GATE 522U
|
#define DBCLK_GPIO_GATE 523U
|
#define CLK_TIMER_GATE 524U
|
#define ACLK_MCU_GATE 525U
|
#define PCLK_INTMUX_GATE 526U
|
#define PCLK_MAILBOX_GATE 527U
|
/********Name=GATE_CON33,Offset=0x384********/
|
#define ACLK_TOP_HIGH_GATE 528U
|
#define ACLK_TOP_LOW_GATE 529U
|
#define HCLK_TOP_GATE 530U
|
#define PCLK_TOP_GATE 531U
|
#define ACLK_TOP_HIGH_NIU_GATE 532U
|
#define ACLK_TOP_LOW_NIU_GATE 533U
|
#define HCLK_TOP_NIU_GATE 534U
|
#define PCLK_TOP_NIU_GATE 535U
|
#define PCLK_PCIE30PHY_GATE 536U
|
#define CLK_OTPC_ARB_GATE 537U
|
#define PCLK_TOP_CRU_GATE 540U
|
#define PCLK_MIPICSIPHY_GATE 541U
|
#define PCLK_MIPIDSIPHY0_GATE 542U
|
#define PCLK_MIPIDSIPHY1_GATE 543U
|
/********Name=GATE_CON34,Offset=0x388********/
|
#define PCLK_APB2ASB_CHIP_LEFT_GATE 544U
|
#define PCLK_APB2ASB_CHIP_BOTTOM_GATE 545U
|
#define PCLK_ASB2APB_CHIP_LEFT_GATE 546U
|
#define PCLK_ASB2APB_CHIP_BOTTOM_GATE 547U
|
#define PCLK_PIPEPHY0_GATE 548U
|
#define PCLK_PIPEPHY1_GATE 549U
|
#define PCLK_PIPEPHY2_GATE 550U
|
#define PCLK_USB2PHY0_GRF_GATE 551U
|
#define PCLK_USB2PHY1_GRF_GATE 552U
|
#define PCLK_DDRPHY_GATE 553U
|
#define CLK_DDRPHY_GATE 554U
|
#define PCLK_CPU_BOOST_GATE 555U
|
#define CLK_CPU_BOOST_GATE 556U
|
#define PCLK_OTPPHY_GATE 557U
|
#define PCLK_EDPPHY_GRF_GATE 558U
|
#define CLK_TESTOUT_GATE 559U
|
/********Name=GATE_CON35,Offset=0x38C********/
|
#define CLK_GPLL_DIV_400M_GATE 560U
|
#define CLK_GPLL_DIV_300M_GATE 561U
|
#define CLK_GPLL_DIV_200M_GATE 562U
|
#define CLK_GPLL_DIV_150M_GATE 563U
|
#define CLK_GPLL_DIV_100M_GATE 564U
|
#define CLK_GPLL_DIV_75M_GATE 565U
|
#define CLK_GPLL_DIV_20M_GATE 566U
|
#define CLK_CPLL_DIV_500M_GATE 567U
|
#define CLK_CPLL_DIV_333M_GATE 568U
|
#define CLK_CPLL_DIV_250M_GATE 569U
|
#define CLK_CPLL_DIV_125M_GATE 570U
|
#define CLK_CPLL_DIV_100M_GATE 571U
|
#define CLK_CPLL_DIV_62P5_GATE 572U
|
#define CLK_CPLL_DIV_50M_GATE 573U
|
#define CLK_CPLL_DIV_25M_GATE 574U
|
#define CLK_OSC0_DIV_750K_GATE 575U
|
/********Name=PMUGATE_CON00,Offset=0x180********/
|
#define XIN_OSC0_DIV_GATE 576U
|
#define CLK_OSC0_DIV32K_GATE 577U
|
#define PCLK_PDPMU_GATE 578U
|
#define PCLK_PDPMU_NIU_GATE 579U
|
#define PCLK_PMUCRU_GATE 580U
|
#define PCLK_PMUGRF_GATE 581U
|
#define PCLK_PMU_GATE 582U
|
#define CLK_PMU_GATE 583U
|
/********Name=PMUGATE_CON01,Offset=0x184********/
|
#define PCLK_I2C0_GATE 592U
|
#define CLK_I2C0_GATE 593U
|
#define PCLK_UART0_GATE 594U
|
#define SCLK_UART0_DIV_GATE 595U
|
#define SCLK_UART0_FRACDIV_GATE 596U
|
#define SCLK_UART0_GATE 597U
|
#define PCLK_PWM0_GATE 598U
|
#define CLK_PWM0_GATE 599U
|
#define CLK_CAPTURE_PWM0_GATE 600U
|
#define PCLK_GPIO0_GATE 601U
|
#define DBCLK_GPIO0_GATE 602U
|
#define PCLK_PMUPVTM_GATE 603U
|
#define CLK_PMUPVTM_GATE 604U
|
#define CLK_CORE_PMUPVTM_GATE 605U
|
/********Name=PMUGATE_CON02,Offset=0x188********/
|
#define CLK_REF24M_GATE 608U
|
#define XIN_OSC0_USBPHY0_GATE 609U
|
#define XIN_OSC0_USBPHY1_GATE 610U
|
#define XIN_OSC0_MIPIDSIPHY0_GATE 611U
|
#define XIN_OSC0_MIPIDSIPHY1_GATE 612U
|
#define CLK_WIFI_DIV_GATE 613U
|
#define CLK_WIFI_OSC0_GATE 614U
|
#define CLK_PCIEPHY0_DIV_GATE 615U
|
#define CLK_PCIEPHY0_OSC0_GATE 616U
|
#define CLK_PCIEPHY1_DIV_GATE 617U
|
#define CLK_PCIEPHY1_OSC0_GATE 618U
|
#define CLK_PCIEPHY2_DIV_GATE 619U
|
#define CLK_PCIEPHY2_OSC0_GATE 620U
|
#define CLK_PCIE30PHY_REF_M_GATE 621U
|
#define CLK_PCIE30PHY_REF_N_GATE 622U
|
#define XIN_OSC0_EDPPHY_GATE 623U
|
|
/********Name=CLKSEL_CON00,Offset=0x100********/
|
#define CLK_CORE0_DIV 0x05000000U
|
#define CLK_CORE1_DIV 0x05080000U
|
/********Name=CLKSEL_CON01,Offset=0x104********/
|
#define CLK_CORE2_DIV 0x05000001U
|
#define CLK_CORE3_DIV 0x05080001U
|
/********Name=CLKSEL_CON02,Offset=0x108********/
|
#define SCLK_CORE_SRC_DIV 0x04000002U
|
/********Name=CLKSEL_CON03,Offset=0x10C********/
|
#define ATCLK_CORE_DIV 0x05000003U
|
#define GICCLK_CORE_DIV 0x05080003U
|
/********Name=CLKSEL_CON04,Offset=0x110********/
|
#define PCLK_CORE_PRE_DIV 0x05000004U
|
#define PERIPHCLK_CORE_PRE_DIV 0x05080004U
|
/********Name=CLKSEL_CON05,Offset=0x114********/
|
#define ACLK_CORE_NDFT_DIV 0x05080005U
|
/********Name=CLKSEL_CON06,Offset=0x118********/
|
#define CLK_GPU_PRE_DIV 0x04000006U
|
#define ACLK_GPU_PRE_DIV 0x02080006U
|
#define PCLK_GPU_PRE_DIV 0x040C0006U
|
/********Name=CLKSEL_CON07,Offset=0x11C********/
|
#define CLK_NPU_SRC_DIV 0x04000007U
|
#define CLK_NPU_NP5_DIV 0x02040007U
|
/********Name=CLKSEL_CON08,Offset=0x120********/
|
#define HCLK_NPU_PRE_DIV 0x04000008U
|
#define PCLK_NPU_PRE_DIV 0x04040008U
|
/********Name=CLKSEL_CON09,Offset=0x124********/
|
#define CLK_DDRPHY1X_SRC_DIV 0x05000009U
|
/********Name=CLKSEL_CON10,Offset=0x128********/
|
#define CLK_MSCH_DIV 0x0200000AU
|
/********Name=CLKSEL_CON11,Offset=0x12C********/
|
#define CLK_I2S0_8CH_TX_SRC_DIV 0x0700000BU
|
/********Name=CLKSEL_CON12,Offset=0x130********/
|
#define CLK_I2S0_8CH_TX_FRAC_DIV 0x2000000CU
|
/********Name=CLKSEL_CON13,Offset=0x134********/
|
#define CLK_I2S0_8CH_RX_SRC_DIV 0x0700000DU
|
/********Name=CLKSEL_CON14,Offset=0x138********/
|
#define CLK_I2S0_8CH_RX_FRAC_DIV 0x2000000EU
|
/********Name=CLKSEL_CON15,Offset=0x13C********/
|
#define CLK_I2S1_8CH_TX_SRC_DIV 0x0700000FU
|
/********Name=CLKSEL_CON16,Offset=0x140********/
|
#define CLK_I2S1_8CH_TX_FRAC_DIV 0x20000010U
|
/********Name=CLKSEL_CON17,Offset=0x144********/
|
#define CLK_I2S1_8CH_RX_SRC_DIV 0x07000011U
|
/********Name=CLKSEL_CON18,Offset=0x148********/
|
#define CLK_I2S1_8CH_RX_FRAC_DIV 0x20000012U
|
/********Name=CLKSEL_CON19,Offset=0x14C********/
|
#define CLK_I2S2_2CH_SRC_DIV 0x07000013U
|
/********Name=CLKSEL_CON20,Offset=0x150********/
|
#define CLK_I2S2_2CH_FRAC_DIV 0x20000014U
|
/********Name=CLKSEL_CON21,Offset=0x154********/
|
#define CLK_I2S3_2CH_TX_SRC_DIV 0x07000015U
|
/********Name=CLKSEL_CON22,Offset=0x158********/
|
#define CLK_I2S3_2CH_TX_FRAC_DIV 0x20000016U
|
/********Name=CLKSEL_CON23,Offset=0x15C********/
|
#define MCLK_SPDIF_8CH_SRC_DIV 0x07000017U
|
/********Name=CLKSEL_CON24,Offset=0x160********/
|
#define MCLK_SPDIF_8CH_FRAC_DIV 0x20000018U
|
/********Name=CLKSEL_CON25,Offset=0x164********/
|
#define SCLK_AUDPWM_SRC_DIV 0x06000019U
|
/********Name=CLKSEL_CON26,Offset=0x168********/
|
#define SCLK_AUDPWM_FRAC_DIV 0x2000001AU
|
/********Name=CLKSEL_CON27,Offset=0x16C********/
|
/********Name=CLKSEL_CON28,Offset=0x170********/
|
/********Name=CLKSEL_CON29,Offset=0x174********/
|
#define PCLK_PIPE_DIV 0x0404001DU
|
/********Name=CLKSEL_CON30,Offset=0x178********/
|
#define PCLK_PHP_DIV 0x0404001EU
|
/********Name=CLKSEL_CON31,Offset=0x17C********/
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/********Name=CLKSEL_CON32,Offset=0x180********/
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#define PCLK_USB_DIV 0x04040020U
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/********Name=CLKSEL_CON33,Offset=0x184********/
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/********Name=CLKSEL_CON34,Offset=0x188********/
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#define HCLK_VI_DIV 0x04040022U
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#define PCLK_VI_DIV 0x04080022U
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/********Name=CLKSEL_CON35,Offset=0x18C********/
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#define CLK_ISP_DIV 0x05000023U
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#define CLK_CIF_OUT_DIV 0x06080023U
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/********Name=CLKSEL_CON36,Offset=0x190********/
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#define CLK_CAM0_OUT_DIV 0x06000024U
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#define CLK_CAM1_OUT_DIV 0x06080024U
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/********Name=CLKSEL_CON37,Offset=0x194********/
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#define HCLK_VO_DIV 0x04080025U
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#define PCLK_VO_DIV 0x040C0025U
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/********Name=CLKSEL_CON38,Offset=0x198********/
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#define ACLK_VOP_PRE_DIV 0x05000026U
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/********Name=CLKSEL_CON39,Offset=0x19C********/
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#define DCLK0_VOP_DIV 0x08000027U
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/********Name=CLKSEL_CON40,Offset=0x1A0********/
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#define DCLK1_VOP_DIV 0x08000028U
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/********Name=CLKSEL_CON41,Offset=0x1A4********/
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#define DCLK2_VOP_DIV 0x08000029U
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/********Name=CLKSEL_CON42,Offset=0x1A8********/
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#define ACLK_VPU_PRE_DIV 0x0500002AU
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#define HCLK_VPU_PRE_DIV 0x0408002AU
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/********Name=CLKSEL_CON43,Offset=0x1AC********/
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#define HCLK_RGA_PRE_DIV 0x0408002BU
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#define PCLK_RGA_PRE_DIV 0x040C002BU
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/********Name=CLKSEL_CON44,Offset=0x1B0********/
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#define ACLK_RKVENC_PRE_DIV 0x0500002CU
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#define HCLK_RKVENC_PRE_DIV 0x0408002CU
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/********Name=CLKSEL_CON45,Offset=0x1B4********/
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#define CLK_RKVENC_CORE_DIV 0x0500002DU
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/********Name=CLKSEL_CON47,Offset=0x1BC********/
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#define ACLK_RKVDEC_PRE_DIV 0x0500002FU
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#define HCLK_RKVDEC_PRE_DIV 0x0408002FU
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/********Name=CLKSEL_CON48,Offset=0x1C0********/
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#define CLK_RKVDEC_CA_DIV 0x05000030U
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/********Name=CLKSEL_CON49,Offset=0x1C4********/
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#define CLK_RKVDEC_HEVC_CA_DIV 0x05000031U
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#define CLK_RKVDEC_CORE_DIV 0x05080031U
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/********Name=CLKSEL_CON50,Offset=0x1C8********/
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/********Name=CLKSEL_CON51,Offset=0x1CC********/
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#define CLK_TSADC_TSEN_DIV 0x03000033U
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#define CLK_TSADC_DIV 0x07080033U
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/********Name=CLKSEL_CON52,Offset=0x1D0********/
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#define CLK_UART1_SRC_DIV 0x07000034U
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/********Name=CLKSEL_CON53,Offset=0x1D4********/
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#define CLK_UART1_FRAC_DIV 0x20000035U
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/********Name=CLKSEL_CON54,Offset=0x1D8********/
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#define CLK_UART2_SRC_DIV 0x07000036U
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/********Name=CLKSEL_CON55,Offset=0x1DC********/
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#define CLK_UART2_FRAC_DIV 0x20000037U
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/********Name=CLKSEL_CON56,Offset=0x1E0********/
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#define CLK_UART3_SRC_DIV 0x07000038U
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/********Name=CLKSEL_CON57,Offset=0x1E4********/
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#define CLK_UART3_FRAC_DIV 0x20000039U
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/********Name=CLKSEL_CON58,Offset=0x1E8********/
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#define CLK_UART4_SRC_DIV 0x0700003AU
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/********Name=CLKSEL_CON59,Offset=0x1EC********/
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#define CLK_UART4_FRAC_DIV 0x2000003BU
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/********Name=CLKSEL_CON60,Offset=0x1F0********/
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#define CLK_UART5_SRC_DIV 0x0700003CU
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/********Name=CLKSEL_CON61,Offset=0x1F4********/
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#define CLK_UART5_FRAC_DIV 0x2000003DU
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/********Name=CLKSEL_CON62,Offset=0x1F8********/
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#define CLK_UART6_SRC_DIV 0x0700003EU
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/********Name=CLKSEL_CON63,Offset=0x1FC********/
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#define CLK_UART6_FRAC_DIV 0x2000003FU
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/********Name=CLKSEL_CON64,Offset=0x200********/
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#define CLK_UART7_SRC_DIV 0x07000040U
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/********Name=CLKSEL_CON65,Offset=0x204********/
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#define CLK_UART7_FRAC_DIV 0x20000041U
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/********Name=CLKSEL_CON66,Offset=0x208********/
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#define CLK_UART8_SRC_DIV 0x07000042U
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/********Name=CLKSEL_CON67,Offset=0x20C********/
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#define CLK_UART8_FRAC_DIV 0x20000043U
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/********Name=CLKSEL_CON68,Offset=0x210********/
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#define CLK_UART9_SRC_DIV 0x07000044U
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/********Name=CLKSEL_CON69,Offset=0x214********/
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#define CLK_UART9_FRAC_DIV 0x20000045U
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/********Name=CLKSEL_CON70,Offset=0x218********/
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#define CLK_CAN0_DIV 0x05000046U
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#define CLK_CAN1_DIV 0x05080046U
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/********Name=CLKSEL_CON71,Offset=0x21C********/
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#define CLK_CAN2_DIV 0x05000047U
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/********Name=CLKSEL_CON72,Offset=0x220********/
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/********Name=CLKSEL_CON73,Offset=0x224********/
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/********Name=CLKSEL_CON74,Offset=0x228********/
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#define CLK_TESTOUT_DIV 0x0800004AU
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/********Name=CLKSEL_CON75,Offset=0x22C********/
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#define CLK_GPLL_DIV_400M_DIV 0x0500004BU
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#define CLK_GPLL_DIV_300M_DIV 0x0508004BU
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/********Name=CLKSEL_CON76,Offset=0x230********/
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#define CLK_GPLL_DIV_200M_DIV 0x0500004CU
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#define CLK_GPLL_DIV_150M_DIV 0x0508004CU
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/********Name=CLKSEL_CON77,Offset=0x234********/
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#define CLK_GPLL_DIV_100M_DIV 0x0500004DU
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#define CLK_GPLL_DIV_75M_DIV 0x0508004DU
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/********Name=CLKSEL_CON78,Offset=0x238********/
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#define CLK_GPLL_DIV_20M_DIV 0x0600004EU
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#define CLK_CPLL_DIV_500M_DIV 0x0508004EU
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/********Name=CLKSEL_CON79,Offset=0x23C********/
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#define CLK_CPLL_DIV_333M_DIV 0x0500004FU
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#define CLK_CPLL_DIV_250M_DIV 0x0508004FU
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/********Name=CLKSEL_CON80,Offset=0x240********/
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#define CLK_CPLL_DIV_125M_DIV 0x05000050U
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#define CLK_CPLL_DIV_62P5_DIV 0x05080050U
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/********Name=CLKSEL_CON81,Offset=0x244********/
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#define CLK_CPLL_DIV_50M_DIV 0x05000051U
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#define CLK_CPLL_DIV_25M_DIV 0x06080051U
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/********Name=CLKSEL_CON82,Offset=0x248********/
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#define CLK_CPLL_DIV_100M_DIV 0x05000052U
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#define CLK_OSC0_DIV_750K_DIV 0x06080052U
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/********Name=CLKSEL_CON83,Offset=0x24C********/
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#define CLK_I2S3_2CH_RX_SRC_DIV 0x07000053U
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/********Name=CLKSEL_CON84,Offset=0x250********/
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#define CLK_I2S3_2CH_RX_FRAC_DIV 0x20000054U
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/********Name=CLKSEL_CON00,Offset=0x100********/
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#define CLK_CORE_I_SEL 0x01060000U
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#define CLK_CORE_I_SEL_CLK_GPLL_MUX 0U
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#define CLK_CORE_NDFT_SEL 0x01070000U
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#define CLK_CORE_NDFT_SEL_CLK_APLL_CORE 0U
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#define CLK_CORE_NDFT_MUX_SEL 0x010F0000U
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#define CLK_CORE_NDFT_MUX_SEL_CORE_PVTPLL_OUT 0U
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/********Name=CLKSEL_CON01,Offset=0x104********/
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/********Name=CLKSEL_CON02,Offset=0x108********/
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#define SCLK_CORE_SRC_SEL 0x02080002U
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#define SCLK_CORE_SRC_SEL_CLK_NPLL_MUX 0U
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#define SCLK_CORE_PRE_SEL 0x010F0002U
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#define SCLK_CORE_PRE_SEL_CLK_NPLL_CORE 0U
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/********Name=CLKSEL_CON03,Offset=0x10C********/
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/********Name=CLKSEL_CON04,Offset=0x110********/
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/********Name=CLKSEL_CON05,Offset=0x114********/
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#define ACLK_CORE_NIU2BUS_SEL 0x020E0005U
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#define ACLK_CORE_NIU2BUS_SEL_XIN_OSC0_FUNC_MUX 0U
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/********Name=CLKSEL_CON06,Offset=0x118********/
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#define CLK_GPU_PRE_SEL 0x02060006U
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#define CLK_GPU_PRE_SEL_CLK_NPLL_MUX 0U
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#define CLK_GPU_PRE_MUX_SEL 0x010B0006U
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#define CLK_GPU_PRE_MUX_SEL_GPU_PVTPLL_OUT 0U
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/********Name=CLKSEL_CON07,Offset=0x11C********/
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#define CLK_NPU_SRC_SEL 0x01060007U
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#define CLK_NPU_SRC_SEL_CLK_GPLL_MUX 0U
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#define CLK_NPU_NP5_SEL 0x01070007U
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#define CLK_NPU_NP5_SEL_CLK_GPLL_MUX 0U
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#define CLK_NPU_PRE_NDFT_SEL 0x01080007U
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#define CLK_NPU_PRE_NDFT_SEL_CLK_NPU_NP5 0U
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#define CLK_NPU_PRE_MUX_SEL 0x010F0007U
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#define CLK_NPU_PRE_MUX_SEL_NPU_PVTPLL_OUT 0U
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/********Name=CLKSEL_CON08,Offset=0x120********/
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/********Name=CLKSEL_CON09,Offset=0x124********/
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#define CLK_DDRPHY1X_SRC_SEL 0x02060009U
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#define CLK_DDRPHY1X_SRC_SEL_CLK_CPLL_MUX 0U
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#define CLK_DDRPHY1X_SEL 0x010F0009U
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#define CLK_DDRPHY1X_SEL_CLK_DPLL_DDR 0U
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/********Name=CLKSEL_CON10,Offset=0x128********/
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#define ACLK_PERIMID_SEL 0x0204000AU
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#define ACLK_PERIMID_SEL_XIN_OSC0_FUNC_MUX 0U
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#define HCLK_PERIMID_SEL 0x0206000AU
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#define HCLK_PERIMID_SEL_XIN_OSC0_FUNC_MUX 0U
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#define ACLK_GIC_AUDIO_SEL 0x0208000AU
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#define ACLK_GIC_AUDIO_SEL_XIN_OSC0_FUNC_MUX 0U
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#define HCLK_GIC_AUDIO_SEL 0x020A000AU
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#define HCLK_GIC_AUDIO_SEL_XIN_OSC0_FUNC_MUX 0U
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#define DCLK_SDMMC_BUFFER_SEL 0x020C000AU
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#define DCLK_SDMMC_BUFFER_SEL_CLK_CPLL_DIV_50M 0U
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/********Name=CLKSEL_CON11,Offset=0x12C********/
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#define CLK_I2S0_8CH_TX_SRC_SEL 0x0208000BU
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#define CLK_I2S0_8CH_TX_SRC_SEL_CLK_NPLL_MUX 0U
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#define MCLK_I2S0_8CH_TX_SEL 0x020A000BU
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#define MCLK_I2S0_8CH_TX_SEL_XIN_OSC0_HALF 0U
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#define I2S0_MCLKOUT_TX_SEL 0x010F000BU
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#define I2S0_MCLKOUT_TX_SEL_XIN_OSC0_HALF 0U
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/********Name=CLKSEL_CON12,Offset=0x130********/
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/********Name=CLKSEL_CON13,Offset=0x134********/
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#define CLK_I2S0_8CH_RX_SRC_SEL 0x0208000DU
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#define CLK_I2S0_8CH_RX_SRC_SEL_CLK_NPLL_MUX 0U
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#define MCLK_I2S0_8CH_RX_SEL 0x020A000DU
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#define MCLK_I2S0_8CH_RX_SEL_XIN_OSC0_HALF 0U
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#define I2S0_MCLKOUT_RX_SEL 0x010F000DU
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#define I2S0_MCLKOUT_RX_SEL_XIN_OSC0_HALF 0U
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/********Name=CLKSEL_CON14,Offset=0x138********/
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/********Name=CLKSEL_CON15,Offset=0x13C********/
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#define CLK_I2S1_8CH_TX_SRC_SEL 0x0208000FU
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#define CLK_I2S1_8CH_TX_SRC_SEL_CLK_NPLL_MUX 0U
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#define MCLK_I2S1_8CH_TX_SEL 0x020A000FU
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#define MCLK_I2S1_8CH_TX_SEL_XIN_OSC0_HALF 0U
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#define I2S1_MCLKOUT_TX_SEL 0x010F000FU
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#define I2S1_MCLKOUT_TX_SEL_XIN_OSC0_HALF 0U
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/********Name=CLKSEL_CON16,Offset=0x140********/
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/********Name=CLKSEL_CON17,Offset=0x144********/
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#define CLK_I2S1_8CH_RX_SRC_SEL 0x02080011U
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#define CLK_I2S1_8CH_RX_SRC_SEL_CLK_NPLL_MUX 0U
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#define MCLK_I2S1_8CH_RX_SEL 0x020A0011U
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#define MCLK_I2S1_8CH_RX_SEL_XIN_OSC0_HALF 0U
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#define I2S1_MCLKOUT_RX_SEL 0x010F0011U
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#define I2S1_MCLKOUT_RX_SEL_XIN_OSC0_HALF 0U
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/********Name=CLKSEL_CON18,Offset=0x148********/
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/********Name=CLKSEL_CON19,Offset=0x14C********/
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#define CLK_I2S2_2CH_SRC_SEL 0x02080013U
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#define CLK_I2S2_2CH_SRC_SEL_CLK_NPLL_MUX 0U
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#define MCLK_I2S2_2CH_SEL 0x020A0013U
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#define MCLK_I2S2_2CH_SEL_XIN_OSC0_HALF 0U
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#define I2S2_MCLKOUT_SEL 0x010F0013U
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#define I2S2_MCLKOUT_SEL_XIN_OSC0_HALF 0U
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/********Name=CLKSEL_CON20,Offset=0x150********/
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/********Name=CLKSEL_CON21,Offset=0x154********/
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#define CLK_I2S3_2CH_TX_SRC_SEL 0x02080015U
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#define CLK_I2S3_2CH_TX_SRC_SEL_CLK_NPLL_MUX 0U
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#define MCLK_I2S3_2CH_TX_SEL 0x020A0015U
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#define MCLK_I2S3_2CH_TX_SEL_XIN_OSC0_HALF 0U
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#define I2S3_MCLKOUT_TX_SEL 0x010F0015U
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#define I2S3_MCLKOUT_TX_SEL_XIN_OSC0_HALF 0U
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/********Name=CLKSEL_CON22,Offset=0x158********/
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/********Name=CLKSEL_CON23,Offset=0x15C********/
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#define MCLK_PDM_SEL 0x02080017U
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#define MCLK_PDM_SEL_CLK_GPLL_DIV_100M 0U
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#define CLK_ACDCDIG_I2C_SEL 0x020A0017U
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#define CLK_ACDCDIG_I2C_SEL_CLK_CPLL_DIV_100M 0U
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#define MCLK_SPDIF_8CH_SRC_SEL 0x010E0017U
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#define MCLK_SPDIF_8CH_SRC_SEL_CLK_GPLL_MUX 0U
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#define MCLK_SPDIF_8CH_SEL 0x010F0017U
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#define MCLK_SPDIF_8CH_SEL_MCLK_SPDIF_8CH_FRAC 0U
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/********Name=CLKSEL_CON24,Offset=0x160********/
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/********Name=CLKSEL_CON25,Offset=0x164********/
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#define SCLK_AUDPWM_SRC_SEL 0x010E0019U
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#define SCLK_AUDPWM_SRC_SEL_CLK_CPLL_MUX 0U
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#define SCLK_AUDPWM_SEL 0x010F0019U
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#define SCLK_AUDPWM_SEL_SCLK_AUDPWM_FRAC 0U
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/********Name=CLKSEL_CON26,Offset=0x168********/
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/********Name=CLKSEL_CON27,Offset=0x16C********/
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#define ACLK_SECURE_FLASH_SEL 0x0200001BU
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#define ACLK_SECURE_FLASH_SEL_XIN_OSC0_FUNC_MUX 0U
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#define HCLK_SECURE_FLASH_SEL 0x0202001BU
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#define HCLK_SECURE_FLASH_SEL_XIN_OSC0_FUNC_MUX 0U
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#define CLK_CRYPTO_NS_CORE_SEL 0x0204001BU
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#define CLK_CRYPTO_NS_CORE_SEL_CLK_GPLL_DIV_100M 0U
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#define CLK_CRYPTO_NS_PKA_SEL 0x0206001BU
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#define CLK_CRYPTO_NS_PKA_SEL_CLK_GPLL_DIV_100M 0U
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/********Name=CLKSEL_CON28,Offset=0x170********/
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#define NCLK_NANDC_SEL 0x0200001CU
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#define NCLK_NANDC_SEL_XIN_OSC0_FUNC_MUX 0U
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#define SCLK_SFC_SEL 0x0304001CU
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#define SCLK_SFC_SEL_CLK_GPLL_DIV_150M 0U
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#define BCLK_EMMC_SEL 0x0208001CU
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#define BCLK_EMMC_SEL_CLK_CPLL_DIV_125M 0U
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#define CCLK_EMMC_SEL 0x030C001CU
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#define CCLK_EMMC_SEL_CLK_OSC0_DIV_375K 0U
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/********Name=CLKSEL_CON29,Offset=0x174********/
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#define ACLK_PIPE_SEL 0x0200001DU
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#define ACLK_PIPE_SEL_XIN_OSC0_FUNC_MUX 0U
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#define CLK_USB3OTG0_SUSPEND_SEL 0x0108001DU
|
#define CLK_USB3OTG0_SUSPEND_SEL_CLK_RTC_32K 0U
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#define CLK_USB3OTG1_SUSPEND_SEL 0x0109001DU
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#define CLK_USB3OTG1_SUSPEND_SEL_CLK_RTC_32K 0U
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#define CLK_XPCS_EEE_SEL 0x010D001DU
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#define CLK_XPCS_EEE_SEL_CLK_CPLL_DIV_125M 0U
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/********Name=CLKSEL_CON30,Offset=0x178********/
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#define ACLK_PHP_SEL 0x0200001EU
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#define ACLK_PHP_SEL_XIN_OSC0_FUNC_MUX 0U
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#define HCLK_PHP_SEL 0x0202001EU
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#define HCLK_PHP_SEL_XIN_OSC0_FUNC_MUX 0U
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#define CLK_SDMMC0_SEL 0x0308001EU
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#define CLK_SDMMC0_SEL_CLK_OSC0_DIV_750K 0U
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#define CLK_SDMMC1_SEL 0x030C001EU
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#define CLK_SDMMC1_SEL_CLK_OSC0_DIV_750K 0U
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/********Name=CLKSEL_CON31,Offset=0x17C********/
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#define CLK_GMAC0_RX_TX_SEL 0x0200001FU
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#define RMII0_EXTCLK_SEL 0x0102001FU
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#define RMII0_EXTCLK_SEL_IO 0U
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#define RMII0_CLK_SEL 0x0103001FU
|
#define RMII0_CLK_SEL_25M 0U
|
#define RGMII0_CLK_SEL 0x0204001FU
|
#define RGMII0_CLK_SEL_25M 0U
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#define CLK_MAC0_2TOP_SEL 0x0208001FU
|
#define CLK_MAC0_2TOP_SEL_CLK_PPLL_MUX 0U
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#define CLK_GMAC0_PTP_REF_SEL 0x020C001FU
|
#define CLK_GMAC0_PTP_REF_SEL_XIN_OSC0_FUNC_MUX 0U
|
#define CLK_MAC0_OUT_SEL 0x020E001FU
|
#define CLK_MAC0_OUT_SEL_XIN_OSC0_FUNC_MUX 0U
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/********Name=CLKSEL_CON32,Offset=0x180********/
|
#define ACLK_USB_SEL 0x02000020U
|
#define ACLK_USB_SEL_XIN_OSC0_FUNC_MUX 0U
|
#define HCLK_USB_SEL 0x02020020U
|
#define HCLK_USB_SEL_XIN_OSC0_FUNC_MUX 0U
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#define CLK_SDMMC2_SEL 0x03080020U
|
#define CLK_SDMMC2_SEL_CLK_OSC0_DIV_750K 0U
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/********Name=CLKSEL_CON33,Offset=0x184********/
|
#define CLK_GMAC1_RX_TX_SEL 0x02000021U
|
#define RMII1_EXTCLK_SEL 0x01020021U
|
#define RMII1_EXTCLK_SEL_IO 0U
|
#define RMII1_CLK_SEL 0x01030021U
|
#define RMII1_CLK_SEL_25M 0U
|
#define RGMII1_CLK_SEL 0x02040021U
|
#define RGMII1_CLK_SEL_25M 0U
|
#define CLK_MAC1_2TOP_SEL 0x02080021U
|
#define CLK_MAC1_2TOP_SEL_CLK_PPLL_MUX 0U
|
#define CLK_GMAC1_PTP_REF_SEL 0x020C0021U
|
#define CLK_GMAC1_PTP_REF_SEL_XIN_OSC0_FUNC_MUX 0U
|
#define CLK_MAC1_OUT_SEL 0x020E0021U
|
#define CLK_MAC1_OUT_SEL_XIN_OSC0_FUNC_MUX 0U
|
/********Name=CLKSEL_CON34,Offset=0x188********/
|
#define ACLK_VI_SEL 0x02000022U
|
#define ACLK_VI_SEL_XIN_OSC0_FUNC_MUX 0U
|
#define DCLK_VICAP1_SEL 0x020E0022U
|
#define DCLK_VICAP1_SEL_CLK_GPLL_DIV_200M 0U
|
/********Name=CLKSEL_CON35,Offset=0x18C********/
|
#define CLK_ISP_SEL 0x02060023U
|
#define CLK_ISP_SEL_CLK_HPLL_MUX 0U
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#define CLK_CIF_OUT_SEL 0x020E0023U
|
#define CLK_CIF_OUT_SEL_XIN_OSC0_FUNC_MUX 0U
|
/********Name=CLKSEL_CON36,Offset=0x190********/
|
#define CLK_CAM0_OUT_SEL 0x02060024U
|
#define CLK_CAM0_OUT_SEL_XIN_OSC0_FUNC_MUX 0U
|
#define CLK_CAM1_OUT_SEL 0x020E0024U
|
#define CLK_CAM1_OUT_SEL_XIN_OSC0_FUNC_MUX 0U
|
/********Name=CLKSEL_CON37,Offset=0x194********/
|
#define ACLK_VO_SEL 0x02000025U
|
#define ACLK_VO_SEL_XIN_OSC0_FUNC_MUX 0U
|
/********Name=CLKSEL_CON38,Offset=0x198********/
|
#define ACLK_VOP_PRE_SEL 0x02060026U
|
#define ACLK_VOP_PRE_SEL_CLK_VPLL_MUX 0U
|
#define CLK_EDP_200M_SEL 0x02080026U
|
#define CLK_EDP_200M_SEL_CLK_CPLL_DIV_125M 0U
|
/********Name=CLKSEL_CON39,Offset=0x19C********/
|
#define DCLK0_VOP_SEL 0x020A0027U
|
#define DCLK0_VOP_SEL_CLK_CPLL_MUX 0U
|
/********Name=CLKSEL_CON40,Offset=0x1A0********/
|
#define DCLK1_VOP_SEL 0x020A0028U
|
#define DCLK1_VOP_SEL_CLK_CPLL_MUX 0U
|
/********Name=CLKSEL_CON41,Offset=0x1A4********/
|
#define DCLK2_VOP_SEL 0x020A0029U
|
#define DCLK2_VOP_SEL_CLK_CPLL_MUX 0U
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/********Name=CLKSEL_CON42,Offset=0x1A8********/
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#define ACLK_VPU_PRE_SEL 0x0107002AU
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#define ACLK_VPU_PRE_SEL_CLK_CPLL_MUX 0U
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/********Name=CLKSEL_CON43,Offset=0x1AC********/
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#define ACLK_RGA_PRE_SEL 0x0200002BU
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#define ACLK_RGA_PRE_SEL_XIN_OSC0_FUNC_MUX 0U
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#define CLK_RGA_CORE_SEL 0x0202002BU
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#define CLK_RGA_CORE_SEL_CLK_CPLL_DIV_100M 0U
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#define CLK_IEP_CORE_SEL 0x0204002BU
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#define CLK_IEP_CORE_SEL_CLK_CPLL_DIV_100M 0U
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#define DCLK_EBC_SEL 0x0206002BU
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#define DCLK_EBC_SEL_CLK_GPLL_DIV_200M 0U
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/********Name=CLKSEL_CON44,Offset=0x1B0********/
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#define ACLK_RKVENC_PRE_SEL 0x0206002CU
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#define ACLK_RKVENC_PRE_SEL_CLK_NPLL_MUX 0U
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/********Name=CLKSEL_CON45,Offset=0x1B4********/
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#define CLK_RKVENC_CORE_SEL 0x020E002DU
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#define CLK_RKVENC_CORE_SEL_CLK_VPLL_MUX 0U
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/********Name=CLKSEL_CON47,Offset=0x1BC********/
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#define ACLK_RKVDEC_PRE_SEL 0x0107002FU
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#define ACLK_RKVDEC_PRE_SEL_CLK_CPLL_MUX 0U
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/********Name=CLKSEL_CON48,Offset=0x1C0********/
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#define CLK_RKVDEC_CA_SEL 0x02060030U
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#define CLK_RKVDEC_CA_SEL_CLK_VPLL_MUX 0U
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/********Name=CLKSEL_CON49,Offset=0x1C4********/
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#define CLK_RKVDEC_HEVC_CA_SEL 0x02060031U
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#define CLK_RKVDEC_HEVC_CA_SEL_CLK_VPLL_MUX 0U
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#define CLK_RKVDEC_CORE_SEL 0x020E0031U
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#define CLK_RKVDEC_CORE_SEL_CLK_VPLL_MUX 0U
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/********Name=CLKSEL_CON50,Offset=0x1C8********/
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#define ACLK_BUS_SEL 0x02000032U
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#define ACLK_BUS_SEL_XIN_OSC0_FUNC_MUX 0U
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#define PCLK_BUS_SEL 0x02040032U
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#define PCLK_BUS_SEL_XIN_OSC0_FUNC_MUX 0U
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/********Name=CLKSEL_CON51,Offset=0x1CC********/
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#define CLK_TSADC_TSEN_SEL 0x02040033U
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#define CLK_TSADC_TSEN_SEL_CLK_CPLL_DIV_100M 0U
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/********Name=CLKSEL_CON52,Offset=0x1D0********/
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#define CLK_UART1_SRC_SEL 0x02080034U
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#define CLK_UART1_SRC_SEL_USBPHY480M_MUX 0U
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#define SCLK_UART1_SEL 0x020C0034U
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#define SCLK_UART1_SEL_XIN_OSC0_FUNC_MUX 0U
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/********Name=CLKSEL_CON53,Offset=0x1D4********/
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/********Name=CLKSEL_CON54,Offset=0x1D8********/
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#define CLK_UART2_SRC_SEL 0x02080036U
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#define CLK_UART2_SRC_SEL_USBPHY480M_MUX 0U
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#define SCLK_UART2_SEL 0x020C0036U
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#define SCLK_UART2_SEL_XIN_OSC0_FUNC_MUX 0U
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/********Name=CLKSEL_CON55,Offset=0x1DC********/
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/********Name=CLKSEL_CON56,Offset=0x1E0********/
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#define CLK_UART3_SRC_SEL 0x02080038U
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#define CLK_UART3_SRC_SEL_USBPHY480M_MUX 0U
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#define SCLK_UART3_SEL 0x020C0038U
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#define SCLK_UART3_SEL_XIN_OSC0_FUNC_MUX 0U
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/********Name=CLKSEL_CON57,Offset=0x1E4********/
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/********Name=CLKSEL_CON58,Offset=0x1E8********/
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#define CLK_UART4_SRC_SEL 0x0208003AU
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#define CLK_UART4_SRC_SEL_USBPHY480M_MUX 0U
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#define SCLK_UART4_SEL 0x020C003AU
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#define SCLK_UART4_SEL_XIN_OSC0_FUNC_MUX 0U
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/********Name=CLKSEL_CON59,Offset=0x1EC********/
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/********Name=CLKSEL_CON60,Offset=0x1F0********/
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#define CLK_UART5_SRC_SEL 0x0208003CU
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#define CLK_UART5_SRC_SEL_USBPHY480M_MUX 0U
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#define SCLK_UART5_SEL 0x020C003CU
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#define SCLK_UART5_SEL_XIN_OSC0_FUNC_MUX 0U
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/********Name=CLKSEL_CON61,Offset=0x1F4********/
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/********Name=CLKSEL_CON62,Offset=0x1F8********/
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#define CLK_UART6_SRC_SEL 0x0208003EU
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#define CLK_UART6_SRC_SEL_USBPHY480M_MUX 0U
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#define SCLK_UART6_SEL 0x020C003EU
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#define SCLK_UART6_SEL_XIN_OSC0_FUNC_MUX 0U
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/********Name=CLKSEL_CON63,Offset=0x1FC********/
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/********Name=CLKSEL_CON64,Offset=0x200********/
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#define CLK_UART7_SRC_SEL 0x02080040U
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#define CLK_UART7_SRC_SEL_USBPHY480M_MUX 0U
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#define SCLK_UART7_SEL 0x020C0040U
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#define SCLK_UART7_SEL_XIN_OSC0_FUNC_MUX 0U
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/********Name=CLKSEL_CON65,Offset=0x204********/
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/********Name=CLKSEL_CON66,Offset=0x208********/
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#define CLK_UART8_SRC_SEL 0x02080042U
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#define CLK_UART8_SRC_SEL_USBPHY480M_MUX 0U
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#define SCLK_UART8_SEL 0x020C0042U
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#define SCLK_UART8_SEL_XIN_OSC0_FUNC_MUX 0U
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/********Name=CLKSEL_CON67,Offset=0x20C********/
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/********Name=CLKSEL_CON68,Offset=0x210********/
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#define CLK_UART9_SRC_SEL 0x02080044U
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#define CLK_UART9_SRC_SEL_USBPHY480M_MUX 0U
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#define SCLK_UART9_SEL 0x020C0044U
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#define SCLK_UART9_SEL_XIN_OSC0_FUNC_MUX 0U
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/********Name=CLKSEL_CON69,Offset=0x214********/
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/********Name=CLKSEL_CON70,Offset=0x218********/
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#define CLK_CAN0_SEL 0x01070046U
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#define CLK_CAN0_SEL_CLK_CPLL_MUX 0U
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#define CLK_CAN1_SEL 0x010F0046U
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#define CLK_CAN1_SEL_CLK_CPLL_MUX 0U
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/********Name=CLKSEL_CON71,Offset=0x21C********/
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#define CLK_CAN2_SEL 0x01070047U
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#define CLK_CAN2_SEL_CLK_CPLL_MUX 0U
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#define CLK_I2C_SEL 0x02080047U
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#define CLK_I2C_SEL_CLK_CPLL_DIV_100M 0U
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/********Name=CLKSEL_CON72,Offset=0x220********/
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#define CLK_SPI0_SEL 0x02000048U
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#define CLK_SPI0_SEL_CLK_CPLL_DIV_100M 0U
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#define CLK_SPI1_SEL 0x02020048U
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#define CLK_SPI1_SEL_CLK_CPLL_DIV_100M 0U
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#define CLK_SPI2_SEL 0x02040048U
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#define CLK_SPI2_SEL_CLK_CPLL_DIV_100M 0U
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#define CLK_SPI3_SEL 0x02060048U
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#define CLK_SPI3_SEL_CLK_CPLL_DIV_100M 0U
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#define CLK_PWM1_SEL 0x02080048U
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#define CLK_PWM1_SEL_CLK_CPLL_DIV_100M 0U
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#define CLK_PWM2_SEL 0x020A0048U
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#define CLK_PWM2_SEL_CLK_CPLL_DIV_100M 0U
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#define CLK_PWM3_SEL 0x020C0048U
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#define CLK_PWM3_SEL_CLK_CPLL_DIV_100M 0U
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#define DBCLK_GPIO_SEL 0x010E0048U
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#define DBCLK_GPIO_SEL_CLK_RTC_32K 0U
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/********Name=CLKSEL_CON73,Offset=0x224********/
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#define ACLK_TOP_HIGH_SEL 0x02000049U
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#define ACLK_TOP_HIGH_SEL_XIN_OSC0_FUNC_MUX 0U
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#define ACLK_TOP_LOW_SEL 0x02040049U
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#define ACLK_TOP_LOW_SEL_XIN_OSC0_FUNC_MUX 0U
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#define HCLK_TOP_SEL 0x02080049U
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#define HCLK_TOP_SEL_XIN_OSC0_FUNC_MUX 0U
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#define PCLK_TOP_SEL 0x020C0049U
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#define PCLK_TOP_SEL_XIN_OSC0_FUNC_MUX 0U
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#define CLK_OTPC_ARB_SEL 0x010F0049U
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#define CLK_OTPC_ARB_SEL_CLK_CPLL_DIV_100M 0U
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/********Name=CLKSEL_CON74,Offset=0x228********/
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#define CLK_TESTOUT_SEL 0x0508004AU
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#define CLK_TESTOUT_SEL_USBPHY480M_I 0U
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/********Name=CLKSEL_CON75,Offset=0x22C********/
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/********Name=CLKSEL_CON76,Offset=0x230********/
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/********Name=CLKSEL_CON77,Offset=0x234********/
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/********Name=CLKSEL_CON78,Offset=0x238********/
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/********Name=CLKSEL_CON79,Offset=0x23C********/
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/********Name=CLKSEL_CON80,Offset=0x240********/
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/********Name=CLKSEL_CON81,Offset=0x244********/
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/********Name=CLKSEL_CON82,Offset=0x248********/
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/********Name=CLKSEL_CON83,Offset=0x24C********/
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#define CLK_I2S3_2CH_RX_SRC_SEL 0x02080053U
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#define CLK_I2S3_2CH_RX_SRC_SEL_CLK_NPLL_MUX 0U
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#define MCLK_I2S3_2CH_RX_SEL 0x020A0053U
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#define MCLK_I2S3_2CH_RX_SEL_XIN_OSC0_HALF 0U
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#define I2S3_MCLKOUT_RX_SEL 0x010F0053U
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#define I2S3_MCLKOUT_RX_SEL_XIN_OSC0_HALF 0U
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/********Name=CLKSEL_CON84,Offset=0x250********/
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/********Name=PMUCLKSEL_CON9,Offset=0x124********/
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#define CLK_PCIEPHY0_REF_DIV 0x0300005DU
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#define CLK_PCIEPHY1_REF_DIV 0x0304005DU
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#define CLK_PCIEPHY2_REF_DIV 0x0308005DU
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/********Name=PMUCLKSEL_CON9,Offset=0x124********/
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#define CLK_PCIEPHY0_REF_SEL 0x0103005DU
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#define CLK_PCIEPHY1_REF_SEL 0x0107005DU
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#define CLK_PCIEPHY2_REF_SEL 0x010B005DU
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __RK3568_H */
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