/**
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Copyright (c) 2021, Rockchip Inc. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "Soc.h"
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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#include <Library/SpiLib.h>
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/** @defgroup How_To_Use How To Use
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*
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The SPI HAL driver can be used as follows:
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- Declare a SPI_Handle handle structure, for example:
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```
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SPI_Handle instance;
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```
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- Invoke SPI_Init() API to configure default config:
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- opMode: slave or master
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- apbTransform
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- endianMode
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- ssd
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- Clock rate
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- Invoke SPI_Configure() API to program other mode:
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- Data size
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- Clock polarity and phase
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- FirstBit
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- Clock div
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- Number of data frames received at RX only mode
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- IT FIFO Level and DMA FIFO Level
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- Transfer Mode
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- Blocking transfer:
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- The communication is performed in polling mode by calling SPI_PioTransfer().
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- after transfer done, invoke SPI_Stop to release the chip select.
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*/
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#define HAL_SPI_FIFO_LENGTH 64
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/* Bit fields in SR */
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#define HAL_SPI_SR_BUSY (0x1 << SPI_SR_BSF_SHIFT)
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#define HAL_SPI_SR_STB_BUSY (0x1 << SPI_SR_STB_SHIFT)
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/* Bit fields in ISR, IMR, RISR, 7 bits */
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#define SPI_INT_TXEI (1 << SPI_IMR_TFEIM_SHIFT)
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#define SPI_INT_TXOI (1 << SPI_IMR_TFOIM_SHIFT)
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#define SPI_INT_RXUI (1 << SPI_IMR_RFUIM_SHIFT)
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#define SPI_INT_RXOI (1 << SPI_IMR_RFOIM_SHIFT)
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#define SPI_INT_RXFI (1 << SPI_IMR_RFFIM_SHIFT)
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#define SPI_INT_TOI (1 << SPI_IMR_TOIM_SHIFT)
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#define SPI_INT_SSPI (1 << SPI_IMR_SSPIM_SHIFT)
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#define SPI_INT_TXFIM (1 << SPI_IMR_TXFIM_SHIFT)
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/* Bit fields in ICR */
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#define SPI_CLEAR_INT_ALL (1 << SPI_ICR_CCI_SHIFT)
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#define SPI_CLEAR_INT_RXUI (1 << SPI_ICR_CRFUI_SHIFT)
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#define SPI_CLEAR_INT_RXOI (1 << SPI_ICR_CRFOI_SHIFT)
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#define SPI_CLEAR_INT_TXOI (1 << SPI_ICR_CTFOI_SHIFT)
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#define SPI_CLEAR_INT_TOI (1 << SPI_ICR_CTOI_SHIFT)
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#define SPI_ICR_SSPI_SHIFT (1 << SPI_ICR_CSSPI_SHIFT)
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#define SPI_CLEAR_INT_TXFI (1 << SPI_ICR_CTXFI_SHIFT)
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/* Bit fields in DMACR */
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#define SPI_DMACR_TX_ENABLE (1 << SPI_DMACR_TDE_SHIFT)
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#define SPI_DMACR_RX_ENABLE (1 << SPI_DMACR_RDE_SHIFT)
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/* Bit fields in SPI TIMEOUT */
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#define SPI_TIMEOUT_ENABLE (1 << SPI_TIMEOUT_TOE_SHIFT)
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#define SPI_TIMEOUT_DISABLE 0
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#define IS_SPI_MODE(__MODE__) (((__MODE__) == CR0_OPM_SLAVE) || \
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((__MODE__) == CR0_OPM_MASTER))
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#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == CR0_XFM_TR) || \
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((__MODE__) == CR0_XFM_TO) || \
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((__MODE__) == CR0_XFM_RO))
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#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == CR0_DATA_FRAME_SIZE_4BIT) || \
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((__DATASIZE__) == CR0_DATA_FRAME_SIZE_8BIT) || \
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((__DATASIZE__) == CR0_DATA_FRAME_SIZE_16BIT))
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#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == CR0_POLARITY_LOW) || \
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((__CPOL__) == CR0_POLARITY_HIGH))
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#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == CR0_PHASE_1EDGE) || \
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((__CPHA__) == CR0_PHASE_2EDGE))
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#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == CR0_FIRSTBIT_MSB) || \
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((__BIT__) == CR0_FIRSTBIT_LSB))
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#define IS_SPI_APBTRANSFORM(__MODE__) (((__MODE__) == CR0_BHT_16BIT) || \
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((__MODE__) == CR0_BHT_8BIT))
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#define IS_SPI_ENDIAN_MODE(__MODE__) (((__MODE__) == CR0_EM_BIG) || \
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((__MODE__) == CR0_EM_LITTLE))
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#define IS_SPI_SSD_BIT(__MODE__) (((__MODE__) == CR0_SSD_HALF) || \
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((__MODE__) == CR0_SSD_ONE))
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#define IS_SPI_CSM(__NCYCLES__) (((__NCYCLES__) == CR0_CSM_0CYCLE) || \
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((__NCYCLES__) == CR0_CSM_1CYCLE) || \
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((__NCYCLES__) == CR0_CSM_2CYCLES) || \
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((__NCYCLES__) == CR0_CSM_3CYCLES))
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/**
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* @brief Initialize the SPI according to the specified parameters.
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* @param pSPI: pointer to a SPI_Handle structure that contains
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* the configuration information for SPI module.
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* @param base: SPI controller register base address.
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* @return status
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*/
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RETURN_STATUS
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EFIAPI
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SPI_Init(struct SPI_HANDLE *pSPI, UINT32 base)
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{
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pSPI->pReg = (struct SPI_REG *)(long)base;
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pSPI->config.opMode = CR0_OPM_MASTER;
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/* Default config */
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pSPI->config.apbTransform = CR0_BHT_8BIT;
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pSPI->config.endianMode = CR0_EM_BIG;
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pSPI->config.ssd = CR0_SSD_ONE;
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pSPI->config.csm = CR0_CSM_0CYCLE;
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return RETURN_SUCCESS;
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}
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/**
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* @brief Start or stop the spi module.
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* @param pSPI: pointer to a SPI_Handle structure that contains
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* the configuration information for SPI module.
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* @param enable: start or stop the spi module.
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* @return status
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*/
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static inline RETURN_STATUS SPI_EnableChip(struct SPI_HANDLE *pSPI, int enable)
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{
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WRITE_REG(pSPI->pReg->ENR, (enable ? 1 : 0));
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return RETURN_SUCCESS;
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}
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/**
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* @brief Configure the spi clock division.
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* @param pSPI: pointer to a SPI_Handle structure that contains
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* the configuration information for SPI module.
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* @param div: clock division.
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* @return status
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*/
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static inline RETURN_STATUS SPI_SetClock(struct SPI_HANDLE *pSPI, UINT16 div)
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{
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WRITE_REG(pSPI->pReg->BAUDR, div);
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return RETURN_SUCCESS;
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}
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/**
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* @brief Configure the cs signal.
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* @param pSPI: pointer to a SPI_Handle structure that contains
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* the configuration information for SPI module.
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* @param select: cs number select.
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* @param enable: active or inactive the cs signal.
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* @return status
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*/
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RETURN_STATUS
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EFIAPI
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SPI_SetCS(struct SPI_HANDLE *pSPI, UINT8 select, UINT8 enable)
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{
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UINT32 ser;
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ASSERT(pSPI != NULL);
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ser = READ_REG(pSPI->pReg->SER) & SPI_SER_SER_MASK;
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if (enable) {
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ser |= 1 << select;
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} else {
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ser &= ~(1 << select);
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}
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WRITE_REG(pSPI->pReg->SER, ser);
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return RETURN_SUCCESS;
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}
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/**
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* @brief Wait for the transfer finished.
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* @param pSPI: pointer to a SPI_Handle structure that contains
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* the configuration information for SPI module.
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* @return status
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*/
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RETURN_STATUS
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EFIAPI
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SPI_FlushFifo(struct SPI_HANDLE *pSPI)
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{
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ASSERT(pSPI != NULL);
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while (READ_REG(pSPI->pReg->RXFLR)) {
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READ_REG(pSPI->pReg->RXDR);
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}
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return RETURN_SUCCESS;
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}
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/**
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* @brief The max amount of data can be written in blocking mode.
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* @param pSPI: pointer to a SPI_Handle structure that contains
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* the configuration information for SPI module.
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* @return Max bytes can xfer.
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*/
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static inline UINT32 SPI_TxMax(struct SPI_HANDLE *pSPI)
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{
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UINT32 txLeft, txRoom;
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txLeft = (pSPI->pTxBufferEnd - pSPI->pTxBuffer) / pSPI->config.nBytes;
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txRoom = HAL_SPI_FIFO_LENGTH - READ_REG(pSPI->pReg->TXFLR);
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return MIN(txLeft, txRoom);
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}
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/**
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* @brief Send an amount of data in blocking mode.
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* @param pSPI: pointer to a SPI_Handle structure that contains
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* the configuration information for SPI module.
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* @return status
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*/
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static RETURN_STATUS SPI_PioWrite(struct SPI_HANDLE *pSPI)
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{
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UINT32 max = SPI_TxMax(pSPI);
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UINT32 txw = 0;
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while (max--) {
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if (pSPI->config.nBytes == 1) {
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txw = *(const UINT8 *)(pSPI->pTxBuffer);
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} else {
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txw = *(const UINT16 *)(pSPI->pTxBuffer);
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}
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WRITE_REG(pSPI->pReg->TXDR, txw);
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pSPI->pTxBuffer += pSPI->config.nBytes;
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}
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return RETURN_SUCCESS;
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}
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/**
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* @brief Read an amount of data(byte) in blocking mode.
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* @param pSPI: pointer to a SPI_Handle structure that contains
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* the configuration information for SPI module.
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* @return status
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*/
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static RETURN_STATUS SPI_PioReadByte(struct SPI_HANDLE *pSPI)
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{
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UINT32 rxLeft = pSPI->pRxBufferEnd - pSPI->pRxBuffer;
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UINT32 rxRoom = READ_REG(pSPI->pReg->RXFLR);
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UINT32 max = MIN(rxLeft, rxRoom);
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while (max > 7) {
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*(pSPI->pRxBuffer + 0) = (UINT8)READ_REG(pSPI->pReg->RXDR);
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*(pSPI->pRxBuffer + 1) = (UINT8)READ_REG(pSPI->pReg->RXDR);
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*(pSPI->pRxBuffer + 2) = (UINT8)READ_REG(pSPI->pReg->RXDR);
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*(pSPI->pRxBuffer + 3) = (UINT8)READ_REG(pSPI->pReg->RXDR);
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*(pSPI->pRxBuffer + 4) = (UINT8)READ_REG(pSPI->pReg->RXDR);
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*(pSPI->pRxBuffer + 5) = (UINT8)READ_REG(pSPI->pReg->RXDR);
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*(pSPI->pRxBuffer + 6) = (UINT8)READ_REG(pSPI->pReg->RXDR);
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*(pSPI->pRxBuffer + 7) = (UINT8)READ_REG(pSPI->pReg->RXDR);
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pSPI->pRxBuffer += 8;
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max -= 8;
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}
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while (max--) {
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*pSPI->pRxBuffer = (UINT8)READ_REG(pSPI->pReg->RXDR);
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pSPI->pRxBuffer++;
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}
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return RETURN_SUCCESS;
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}
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/**
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* @brief Read an amount of data(short) in blocking mode.
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* @param pSPI: pointer to a SPI_Handle structure that contains
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* the configuration information for SPI module.
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* @return status
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*/
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static RETURN_STATUS SPI_PioReadShort(struct SPI_HANDLE *pSPI)
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{
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UINT32 rxLeft = (pSPI->pRxBufferEnd - pSPI->pRxBuffer) >> 1;
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UINT32 rxRoom = READ_REG(pSPI->pReg->RXFLR);
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UINT32 max = MIN(rxLeft, rxRoom);
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while (max > 7) {
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*((UINT16 *)pSPI->pRxBuffer + 0) = (UINT16)READ_REG(pSPI->pReg->RXDR);
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*((UINT16 *)pSPI->pRxBuffer + 1) = (UINT16)READ_REG(pSPI->pReg->RXDR);
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*((UINT16 *)pSPI->pRxBuffer + 2) = (UINT16)READ_REG(pSPI->pReg->RXDR);
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*((UINT16 *)pSPI->pRxBuffer + 3) = (UINT16)READ_REG(pSPI->pReg->RXDR);
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*((UINT16 *)pSPI->pRxBuffer + 4) = (UINT16)READ_REG(pSPI->pReg->RXDR);
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*((UINT16 *)pSPI->pRxBuffer + 5) = (UINT16)READ_REG(pSPI->pReg->RXDR);
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*((UINT16 *)pSPI->pRxBuffer + 6) = (UINT16)READ_REG(pSPI->pReg->RXDR);
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*((UINT16 *)pSPI->pRxBuffer + 7) = (UINT16)READ_REG(pSPI->pReg->RXDR);
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pSPI->pRxBuffer += 16;
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max -= 8;
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}
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while (max--) {
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*((UINT16 *)pSPI->pRxBuffer) = (UINT16)READ_REG(pSPI->pReg->RXDR);
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pSPI->pRxBuffer += 2;
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}
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return RETURN_SUCCESS;
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}
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/**
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* @brief Transmit an amount of data in blocking mode.
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* @param pSPI: pointer to a SPI_Handle structure that contains
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* the configuration information for SPI module.
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* @return status
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*/
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RETURN_STATUS
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EFIAPI
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SPI_PioTransfer(struct SPI_HANDLE *pSPI)
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{
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UINT32 remain = 0;
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ASSERT(pSPI != NULL);
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pSPI->type = SPI_POLL;
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SPI_EnableChip(pSPI, 1);
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do {
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if (pSPI->pTxBuffer) {
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remain = pSPI->pTxBufferEnd - pSPI->pTxBuffer;
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SPI_PioWrite(pSPI);
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}
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if (pSPI->pRxBuffer) {
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remain = pSPI->pRxBufferEnd - pSPI->pRxBuffer;
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if (pSPI->config.nBytes == 1) {
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SPI_PioReadByte(pSPI);
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} else {
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SPI_PioReadShort(pSPI);
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}
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}
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} while (remain);
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return RETURN_SUCCESS;
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}
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/**
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* @brief Query the SPI bus state is idle or busy.
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* @param pSPI: pointer to a SPI_Handle structure that contains
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* the configuration information for SPI module.
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* @return HAL status
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*/
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RETURN_STATUS SPI_QueryBusState(struct SPI_HANDLE *pSPI)
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{
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HAL_ASSERT(pSPI != NULL);
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if (!(READ_REG(pSPI->pReg->SR) & HAL_SPI_SR_BUSY)) {
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return RETURN_SUCCESS;
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}
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return -2;
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}
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/**
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* @brief Stop the transmit.
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* @param pSPI: pointer to a SPI_Handle structure that contains
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* the configuration information for SPI module.
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* @return status
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*/
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RETURN_STATUS
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EFIAPI
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SPI_Stop(struct SPI_HANDLE *pSPI)
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{
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UINT32 ret;
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ASSERT(pSPI != NULL);
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do
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{
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ret = SPI_QueryBusState(pSPI);
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if (ret == RETURN_SUCCESS)
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break;
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} while(1);
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SPI_EnableChip(pSPI, 0);
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return RETURN_SUCCESS;
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}
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/**
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* @brief Configure the SPI transfer mode depend on the tx/rx buffer.
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* @param pSPI: pointer to a SPI_Handle structure that contains
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* the configuration information for SPI module.
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* @return status
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*/
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static RETURN_STATUS HAL_SPI_ConfigureTransferMode(struct SPI_HANDLE *pSPI)
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{
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UINT32 cr0;
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if (pSPI->pTxBuffer && pSPI->pRxBuffer) {
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pSPI->config.xfmMode = CR0_XFM_TR;
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} else if (pSPI->pTxBuffer) {
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pSPI->config.xfmMode = CR0_XFM_TO;
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} else if (pSPI->pRxBuffer) {
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pSPI->config.xfmMode = CR0_XFM_RO;
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}
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cr0 = READ_REG(pSPI->pReg->CTRLR[0]);
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cr0 &= ~SPI_CTRLR0_XFM_MASK;
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cr0 |= pSPI->config.xfmMode;
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WRITE_REG(pSPI->pReg->DMARDLR, pSPI->dmaBurstSize - 1);
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WRITE_REG(pSPI->pReg->CTRLR[0], cr0);
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return RETURN_SUCCESS;
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}
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/**
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* @brief Program the SPI config via this api.
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* @param pSPI: pointer to a SPI_Handle structure that contains
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* the configuration information for SPI module.
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* @param pTxData: pointer to TX buffer.
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* @param pRxData: pointer to RX buffer.
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* @param size: amount of data to be sent.
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* @return status
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*/
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RETURN_STATUS
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EFIAPI
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SPI_Configure(struct SPI_HANDLE *pSPI, const UINT8 *pTxData, UINT8 *pRxData, UINT32 size)
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{
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UINT32 cr0 = 0;
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UINT32 div = 0;
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cr0 |= pSPI->config.opMode;
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cr0 |= pSPI->config.apbTransform | pSPI->config.endianMode | pSPI->config.ssd;
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/* Data width */
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cr0 |= pSPI->config.nBytes;
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/* Mode for polarity, phase, first bit and endian */
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cr0 |= pSPI->config.clkPolarity | pSPI->config.clkPhase | pSPI->config.firstBit;
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/* Config CSM cycles */
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cr0 |= pSPI->config.csm;
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/* div doesn't support odd number */
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div = DIV_ROUND_UP(pSPI->maxFreq, pSPI->config.speed);
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div = (div + 1) & 0xfffe;
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WRITE_REG(pSPI->pReg->CTRLR[0], cr0);
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WRITE_REG(pSPI->pReg->TXFTLR, HAL_SPI_FIFO_LENGTH / 2 - 1);
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WRITE_REG(pSPI->pReg->RXFTLR, HAL_SPI_FIFO_LENGTH / 2 - 1);
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WRITE_REG(pSPI->pReg->DMATDLR, HAL_SPI_FIFO_LENGTH / 2 - 1);
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WRITE_REG(pSPI->pReg->DMARDLR, 0);
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SPI_SetClock(pSPI, div);
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pSPI->pTxBuffer = pTxData;
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pSPI->pTxBufferEnd = pTxData + size;
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pSPI->pRxBuffer = pRxData;
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pSPI->pRxBufferEnd = pRxData + size;
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pSPI->len = size;
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HAL_SPI_ConfigureTransferMode(pSPI);
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if (pSPI->config.xfmMode == CR0_XFM_RO) {
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if (pSPI->config.nBytes == 1) {
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WRITE_REG(pSPI->pReg->CTRLR[1], pSPI->len - 1);
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} else if (pSPI->config.nBytes == 2) {
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WRITE_REG(pSPI->pReg->CTRLR[1], (pSPI->len / 2) - 1);
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} else {
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WRITE_REG(pSPI->pReg->CTRLR[1], (pSPI->len * 2) - 1);
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}
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}
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return RETURN_SUCCESS;
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}
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