/** @file
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Serial I/O Port library functions with no library constructor/destructor
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Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
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Copyright (c) 2017, Rockchip Inc. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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#include <Library/UartLib.h>
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/* uart some key registers offset */
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#define UART_RBR 0x00
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#define UART_THR 0x00
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#define UART_DLL 0x00
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#define UART_DLH 0x04
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#define UART_IER 0x04
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#define UART_LCR 0x0c
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#define UART_MCR 0x10
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#define UART_LSR 0x14
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#define UART_USR 0x7c
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#define UART_SRR 0x88
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#define UART_SFE 0x98
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#define UART_SRT 0x9c
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#define UART_STET 0xa0
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#define UART_LSR_TEMT 0x40 /* Transmitter empty */
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/* UART_IER */
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#define THRE_INT_ENABLE (1<<7)
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#define THRE_INT_DISABLE (0)
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#define ENABLE_MODEM_STATUS_INT (1<<3)
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#define DISABLE_MODEM_STATUS_INT (0)
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#define ENABLE_RECEIVER_LINE_STATUS_INT (1<<2)
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#define DISABLE_RECEIVER_LINE_STATUS_INT (0)
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#define ENABLE_TRANSMIT_HOLDING_EM_INT (1<<1) /* Enable Transmit Holding Register Empty Interrupt. */
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#define DISABLE_TRANSMIT_HOLDING_EM_INT (0)
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#define ENABLE_RECEIVER_DATA_INT (1) /* Enable Received Data Available Interrupt. */
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#define DISABLE_RECEIVER_DATA_INT (0)
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/* UART_IIR */
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#define IR_MODEM_STATUS (0)
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#define NO_INT_PENDING (1)
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#define THR_EMPTY (2)
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#define RECEIVER_DATA_AVAILABLE (0x04)
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#define RECEIVER_LINE_AVAILABLE (0x06)
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#define BUSY_DETECT (0x07)
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#define CHARACTER_TIMEOUT (0x0c)
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/* UART_LCR */
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#define LCR_DLA_EN (1<<7)
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#define BREAK_CONTROL_BIT (1<<6)
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#define PARITY_DISABLED (0)
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#define PARITY_ENABLED (1<<3)
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#define ONE_STOP_BIT (0)
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#define ONE_HALF_OR_TWO_BIT (1<<2)
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#define LCR_WLS_5 (0x00)
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#define LCR_WLS_6 (0x01)
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#define LCR_WLS_7 (0x02)
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#define LCR_WLS_8 (0x03)
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#define UART_DATABIT_MASK (0x03)
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/* UART_MCR */
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#define IRDA_SIR_DISABLED (0)
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#define IRDA_SIR_ENSABLED (1<<6)
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#define AUTO_FLOW_DISABLED (0)
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#define AUTO_FLOW_ENSABLED (1<<5)
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/* UART_LSR */
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#define THRE_BIT_EN (1<<5)
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/* UART_USR */
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#define UART_RECEIVE_FIFO_EMPTY (0)
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#define UART_RECEIVE_FIFO_NOT_EMPTY (1<<3)
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#define UART_TRANSMIT_FIFO_FULL (0)
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#define UART_TRANSMIT_FIFO_NOT_FULL (1<<1)
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#define UART_TRANSMIT_FIFO_EMPTY (1<<2)
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#define UART_IS_BUSY (1<<0)
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/* UART_SFE */
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#define SHADOW_FIFI_ENABLED (1)
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#define SHADOW_FIFI_DISABLED (0)
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/* UART_SRT */
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#define RCVR_TRIGGER_ONE (0)
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#define RCVR_TRIGGER_QUARTER_FIFO (1)
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#define RCVR_TRIGGER_HALF_FIFO (2)
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#define RCVR_TRIGGER_TWO_LESS_FIFO (3)
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/* UART_STET */
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#define TX_TRIGGER_EMPTY (0)
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#define TX_TRIGGER_TWO_IN_FIFO (1)
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#define TX_TRIGGER_ONE_FOUR_FIFO (2)
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#define TX_TRIGGER_HALF_FIFO (3)
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/* UART_SRR */
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#define UART_RESET (1)
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#define RCVR_FIFO_REST (1<<1)
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#define XMIT_FIFO_RESET (1<<2)
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#define UART_MODE_X_DIV 16
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#define UART_BIT5 5
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#define UART_BIT6 6
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#define UART_BIT7 7
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#define UART_BIT8 8
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/**
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Initialise the serial port to the specified settings.
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The serial port is re-configured only if the specified settings
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are different from the current settings.
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All unspecified settings will be set to the default values.
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@param UartBase The base address of the serial device.
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@param UartClkInHz The clock in Hz for the serial device.
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Ignored if the PCD PL011UartInteger is not 0
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@param BaudRate The baud rate of the serial device. If the
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baud rate is not supported, the speed will be
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reduced to the nearest supported one and the
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variable's value will be updated accordingly.
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@param ReceiveFifoDepth The number of characters the device will
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buffer on input. Value of 0 will use the
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device's default FIFO depth.
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@param Parity If applicable, this is the EFI_PARITY_TYPE
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that is computed or checked as each character
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is transmitted or received. If the device
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does not support parity, the value is the
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default parity value.
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@param DataBits The number of data bits in each character.
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@param StopBits If applicable, the EFI_STOP_BITS_TYPE number
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of stop bits per character.
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If the device does not support stop bits, the
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value is the default stop bit value.
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@retval RETURN_SUCCESS All attributes were set correctly on the
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serial device.
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@retval RETURN_INVALID_PARAMETER One or more of the attributes has an
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unsupported value.
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**/
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RETURN_STATUS
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EFIAPI
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UartInitializePort (
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IN UINTN UartBase,
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IN UINT32 UartClkInHz,
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IN OUT UINT64 *BaudRate,
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IN OUT UINT32 *ReceiveFifoDepth,
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IN OUT EFI_PARITY_TYPE *Parity,
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IN OUT UINT8 *DataBits,
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IN OUT EFI_STOP_BITS_TYPE *StopBits
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)
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{
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UINT32 Lcr, Rate;
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//do {} while ((MmioRead32(UartBase + UART_USR) & UART_IS_BUSY));
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// UART reset, rx fifo & tx fifo reset
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MmioWrite32(UartBase + UART_SRR, UART_RESET | RCVR_FIFO_REST | XMIT_FIFO_RESET);
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// UART interrupt disable
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MmioWrite32(UartBase + UART_IER, 0x00);
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// UART set iop
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MmioWrite32(UartBase + UART_MCR, IRDA_SIR_DISABLED);
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// UART set lcr
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Lcr = MmioRead32(UartBase + UART_LCR);
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Lcr &= ~UART_DATABIT_MASK;
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// byte set
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switch (*DataBits) {
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case UART_BIT5:
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Lcr |= LCR_WLS_5;
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break;
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case UART_BIT6:
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Lcr |= LCR_WLS_6;
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break;
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case UART_BIT7:
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Lcr |= LCR_WLS_7;
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break;
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case UART_BIT8:
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default:
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Lcr |= LCR_WLS_8;
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break;
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}
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// Parity set
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switch (*Parity) {
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case NoParity:
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Lcr |= PARITY_DISABLED;
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break;
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case DefaultParity:
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default:
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Lcr |= PARITY_ENABLED;
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break;
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}
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// stopbits set
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switch (*StopBits) {
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case TwoStopBits:
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case OneFiveStopBits:
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Lcr |= ONE_HALF_OR_TWO_BIT;
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break;
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case OneStopBit:
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default:
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Lcr |= ONE_STOP_BIT;
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break;
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}
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MmioWrite32(UartBase + UART_LCR, Lcr);
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// UART set baudrate
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/* uart rate is div for 24M input clock */
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Rate = PcdGet32 (UartClkInHz) / UART_MODE_X_DIV / *BaudRate;
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Lcr = MmioRead32(UartBase + UART_LCR);
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MmioWrite32(UartBase + UART_LCR, Lcr | LCR_DLA_EN);
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MmioWrite32(UartBase + UART_DLL, Rate & 0xFF);
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MmioWrite32(UartBase + UART_DLH, (Rate >> 8) & 0xff);
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Lcr = MmioRead32(UartBase + UART_LCR);
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MmioWrite32(UartBase + UART_LCR, Lcr & (~LCR_DLA_EN));
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// UART set fifo
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/* shadow FIFO enable */
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MmioWrite32(UartBase + UART_SFE, SHADOW_FIFI_ENABLED);
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/* fifo 2 less than */
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MmioWrite32(UartBase + UART_SRT, RCVR_TRIGGER_TWO_LESS_FIFO);
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/* 2 char in tx fifo */
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MmioWrite32(UartBase + UART_STET, TX_TRIGGER_TWO_IN_FIFO);
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return RETURN_SUCCESS;
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}
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/**
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Assert or deassert the control signals on a serial port.
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The following control signals are set according their bit settings :
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. Request to Send
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. Data Terminal Ready
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@param[in] UartBase UART registers base address
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@param[in] Control The following bits are taken into account :
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. EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the
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"Request To Send" control signal if this bit is
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equal to one/zero.
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. EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert
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the "Data Terminal Ready" control signal if this
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bit is equal to one/zero.
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. EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable
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the hardware loopback if this bit is equal to
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one/zero.
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. EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.
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. EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/
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disable the hardware flow control based on CTS (Clear
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To Send) and RTS (Ready To Send) control signals.
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@retval RETURN_SUCCESS The new control bits were set on the device.
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@retval RETURN_UNSUPPORTED The device does not support this operation.
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**/
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RETURN_STATUS
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EFIAPI
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UartSetControl (
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IN UINTN UartBase,
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IN UINT32 Control
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)
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{
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return RETURN_SUCCESS;
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}
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/**
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Retrieve the status of the control bits on a serial device.
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@param[in] UartBase UART registers base address
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@param[out] Control Status of the control bits on a serial device :
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. EFI_SERIAL_DATA_CLEAR_TO_SEND,
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EFI_SERIAL_DATA_SET_READY,
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EFI_SERIAL_RING_INDICATE,
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EFI_SERIAL_CARRIER_DETECT,
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EFI_SERIAL_REQUEST_TO_SEND,
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EFI_SERIAL_DATA_TERMINAL_READY
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are all related to the DTE (Data Terminal Equipment)
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and DCE (Data Communication Equipment) modes of
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operation of the serial device.
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. EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the
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receive buffer is empty, 0 otherwise.
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. EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the
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transmit buffer is empty, 0 otherwise.
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. EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if
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the hardware loopback is enabled (the ouput feeds the
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receive buffer), 0 otherwise.
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. EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if
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a loopback is accomplished by software, 0 otherwise.
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. EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to
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one if the hardware flow control based on CTS (Clear
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To Send) and RTS (Ready To Send) control signals is
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enabled, 0 otherwise.
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@retval RETURN_SUCCESS The control bits were read from the serial device.
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**/
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RETURN_STATUS
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EFIAPI
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UartGetControl (
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IN UINTN UartBase,
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OUT UINT32 *Control
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)
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{
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return RETURN_SUCCESS;
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}
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/**
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Write data to serial device.
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@param Buffer Point of data buffer which need to be written.
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@param NumberOfBytes Number of output bytes which are cached in Buffer.
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@retval 0 Write data failed.
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@retval !0 Actual number of bytes written to serial device.
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**/
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UINTN
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EFIAPI
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UartWrite (
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IN UINTN UartBase,
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IN UINT8 *Buffer,
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IN UINTN NumberOfBytes
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)
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{
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UINT8* CONST Final = &Buffer[NumberOfBytes];
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while (Buffer < Final) {
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do {} while ((MmioRead32(UartBase + UART_USR) & UART_TRANSMIT_FIFO_NOT_FULL) == 0);
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MmioWrite32(UartBase + UART_THR, *Buffer++);
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}
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return NumberOfBytes;
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}
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/**
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Read data from serial device and save the data in buffer.
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@param Buffer Point of data buffer which need to be written.
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@param NumberOfBytes Number of output bytes which are cached in Buffer.
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@retval 0 Read data failed.
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@retval !0 Actual number of bytes read from serial device.
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**/
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UINTN
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EFIAPI
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UartRead (
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IN UINTN UartBase,
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OUT UINT8 *Buffer,
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IN UINTN NumberOfBytes
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)
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{
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UINTN Count;
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for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
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do {} while ((MmioRead32(UartBase + UART_USR) & UART_RECEIVE_FIFO_NOT_EMPTY) == 0);
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*Buffer = (UINT8)MmioRead32(UartBase + UART_RBR);
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}
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return NumberOfBytes;
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}
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/**
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Check to see if any data is available to be read from the debug device.
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@retval TRUE At least one byte of data is available to be read
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@retval FALSE No data is available to be read
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**/
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BOOLEAN
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EFIAPI
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UartPoll (
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IN UINTN UartBase
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)
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{
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return (MmioRead32(UartBase + UART_USR) & UART_RECEIVE_FIFO_NOT_EMPTY) == UART_RECEIVE_FIFO_NOT_EMPTY;
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}
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