/** @file
|
Functions in this library instance make use of MMIO functions in IoLib to
|
access memory mapped PCI configuration space.
|
|
All assertions for I/O operations are handled in MMIO functions in the IoLib
|
Library.
|
|
Copyright (c) 2022, Rockchip Corporation. All rights reserved.<BR>
|
|
On the Rockchisp SoCs, ECAM is not usable, so we have to rewrite the whole
|
library.
|
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
|
**/
|
|
|
#include <Base.h>
|
|
#include <Library/BaseLib.h>
|
#include <Library/PciExpressLib.h>
|
#include <Library/IoLib.h>
|
#include <Library/DebugLib.h>
|
#include <Library/PcdLib.h>
|
#include <Library/TimerLib.h>
|
|
/* We are not ECAM compatible, so single bus multiple dev is a bit problem */
|
#define DROP_DEV1 1
|
|
/**
|
Assert the validity of a PCI address. A valid PCI address should contain 1's
|
only in the low 28 bits.
|
|
@param A The address to validate.
|
|
**/
|
#define ASSERT_INVALID_PCI_ADDRESS(A) \
|
ASSERT (((A) & ~0xfffffff) == 0)
|
|
/* Root port Entry, BDF Entries Count */
|
#define BDF_TABLE_ENTRY_SIZE 4
|
#define BDF_TABLE_HEADER_COUNT 2
|
#define BDF_TABLE_HEADER_SIZE 8
|
|
/* BDF table offsets for PCIe */
|
#define PCIE_BDF_TABLE_OFFSET 0
|
|
#define GET_BUS_NUM(Address) (((Address) >> 20) & 0x7F)
|
#define GET_DEV_NUM(Address) (((Address) >> 15) & 0x1F)
|
#define GET_FUNC_NUM(Address) (((Address) >> 12) & 0x07)
|
#define GET_REG_NUM(Address) ((Address) & 0xFFF)
|
|
/**
|
BDF Table structure : (Header + BDF Entries)
|
--------------------------------------------
|
[Offset 0x00] ROOT PORT ADDRESS
|
[Offset 0x04] BDF ENTRIES COUNT
|
[Offset 0x08] BDF ENTRY 0
|
[Offset 0x0C] BDF ENTRY 1
|
[Offset 0x10] BDF ENTRY 2
|
[Offset 0x14] BDF ENTRY 3
|
[Offset 0x18] BDF ENTRY 4
|
...
|
[Offset 0x--] BDF ENTRY N
|
--------------------------------------------
|
**/
|
|
/**
|
Value returned for reads on configuration space of unimplemented
|
device functions.
|
**/
|
//STATIC UINTN mDummyConfigData = 0xFFFFFFFF;
|
|
/**
|
Registers a PCI device so PCI configuration registers may be accessed after
|
SetVirtualAddressMap().
|
|
Registers the PCI device specified by Address so all the PCI configuration
|
registers associated with that PCI device may be accessed after SetVirtualAddressMap()
|
is called.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
Register.
|
|
@retval RETURN_SUCCESS The PCI device was registered for runtime access.
|
@retval RETURN_UNSUPPORTED An attempt was made to call this function
|
after ExitBootServices().
|
@retval RETURN_UNSUPPORTED The resources required to access the PCI device
|
at runtime could not be mapped.
|
@retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
|
complete the registration.
|
|
**/
|
RETURN_STATUS
|
EFIAPI
|
PciExpressRegisterForRuntimeAccess (
|
IN UINTN Address
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
return RETURN_UNSUPPORTED;
|
}
|
|
/*
|
* iATU Unroll-specific register definitions
|
* From 4.80 core version the address translation will be made by unroll.
|
* The registers are offset from atu_base
|
*/
|
#define PCIE_ATU_UNR_REGION_CTRL1 0x00
|
#define PCIE_ATU_UNR_REGION_CTRL2 0x04
|
#define PCIE_ATU_UNR_LOWER_BASE 0x08
|
#define PCIE_ATU_UNR_UPPER_BASE 0x0c
|
#define PCIE_ATU_UNR_LIMIT 0x10
|
#define PCIE_ATU_UNR_LOWER_TARGET 0x14
|
#define PCIE_ATU_UNR_UPPER_TARGET 0x18
|
|
#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
|
#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
|
#define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
|
#define PCIE_ATU_REGION_INDEX3 (0x3 << 0)
|
|
|
#define PCIE_ATU_TYPE_MEM (0x0 << 0)
|
#define PCIE_ATU_TYPE_IO (0x2 << 0)
|
#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
|
#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
|
#define PCIE_ATU_ENABLE (0x1 << 31)
|
#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
|
#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
|
#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
|
#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
|
|
/* Register address builder */
|
#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \
|
((0x3 << 20) | ((region) << 9))
|
#define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \
|
((0x3 << 20) | ((region) << 9) | (0x1 << 8))
|
|
/* Parameters for the waiting for iATU enabled routine */
|
#define LINK_WAIT_MAX_IATU_RETRIES 5
|
#define LINK_WAIT_IATU 10
|
|
#define upper_32_bits(n) ((UINT32)(((n) >> 16) >> 16))
|
#define lower_32_bits(n) ((UINT32)(n))
|
|
STATIC VOID rk_pcie_writel_ob_unroll(UINT32 index,
|
UINT32 reg, UINT32 val)
|
{
|
UINT32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
|
UINTN base = PcdGet64 (PcdPcieRootPortDbiBaseAddress);
|
|
MmioWrite32(base + offset + reg, val);
|
}
|
|
STATIC UINT32 rk_pcie_readl_ob_unroll(UINT32 index, UINT32 reg)
|
{
|
UINT32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
|
UINTN base = PcdGet64 (PcdPcieRootPortDbiBaseAddress);
|
|
return MmioRead32(base + offset + reg);
|
}
|
|
STATIC VOID rk_pcie_prog_outbound_atu_unroll(
|
UINT32 index, UINT32 type, UINT64 cpu_addr, UINT64 pci_addr, UINT32 size)
|
{
|
UINT32 retries, val;
|
|
DEBUG((EFI_D_INFO, "%s: ATU programmed with: index: %d, type: %d, cpu addr: %8llx, pci addr: %8llx, size: %8x\n",
|
__func__, index, type, cpu_addr, pci_addr, size));
|
|
rk_pcie_writel_ob_unroll(index, PCIE_ATU_UNR_LOWER_BASE, lower_32_bits(cpu_addr));
|
rk_pcie_writel_ob_unroll(index, PCIE_ATU_UNR_UPPER_BASE, upper_32_bits(cpu_addr));
|
rk_pcie_writel_ob_unroll(index, PCIE_ATU_UNR_LIMIT, lower_32_bits(cpu_addr + size - 1));
|
rk_pcie_writel_ob_unroll(index, PCIE_ATU_UNR_LOWER_TARGET, lower_32_bits(pci_addr));
|
rk_pcie_writel_ob_unroll(index, PCIE_ATU_UNR_UPPER_TARGET, upper_32_bits(pci_addr));
|
rk_pcie_writel_ob_unroll(index, PCIE_ATU_UNR_REGION_CTRL1, type);
|
rk_pcie_writel_ob_unroll(index, PCIE_ATU_UNR_REGION_CTRL2, PCIE_ATU_ENABLE);
|
|
/*
|
* Make sure ATU enable takes effect before any subsequent config
|
* and I/O accesses.
|
*/
|
for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
|
val = rk_pcie_readl_ob_unroll(index, PCIE_ATU_UNR_REGION_CTRL2);
|
if (val & PCIE_ATU_ENABLE)
|
return;
|
|
MicroSecondDelay(LINK_WAIT_IATU * 100);
|
}
|
|
DEBUG((DEBUG_ERROR, "outbound iATU is not being enabled\n"));
|
}
|
|
STATIC UINTN set_cfg_address(UINTN Address)
|
{
|
UINT8 bus, dev, func;
|
UINT32 reg;
|
UINTN va_address, d;
|
UINT32 atu_type;
|
|
bus = GET_BUS_NUM (Address);
|
dev = GET_DEV_NUM(Address);
|
func = GET_FUNC_NUM (Address);
|
reg = GET_REG_NUM(Address);
|
|
DEBUG((EFI_D_INFO, "set_cfg_address: bus %d, dev %d, func %d, reg 0x%x\n", bus, dev, func, reg));
|
|
rk_pcie_prog_outbound_atu_unroll(PCIE_ATU_REGION_INDEX0, PCIE_ATU_TYPE_MEM,
|
PcdGet32(PcdPcieRootPortMemBaseAddress), PcdGet32(PcdPcieRootPortMemBaseAddress), PcdGet32(PcdPcieRootPortMemSize));
|
|
//rk_pcie_prog_outbound_atu_unroll(PCIE_ATU_REGION_INDEX0, PCIE_ATU_TYPE_MEM, 0xf0200000,0xf0210000, 0x4000);
|
//rk_pcie_prog_outbound_atu_unroll(PCIE_ATU_REGION_INDEX2, PCIE_ATU_TYPE_MEM, 0xf0200000,0xf0200000, 0x100000);
|
rk_pcie_prog_outbound_atu_unroll(PCIE_ATU_REGION_INDEX2, PCIE_ATU_TYPE_IO,
|
PcdGet32(PcdPcieRootPortIoBaseAddress), PcdGet32(PcdPcieRootPortIoBaseAddress), PcdGet32(PcdPcieRootPortIoSize));
|
rk_pcie_prog_outbound_atu_unroll(PCIE_ATU_REGION_INDEX3, PCIE_ATU_TYPE_MEM,
|
PcdGet64(PcdPcieRootPortMemBaseAddress64), PcdGet64(PcdPcieRootPortMemBaseAddress64), PcdGet64(PcdPcieRootPortMemSize64));
|
|
/* Use dbi_base for own configuration read and write */
|
if (!bus) {
|
va_address = PcdGet64 (PcdPcieRootPortDbiBaseAddress);
|
goto out;
|
}
|
|
if (bus == 1)
|
/*
|
* For local bus whose primary bus number is root bridge,
|
* change TLP Type field to 4.
|
*/
|
atu_type = PCIE_ATU_TYPE_CFG0;
|
else
|
/* Otherwise, change TLP Type field to 5. */
|
atu_type = PCIE_ATU_TYPE_CFG1;
|
|
d = bus << 16 | dev << 8 | func;
|
va_address = PcdGet64 (PcdPcieRootPortCfgBaseAddress);
|
rk_pcie_prog_outbound_atu_unroll(PCIE_ATU_REGION_INDEX1, atu_type, va_address, d << 8, 0x100000);
|
|
out:
|
va_address += reg ;
|
|
return va_address;
|
}
|
|
/**
|
Reads an 8-bit PCI configuration register.
|
|
Reads and returns the 8-bit PCI configuration register specified by Address.
|
This function must guarantee that all PCI read and write operations are
|
serialized.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
Register.
|
|
@return The read value from the PCI configuration register.
|
|
**/
|
UINT8
|
EFIAPI
|
PciExpressRead8 (
|
IN UINTN Address
|
)
|
{
|
UINT8 val;
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
#if DROP_DEV1
|
if (GET_BUS_NUM(Address) ==0 && GET_DEV_NUM(Address) >= 1)
|
return 0xff;
|
#endif
|
val = MmioRead8(set_cfg_address(Address));
|
|
return val;
|
}
|
|
|
/**
|
Writes an 8-bit PCI configuration register.
|
|
Writes the 8-bit PCI configuration register specified by Address with the
|
value specified by Value. Value is returned. This function must guarantee
|
that all PCI read and write operations are serialized.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
Register.
|
@param Value The value to write.
|
|
@return The value written to the PCI configuration register.
|
|
**/
|
UINT8
|
EFIAPI
|
PciExpressWrite8 (
|
IN UINTN Address,
|
IN UINT8 Value
|
)
|
{
|
#if DROP_DEV1
|
if (GET_BUS_NUM(Address) ==0 && GET_DEV_NUM(Address) >= 1)
|
return Value;
|
#endif
|
return MmioWrite8(set_cfg_address(Address), Value);
|
}
|
|
/**
|
Performs a bitwise OR of an 8-bit PCI configuration register with
|
an 8-bit value.
|
|
Reads the 8-bit PCI configuration register specified by Address, performs a
|
bitwise OR between the read result and the value specified by
|
OrData, and writes the result to the 8-bit PCI configuration register
|
specified by Address. The value written to the PCI configuration register is
|
returned. This function must guarantee that all PCI read and write operations
|
are serialized.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
Register.
|
@param OrData The value to OR with the PCI configuration register.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT8
|
EFIAPI
|
PciExpressOr8 (
|
IN UINTN Address,
|
IN UINT8 OrData
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_DEV_NUM(Address) >= 1)
|
ASSERT(1);
|
#endif
|
return MmioOr8((UINTN)set_cfg_address (Address), OrData);
|
}
|
|
/**
|
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
|
value.
|
|
Reads the 8-bit PCI configuration register specified by Address, performs a
|
bitwise AND between the read result and the value specified by AndData, and
|
writes the result to the 8-bit PCI configuration register specified by
|
Address. The value written to the PCI configuration register is returned.
|
This function must guarantee that all PCI read and write operations are
|
serialized.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
Register.
|
@param AndData The value to AND with the PCI configuration register.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT8
|
EFIAPI
|
PciExpressAnd8 (
|
IN UINTN Address,
|
IN UINT8 AndData
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_DEV_NUM(Address) >= 1)
|
ASSERT(1);
|
#endif
|
return MmioAnd8 ((UINTN)set_cfg_address(Address), AndData);
|
}
|
|
/**
|
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
|
value, followed a bitwise OR with another 8-bit value.
|
|
Reads the 8-bit PCI configuration register specified by Address, performs a
|
bitwise AND between the read result and the value specified by AndData,
|
performs a bitwise OR between the result of the AND operation and
|
the value specified by OrData, and writes the result to the 8-bit PCI
|
configuration register specified by Address. The value written to the PCI
|
configuration register is returned. This function must guarantee that all PCI
|
read and write operations are serialized.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
Register.
|
@param AndData The value to AND with the PCI configuration register.
|
@param OrData The value to OR with the result of the AND operation.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT8
|
EFIAPI
|
PciExpressAndThenOr8 (
|
IN UINTN Address,
|
IN UINT8 AndData,
|
IN UINT8 OrData
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_DEV_NUM(Address) >= 1)
|
ASSERT(1);
|
#endif
|
return MmioAndThenOr8 (
|
(UINTN)set_cfg_address(Address),
|
AndData,
|
OrData
|
);
|
}
|
|
/**
|
Reads a bit field of a PCI configuration register.
|
|
Reads the bit field in an 8-bit PCI configuration register. The bit field is
|
specified by the StartBit and the EndBit. The value of the bit field is
|
returned.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
If StartBit is greater than 7, then ASSERT().
|
If EndBit is greater than 7, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
|
@param Address The PCI configuration register to read.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..7.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..7.
|
|
@return The value of the bit field read from the PCI configuration register.
|
|
**/
|
UINT8
|
EFIAPI
|
PciExpressBitFieldRead8 (
|
IN UINTN Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_DEV_NUM(Address) >= 1)
|
ASSERT(1);
|
#endif
|
return MmioBitFieldRead8 (
|
(UINTN)set_cfg_address(Address),
|
StartBit,
|
EndBit
|
);
|
}
|
|
/**
|
Writes a bit field to a PCI configuration register.
|
|
Writes Value to the bit field of the PCI configuration register. The bit
|
field is specified by the StartBit and the EndBit. All other bits in the
|
destination PCI configuration register are preserved. The new value of the
|
8-bit register is returned.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
If StartBit is greater than 7, then ASSERT().
|
If EndBit is greater than 7, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
@param Address The PCI configuration register to write.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..7.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..7.
|
@param Value The new value of the bit field.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT8
|
EFIAPI
|
PciExpressBitFieldWrite8 (
|
IN UINTN Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit,
|
IN UINT8 Value
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_DEV_NUM(Address) >= 1)
|
ASSERT(1);
|
#endif
|
return MmioBitFieldWrite8 (
|
(UINTN)set_cfg_address(Address),
|
StartBit,
|
EndBit,
|
Value
|
);
|
}
|
|
/**
|
Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
|
writes the result back to the bit field in the 8-bit port.
|
|
Reads the 8-bit PCI configuration register specified by Address, performs a
|
bitwise OR between the read result and the value specified by
|
OrData, and writes the result to the 8-bit PCI configuration register
|
specified by Address. The value written to the PCI configuration register is
|
returned. This function must guarantee that all PCI read and write operations
|
are serialized. Extra left bits in OrData are stripped.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
If StartBit is greater than 7, then ASSERT().
|
If EndBit is greater than 7, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
@param Address The PCI configuration register to write.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..7.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..7.
|
@param OrData The value to OR with the PCI configuration register.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT8
|
EFIAPI
|
PciExpressBitFieldOr8 (
|
IN UINTN Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit,
|
IN UINT8 OrData
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_DEV_NUM(Address) >= 1)
|
ASSERT(1);
|
#endif
|
return MmioBitFieldOr8 (
|
(UINTN)set_cfg_address(Address),
|
StartBit,
|
EndBit,
|
OrData
|
);
|
}
|
|
/**
|
Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
|
AND, and writes the result back to the bit field in the 8-bit register.
|
|
Reads the 8-bit PCI configuration register specified by Address, performs a
|
bitwise AND between the read result and the value specified by AndData, and
|
writes the result to the 8-bit PCI configuration register specified by
|
Address. The value written to the PCI configuration register is returned.
|
This function must guarantee that all PCI read and write operations are
|
serialized. Extra left bits in AndData are stripped.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
If StartBit is greater than 7, then ASSERT().
|
If EndBit is greater than 7, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
@param Address The PCI configuration register to write.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..7.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..7.
|
@param AndData The value to AND with the PCI configuration register.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT8
|
EFIAPI
|
PciExpressBitFieldAnd8 (
|
IN UINTN Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit,
|
IN UINT8 AndData
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_DEV_NUM(Address) >= 1)
|
ASSERT(1);
|
#endif
|
return MmioBitFieldAnd8 (
|
(UINTN)set_cfg_address(Address),
|
StartBit,
|
EndBit,
|
AndData
|
);
|
}
|
|
/**
|
Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
|
bitwise OR, and writes the result back to the bit field in the
|
8-bit port.
|
|
Reads the 8-bit PCI configuration register specified by Address, performs a
|
bitwise AND followed by a bitwise OR between the read result and
|
the value specified by AndData, and writes the result to the 8-bit PCI
|
configuration register specified by Address. The value written to the PCI
|
configuration register is returned. This function must guarantee that all PCI
|
read and write operations are serialized. Extra left bits in both AndData and
|
OrData are stripped.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
If StartBit is greater than 7, then ASSERT().
|
If EndBit is greater than 7, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
@param Address The PCI configuration register to write.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..7.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..7.
|
@param AndData The value to AND with the PCI configuration register.
|
@param OrData The value to OR with the result of the AND operation.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT8
|
EFIAPI
|
PciExpressBitFieldAndThenOr8 (
|
IN UINTN Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit,
|
IN UINT8 AndData,
|
IN UINT8 OrData
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_DEV_NUM(Address) >= 1)
|
ASSERT(1);
|
#endif
|
return MmioBitFieldAndThenOr8 (
|
(UINTN)set_cfg_address(Address),
|
StartBit,
|
EndBit,
|
AndData,
|
OrData
|
);
|
}
|
|
/**
|
Reads a 16-bit PCI configuration register.
|
|
Reads and returns the 16-bit PCI configuration register specified by Address.
|
This function must guarantee that all PCI read and write operations are
|
serialized.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
Register.
|
|
@return The read value from the PCI configuration register.
|
|
**/
|
UINT16
|
EFIAPI
|
PciExpressRead16 (
|
IN UINTN Address
|
)
|
{
|
UINT16 val;
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_BUS_NUM(Address) ==0 && GET_DEV_NUM(Address) >= 1)
|
return 0xffff;
|
|
#endif
|
val = MmioRead16 ((UINTN)set_cfg_address(Address));
|
|
return val;
|
}
|
|
/**
|
Writes a 16-bit PCI configuration register.
|
|
Writes the 16-bit PCI configuration register specified by Address with the
|
value specified by Value. Value is returned. This function must guarantee
|
that all PCI read and write operations are serialized.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
Register.
|
@param Value The value to write.
|
|
@return The value written to the PCI configuration register.
|
|
**/
|
UINT16
|
EFIAPI
|
PciExpressWrite16 (
|
IN UINTN Address,
|
IN UINT16 Value
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_BUS_NUM(Address) ==0 && GET_DEV_NUM(Address) >= 1)
|
return Value;
|
#endif
|
return MmioWrite16 ((UINTN)set_cfg_address (Address), Value);
|
}
|
|
/**
|
Performs a bitwise OR of a 16-bit PCI configuration register with
|
a 16-bit value.
|
|
Reads the 16-bit PCI configuration register specified by Address, performs a
|
bitwise OR between the read result and the value specified by
|
OrData, and writes the result to the 16-bit PCI configuration register
|
specified by Address. The value written to the PCI configuration register is
|
returned. This function must guarantee that all PCI read and write operations
|
are serialized.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
Register.
|
@param OrData The value to OR with the PCI configuration register.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT16
|
EFIAPI
|
PciExpressOr16 (
|
IN UINTN Address,
|
IN UINT16 OrData
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_DEV_NUM(Address) >= 1)
|
ASSERT(1);
|
#endif
|
return MmioOr16 ((UINTN)set_cfg_address (Address), OrData);
|
}
|
|
/**
|
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
|
value.
|
|
Reads the 16-bit PCI configuration register specified by Address, performs a
|
bitwise AND between the read result and the value specified by AndData, and
|
writes the result to the 16-bit PCI configuration register specified by
|
Address. The value written to the PCI configuration register is returned.
|
This function must guarantee that all PCI read and write operations are
|
serialized.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
Register.
|
@param AndData The value to AND with the PCI configuration register.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT16
|
EFIAPI
|
PciExpressAnd16 (
|
IN UINTN Address,
|
IN UINT16 AndData
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_DEV_NUM(Address) >= 1)
|
ASSERT(1);
|
#endif
|
return MmioAnd16 ((UINTN)set_cfg_address (Address), AndData);
|
}
|
|
/**
|
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
|
value, followed a bitwise OR with another 16-bit value.
|
|
Reads the 16-bit PCI configuration register specified by Address, performs a
|
bitwise AND between the read result and the value specified by AndData,
|
performs a bitwise OR between the result of the AND operation and
|
the value specified by OrData, and writes the result to the 16-bit PCI
|
configuration register specified by Address. The value written to the PCI
|
configuration register is returned. This function must guarantee that all PCI
|
read and write operations are serialized.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
Register.
|
@param AndData The value to AND with the PCI configuration register.
|
@param OrData The value to OR with the result of the AND operation.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT16
|
EFIAPI
|
PciExpressAndThenOr16 (
|
IN UINTN Address,
|
IN UINT16 AndData,
|
IN UINT16 OrData
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_DEV_NUM(Address) >= 1)
|
ASSERT(1);
|
#endif
|
return MmioAndThenOr16 (
|
(UINTN)set_cfg_address (Address),
|
AndData,
|
OrData
|
);
|
}
|
|
/**
|
Reads a bit field of a PCI configuration register.
|
|
Reads the bit field in a 16-bit PCI configuration register. The bit field is
|
specified by the StartBit and the EndBit. The value of the bit field is
|
returned.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
If StartBit is greater than 15, then ASSERT().
|
If EndBit is greater than 15, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
|
@param Address The PCI configuration register to read.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..15.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..15.
|
|
@return The value of the bit field read from the PCI configuration register.
|
|
**/
|
UINT16
|
EFIAPI
|
PciExpressBitFieldRead16 (
|
IN UINTN Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_DEV_NUM(Address) >= 1)
|
ASSERT(1);
|
#endif
|
return MmioBitFieldRead16 (
|
(UINTN)set_cfg_address (Address),
|
StartBit,
|
EndBit
|
);
|
}
|
|
/**
|
Writes a bit field to a PCI configuration register.
|
|
Writes Value to the bit field of the PCI configuration register. The bit
|
field is specified by the StartBit and the EndBit. All other bits in the
|
destination PCI configuration register are preserved. The new value of the
|
16-bit register is returned.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
If StartBit is greater than 15, then ASSERT().
|
If EndBit is greater than 15, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
@param Address The PCI configuration register to write.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..15.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..15.
|
@param Value The new value of the bit field.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT16
|
EFIAPI
|
PciExpressBitFieldWrite16 (
|
IN UINTN Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit,
|
IN UINT16 Value
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_DEV_NUM(Address) >= 1)
|
ASSERT(1);
|
#endif
|
return MmioBitFieldWrite16 (
|
(UINTN)set_cfg_address (Address),
|
StartBit,
|
EndBit,
|
Value
|
);
|
}
|
|
/**
|
Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
|
writes the result back to the bit field in the 16-bit port.
|
|
Reads the 16-bit PCI configuration register specified by Address, performs a
|
bitwise OR between the read result and the value specified by
|
OrData, and writes the result to the 16-bit PCI configuration register
|
specified by Address. The value written to the PCI configuration register is
|
returned. This function must guarantee that all PCI read and write operations
|
are serialized. Extra left bits in OrData are stripped.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
If StartBit is greater than 15, then ASSERT().
|
If EndBit is greater than 15, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
@param Address The PCI configuration register to write.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..15.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..15.
|
@param OrData The value to OR with the PCI configuration register.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT16
|
EFIAPI
|
PciExpressBitFieldOr16 (
|
IN UINTN Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit,
|
IN UINT16 OrData
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_DEV_NUM(Address) >= 1)
|
ASSERT(1);
|
#endif
|
return MmioBitFieldOr16 (
|
(UINTN)set_cfg_address (Address),
|
StartBit,
|
EndBit,
|
OrData
|
);
|
}
|
|
/**
|
Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
|
AND, and writes the result back to the bit field in the 16-bit register.
|
|
Reads the 16-bit PCI configuration register specified by Address, performs a
|
bitwise AND between the read result and the value specified by AndData, and
|
writes the result to the 16-bit PCI configuration register specified by
|
Address. The value written to the PCI configuration register is returned.
|
This function must guarantee that all PCI read and write operations are
|
serialized. Extra left bits in AndData are stripped.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
If StartBit is greater than 15, then ASSERT().
|
If EndBit is greater than 15, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
@param Address The PCI configuration register to write.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..15.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..15.
|
@param AndData The value to AND with the PCI configuration register.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT16
|
EFIAPI
|
PciExpressBitFieldAnd16 (
|
IN UINTN Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit,
|
IN UINT16 AndData
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_DEV_NUM(Address) >= 1)
|
ASSERT(1);
|
#endif
|
return MmioBitFieldAnd16 (
|
(UINTN)set_cfg_address (Address),
|
StartBit,
|
EndBit,
|
AndData
|
);
|
}
|
|
/**
|
Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
|
bitwise OR, and writes the result back to the bit field in the
|
16-bit port.
|
|
Reads the 16-bit PCI configuration register specified by Address, performs a
|
bitwise AND followed by a bitwise OR between the read result and
|
the value specified by AndData, and writes the result to the 16-bit PCI
|
configuration register specified by Address. The value written to the PCI
|
configuration register is returned. This function must guarantee that all PCI
|
read and write operations are serialized. Extra left bits in both AndData and
|
OrData are stripped.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
If StartBit is greater than 15, then ASSERT().
|
If EndBit is greater than 15, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
@param Address The PCI configuration register to write.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..15.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..15.
|
@param AndData The value to AND with the PCI configuration register.
|
@param OrData The value to OR with the result of the AND operation.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT16
|
EFIAPI
|
PciExpressBitFieldAndThenOr16 (
|
IN UINTN Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit,
|
IN UINT16 AndData,
|
IN UINT16 OrData
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_DEV_NUM(Address) >= 1)
|
ASSERT(1);
|
#endif
|
return MmioBitFieldAndThenOr16 (
|
(UINTN)set_cfg_address (Address),
|
StartBit,
|
EndBit,
|
AndData,
|
OrData
|
);
|
}
|
|
/**
|
Reads a 32-bit PCI configuration register.
|
|
Reads and returns the 32-bit PCI configuration register specified by Address.
|
This function must guarantee that all PCI read and write operations are
|
serialized.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
Register.
|
|
@return The read value from the PCI configuration register.
|
|
**/
|
UINT32
|
EFIAPI
|
PciExpressRead32 (
|
IN UINTN Address
|
)
|
{
|
UINT32 val;
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_BUS_NUM(Address) ==0 && GET_DEV_NUM(Address) >= 1)
|
return 0xffffffff;
|
#endif
|
val = MmioRead32 ((UINTN)set_cfg_address (Address));
|
return val;
|
|
}
|
|
/**
|
Writes a 32-bit PCI configuration register.
|
|
Writes the 32-bit PCI configuration register specified by Address with the
|
value specified by Value. Value is returned. This function must guarantee
|
that all PCI read and write operations are serialized.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
Register.
|
@param Value The value to write.
|
|
@return The value written to the PCI configuration register.
|
|
**/
|
UINT32
|
EFIAPI
|
PciExpressWrite32 (
|
IN UINTN Address,
|
IN UINT32 Value
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
|
#if DROP_DEV1
|
if (GET_BUS_NUM(Address) ==0 && GET_DEV_NUM(Address) >= 1)
|
return Value;
|
|
#endif
|
return MmioWrite32 ((UINTN)set_cfg_address (Address), Value);
|
}
|
|
/**
|
Performs a bitwise OR of a 32-bit PCI configuration register with
|
a 32-bit value.
|
|
Reads the 32-bit PCI configuration register specified by Address, performs a
|
bitwise OR between the read result and the value specified by
|
OrData, and writes the result to the 32-bit PCI configuration register
|
specified by Address. The value written to the PCI configuration register is
|
returned. This function must guarantee that all PCI read and write operations
|
are serialized.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
Register.
|
@param OrData The value to OR with the PCI configuration register.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT32
|
EFIAPI
|
PciExpressOr32 (
|
IN UINTN Address,
|
IN UINT32 OrData
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_DEV_NUM(Address) >= 1)
|
ASSERT(1);
|
#endif
|
return MmioOr32 ((UINTN)set_cfg_address (Address), OrData);
|
}
|
|
/**
|
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
|
value.
|
|
Reads the 32-bit PCI configuration register specified by Address, performs a
|
bitwise AND between the read result and the value specified by AndData, and
|
writes the result to the 32-bit PCI configuration register specified by
|
Address. The value written to the PCI configuration register is returned.
|
This function must guarantee that all PCI read and write operations are
|
serialized.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
Register.
|
@param AndData The value to AND with the PCI configuration register.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT32
|
EFIAPI
|
PciExpressAnd32 (
|
IN UINTN Address,
|
IN UINT32 AndData
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_DEV_NUM(Address) >= 1)
|
ASSERT(1);
|
#endif
|
return MmioAnd32 ((UINTN)set_cfg_address (Address), AndData);
|
}
|
|
/**
|
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
|
value, followed a bitwise OR with another 32-bit value.
|
|
Reads the 32-bit PCI configuration register specified by Address, performs a
|
bitwise AND between the read result and the value specified by AndData,
|
performs a bitwise OR between the result of the AND operation and
|
the value specified by OrData, and writes the result to the 32-bit PCI
|
configuration register specified by Address. The value written to the PCI
|
configuration register is returned. This function must guarantee that all PCI
|
read and write operations are serialized.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
Register.
|
@param AndData The value to AND with the PCI configuration register.
|
@param OrData The value to OR with the result of the AND operation.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT32
|
EFIAPI
|
PciExpressAndThenOr32 (
|
IN UINTN Address,
|
IN UINT32 AndData,
|
IN UINT32 OrData
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_DEV_NUM(Address) >= 1)
|
ASSERT(1);
|
#endif
|
return MmioAndThenOr32 (
|
(UINTN)set_cfg_address (Address),
|
AndData,
|
OrData
|
);
|
}
|
|
/**
|
Reads a bit field of a PCI configuration register.
|
|
Reads the bit field in a 32-bit PCI configuration register. The bit field is
|
specified by the StartBit and the EndBit. The value of the bit field is
|
returned.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
If StartBit is greater than 31, then ASSERT().
|
If EndBit is greater than 31, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
|
@param Address The PCI configuration register to read.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..31.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..31.
|
|
@return The value of the bit field read from the PCI configuration register.
|
|
**/
|
UINT32
|
EFIAPI
|
PciExpressBitFieldRead32 (
|
IN UINTN Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_DEV_NUM(Address) >= 1)
|
ASSERT(1);
|
#endif
|
return MmioBitFieldRead32 (
|
(UINTN)set_cfg_address (Address),
|
StartBit,
|
EndBit
|
);
|
}
|
|
/**
|
Writes a bit field to a PCI configuration register.
|
|
Writes Value to the bit field of the PCI configuration register. The bit
|
field is specified by the StartBit and the EndBit. All other bits in the
|
destination PCI configuration register are preserved. The new value of the
|
32-bit register is returned.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
If StartBit is greater than 31, then ASSERT().
|
If EndBit is greater than 31, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
@param Address The PCI configuration register to write.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..31.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..31.
|
@param Value The new value of the bit field.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT32
|
EFIAPI
|
PciExpressBitFieldWrite32 (
|
IN UINTN Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit,
|
IN UINT32 Value
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_DEV_NUM(Address) >= 1)
|
ASSERT(1);
|
#endif
|
return MmioBitFieldWrite32 (
|
(UINTN)set_cfg_address (Address),
|
StartBit,
|
EndBit,
|
Value
|
);
|
}
|
|
/**
|
Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
|
writes the result back to the bit field in the 32-bit port.
|
|
Reads the 32-bit PCI configuration register specified by Address, performs a
|
bitwise OR between the read result and the value specified by
|
OrData, and writes the result to the 32-bit PCI configuration register
|
specified by Address. The value written to the PCI configuration register is
|
returned. This function must guarantee that all PCI read and write operations
|
are serialized. Extra left bits in OrData are stripped.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
If StartBit is greater than 31, then ASSERT().
|
If EndBit is greater than 31, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
@param Address The PCI configuration register to write.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..31.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..31.
|
@param OrData The value to OR with the PCI configuration register.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT32
|
EFIAPI
|
PciExpressBitFieldOr32 (
|
IN UINTN Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit,
|
IN UINT32 OrData
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_DEV_NUM(Address) >= 1)
|
ASSERT(1);
|
#endif
|
return MmioBitFieldOr32 (
|
(UINTN)set_cfg_address (Address),
|
StartBit,
|
EndBit,
|
OrData
|
);
|
}
|
|
/**
|
Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
|
AND, and writes the result back to the bit field in the 32-bit register.
|
|
Reads the 32-bit PCI configuration register specified by Address, performs a
|
bitwise AND between the read result and the value specified by AndData, and
|
writes the result to the 32-bit PCI configuration register specified by
|
Address. The value written to the PCI configuration register is returned.
|
This function must guarantee that all PCI read and write operations are
|
serialized. Extra left bits in AndData are stripped.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
If StartBit is greater than 31, then ASSERT().
|
If EndBit is greater than 31, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
@param Address The PCI configuration register to write.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..31.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..31.
|
@param AndData The value to AND with the PCI configuration register.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT32
|
EFIAPI
|
PciExpressBitFieldAnd32 (
|
IN UINTN Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit,
|
IN UINT32 AndData
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_DEV_NUM(Address) >= 1)
|
ASSERT(1);
|
#endif
|
return MmioBitFieldAnd32 (
|
(UINTN)set_cfg_address (Address),
|
StartBit,
|
EndBit,
|
AndData
|
);
|
}
|
|
/**
|
Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
|
bitwise OR, and writes the result back to the bit field in the
|
32-bit port.
|
|
Reads the 32-bit PCI configuration register specified by Address, performs a
|
bitwise AND followed by a bitwise OR between the read result and
|
the value specified by AndData, and writes the result to the 32-bit PCI
|
configuration register specified by Address. The value written to the PCI
|
configuration register is returned. This function must guarantee that all PCI
|
read and write operations are serialized. Extra left bits in both AndData and
|
OrData are stripped.
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
If StartBit is greater than 31, then ASSERT().
|
If EndBit is greater than 31, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
@param Address The PCI configuration register to write.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..31.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..31.
|
@param AndData The value to AND with the PCI configuration register.
|
@param OrData The value to OR with the result of the AND operation.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT32
|
EFIAPI
|
PciExpressBitFieldAndThenOr32 (
|
IN UINTN Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit,
|
IN UINT32 AndData,
|
IN UINT32 OrData
|
)
|
{
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
#if DROP_DEV1
|
if (GET_DEV_NUM(Address) >= 1)
|
ASSERT(1);
|
#endif
|
return MmioBitFieldAndThenOr32 (
|
(UINTN)set_cfg_address (Address),
|
StartBit,
|
EndBit,
|
AndData,
|
OrData
|
);
|
}
|
|
/**
|
Reads a range of PCI configuration registers into a caller supplied buffer.
|
|
Reads the range of PCI configuration registers specified by StartAddress and
|
Size into the buffer specified by Buffer. This function only allows the PCI
|
configuration registers from a single PCI function to be read. Size is
|
returned. When possible 32-bit PCI configuration read cycles are used to read
|
from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
|
and 16-bit PCI configuration read cycles may be used at the beginning and the
|
end of the range.
|
|
If StartAddress > 0x0FFFFFFF, then ASSERT().
|
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
|
If Size > 0 and Buffer is NULL, then ASSERT().
|
|
@param StartAddress The starting address that encodes the PCI Bus, Device,
|
Function and Register.
|
@param Size The size in bytes of the transfer.
|
@param Buffer The pointer to a buffer receiving the data read.
|
|
@return Size read data from StartAddress.
|
|
**/
|
UINTN
|
EFIAPI
|
PciExpressReadBuffer (
|
IN UINTN StartAddress,
|
IN UINTN Size,
|
OUT VOID *Buffer
|
)
|
{
|
UINTN ReturnValue;
|
|
ASSERT_INVALID_PCI_ADDRESS (StartAddress);
|
//ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
|
if (GET_DEV_NUM(StartAddress) >= 1)
|
return 0xffffffff;
|
ASSERT(1);
|
|
if (Size == 0) {
|
return Size;
|
}
|
|
ASSERT (Buffer != NULL);
|
|
//
|
// Save Size for return
|
//
|
ReturnValue = Size;
|
|
if ((StartAddress & 1) != 0) {
|
//
|
// Read a byte if StartAddress is byte aligned
|
//
|
*(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);
|
StartAddress += sizeof (UINT8);
|
Size -= sizeof (UINT8);
|
Buffer = (UINT8*)Buffer + 1;
|
}
|
|
if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
|
//
|
// Read a word if StartAddress is word aligned
|
//
|
WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));
|
|
StartAddress += sizeof (UINT16);
|
Size -= sizeof (UINT16);
|
Buffer = (UINT16*)Buffer + 1;
|
}
|
|
while (Size >= sizeof (UINT32)) {
|
//
|
// Read as many double words as possible
|
//
|
WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress));
|
|
StartAddress += sizeof (UINT32);
|
Size -= sizeof (UINT32);
|
Buffer = (UINT32*)Buffer + 1;
|
}
|
|
if (Size >= sizeof (UINT16)) {
|
//
|
// Read the last remaining word if exist
|
//
|
WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));
|
StartAddress += sizeof (UINT16);
|
Size -= sizeof (UINT16);
|
Buffer = (UINT16*)Buffer + 1;
|
}
|
|
if (Size >= sizeof (UINT8)) {
|
//
|
// Read the last remaining byte if exist
|
//
|
*(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);
|
}
|
|
return ReturnValue;
|
}
|
|
/**
|
Copies the data in a caller supplied buffer to a specified range of PCI
|
configuration space.
|
|
Writes the range of PCI configuration registers specified by StartAddress and
|
Size from the buffer specified by Buffer. This function only allows the PCI
|
configuration registers from a single PCI function to be written. Size is
|
returned. When possible 32-bit PCI configuration write cycles are used to
|
write from StartAdress to StartAddress + Size. Due to alignment restrictions,
|
8-bit and 16-bit PCI configuration write cycles may be used at the beginning
|
and the end of the range.
|
|
If StartAddress > 0x0FFFFFFF, then ASSERT().
|
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
|
If Size > 0 and Buffer is NULL, then ASSERT().
|
|
@param StartAddress The starting address that encodes the PCI Bus, Device,
|
Function and Register.
|
@param Size The size in bytes of the transfer.
|
@param Buffer The pointer to a buffer containing the data to write.
|
|
@return Size written to StartAddress.
|
|
**/
|
UINTN
|
EFIAPI
|
PciExpressWriteBuffer (
|
IN UINTN StartAddress,
|
IN UINTN Size,
|
IN VOID *Buffer
|
)
|
{
|
UINTN ReturnValue;
|
|
ASSERT_INVALID_PCI_ADDRESS (StartAddress);
|
//ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
|
if (GET_DEV_NUM(StartAddress) >= 1)
|
return Size;
|
|
if (Size == 0) {
|
return 0;
|
}
|
|
ASSERT (Buffer != NULL);
|
|
//
|
// Save Size for return
|
//
|
ReturnValue = Size;
|
|
if ((StartAddress & 1) != 0) {
|
//
|
// Write a byte if StartAddress is byte aligned
|
//
|
PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
|
StartAddress += sizeof (UINT8);
|
Size -= sizeof (UINT8);
|
Buffer = (UINT8*)Buffer + 1;
|
}
|
|
if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
|
//
|
// Write a word if StartAddress is word aligned
|
//
|
PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));
|
StartAddress += sizeof (UINT16);
|
Size -= sizeof (UINT16);
|
Buffer = (UINT16*)Buffer + 1;
|
}
|
|
while (Size >= sizeof (UINT32)) {
|
//
|
// Write as many double words as possible
|
//
|
PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));
|
StartAddress += sizeof (UINT32);
|
Size -= sizeof (UINT32);
|
Buffer = (UINT32*)Buffer + 1;
|
}
|
|
if (Size >= sizeof (UINT16)) {
|
//
|
// Write the last remaining word if exist
|
//
|
PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));
|
StartAddress += sizeof (UINT16);
|
Size -= sizeof (UINT16);
|
Buffer = (UINT16*)Buffer + 1;
|
}
|
|
if (Size >= sizeof (UINT8)) {
|
//
|
// Write the last remaining byte if exist
|
//
|
PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
|
}
|
|
return ReturnValue;
|
}
|
