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/** @file
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Copyright (c) 2017, Linaro, Ltd. All rights reserved.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Uefi/UefiBaseType.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/TimerLib.h>
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#include <Library/BaseLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/AnalogixDpLib.h>
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#include <Library/PWMLib.h>
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#include <Library/DrmModes.h>
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VOID
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RockchipHdptxPhyInit(
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VOID
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)
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{
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/* start up sequence for phy */
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MmioWrite32(0xFD7F0A0C,0xFFFF8000);
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MmioWrite32(EDPTX_PHY_BASE+0x0C78,0x00);
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#if RK3588S_EVB1
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MmioWrite32(EDPTX_PHY_BASE+0x1478,0x00);
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#elif ARMPC
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MmioWrite32(EDPTX_PHY_BASE+0x1078,0x00);
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#else
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MmioWrite32(EDPTX_PHY_BASE+0x1078,0x04);
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#endif
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MmioWrite32(EDPTX_PHY_BASE+0x1878,0x00);
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MmioWrite32(HDPTXPHY0_GRF_BASE,0xFFFF0001);
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/* rockchip_hDptx_phy_power_on */
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MmioWrite32(EDPTX_PHY_BASE+0x0800,0x00);
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MmioWrite32(EDPTX_PHY_BASE+0x0818,0x02);
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/* rockchip_hDptx_phy_Dp_pll_init */
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MmioWrite32(EDPTX_PHY_BASE+0x0020,0x80);
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MmioWrite32(EDPTX_PHY_BASE+0x00F4,0xC0);
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MmioWrite32(EDPTX_PHY_BASE+0x0138,0x34);
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MmioWrite32(EDPTX_PHY_BASE+0x0144,0x87);
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MmioWrite32(0xFD5A402C,0xFFFF0011);
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MmioWrite32(EDPTX_PHY_BASE+0x0148,0x71);
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MmioWrite32(EDPTX_PHY_BASE+0x014C,0x71);
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MmioWrite32(EDPTX_PHY_BASE+0x0154,0x87);
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MmioWrite32(EDPTX_PHY_BASE+0x0158,0x71);
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MmioWrite32(EDPTX_PHY_BASE+0x015C,0x71);
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MmioWrite32(EDPTX_PHY_BASE+0x0164,0x11);
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MmioWrite32(EDPTX_PHY_BASE+0x0168,0x31);
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MmioWrite32(EDPTX_PHY_BASE+0x016C,0x03);
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MmioWrite32(EDPTX_PHY_BASE+0x0178,0x7F);
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MmioWrite32(EDPTX_PHY_BASE+0x017C,0x31);
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MmioWrite32(EDPTX_PHY_BASE+0x0180,0x21);
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MmioWrite32(EDPTX_PHY_BASE+0x0184,0x27);
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MmioWrite32(EDPTX_PHY_BASE+0x0188,0x27);
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MmioWrite32(EDPTX_PHY_BASE+0x0194,0x00);
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MmioWrite32(EDPTX_PHY_BASE+0x0198,0x0D);
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MmioWrite32(EDPTX_PHY_BASE+0x019C,0x0D);
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MmioWrite32(EDPTX_PHY_BASE+0x01A4,0x02);
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MmioWrite32(EDPTX_PHY_BASE+0x01A8,0x09);
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MmioWrite32(EDPTX_PHY_BASE+0x01B0,0x03);
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MmioWrite32(EDPTX_PHY_BASE+0x01B4,0x07);
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MmioWrite32(EDPTX_PHY_BASE+0x01B8,0x07);
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MmioWrite32(EDPTX_PHY_BASE+0x01C0,0x08);
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MmioWrite32(EDPTX_PHY_BASE+0x01C4,0x18);
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MmioWrite32(EDPTX_PHY_BASE+0x01C8,0x18);
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MmioWrite32(EDPTX_PHY_BASE+0x01D0,0x0F);
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MmioWrite32(EDPTX_PHY_BASE+0x01DC,0x08);
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MmioWrite32(EDPTX_PHY_BASE+0x0118,0xEE);
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MmioWrite32(EDPTX_PHY_BASE+0x011C,0x24);
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MmioWrite32(EDPTX_PHY_BASE+0x0204,0x01);
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MmioWrite32(EDPTX_PHY_BASE+0x025C,0x02);
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MmioWrite32(EDPTX_PHY_BASE+0x021C,0x04);
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MmioWrite32(EDPTX_PHY_BASE+0x0204,0x01);
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MmioWrite32(EDPTX_PHY_BASE+0x0264,0x84);
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MmioWrite32(EDPTX_PHY_BASE+0x0208,0x04);
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MmioWrite32(EDPTX_PHY_BASE+0x00F0,0x80);
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MmioWrite32(EDPTX_PHY_BASE+0x020C,0x24);
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MmioWrite32(EDPTX_PHY_BASE+0x0214,0x03);
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MmioWrite32(EDPTX_PHY_BASE+0x0210,0x20);
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MmioWrite32(EDPTX_PHY_BASE+0x0268,0x01);
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MmioWrite32(EDPTX_PHY_BASE+0x026C,0x10);
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MmioWrite32(0xFDEC03C8,0xC8);
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/* rockchip_hDptx_phy_Dp_aux_init */
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MmioWrite32(EDPTX_PHY_BASE+0x044C,0x13);
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MmioWrite32(EDPTX_PHY_BASE+0x0450,0x12);
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MmioWrite32(EDPTX_PHY_BASE+0x0454,0x12);
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MmioWrite32(EDPTX_PHY_BASE+0x0458,0x20);
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MmioWrite32(EDPTX_PHY_BASE+0x045C,0x04);
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MmioWrite32(EDPTX_PHY_BASE+0x0460,0x0A);
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MmioWrite32(EDPTX_PHY_BASE+0x0468,0x03);
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#if ARMPC
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MmioWrite32(EDPTX_PHY_BASE+0x046C,0x13);
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#else
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MmioWrite32(EDPTX_PHY_BASE+0x046C,0x03);
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#endif
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MmioWrite32(EDPTX_PHY_BASE+0x0470,0x04);
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MmioWrite32(EDPTX_PHY_BASE+0x0474,0x67);
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MmioWrite32(EDPTX_PHY_BASE+0x0478,0x6a);
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MmioWrite32(EDPTX_PHY_BASE+0x047C,0x16);
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MmioWrite32(EDPTX_PHY_BASE+0x0434,0x10);
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MmioWrite32(EDPTX_PHY_BASE+0x0440,0x03);
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MmioWrite32(EDPTX_PHY_BASE+0x043C,0xC0);
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MmioWrite32(EDPTX_PHY_BASE+0x0408,0x33);
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MmioWrite32(EDPTX_PHY_BASE+0x040C,0x1B);
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MmioWrite32(EDPTX_PHY_BASE+0x047C,0x16);
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MmioWrite32(EDPTX_PHY_BASE+0x0410,0x33);
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MmioWrite32(EDPTX_PHY_BASE+0x0480,0x80);
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MmioWrite32(EDPTX_PHY_BASE+0x040C,0x1B);//double
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MmioWrite32(EDPTX_PHY_BASE+0x0410,0x33);
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MmioWrite32(EDPTX_PHY_BASE+0x0408,0x33);
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MmioWrite32(EDPTX_PHY_BASE+0x043C,0xC0);
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MmioWrite32(EDPTX_PHY_BASE+0x0410,0x33);//double
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/* BGR_EN BIAS_EN */
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NanoSecondDelay (10000);
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MmioWrite32(HDPTXPHY0_GRF_BASE,0x10000);
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NanoSecondDelay (100000);
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MmioWrite32(HDPTXPHY0_GRF_BASE,0xFFFF0060);
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NanoSecondDelay (10000);
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MmioWrite32(EDPTX_PHY_BASE+0x040C,0x1B);
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MmioWrite32(EDPTX_PHY_BASE+0x0410,0x33);
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MmioWrite32(EDPTX_PHY_BASE+0x0408,0x33);
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MmioWrite32(EDPTX_PHY_BASE+0x043C,0xC0);
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MmioWrite32(EDPTX_PHY_BASE+0x0410,0x33);
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MmioWrite32(0xFED60028,0x83);
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MmioWrite32(0xFED60190,0x07);
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}
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VOID
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RockchipHdpPhySetRate(
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VOID
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)
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{
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DEBUG ((DEBUG_WARN, "[DRIVER]enter %a\n", __func__));
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/* RockchipHdpPhySetRate */
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MmioWrite32(HDPTXPHY0_GRF_BASE,0xFFFF0061);
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NanoSecondDelay (10000);
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#if ARMPC
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MmioWrite32(EDPTX_PHY_BASE+0x081C,0x03);
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MmioWrite32(EDPTX_PHY_BASE+0x0254,0x01);
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NanoSecondDelay (10000);
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#else
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MmioWrite32(EDPTX_PHY_BASE+0x081C,0x0F);
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MmioWrite32(EDPTX_PHY_BASE+0x0254,0x00);
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NanoSecondDelay (10000);
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#endif
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MmioWrite32(EDPTX_PHY_BASE+0x01D0,0x0F);
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MmioWrite32(EDPTX_PHY_BASE+0x01D4,0x0E);
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MmioWrite32(EDPTX_PHY_BASE+0x01D8,0x68);
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NanoSecondDelay (10000);
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#if ARMPC
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MmioWrite32(EDPTX_PHY_BASE+0x100C,0x26);
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#else
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MmioWrite32(EDPTX_PHY_BASE+0x100C,0x23);
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#endif
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MmioWrite32(EDPTX_PHY_BASE+0x1010,0x11);
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MmioWrite32(EDPTX_PHY_BASE+0x1014,0x44);
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MmioWrite32(EDPTX_PHY_BASE+0x101C,0x60);
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MmioWrite32(EDPTX_PHY_BASE+0x1040,0x03);
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#if ARMPC
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MmioWrite32(EDPTX_PHY_BASE+0x1044,0x04);
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#else
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MmioWrite32(EDPTX_PHY_BASE+0x1044,0x08);
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#endif
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MmioWrite32(EDPTX_PHY_BASE+0x1058,0x02);
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MmioWrite32(EDPTX_PHY_BASE+0x106C,0x01);
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#if ARMPC
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MmioWrite32(EDPTX_PHY_BASE+0x140C,0x00);
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MmioWrite32(EDPTX_PHY_BASE+0x1410,0x00);
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MmioWrite32(EDPTX_PHY_BASE+0x1414,0x00);
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MmioWrite32(EDPTX_PHY_BASE+0x1418,0x98);
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MmioWrite32(EDPTX_PHY_BASE+0x141C,0x00);
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MmioWrite32(EDPTX_PHY_BASE+0x1440,0x02);
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MmioWrite32(EDPTX_PHY_BASE+0x146C,0x00);
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MmioWrite32(EDPTX_PHY_BASE+0x180C,0x00);
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MmioWrite32(EDPTX_PHY_BASE+0x1818,0x98);
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MmioWrite32(EDPTX_PHY_BASE+0x181C,0x00);
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MmioWrite32(EDPTX_PHY_BASE+0x1840,0x02);
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MmioWrite32(EDPTX_PHY_BASE+0x1858,0x00);
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MmioWrite32(EDPTX_PHY_BASE+0x1854,0x21);
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MmioWrite32(EDPTX_PHY_BASE+0x186C,0x00);
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MmioWrite32(EDPTX_PHY_BASE+0x101C,0x60);
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MmioWrite32(EDPTX_PHY_BASE+0x141C,0x00);
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MmioWrite32(EDPTX_PHY_BASE+0x181C,0x00);
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#else
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MmioWrite32(EDPTX_PHY_BASE+0x140C,0x23);
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MmioWrite32(EDPTX_PHY_BASE+0x1410,0x11);
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MmioWrite32(EDPTX_PHY_BASE+0x1414,0x44);
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MmioWrite32(EDPTX_PHY_BASE+0x141C,0x38);
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MmioWrite32(EDPTX_PHY_BASE+0x1440,0x03);
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MmioWrite32(EDPTX_PHY_BASE+0x146C,0x01);
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MmioWrite32(EDPTX_PHY_BASE+0x180C,0x23);
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MmioWrite32(EDPTX_PHY_BASE+0x181C,0x60);
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MmioWrite32(EDPTX_PHY_BASE+0x1840,0x03);
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MmioWrite32(EDPTX_PHY_BASE+0x1858,0x02);
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MmioWrite32(EDPTX_PHY_BASE+0x186C,0x01);
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MmioWrite32(EDPTX_PHY_BASE+0x101C,0x38);
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MmioWrite32(EDPTX_PHY_BASE+0x141C,0x38);
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MmioWrite32(EDPTX_PHY_BASE+0x181C,0x38);
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#endif
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MmioWrite32(0xFED60028,0x83);
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MmioWrite32(0xFED60190,0xffff0007);
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MmioWrite32(0xFED6046C,0x13);
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MmioWrite32(0xFED60C10,0x11);
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MmioWrite32(0xFED60C14,0x44);
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MmioWrite32(0xFED60C40,0x03);
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MmioWrite32(0xFED60C58,0x02);
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#if ARMPC
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MmioWrite32(0xFED61028,0x10);
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MmioWrite32(0xFED61458,0x00);
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MmioWrite32(0xFED6145C,0x00);
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MmioWrite32(0xFED61810,0x00);
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MmioWrite32(0xFED61814,0x00);
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#else
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MmioWrite32(0xFED61028,0x17);
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MmioWrite32(0xFED61458,0x02);
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MmioWrite32(0xFED6145C,0x00);
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MmioWrite32(0xFED61810,0x11);
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MmioWrite32(0xFED61814,0x44);
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#endif
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MmioWrite32(HDPTXPHY0_GRF_BASE,0xFFFF00E1);
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}
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VOID
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RockchipHdptxPhySetVoltage (
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VOID
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)
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{
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DEBUG ((DEBUG_WARN, "[DRIVER]enter %a\n", __func__));
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/* RockchipHdptxPhySetVoltage */
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#if ARMPC
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MmioWrite32(EDPTX_PHY_BASE+0x0C28,0x10);
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MmioWrite32(EDPTX_PHY_BASE+0x0C30,0x00);
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MmioWrite32(EDPTX_PHY_BASE+0x0C44,0x04);
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NanoSecondDelay (10000);
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MmioWrite32(EDPTX_PHY_BASE+0x1828,0x00);
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MmioWrite32(EDPTX_PHY_BASE+0x1830,0x00);
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MmioWrite32(EDPTX_PHY_BASE+0x1844,0x00);
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NanoSecondDelay (10000);
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MmioWrite32(EDPTX_PHY_BASE+0x1028,0x10);
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MmioWrite32(EDPTX_PHY_BASE+0x1030,0x00);
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MmioWrite32(EDPTX_PHY_BASE+0x1044,0x04);
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NanoSecondDelay (10000);
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MmioWrite32(EDPTX_PHY_BASE+0x1428,0x00);
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MmioWrite32(EDPTX_PHY_BASE+0x1430,0x00);
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MmioWrite32(EDPTX_PHY_BASE+0x1444,0x00);
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NanoSecondDelay (10000);
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MmioWrite32(EDPTX_PHY_BASE+0x0c0c,0x26);
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MmioWrite32(EDPTX_PHY_BASE+0x0c1c,0x60);
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MmioWrite32(EDPTX_PHY_BASE+0x0c2c,0x70);
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MmioWrite32(EDPTX_PHY_BASE+0x0c34,0x70);
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MmioWrite32(EDPTX_PHY_BASE+0x0c6c,0x01);
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MmioWrite32(EDPTX_PHY_BASE+0x102c,0x70);
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MmioWrite32(EDPTX_PHY_BASE+0x1034,0x70);
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#else
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MmioWrite32(EDPTX_PHY_BASE+0x0C28,0x17);
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MmioWrite32(EDPTX_PHY_BASE+0x0C30,0x07);
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MmioWrite32(EDPTX_PHY_BASE+0x0C44,0x08);
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NanoSecondDelay (10000);
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MmioWrite32(EDPTX_PHY_BASE+0x1828,0x17);
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MmioWrite32(EDPTX_PHY_BASE+0x1844,0x08);
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NanoSecondDelay (10000);
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MmioWrite32(EDPTX_PHY_BASE+0x1028,0x17);
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MmioWrite32(EDPTX_PHY_BASE+0x1030,0x07);
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MmioWrite32(EDPTX_PHY_BASE+0x1044,0x08);
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NanoSecondDelay (10000);
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MmioWrite32(EDPTX_PHY_BASE+0x1428,0x17);
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MmioWrite32(EDPTX_PHY_BASE+0x1430,0x07);
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MmioWrite32(EDPTX_PHY_BASE+0x1444,0x08);
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NanoSecondDelay (10000);
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#endif
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}
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