/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
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*/
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#include "Include/Library/CruLib.h"
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include <Library/TimerLib.h>
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/** @addtogroup RK_HAL_Driver
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* @{
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*/
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/** @addtogroup CRU
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* @{
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*/
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/** @defgroup CRU_How_To_Use How To Use
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* @{
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The CRU driver can be used as follows:
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- Invoke cru functions to set clk rate, enable or disable clk, reset clk in each device.
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- The gate and soft reset id is include register offset and shift information:
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con_offset: id /16
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shift: id %16
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- The mux and div id is include register offset, shift, mask information:
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[15:0]: con
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[23:16]: shift
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[31:24]: width
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- CRU driver is just responsible for passing simple command data, And
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the usecount is the user's responsibility. Protection the usecount at the driver layer.
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- More details refer to APIs' descriptions as below.
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@} */
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/** @defgroup CRU_Private_Definition Private Definition
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* @{
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*/
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/********************* Private MACRO Definition ******************************/
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#define PWRDOWN_SHIT 13
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#define PWRDOWN_MASK 1 << PWRDOWN_SHIT
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#define PLL_POSTDIV1_SHIFT 12
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#define PLL_POSTDIV1_MASK 0x7 << PLL_POSTDIV1_SHIFT
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#define PLL_FBDIV_SHIFT 0
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#define PLL_FBDIV_MASK 0xfff << PLL_FBDIV_SHIFT
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#define PLL_POSTDIV2_SHIFT 6
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#define PLL_POSTDIV2_MASK 0x7 << PLL_POSTDIV2_SHIFT
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#define PLL_REFDIV_SHIFT 0
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#define PLL_REFDIV_MASK 0x3f << PLL_REFDIV_SHIFT
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#define PLL_DSMPD_SHIFT 12
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#define PLL_DSMPD_MASK 1 << PLL_DSMPD_SHIFT
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#define PLL_FRAC_SHIFT 0
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#define PLL_FRAC_MASK 0xffffff << PLL_FRAC_SHIFT
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#define PLLCON0_M_SHIFT 0
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#define PLLCON0_M_MASK 0x3ff << PLLCON0_M_SHIFT
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#define PLLCON1_P_SHIFT 0
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#define PLLCON1_P_MASK 0x3f << PLLCON1_P_SHIFT
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#define PLLCON1_S_SHIFT 6
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#define PLLCON1_S_MASK 0x7 << PLLCON1_S_SHIFT
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#define PLLCON2_K_SHIFT 0
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#define PLLCON2_K_MASK 0xffff << PLLCON2_K_SHIFT
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#define PLLCON1_PWRDOWN BIT(13)
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#define PLLCON6_LOCK_STATUS BIT(15)
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#define MIN_FOUTVCO_FREQ (800 * MHZ)
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#define MAX_FOUTVCO_FREQ (2000 * MHZ)
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#define MIN_FOUT_FREQ (24 * MHZ)
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#define MAX_FOUT_FREQ (1600 * MHZ)
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#define EXPONENT_OF_FRAC_PLL 24
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#define RK_PLL_MODE_SLOW 0
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#define RK_PLL_MODE_NORMAL 1
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#define RK_PLL_MODE_DEEP 2
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#define PLL_GET_PLLMODE(val, shift, mask) (((uint32_t)(val) & mask) >> shift)
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#define PLL_GET_FBDIV(x) (((uint32_t)(x) & (PLL_FBDIV_MASK)) >> PLL_FBDIV_SHIFT)
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#define PLL_GET_REFDIV(x) \
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(((uint32_t)(x) & (PLL_REFDIV_MASK)) >> PLL_REFDIV_SHIFT)
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#define PLL_GET_POSTDIV1(x) \
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(((uint32_t)(x) & (PLL_POSTDIV1_MASK)) >> PLL_POSTDIV1_SHIFT)
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#define PLL_GET_POSTDIV2(x) \
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(((uint32_t)(x) & (PLL_POSTDIV2_MASK)) >> PLL_POSTDIV2_SHIFT)
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#define PLL_GET_DSMPD(x) (((uint32_t)(x) & (PLL_DSMPD_MASK)) >> PLL_DSMPD_SHIFT)
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#define PLL_GET_FRAC(x) (((uint32_t)(x) & (PLL_FRAC_MASK)) >> PLL_FRAC_SHIFT)
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#define CRU_PLL_ROUND_UP_TO_KHZ(x) (HAL_DIV_ROUND_UP((x), KHZ) * KHZ)
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/********************* Private Structure Definition **************************/
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static struct PLL_CONFIG g_rockchipAutoTable;
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/********************* Private Variable Definition ***************************/
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/********************* Private Function Definition ***************************/
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/** Calculate the greatest common divisor */
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static uint32_t CRU_Gcd(uint32_t m, uint32_t n)
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{
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int t;
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while (m > 0) {
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if (n > m) {
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t = m;
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m = n;
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n = t;
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}
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m -= n;
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}
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return n;
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}
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/**
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* @brief Rockchip pll clk set postdiv.
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* @param foutHz: output freq
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* @param *postDiv1: pll postDiv1
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* @param *postDiv2: pll postDiv2
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* @param *foutVco: pll vco
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* @return HAL_Status.
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* How to calculate the PLL:
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* Formulas also embedded within the fractional PLL Verilog model:
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* If DSMPD = 1 (DSM is disabled, "integer mode")
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* FOUTVCO = FREF / REFDIV * FBDIV
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* FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
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* Where:
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* FOUTVCO = fractional PLL non-divided output frequency
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* FOUTPOSTDIV = fractional PLL divided output frequency
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* (output of second post divider)
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*/
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static HAL_Status CRU_PllSetPostDiv(uint32_t foutHz, uint32_t *postDiv1,
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uint32_t *postDiv2, uint32_t *foutVco)
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{
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uint32_t freq;
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if (foutHz < MIN_FOUTVCO_FREQ) {
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for (*postDiv1 = 1; *postDiv1 <= 7; (*postDiv1)++) {
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for (*postDiv2 = 1; *postDiv2 <= 7; (*postDiv2)++) {
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freq = foutHz * (*postDiv1) * (*postDiv2);
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if (freq >= MIN_FOUTVCO_FREQ && freq <= MAX_FOUTVCO_FREQ) {
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*foutVco = freq;
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return HAL_OK;
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}
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}
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}
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return HAL_ERROR;
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} else {
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*postDiv1 = 1;
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*postDiv2 = 1;
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return HAL_OK;
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}
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}
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/**
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* @brief Get pll parameter by auto.
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* @param finHz: pll intput freq
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* @param foutHz: pll output freq
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* @return struct PLL_CONFIG.
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* How to calculate the PLL:
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* Formulas also embedded within the fractional PLL Verilog model:
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* If DSMPD = 1 (DSM is disabled, "integer mode")
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* FOUTVCO = FREF / REFDIV * FBDIV
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* FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
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* Where:
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* FOUTVCO = fractional PLL non-divided output frequency
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* FOUTPOSTDIV = fractional PLL divided output frequency
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* (output of second post divider)
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* FREF = fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
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* REFDIV = fractional PLL input reference clock divider
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* FBDIV = Integer value programmed into feedback divide
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*/
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static const struct PLL_CONFIG *CRU_PllSetByAuto(uint32_t finHz,
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uint32_t foutHz)
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{
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struct PLL_CONFIG *rateTable = &g_rockchipAutoTable;
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uint32_t foutVco = foutHz;
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uint64_t fin64, frac64;
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uint32_t postDiv1, postDiv2;
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uint32_t clkGcd = 0;
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HAL_Status error;
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if (finHz == 0 || foutHz == 0 || foutHz == finHz) {
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return NULL;
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}
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error = CRU_PllSetPostDiv(foutHz, &postDiv1, &postDiv2, &foutVco);
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if (error) {
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return NULL;
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}
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rateTable->postDiv1 = postDiv1;
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rateTable->postDiv2 = postDiv2;
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rateTable->dsmpd = 1;
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if (finHz / MHZ * MHZ == finHz && foutHz / MHZ * MHZ == foutHz) {
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finHz /= MHZ;
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foutVco /= MHZ;
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clkGcd = CRU_Gcd(finHz, foutVco);
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rateTable->refDiv = finHz / clkGcd;
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rateTable->fbDiv = foutVco / clkGcd;
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rateTable->frac = 0;
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} else if (finHz / MHZ * MHZ != finHz) {
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clkGcd = foutHz / finHz;
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rateTable->fbDiv = clkGcd;
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rateTable->refDiv = 1;
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rateTable->postDiv1 = 1;
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rateTable->postDiv2 = 1;
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fin64 = foutHz * rateTable->refDiv;
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fin64 = HAL_DivU64(fin64 << EXPONENT_OF_FRAC_PLL, finHz);
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frac64 = rateTable->fbDiv;
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frac64 = rateTable->fbDiv << EXPONENT_OF_FRAC_PLL;
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frac64 = fin64 - frac64;
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rateTable->frac = frac64;
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if (rateTable->frac > 0) {
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rateTable->dsmpd = 0;
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}
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} else {
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clkGcd = CRU_Gcd(finHz / MHZ, foutVco / MHZ);
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rateTable->refDiv = finHz / MHZ / clkGcd;
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rateTable->fbDiv = foutVco / MHZ / clkGcd;
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rateTable->frac = 0;
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frac64 = (foutVco % MHZ);
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fin64 = finHz;
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frac64 = frac64 * rateTable->refDiv;
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frac64 = HAL_DivU64(frac64 << EXPONENT_OF_FRAC_PLL, fin64);
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rateTable->frac = frac64;
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if (rateTable->frac > 0) {
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rateTable->dsmpd = 0;
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}
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}
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return rateTable;
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}
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/**
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* @brief Get pll parameter by rateTable.
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* @param *pSetup: struct PLL_SETUP struct, Contains PLL register parameters
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* @param rate: pll target rate.
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* @return struct PLL_CONFIG.
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* How to calculate the PLL:
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* Look up the rateTable to get the PLL config parameter
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*/
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static const struct PLL_CONFIG *CRU_PllGetSettings(struct PLL_SETUP *pSetup,
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uint32_t rate)
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{
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const struct PLL_CONFIG *rateTable = pSetup->rateTable;
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if (rateTable == NULL) {
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return CRU_PllSetByAuto(PLL_INPUT_OSC_RATE, rate);
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}
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while (rateTable->rate) {
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if (rateTable->rate == rate) {
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break;
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}
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rateTable++;
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}
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if (rateTable->rate != rate) {
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return CRU_PllSetByAuto(PLL_INPUT_OSC_RATE, rate);
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} else {
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return rateTable;
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}
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}
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/** @} */
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/********************* Public Function Definition ****************************/
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/** @defgroup CRU_Exported_Functions_Group5 Other Functions
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* @attention these APIs allow direct use in the HAL layer.
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* @{
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*/
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/**
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* @brief Get pll freq.
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* @param *pSetup: struct PLL_SETUP struct,Contains PLL register parameters
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* @return pll rate.
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* How to calculate the PLL:
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* Formulas also embedded within the fractional PLL Verilog model:
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* If DSMPD = 1 (DSM is disabled, "integer mode")
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* FOUTVCO = FREF / REFDIV * FBDIV
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* FOUT = FOUTVCO / POSTDIV1 / POSTDIV2
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* If DSMPD = 0 (DSM is enabled, "fractional mode")
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* FOUTVCO = (FREF / REFDIV) * (FBDIV + FRAC / (2^24))
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* FOUTPOSTDIV = FOUTVCO / (POSTDIV1*POSTDIV2)
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* FOUT = FOUTVCO / POSTDIV1 / POSTDIV2
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*/
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uint32_t HAL_CRU_GetPllFreq(struct PLL_SETUP *pSetup)
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{
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uint32_t refDiv, fbDiv, postdDv1, postDiv2, frac, dsmpd;
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uint32_t mode = 0, rate = PLL_INPUT_OSC_RATE;
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mode = PLL_GET_PLLMODE(READ_REG(*(pSetup->modeOffset)), pSetup->modeShift,
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pSetup->modeMask);
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switch (mode) {
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case RK_PLL_MODE_SLOW:
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rate = PLL_INPUT_OSC_RATE;
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break;
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case RK_PLL_MODE_NORMAL:
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postdDv1 = PLL_GET_POSTDIV1(READ_REG(*(pSetup->conOffset0)));
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fbDiv = PLL_GET_FBDIV(READ_REG(*(pSetup->conOffset0)));
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postDiv2 = PLL_GET_POSTDIV2(READ_REG(*(pSetup->conOffset1)));
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refDiv = PLL_GET_REFDIV(READ_REG(*(pSetup->conOffset1)));
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dsmpd = PLL_GET_DSMPD(READ_REG(*(pSetup->conOffset1)));
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frac = PLL_GET_FRAC(READ_REG(*(pSetup->conOffset2)));
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rate = (rate / refDiv) * fbDiv;
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if (dsmpd == 0) {
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uint64_t fracRate = PLL_INPUT_OSC_RATE;
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fracRate *= frac;
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fracRate = fracRate >> EXPONENT_OF_FRAC_PLL;
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fracRate = fracRate / refDiv;
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rate += fracRate;
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}
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rate = rate / (postdDv1 * postDiv2);
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rate = CRU_PLL_ROUND_UP_TO_KHZ(rate);
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break;
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case RK_PLL_MODE_DEEP:
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default:
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rate = 32768;
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break;
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}
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return rate;
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}
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/**
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* @brief Set pll freq.
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* @param *pSetup: struct PLL_SETUP struct,Contains PLL register parameters
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* @param rate: pll set rate
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* @return HAL_Status.
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* How to calculate the PLL:
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* Force PLL into slow mode
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* Pll Power down
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* Pll Config fbDiv, refDiv, postdDv1, postDiv2, dsmpd, frac
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* Pll Power up
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* Waiting for pll lock
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* Force PLL into normal mode
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*/
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HAL_Status HAL_CRU_SetPllFreq(struct PLL_SETUP *pSetup, uint32_t rate)
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{
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const struct PLL_CONFIG *pConfig;
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int delay = 2400;
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if (rate == HAL_CRU_GetPllFreq(pSetup)) {
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return HAL_OK;
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} else if (rate < MIN_FOUT_FREQ) {
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return HAL_INVAL;
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} else if (rate > MAX_FOUT_FREQ) {
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return HAL_INVAL;
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}
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pConfig = CRU_PllGetSettings(pSetup, rate);
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if (!pConfig) {
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return HAL_ERROR;
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}
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/* Force PLL into slow mode to ensure output stable clock */
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WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_SLOW << pSetup->modeShift);
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/* Pll Power down */
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WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 1 << PWRDOWN_SHIT);
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/* Pll Config */
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WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_POSTDIV2_MASK, pConfig->postDiv2 << PLL_POSTDIV2_SHIFT);
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WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_REFDIV_MASK, pConfig->refDiv << PLL_REFDIV_SHIFT);
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WRITE_REG_MASK_WE(*(pSetup->conOffset0), PLL_POSTDIV1_MASK, pConfig->postDiv1 << PLL_POSTDIV1_SHIFT);
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WRITE_REG_MASK_WE(*(pSetup->conOffset0), PLL_FBDIV_MASK, pConfig->fbDiv << PLL_FBDIV_SHIFT);
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WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_DSMPD_MASK, pConfig->dsmpd << PLL_DSMPD_SHIFT);
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if (pConfig->frac) {
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WRITE_REG(*(pSetup->conOffset2), (READ_REG(*(pSetup->conOffset2)) & 0xff000000) | pConfig->frac);
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}
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/* Pll Power up */
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WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 0 << PWRDOWN_SHIT);
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/* Waiting for pll lock */
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while (delay > 0) {
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if (pSetup->stat0) {
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if (READ_REG(*(pSetup->stat0)) & (1 << pSetup->lockShift)) {
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break;
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}
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} else {
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if (READ_REG(*(pSetup->conOffset1)) & (1 << pSetup->lockShift)) {
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break;
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}
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}
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HAL_CPUDelayUs(1000);
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delay--;
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}
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if (delay == 0) {
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return HAL_TIMEOUT;
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}
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/* Force PLL into normal mode */
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WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_NORMAL << pSetup->modeShift);
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return HAL_OK;
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}
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/**
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* @brief Get pll v1 freq(RK3588).
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* @param *pSetup: struct PLL_SETUP struct,Contains PLL register parameters
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* @return pll rate.
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* How to calculate the PLL:
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* Formulas also embedded within the fractional PLL Verilog model:
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* If K = 0 (DSM is disabled, "integer mode")
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* FOUTVCO = FREF / P * M
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* FOUT = FOUTVCO / 2^S
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* If K > 0 (DSM is enabled, "fractional mode")
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* FOUTVCO = (FREF / P) * (M + K / 65536)
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* FOUT = FOUTVCO / 2^S
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*/
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uint32_t HAL_CRU_GetPllV1Freq(struct PLL_SETUP *pSetup)
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{
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uint32_t m, p, s, k;
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uint64_t rate = PLL_INPUT_OSC_RATE;
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uint32_t mode = 0;
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if (pSetup->modeMask)
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mode = PLL_GET_PLLMODE(READ_REG(*(pSetup->modeOffset)), pSetup->modeShift,
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pSetup->modeMask);
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else
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mode = RK_PLL_MODE_NORMAL;
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switch (mode) {
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case RK_PLL_MODE_SLOW:
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rate = PLL_INPUT_OSC_RATE;
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break;
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case RK_PLL_MODE_NORMAL:
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m = (READ_REG(*(pSetup->conOffset0)) & PLLCON0_M_MASK) >> PLLCON0_M_SHIFT;
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p = (READ_REG(*(pSetup->conOffset1)) & PLLCON1_P_MASK) >> PLLCON1_P_SHIFT;
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s = (READ_REG(*(pSetup->conOffset1)) & PLLCON1_S_MASK) >> PLLCON1_S_SHIFT;
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k = (READ_REG(*(pSetup->conOffset2)) & PLLCON2_K_MASK) >> PLLCON2_K_SHIFT;
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rate *= m;
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rate = rate / p;
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if (k) {
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/* fractional mode */
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uint64_t frac = PLL_INPUT_OSC_RATE / p;
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frac *= k;
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frac = frac / 65536;
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rate += frac;
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}
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rate = rate >> s;
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break;
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case RK_PLL_MODE_DEEP:
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default:
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rate = 32768;
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break;
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}
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return rate;
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}
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/**
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* @brief Set pll v1 freq(RK3588).
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* @param *pSetup: struct PLL_SETUP struct,Contains PLL register parameters
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* @param rate: pll set rate
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* @return HAL_Status.
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* How to calculate the PLL:
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* Force PLL into slow mode
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* Pll Power down
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* Pll Config M, P, S, K
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* Pll Power up
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* Waiting for pll lock
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* Force PLL into normal mode
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*/
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HAL_Status HAL_CRU_SetPllV1Freq(struct PLL_SETUP *pSetup, uint32_t rate)
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{
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const struct PLL_CONFIG *pConfig;
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int delay = 24000000;
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if (rate == HAL_CRU_GetPllV1Freq(pSetup)) {
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return HAL_OK;
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} else if (rate < MIN_FOUT_FREQ) {
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return HAL_INVAL;
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} else if (rate > MAX_FOUT_FREQ) {
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return HAL_INVAL;
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}
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pConfig = CRU_PllGetSettings(pSetup, rate);
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if (!pConfig) {
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return HAL_ERROR;
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}
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/* Force PLL into slow mode to ensure output stable clock */
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if (pSetup->modeMask)
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WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_SLOW << pSetup->modeShift);
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/* Pll Power down */
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WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 1 << PWRDOWN_SHIT);
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/* Pll Config */
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WRITE_REG_MASK_WE(*(pSetup->conOffset0), PLLCON0_M_MASK, pConfig->m << PLLCON0_M_SHIFT);
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WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLLCON1_P_MASK, pConfig->p << PLLCON1_P_SHIFT);
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WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLLCON1_S_MASK, pConfig->s << PLLCON1_S_SHIFT);
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if (pConfig->k)
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WRITE_REG_MASK_WE(*(pSetup->conOffset2), PLLCON2_K_MASK, pConfig->k << PLLCON2_K_SHIFT);
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/* Pll Power up */
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WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 0 << PWRDOWN_SHIT);
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/* Waiting for pll lock */
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while (delay > 0) {
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if (READ_REG(*(pSetup->conOffset6)) & (1 << pSetup->lockShift)) {
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break;
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}
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delay--;
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}
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if (delay == 0) {
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return HAL_TIMEOUT;
|
}
|
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/* Force PLL into normal mode */
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if (pSetup->modeMask)
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WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_NORMAL << pSetup->modeShift);
|
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return HAL_OK;
|
}
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/**
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* @brief Set pll power up.
|
* @param *pSetup: struct PLL_SETUP struct,Contains PLL register parameters
|
* @return HAL_Status.
|
*/
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HAL_Status HAL_CRU_SetPllPowerUp(struct PLL_SETUP *pSetup)
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{
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int delay = 2400;
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/* Pll Power up */
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WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 0 << PWRDOWN_SHIT);
|
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/* Waiting for pll lock */
|
while (delay > 0) {
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if (pSetup->stat0) {
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if (READ_REG(*(pSetup->stat0)) & (1 << pSetup->lockShift)) {
|
break;
|
}
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} else {
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if (READ_REG(*(pSetup->conOffset1)) & (1 << pSetup->lockShift)) {
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break;
|
}
|
}
|
HAL_CPUDelayUs(1000);
|
delay--;
|
}
|
if (delay == 0) {
|
return HAL_TIMEOUT;
|
}
|
|
return HAL_OK;
|
}
|
|
/**
|
* @brief Set pll power down.
|
* @param *pSetup: struct PLL_SETUP struct,Contains PLL register parameters
|
* @return HAL_Status.
|
*/
|
HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup)
|
{
|
/* Pll Power down */
|
WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 1 << PWRDOWN_SHIT);
|
|
return HAL_OK;
|
}
|
|
/**
|
* @brief IP Clock is Enabled API
|
* @param clk: clk gate id
|
* @return HAL_Check
|
*/
|
HAL_Check HAL_CRU_ClkIsEnabled(uint32_t clk)
|
{
|
uint32_t index = CLK_GATE_GET_REG_OFFSET(clk);
|
uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk);
|
HAL_Check ret;
|
|
#ifdef CRU_GATE_CON_CNT
|
if (index < CRU_GATE_CON_CNT) {
|
ret = (HAL_Check)(!((CRU->CRU_CLKGATE_CON[index] & (1 << shift)) >> shift));
|
} else {
|
#ifdef PMUCRU_BASE
|
ret = (HAL_Check)(!((PMUCRU->CRU_CLKGATE_CON[index - CRU_GATE_CON_CNT] & (1 << shift)) >> shift));
|
#else
|
ret = (HAL_Check)(!((CRU->PMU_CLKGATE_CON[index - CRU_GATE_CON_CNT] & (1 << shift)) >> shift));
|
#endif
|
}
|
#else
|
ret = (HAL_Check)(!((CRU->CRU_CLKGATE_CON[index] & (1 << shift)) >> shift));
|
#endif
|
|
return ret;
|
}
|
|
/**
|
* @brief IP Clock Enable API
|
* @param clk: clk gate id
|
* @return NONE
|
*/
|
HAL_Status HAL_CRU_ClkEnable(uint32_t clk)
|
{
|
uint32_t index = CLK_GATE_GET_REG_OFFSET(clk);
|
uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk);
|
|
#ifdef CRU_GATE_CON_CNT
|
if (index < CRU_GATE_CON_CNT) {
|
CRU->CRU_CLKGATE_CON[index] = VAL_MASK_WE(1U << shift, 0U << shift);
|
} else {
|
#ifdef PMUCRU_BASE
|
PMUCRU->CRU_CLKGATE_CON[index - CRU_GATE_CON_CNT] = VAL_MASK_WE(1U << shift, 0U << shift);
|
#else
|
CRU->PMU_CLKGATE_CON[index - CRU_GATE_CON_CNT] = VAL_MASK_WE(1U << shift, 0U << shift);
|
#endif
|
}
|
#else
|
CRU->CRU_CLKGATE_CON[index] = VAL_MASK_WE(1U << shift, 0U << shift);
|
#endif
|
|
return HAL_OK;
|
}
|
|
/**
|
* @brief IP Clock Disabled API
|
* @param clk: clk gate id
|
* @return NONE
|
*/
|
HAL_Status HAL_CRU_ClkDisable(uint32_t clk)
|
{
|
uint32_t index = CLK_GATE_GET_REG_OFFSET(clk);
|
uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk);
|
|
#ifdef CRU_GATE_CON_CNT
|
if (index < CRU_GATE_CON_CNT) {
|
CRU->CRU_CLKGATE_CON[index] = VAL_MASK_WE(1U << shift, 1U << shift);
|
} else {
|
#ifdef PMUCRU_BASE
|
PMUCRU->CRU_CLKGATE_CON[index - CRU_GATE_CON_CNT] = VAL_MASK_WE(1U << shift, 1U << shift);
|
#else
|
CRU->PMU_CLKGATE_CON[index - CRU_GATE_CON_CNT] = VAL_MASK_WE(1U << shift, 1U << shift);
|
#endif
|
}
|
#else
|
CRU->CRU_CLKGATE_CON[index] = VAL_MASK_WE(1U << shift, 1U << shift);
|
#endif
|
|
return HAL_OK;
|
}
|
|
/**
|
* @brief IP Clock is reset API
|
* @param clk: clk reset id
|
* @return HAL_Check
|
*/
|
HAL_Check HAL_CRU_ClkIsReset(uint32_t clk)
|
{
|
uint32_t index = CLK_GATE_GET_REG_OFFSET(clk);
|
uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk);
|
HAL_Check ret;
|
|
#ifdef CRU_SRST_CON_CNT
|
if (index < CRU_SRST_CON_CNT) {
|
ret = (HAL_Check)((CRU->CRU_CLKGATE_CON[index] & (1 << shift)) >> shift);
|
} else {
|
ret = (HAL_Check)((PMUCRU->CRU_CLKGATE_CON[index - CRU_SRST_CON_CNT] & (1 << shift)) >> shift);
|
}
|
#else
|
ret = (HAL_Check)((CRU->CRU_CLKGATE_CON[index] & (1 << shift)) >> shift);
|
#endif
|
|
return ret;
|
}
|
|
/**
|
* @brief IP Clock Reset Assert API
|
* @param clk: clk reset id
|
* @return NONE
|
*/
|
HAL_Status HAL_CRU_ClkResetAssert(uint32_t clk)
|
{
|
uint32_t index = CLK_RESET_GET_REG_OFFSET(clk);
|
uint32_t shift = CLK_RESET_GET_BITS_SHIFT(clk);
|
|
HAL_ASSERT(shift < 16);
|
#ifdef CRU_SRST_CON_CNT
|
if (index < CRU_SRST_CON_CNT) {
|
CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(1U << shift, 1U << shift);
|
} else {
|
PMUCRU->CRU_SOFTRST_CON[index - CRU_SRST_CON_CNT] = VAL_MASK_WE(1U << shift, 1U << shift);
|
}
|
#else
|
CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(1U << shift, 1U << shift);
|
#endif
|
|
return HAL_OK;
|
}
|
|
/**
|
* @brief IP Clock Reset Deassert API
|
* @param clk: clk reset id
|
* @return NONE
|
*/
|
HAL_Status HAL_CRU_ClkResetDeassert(uint32_t clk)
|
{
|
uint32_t index = CLK_RESET_GET_REG_OFFSET(clk);
|
uint32_t shift = CLK_RESET_GET_BITS_SHIFT(clk);
|
|
HAL_ASSERT(shift < 16);
|
#ifdef CRU_SRST_CON_CNT
|
if (index < CRU_SRST_CON_CNT) {
|
CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(1U << shift, 0U << shift);
|
} else {
|
PMUCRU->CRU_SOFTRST_CON[index - CRU_SRST_CON_CNT] = VAL_MASK_WE(1U << shift, 0U << shift);
|
}
|
#else
|
CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(1U << shift, 0U << shift);
|
#endif
|
|
return HAL_OK;
|
}
|
|
/**
|
* @brief IP Clock set div API
|
* @param divName: div id(Contains div offset, shift, mask information)
|
* @param divValue: div value
|
* @return NONE
|
*/
|
HAL_Status HAL_CRU_ClkSetDiv(uint32_t divName, uint32_t divValue)
|
{
|
uint32_t shift, mask, index;
|
|
index = CLK_DIV_GET_REG_OFFSET(divName);
|
shift = CLK_DIV_GET_BITS_SHIFT(divName);
|
HAL_ASSERT(shift < 16);
|
mask = CLK_DIV_GET_MASK(divName);
|
if (divValue > mask) {
|
divValue = mask;
|
}
|
|
#ifdef CRU_CLK_DIV_CON_CNT
|
if (index < CRU_CLK_DIV_CON_CNT) {
|
CRU->CRU_CLKSEL_CON[index] = VAL_MASK_WE(mask, (divValue - 1U) << shift);
|
} else {
|
#ifdef PMUCRU_BASE
|
PMUCRU->CRU_CLKSEL_CON[index - CRU_CLK_DIV_CON_CNT] = VAL_MASK_WE(mask, (divValue - 1U) << shift);
|
#else
|
CRU->PMU_CLKSEL_CON[index - CRU_CLK_DIV_CON_CNT] = VAL_MASK_WE(mask, (divValue - 1U) << shift);
|
#endif
|
}
|
#else
|
CRU->CRU_CLKSEL_CON[index] = VAL_MASK_WE(mask, (divValue - 1U) << shift);
|
#endif
|
|
return HAL_OK;
|
}
|
|
/**
|
* @brief IP Clock get div API
|
* @param divName: div id(Contains div offset, shift, mask information)
|
* @return div value
|
*/
|
uint32_t HAL_CRU_ClkGetDiv(uint32_t divName)
|
{
|
uint32_t shift, mask, index, divValue;
|
|
index = CLK_DIV_GET_REG_OFFSET(divName);
|
shift = CLK_DIV_GET_BITS_SHIFT(divName);
|
HAL_ASSERT(shift < 16);
|
mask = CLK_DIV_GET_MASK(divName);
|
|
#ifdef CRU_CLK_DIV_CON_CNT
|
if (index < CRU_CLK_DIV_CON_CNT) {
|
divValue = ((((CRU->CRU_CLKSEL_CON[index]) & mask) >> shift) + 1);
|
} else {
|
#ifdef PMUCRU_BASE
|
divValue = ((((PMUCRU->CRU_CLKSEL_CON[index - CRU_CLK_DIV_CON_CNT]) & mask) >> shift) + 1);
|
#else
|
divValue = ((((CRU->PMU_CLKSEL_CON[index - CRU_CLK_DIV_CON_CNT]) & mask) >> shift) + 1);
|
#endif
|
}
|
#else
|
divValue = ((((CRU->CRU_CLKSEL_CON[index]) & mask) >> shift) + 1);
|
#endif
|
|
return divValue;
|
}
|
|
/**
|
* @brief IP Clock set mux API
|
* @param muxName: mux id(Contains mux offset, shift, mask information)
|
* @param muxValue: mux value
|
* @return NONE
|
*/
|
HAL_SECTION_SRAM_CODE
|
HAL_Status HAL_CRU_ClkSetMux(uint32_t muxName, uint32_t muxValue)
|
{
|
uint32_t shift, mask, index;
|
|
index = CLK_MUX_GET_REG_OFFSET(muxName);
|
shift = CLK_MUX_GET_BITS_SHIFT(muxName);
|
HAL_ASSERT(shift < 16);
|
mask = CLK_MUX_GET_MASK(muxName);
|
|
#ifdef CRU_CLK_SEL_CON_CNT
|
if (index < CRU_CLK_DIV_CON_CNT) {
|
CRU->CRU_CLKSEL_CON[index] = VAL_MASK_WE(mask, muxValue << shift);
|
} else {
|
#ifdef PMUCRU_BASE
|
PMUCRU->CRU_CLKSEL_CON[index - CRU_CLK_SEL_CON_CNT] = VAL_MASK_WE(mask, muxValue << shift);
|
#else
|
CRU->PMU_CLKSEL_CON[index - CRU_CLK_SEL_CON_CNT] = VAL_MASK_WE(mask, muxValue << shift);
|
#endif
|
}
|
#else
|
CRU->CRU_CLKSEL_CON[index] = VAL_MASK_WE(mask, muxValue << shift);
|
#endif
|
|
return HAL_OK;
|
}
|
|
/**
|
* @brief IP Clock get mux API
|
* @param muxName: mux id(Contains mux offset, shift, mask information)
|
* @return mux value
|
*/
|
HAL_SECTION_SRAM_CODE
|
uint32_t HAL_CRU_ClkGetMux(uint32_t muxName)
|
{
|
uint32_t shift, mask, index, muxValue;
|
|
index = CLK_MUX_GET_REG_OFFSET(muxName);
|
shift = CLK_MUX_GET_BITS_SHIFT(muxName);
|
HAL_ASSERT(shift < 16);
|
mask = CLK_MUX_GET_MASK(muxName);
|
|
#ifdef CRU_CLK_SEL_CON_CNT
|
if (index < CRU_CLK_SEL_CON_CNT) {
|
muxValue = ((CRU->CRU_CLKSEL_CON[index] & mask) >> shift);
|
} else {
|
#ifdef PMUCRU_BASE
|
muxValue = ((PMUCRU->CRU_CLKSEL_CON[index - CRU_CLK_SEL_CON_CNT] & mask) >> shift);
|
#else
|
muxValue = ((CRU->PMU_CLKSEL_CON[index - CRU_CLK_SEL_CON_CNT] & mask) >> shift);
|
#endif
|
}
|
#else
|
muxValue = ((CRU->CRU_CLKSEL_CON[index] & mask) >> shift);
|
#endif
|
|
return muxValue;
|
}
|
|
/**
|
* @brief Get frac div config.
|
* @param rateOut: clk out rate.
|
* @param rate: clk src rate.
|
* @param numerator: the returned numerator.
|
* @param denominator: the returned denominator.
|
* @return HAL_Status.
|
*/
|
HAL_Status HAL_CRU_FracdivGetConfig(uint32_t rateOut, uint32_t rate,
|
uint32_t *numerator,
|
uint32_t *denominator)
|
{
|
uint32_t gcdVal;
|
|
gcdVal = CRU_Gcd(rate, rateOut);
|
if (!gcdVal) {
|
return HAL_ERROR;
|
}
|
|
*numerator = rateOut / gcdVal;
|
*denominator = rate / gcdVal;
|
|
if (*numerator < 4) {
|
*numerator *= 4;
|
*denominator *= 4;
|
}
|
if (*numerator > 0xffff || *denominator > 0xffff) {
|
return HAL_INVAL;
|
}
|
|
return HAL_OK;
|
}
|
|
/**
|
* @brief Get Np5 best div.
|
* @param clockName: clk id.
|
* @param rate: clk rate.
|
* @param pRate: clk parent rate
|
* @param bestdiv: the returned bestdiv.
|
* @return HAL_Status.
|
*/
|
HAL_Status HAL_CRU_ClkNp5BestDiv(eCLOCK_Name clockName, uint32_t rate, uint32_t pRate, uint32_t *bestdiv)
|
{
|
uint32_t div = CLK_GET_DIV(clockName);
|
uint32_t maxDiv = CLK_DIV_GET_MASK(div);
|
uint32_t i;
|
|
for (i = 0; i < maxDiv; i++) {
|
if (((pRate * 2) == (rate * (i * 2 + 3)))) {
|
*bestdiv = i;
|
|
return HAL_OK;
|
}
|
}
|
|
return HAL_ERROR;
|
}
|
|
/**
|
* @brief vop dclk enable.
|
* @param gateId: gate id
|
* @return HAL_Status.
|
* @attention these APIs allow direct use in the HAL layer.
|
*/
|
__WEAK HAL_Status HAL_CRU_VopDclkEnable(uint32_t gateId)
|
{
|
HAL_CRU_ClkEnable(gateId);
|
|
return HAL_OK;
|
}
|
|
/**
|
* @brief vop dclk disable.
|
* @param gateId: gate id
|
* @return HAL_Status.
|
* @attention these APIs allow direct use in the HAL layer.
|
*/
|
__WEAK HAL_Status HAL_CRU_VopDclkDisable(uint32_t gateId)
|
{
|
HAL_CRU_ClkDisable(gateId);
|
|
return HAL_OK;
|
}
|
|
/**
|
* @brief assert CRU global software reset.
|
* @param type: global software reset type.
|
* @return HAL_INVAL if the SoC does not support.
|
*/
|
HAL_Status HAL_CRU_SetGlbSrst(eCRU_GlbSrstType type)
|
{
|
#ifdef CRU_GLB_SRST_FST_VALUE_OFFSET
|
if (type == GLB_SRST_FST) {
|
CRU->GLB_SRST_FST_VALUE = GLB_SRST_FST;
|
}
|
#endif
|
#ifdef CRU_GLB_SRST_SND_VALUE_OFFSET
|
if (type == GLB_SRST_SND) {
|
CRU->GLB_SRST_SND_VALUE = GLB_SRST_SND;
|
}
|
#endif
|
|
return HAL_INVAL;
|
}
|
|
/** @} */
|
|
/** @} */
|
|
/** @} */
|
