/** @file
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Copyright (c) 2022 Rockchip Electronics Co. Ltd.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __VOP2_REGS_H__
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#define __VOP2_REGS_H__
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/* System registers definition */
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#define RK3568_REG_CFG_DONE 0x000
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#define CFG_DONE_EN BIT(15)
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#define RK3568_VERSION_INFO 0x004
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#define EN_MASK 1
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#define ALL_MASK 0xFFFFFFFF
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#define RK3568_AUTO_GATING_CTRL 0x008
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#define RK3568_SYS_AXI_LUT_CTRL 0x024
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#define LUT_DMA_EN_SHIFT 0
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#define RK3568_DSP_IF_EN 0x028
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#define RGB_EN_SHIFT 0
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#define RK3588_DP0_EN_SHIFT 0
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#define RK3588_DP1_EN_SHIFT 1
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#define RK3588_RGB_EN_SHIFT 8
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#define HDMI0_EN_SHIFT 1
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#define EDP0_EN_SHIFT 3
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#define RK3588_EDP0_EN_SHIFT 2
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#define RK3588_HDMI0_EN_SHIFT 3
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#define MIPI0_EN_SHIFT 4
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#define RK3588_EDP1_EN_SHIFT 4
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#define RK3588_HDMI1_EN_SHIFT 5
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#define RK3588_MIPI0_EN_SHIFT 6
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#define MIPI1_EN_SHIFT 20
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#define RK3588_MIPI1_EN_SHIFT 7
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#define LVDS0_EN_SHIFT 5
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#define LVDS1_EN_SHIFT 24
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#define BT1120_EN_SHIFT 6
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#define BT656_EN_SHIFT 7
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#define IF_MUX_MASK 3
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#define RGB_MUX_SHIFT 8
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#define HDMI0_MUX_SHIFT 10
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#define RK3588_DP0_MUX_SHIFT 12
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#define RK3588_DP1_MUX_SHIFT 14
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#define EDP0_MUX_SHIFT 14
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#define RK3588_HDMI_EDP0_MUX_SHIFT 16
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#define RK3588_HDMI_EDP1_MUX_SHIFT 18
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#define MIPI0_MUX_SHIFT 16
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#define RK3588_MIPI0_MUX_SHIFT 20
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#define MIPI1_MUX_SHIFT 21
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#define LVDS0_MUX_SHIFT 18
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#define LVDS1_MUX_SHIFT 25
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#define RK3568_DSP_IF_CTRL 0x02C
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#define LVDS_DUAL_EN_SHIFT 0
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#define LVDS_DUAL_LEFT_RIGHT_EN_SHIFT 1
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#define LVDS_DUAL_SWAP_EN_SHIFT 2
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#define RK3568_DSP_IF_POL 0x030
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#define IF_CTRL_REG_DONE_IMD_MASK 1
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#define IF_CTRL_REG_DONE_IMD_SHIFT 28
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#define IF_CRTL_MIPI_DCLK_POL_SHIT 19
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#define IF_CRTL_EDP_DCLK_POL_SHIT 15
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#define IF_CRTL_HDMI_DCLK_POL_SHIT 7
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#define IF_CRTL_HDMI_PIN_POL_MASK 0x7
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#define IF_CRTL_HDMI_PIN_POL_SHIT 4
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#define RK3588_DP0_PIN_POL_SHIFT 8
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#define RK3588_DP1_PIN_POL_SHIFT 12
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#define RK3588_IF_PIN_POL_MASK 0x7
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#define IF_CRTL_RGB_LVDS_DCLK_POL_SHIT 3
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#define HDMI_EDP0_DCLK_DIV_SHIFT 16
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#define HDMI_EDP0_PIXCLK_DIV_SHIFT 18
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#define HDMI_EDP1_DCLK_DIV_SHIFT 20
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#define HDMI_EDP1_PIXCLK_DIV_SHIFT 22
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#define MIPI0_PIXCLK_DIV_SHIFT 24
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#define MIPI1_PIXCLK_DIV_SHIFT 26
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#define RK3568_SYS_OTP_WIN_EN 0x50
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#define OTP_WIN_EN_SHIFT 0
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#define RK3568_SYS_LUT_PORT_SEL 0x58
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#define GAMMA_PORT_SEL_MASK 0x3
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#define GAMMA_PORT_SEL_SHIFT 0
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#define RK3568_MIPI_DUAL_EN_SHIFT 10
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#define RK3568_SYS_PD_CTRL 0x034
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#define RK3568_VP0_LINE_FLAG 0x70
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#define RK3568_VP1_LINE_FLAG 0x74
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#define RK3568_VP2_LINE_FLAG 0x78
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#define RK3568_SYS0_INT_EN 0x80
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#define RK3568_SYS0_INT_CLR 0x84
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#define RK3568_SYS0_INT_STATUS 0x88
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#define RK3568_SYS1_INT_EN 0x90
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#define RK3568_SYS1_INT_CLR 0x94
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#define RK3568_SYS1_INT_STATUS 0x98
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#define RK3568_VP0_INT_EN 0xA0
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#define RK3568_VP0_INT_CLR 0xA4
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#define RK3568_VP0_INT_STATUS 0xA8
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#define RK3568_VP1_INT_EN 0xB0
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#define RK3568_VP1_INT_CLR 0xB4
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#define RK3568_VP1_INT_STATUS 0xB8
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#define RK3568_VP2_INT_EN 0xC0
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#define RK3568_VP2_INT_CLR 0xC4
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#define RK3568_VP2_INT_STATUS 0xC8
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#define RK3588_CLUSTER0_PD_EN_SHIFT 0
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#define RK3588_CLUSTER1_PD_EN_SHIFT 1
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#define RK3588_CLUSTER2_PD_EN_SHIFT 2
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#define RK3588_CLUSTER3_PD_EN_SHIFT 3
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#define RK3588_ESMART_PD_EN_SHIFT 7
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#define RK3568_SYS_STATUS0 0x60
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#define RK3588_CLUSTER0_PD_STATUS_SHIFT 8
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#define RK3588_CLUSTER1_PD_STATUS_SHIFT 9
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#define RK3588_CLUSTER2_PD_STATUS_SHIFT 10
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#define RK3588_CLUSTER3_PD_STATUS_SHIFT 11
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#define RK3588_ESMART_PD_STATUS_SHIFT 15
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/* Overlay registers definition */
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#define RK3568_OVL_CTRL 0x600
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#define OVL_PORT_MUX_REG_DONE_IMD_SHIFT 28
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#define RK3568_OVL_LAYER_SEL 0x604
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#define LAYER_SEL_MASK 0xF
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#define RK3568_OVL_PORT_SEL 0x608
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#define PORT_MUX_MASK 0xF
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#define PORT_MUX_SHIFT 0
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#define LAYER_SEL_PORT_MASK 0x3
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#define LAYER_SEL_PORT_SHIFT 16
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#define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610
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#define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614
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#define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618
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#define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C
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#define RK3568_MIX0_SRC_COLOR_CTRL 0x650
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#define RK3568_MIX0_DST_COLOR_CTRL 0x654
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#define RK3568_MIX0_SRC_ALPHA_CTRL 0x658
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#define RK3568_MIX0_DST_ALPHA_CTRL 0x65C
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#define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0
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#define RK3568_HDR0_DST_COLOR_CTRL 0x6C4
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#define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8
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#define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC
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#define RK3568_VP0_BG_MIX_CTRL 0x6E0
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#define BG_MIX_CTRL_MASK 0xff
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#define BG_MIX_CTRL_SHIFT 24
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#define RK3568_VP1_BG_MIX_CTRL 0x6E4
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#define RK3568_VP2_BG_MIX_CTRL 0x6E8
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#define RK3568_CLUSTER_DLY_NUM 0x6F0
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#define RK3568_SMART_DLY_NUM 0x6F8
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/* Video Port registers definition */
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#define RK3568_VP0_DSP_CTRL 0xC00
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#define OUT_MODE_MASK 0xF
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#define OUT_MODE_SHIFT 0
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#define DATA_SWAP_MASK 0x1F
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#define DATA_SWAP_SHIFT 8
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#define DSP_BG_SWAP 0x1
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#define DSP_RB_SWAP 0x2
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#define DSP_RG_SWAP 0x4
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#define DSP_DELTA_SWAP 0x8
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#define CORE_DCLK_DIV_EN_SHIFT 4
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#define P2I_EN_SHIFT 5
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#define DSP_FILED_POL 6
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#define INTERLACE_EN_SHIFT 7
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#define POST_DSP_OUT_R2Y_SHIFT 15
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#define PRE_DITHER_DOWN_EN_SHIFT 16
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#define DITHER_DOWN_EN_SHIFT 17
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#define DSP_LUT_EN_SHIFT 28
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#define STANDBY_EN_SHIFT 31
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#define RK3568_VP0_MIPI_CTRL 0xC04
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#define DCLK_DIV2_SHIFT 4
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#define DCLK_DIV2_MASK 0x3
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#define MIPI_DUAL_EN_SHIFT 20
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#define MIPI_DUAL_SWAP_EN_SHIFT 21
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#define RK3568_VP0_COLOR_BAR_CTRL 0xC08
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#define RK3568_VP0_3D_LUT_CTRL 0xC10
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#define VP0_3D_LUT_EN_SHIFT 0
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#define VP0_3D_LUT_UPDATE_SHIFT 2
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#define RK3588_VP0_CLK_CTRL 0xC0C
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#define DCLK_CORE_DIV_SHIFT 0
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#define DCLK_OUT_DIV_SHIFT 2
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#define RK3568_VP0_3D_LUT_MST 0xC20
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#define RK3568_VP0_DSP_BG 0xC2C
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#define RK3568_VP0_PRE_SCAN_HTIMING 0xC30
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#define RK3568_VP0_POST_DSP_HACT_INFO 0xC34
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#define RK3568_VP0_POST_DSP_VACT_INFO 0xC38
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#define RK3568_VP0_POST_SCL_FACTOR_YRGB 0xC3C
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#define RK3568_VP0_POST_SCL_CTRL 0xC40
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#define RK3568_VP0_POST_DSP_VACT_INFO_F1 0xC44
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#define RK3568_VP0_DSP_HTOTAL_HS_END 0xC48
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#define RK3568_VP0_DSP_HACT_ST_END 0xC4C
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#define RK3568_VP0_DSP_VTOTAL_VS_END 0xC50
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#define RK3568_VP0_DSP_VACT_ST_END 0xC54
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#define RK3568_VP0_DSP_VS_ST_END_F1 0xC58
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#define RK3568_VP0_DSP_VACT_ST_END_F1 0xC5C
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#define RK3568_VP0_BCSH_CTRL 0xC60
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#define BCSH_CTRL_Y2R_SHIFT 0
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#define BCSH_CTRL_Y2R_MASK 0x1
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#define BCSH_CTRL_Y2R_CSC_MODE_SHIFT 2
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#define BCSH_CTRL_Y2R_CSC_MODE_MASK 0x3
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#define BCSH_CTRL_R2Y_SHIFT 4
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#define BCSH_CTRL_R2Y_MASK 0x1
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#define BCSH_CTRL_R2Y_CSC_MODE_SHIFT 6
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#define BCSH_CTRL_R2Y_CSC_MODE_MASK 0x3
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#define RK3568_VP0_BCSH_BCS 0xC64
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#define BCSH_BRIGHTNESS_SHIFT 0
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#define BCSH_BRIGHTNESS_MASK 0xFF
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#define BCSH_CONTRAST_SHIFT 8
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#define BCSH_CONTRAST_MASK 0x1FF
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#define BCSH_SATURATION_SHIFT 20
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#define BCSH_SATURATION_MASK 0x3FF
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#define BCSH_OUT_MODE_SHIFT 30
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#define BCSH_OUT_MODE_MASK 0x3
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#define RK3568_VP0_BCSH_H 0xC68
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#define BCSH_SIN_HUE_SHIFT 0
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#define BCSH_SIN_HUE_MASK 0x1FF
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#define BCSH_COS_HUE_SHIFT 16
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#define BCSH_COS_HUE_MASK 0x1FF
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#define RK3568_VP0_BCSH_COLOR 0xC6C
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#define BCSH_EN_SHIFT 31
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#define BCSH_EN_MASK 1
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#define RK3568_VP1_DSP_CTRL 0xD00
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#define RK3568_VP1_MIPI_CTRL 0xD04
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#define RK3568_VP1_COLOR_BAR_CTRL 0xD08
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#define RK3568_VP1_PRE_SCAN_HTIMING 0xD30
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#define RK3568_VP1_POST_DSP_HACT_INFO 0xD34
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#define RK3568_VP1_POST_DSP_VACT_INFO 0xD38
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#define RK3568_VP1_POST_SCL_FACTOR_YRGB 0xD3C
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#define RK3568_VP1_POST_SCL_CTRL 0xD40
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#define RK3568_VP1_DSP_HACT_INFO 0xD34
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#define RK3568_VP1_DSP_VACT_INFO 0xD38
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#define RK3568_VP1_POST_DSP_VACT_INFO_F1 0xD44
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#define RK3568_VP1_DSP_HTOTAL_HS_END 0xD48
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#define RK3568_VP1_DSP_HACT_ST_END 0xD4C
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#define RK3568_VP1_DSP_VTOTAL_VS_END 0xD50
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#define RK3568_VP1_DSP_VACT_ST_END 0xD54
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#define RK3568_VP1_DSP_VS_ST_END_F1 0xD58
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#define RK3568_VP1_DSP_VACT_ST_END_F1 0xD5C
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#define RK3568_VP2_DSP_CTRL 0xE00
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#define RK3568_VP2_MIPI_CTRL 0xE04
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#define RK3568_VP2_COLOR_BAR_CTRL 0xE08
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#define RK3568_VP2_PRE_SCAN_HTIMING 0xE30
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#define RK3568_VP2_POST_DSP_HACT_INFO 0xE34
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#define RK3568_VP2_POST_DSP_VACT_INFO 0xE38
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#define RK3568_VP2_POST_SCL_FACTOR_YRGB 0xE3C
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#define RK3568_VP2_POST_SCL_CTRL 0xE40
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#define RK3568_VP2_DSP_HACT_INFO 0xE34
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#define RK3568_VP2_DSP_VACT_INFO 0xE38
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#define RK3568_VP2_POST_DSP_VACT_INFO_F1 0xE44
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#define RK3568_VP2_DSP_HTOTAL_HS_END 0xE48
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#define RK3568_VP2_DSP_HACT_ST_END 0xE4C
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#define RK3568_VP2_DSP_VTOTAL_VS_END 0xE50
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#define RK3568_VP2_DSP_VACT_ST_END 0xE54
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#define RK3568_VP2_DSP_VS_ST_END_F1 0xE58
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#define RK3568_VP2_DSP_VACT_ST_END_F1 0xE5C
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/* Cluster0 register definition */
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#define RK3568_CLUSTER0_WIN0_CTRL0 0x1000
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#define CLUSTER_YUV2RGB_EN_SHIFT 8
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#define CLUSTER_RGB2YUV_EN_SHIFT 9
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#define CLUSTER_CSC_MODE_SHIFT 10
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#define CLUSTER_YRGB_XSCL_MODE_SHIFT 12
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#define CLUSTER_YRGB_YSCL_MODE_SHIFT 14
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#define RK3568_CLUSTER0_WIN0_CTRL1 0x1004
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#define CLUSTER_YRGB_GT2_SHIFT 28
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#define CLUSTER_YRGB_GT4_SHIFT 29
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#define RK3568_CLUSTER0_WIN0_YRGB_MST 0x1010
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#define RK3568_CLUSTER0_WIN0_CBR_MST 0x1014
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#define RK3568_CLUSTER0_WIN0_VIR 0x1018
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#define RK3568_CLUSTER0_WIN0_ACT_INFO 0x1020
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#define RK3568_CLUSTER0_WIN0_DSP_INFO 0x1024
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#define RK3568_CLUSTER0_WIN0_DSP_ST 0x1028
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#define RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB 0x1030
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#define RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE 0x1054
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#define RK3568_CLUSTER0_WIN0_AFBCD_HDR_PTR 0x1058
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#define RK3568_CLUSTER0_WIN0_AFBCD_VIR_WIDTH 0x105C
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#define RK3568_CLUSTER0_WIN0_AFBCD_PIC_SIZE 0x1060
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#define RK3568_CLUSTER0_WIN0_AFBCD_PIC_OFFSET 0x1064
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#define RK3568_CLUSTER0_WIN0_AFBCD_DSP_OFFSET 0x1068
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#define RK3568_CLUSTER0_WIN0_AFBCD_CTRL 0x106C
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#define RK3568_CLUSTER0_WIN1_CTRL0 0x1080
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#define RK3568_CLUSTER0_WIN1_CTRL1 0x1084
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#define RK3568_CLUSTER0_WIN1_YRGB_MST 0x1090
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#define RK3568_CLUSTER0_WIN1_CBR_MST 0x1094
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#define RK3568_CLUSTER0_WIN1_VIR 0x1098
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#define RK3568_CLUSTER0_WIN1_ACT_INFO 0x10A0
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#define RK3568_CLUSTER0_WIN1_DSP_INFO 0x10A4
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#define RK3568_CLUSTER0_WIN1_DSP_ST 0x10A8
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#define RK3568_CLUSTER0_WIN1_SCL_FACTOR_YRGB 0x10B0
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#define RK3568_CLUSTER0_WIN1_AFBCD_ROTATE_MODE 0x10D4
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#define RK3568_CLUSTER0_WIN1_AFBCD_HDR_PTR 0x10D8
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#define RK3568_CLUSTER0_WIN1_AFBCD_VIR_WIDTH 0x10DC
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#define RK3568_CLUSTER0_WIN1_AFBCD_PIC_SIZE 0x10E0
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#define RK3568_CLUSTER0_WIN1_AFBCD_PIC_OFFSET 0x10E4
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#define RK3568_CLUSTER0_WIN1_AFBCD_DSP_OFFSET 0x10E8
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#define RK3568_CLUSTER0_WIN1_AFBCD_CTRL 0x10EC
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#define RK3568_CLUSTER0_CTRL 0x1100
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#define CLUSTER_EN_SHIFT 0
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#define RK3568_CLUSTER1_WIN0_CTRL0 0x1200
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#define RK3568_CLUSTER1_WIN0_CTRL1 0x1204
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#define RK3568_CLUSTER1_WIN0_YRGB_MST 0x1210
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#define RK3568_CLUSTER1_WIN0_CBR_MST 0x1214
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#define RK3568_CLUSTER1_WIN0_VIR 0x1218
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#define RK3568_CLUSTER1_WIN0_ACT_INFO 0x1220
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#define RK3568_CLUSTER1_WIN0_DSP_INFO 0x1224
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#define RK3568_CLUSTER1_WIN0_DSP_ST 0x1228
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#define RK3568_CLUSTER1_WIN0_SCL_FACTOR_YRGB 0x1230
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#define RK3568_CLUSTER1_WIN0_AFBCD_ROTATE_MODE 0x1254
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#define RK3568_CLUSTER1_WIN0_AFBCD_HDR_PTR 0x1258
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#define RK3568_CLUSTER1_WIN0_AFBCD_VIR_WIDTH 0x125C
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#define RK3568_CLUSTER1_WIN0_AFBCD_PIC_SIZE 0x1260
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#define RK3568_CLUSTER1_WIN0_AFBCD_PIC_OFFSET 0x1264
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#define RK3568_CLUSTER1_WIN0_AFBCD_DSP_OFFSET 0x1268
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#define RK3568_CLUSTER1_WIN0_AFBCD_CTRL 0x126C
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#define RK3568_CLUSTER1_WIN1_CTRL0 0x1280
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#define RK3568_CLUSTER1_WIN1_CTRL1 0x1284
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#define RK3568_CLUSTER1_WIN1_YRGB_MST 0x1290
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#define RK3568_CLUSTER1_WIN1_CBR_MST 0x1294
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#define RK3568_CLUSTER1_WIN1_VIR 0x1298
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#define RK3568_CLUSTER1_WIN1_ACT_INFO 0x12A0
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#define RK3568_CLUSTER1_WIN1_DSP_INFO 0x12A4
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#define RK3568_CLUSTER1_WIN1_DSP_ST 0x12A8
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#define RK3568_CLUSTER1_WIN1_SCL_FACTOR_YRGB 0x12B0
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#define RK3568_CLUSTER1_WIN1_AFBCD_ROTATE_MODE 0x12D4
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#define RK3568_CLUSTER1_WIN1_AFBCD_HDR_PTR 0x12D8
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#define RK3568_CLUSTER1_WIN1_AFBCD_VIR_WIDTH 0x12DC
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#define RK3568_CLUSTER1_WIN1_AFBCD_PIC_SIZE 0x12E0
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#define RK3568_CLUSTER1_WIN1_AFBCD_PIC_OFFSET 0x12E4
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#define RK3568_CLUSTER1_WIN1_AFBCD_DSP_OFFSET 0x12E8
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#define RK3568_CLUSTER1_WIN1_AFBCD_CTRL 0x12EC
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#define RK3568_CLUSTER1_CTRL 0x1300
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/* Esmart register definition */
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#define RK3568_ESMART0_CTRL0 0x1800
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#define RGB2YUV_EN_SHIFT 1
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#define CSC_MODE_SHIFT 2
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#define CSC_MODE_MASK 0x3
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#define RK3568_ESMART0_CTRL1 0x1804
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#define YMIRROR_EN_SHIFT 31
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#define RK3568_ESMART0_REGION0_CTRL 0x1810
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#define REGION0_RB_SWAP_SHIFT 14
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#define WIN_EN_SHIFT 0
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#define WIN_FORMAT_MASK 0x1f
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#define WIN_FORMAT_SHIFT 1
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#define RK3568_ESMART0_REGION0_YRGB_MST 0x1814
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#define RK3568_ESMART0_REGION0_CBR_MST 0x1818
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#define RK3568_ESMART0_REGION0_VIR 0x181C
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#define RK3568_ESMART0_REGION0_ACT_INFO 0x1820
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#define RK3568_ESMART0_REGION0_DSP_INFO 0x1824
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#define RK3568_ESMART0_REGION0_DSP_ST 0x1828
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#define RK3568_ESMART0_REGION0_SCL_CTRL 0x1830
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#define YRGB_XSCL_MODE_MASK 0x3
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#define YRGB_XSCL_MODE_SHIFT 0
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#define YRGB_XSCL_FILTER_MODE_MASK 0x3
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#define YRGB_XSCL_FILTER_MODE_SHIFT 2
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#define YRGB_YSCL_MODE_MASK 0x3
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#define YRGB_YSCL_MODE_SHIFT 4
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#define YRGB_YSCL_FILTER_MODE_MASK 0x3
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#define YRGB_YSCL_FILTER_MODE_SHIFT 6
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#define RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB 0x1834
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#define RK3568_ESMART0_REGION0_SCL_FACTOR_CBR 0x1838
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#define RK3568_ESMART0_REGION0_SCL_OFFSET 0x183C
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#define RK3568_ESMART0_REGION1_CTRL 0x1840
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#define YRGB_GT2_MASK 0x1
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#define YRGB_GT2_SHIFT 8
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#define YRGB_GT4_MASK 0x1
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#define YRGB_GT4_SHIFT 9
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#define RK3568_ESMART0_REGION1_YRGB_MST 0x1844
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#define RK3568_ESMART0_REGION1_CBR_MST 0x1848
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#define RK3568_ESMART0_REGION1_VIR 0x184C
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#define RK3568_ESMART0_REGION1_ACT_INFO 0x1850
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#define RK3568_ESMART0_REGION1_DSP_INFO 0x1854
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#define RK3568_ESMART0_REGION1_DSP_ST 0x1858
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#define RK3568_ESMART0_REGION1_SCL_CTRL 0x1860
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#define RK3568_ESMART0_REGION1_SCL_FACTOR_YRGB 0x1864
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#define RK3568_ESMART0_REGION1_SCL_FACTOR_CBR 0x1868
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#define RK3568_ESMART0_REGION1_SCL_OFFSET 0x186C
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#define RK3568_ESMART0_REGION2_CTRL 0x1870
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#define RK3568_ESMART0_REGION2_YRGB_MST 0x1874
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#define RK3568_ESMART0_REGION2_CBR_MST 0x1878
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#define RK3568_ESMART0_REGION2_VIR 0x187C
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#define RK3568_ESMART0_REGION2_ACT_INFO 0x1880
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#define RK3568_ESMART0_REGION2_DSP_INFO 0x1884
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#define RK3568_ESMART0_REGION2_DSP_ST 0x1888
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#define RK3568_ESMART0_REGION2_SCL_CTRL 0x1890
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#define RK3568_ESMART0_REGION2_SCL_FACTOR_YRGB 0x1894
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#define RK3568_ESMART0_REGION2_SCL_FACTOR_CBR 0x1898
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#define RK3568_ESMART0_REGION2_SCL_OFFSET 0x189C
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#define RK3568_ESMART0_REGION3_CTRL 0x18A0
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#define RK3568_ESMART0_REGION3_YRGB_MST 0x18A4
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#define RK3568_ESMART0_REGION3_CBR_MST 0x18A8
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#define RK3568_ESMART0_REGION3_VIR 0x18AC
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#define RK3568_ESMART0_REGION3_ACT_INFO 0x18B0
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#define RK3568_ESMART0_REGION3_DSP_INFO 0x18B4
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#define RK3568_ESMART0_REGION3_DSP_ST 0x18B8
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#define RK3568_ESMART0_REGION3_SCL_CTRL 0x18C0
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#define RK3568_ESMART0_REGION3_SCL_FACTOR_YRGB 0x18C4
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#define RK3568_ESMART0_REGION3_SCL_FACTOR_CBR 0x18C8
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#define RK3568_ESMART0_REGION3_SCL_OFFSET 0x18CC
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#define RK3568_ESMART1_CTRL0 0x1A00
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#define RK3568_ESMART1_CTRL1 0x1A04
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#define RK3568_ESMART1_REGION0_CTRL 0x1A10
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#define RK3568_ESMART1_REGION0_YRGB_MST 0x1A14
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#define RK3568_ESMART1_REGION0_CBR_MST 0x1A18
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#define RK3568_ESMART1_REGION0_VIR 0x1A1C
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#define RK3568_ESMART1_REGION0_ACT_INFO 0x1A20
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#define RK3568_ESMART1_REGION0_DSP_INFO 0x1A24
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#define RK3568_ESMART1_REGION0_DSP_ST 0x1A28
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#define RK3568_ESMART1_REGION0_SCL_CTRL 0x1A30
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#define RK3568_ESMART1_REGION0_SCL_FACTOR_YRGB 0x1A34
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#define RK3568_ESMART1_REGION0_SCL_FACTOR_CBR 0x1A38
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#define RK3568_ESMART1_REGION0_SCL_OFFSET 0x1A3C
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#define RK3568_ESMART1_REGION1_CTRL 0x1A40
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#define RK3568_ESMART1_REGION1_YRGB_MST 0x1A44
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#define RK3568_ESMART1_REGION1_CBR_MST 0x1A48
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#define RK3568_ESMART1_REGION1_VIR 0x1A4C
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#define RK3568_ESMART1_REGION1_ACT_INFO 0x1A50
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#define RK3568_ESMART1_REGION1_DSP_INFO 0x1A54
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#define RK3568_ESMART1_REGION1_DSP_ST 0x1A58
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#define RK3568_ESMART1_REGION1_SCL_CTRL 0x1A60
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#define RK3568_ESMART1_REGION1_SCL_FACTOR_YRGB 0x1A64
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#define RK3568_ESMART1_REGION1_SCL_FACTOR_CBR 0x1A68
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#define RK3568_ESMART1_REGION1_SCL_OFFSET 0x1A6C
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#define RK3568_ESMART1_REGION2_CTRL 0x1A70
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#define RK3568_ESMART1_REGION2_YRGB_MST 0x1A74
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#define RK3568_ESMART1_REGION2_CBR_MST 0x1A78
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#define RK3568_ESMART1_REGION2_VIR 0x1A7C
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#define RK3568_ESMART1_REGION2_ACT_INFO 0x1A80
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#define RK3568_ESMART1_REGION2_DSP_INFO 0x1A84
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#define RK3568_ESMART1_REGION2_DSP_ST 0x1A88
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#define RK3568_ESMART1_REGION2_SCL_CTRL 0x1A90
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#define RK3568_ESMART1_REGION2_SCL_FACTOR_YRGB 0x1A94
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#define RK3568_ESMART1_REGION2_SCL_FACTOR_CBR 0x1A98
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#define RK3568_ESMART1_REGION2_SCL_OFFSET 0x1A9C
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#define RK3568_ESMART1_REGION3_CTRL 0x1AA0
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#define RK3568_ESMART1_REGION3_YRGB_MST 0x1AA4
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#define RK3568_ESMART1_REGION3_CBR_MST 0x1AA8
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#define RK3568_ESMART1_REGION3_VIR 0x1AAC
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#define RK3568_ESMART1_REGION3_ACT_INFO 0x1AB0
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#define RK3568_ESMART1_REGION3_DSP_INFO 0x1AB4
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#define RK3568_ESMART1_REGION3_DSP_ST 0x1AB8
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#define RK3568_ESMART1_REGION3_SCL_CTRL 0x1AC0
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#define RK3568_ESMART1_REGION3_SCL_FACTOR_YRGB 0x1AC4
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#define RK3568_ESMART1_REGION3_SCL_FACTOR_CBR 0x1AC8
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#define RK3568_ESMART1_REGION3_SCL_OFFSET 0x1ACC
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#define RK3568_SMART0_CTRL0 0x1C00
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#define RK3568_SMART0_CTRL1 0x1C04
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#define RK3568_SMART0_REGION0_CTRL 0x1C10
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#define RK3568_SMART0_REGION0_YRGB_MST 0x1C14
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#define RK3568_SMART0_REGION0_CBR_MST 0x1C18
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#define RK3568_SMART0_REGION0_VIR 0x1C1C
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#define RK3568_SMART0_REGION0_ACT_INFO 0x1C20
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#define RK3568_SMART0_REGION0_DSP_INFO 0x1C24
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#define RK3568_SMART0_REGION0_DSP_ST 0x1C28
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#define RK3568_SMART0_REGION0_SCL_CTRL 0x1C30
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#define RK3568_SMART0_REGION0_SCL_FACTOR_YRGB 0x1C34
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#define RK3568_SMART0_REGION0_SCL_FACTOR_CBR 0x1C38
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#define RK3568_SMART0_REGION0_SCL_OFFSET 0x1C3C
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#define RK3568_SMART0_REGION1_CTRL 0x1C40
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#define RK3568_SMART0_REGION1_YRGB_MST 0x1C44
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#define RK3568_SMART0_REGION1_CBR_MST 0x1C48
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#define RK3568_SMART0_REGION1_VIR 0x1C4C
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#define RK3568_SMART0_REGION1_ACT_INFO 0x1C50
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#define RK3568_SMART0_REGION1_DSP_INFO 0x1C54
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#define RK3568_SMART0_REGION1_DSP_ST 0x1C58
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#define RK3568_SMART0_REGION1_SCL_CTRL 0x1C60
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#define RK3568_SMART0_REGION1_SCL_FACTOR_YRGB 0x1C64
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#define RK3568_SMART0_REGION1_SCL_FACTOR_CBR 0x1C68
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#define RK3568_SMART0_REGION1_SCL_OFFSET 0x1C6C
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#define RK3568_SMART0_REGION2_CTRL 0x1C70
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#define RK3568_SMART0_REGION2_YRGB_MST 0x1C74
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#define RK3568_SMART0_REGION2_CBR_MST 0x1C78
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#define RK3568_SMART0_REGION2_VIR 0x1C7C
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#define RK3568_SMART0_REGION2_ACT_INFO 0x1C80
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#define RK3568_SMART0_REGION2_DSP_INFO 0x1C84
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#define RK3568_SMART0_REGION2_DSP_ST 0x1C88
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#define RK3568_SMART0_REGION2_SCL_CTRL 0x1C90
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#define RK3568_SMART0_REGION2_SCL_FACTOR_YRGB 0x1C94
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#define RK3568_SMART0_REGION2_SCL_FACTOR_CBR 0x1C98
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#define RK3568_SMART0_REGION2_SCL_OFFSET 0x1C9C
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#define RK3568_SMART0_REGION3_CTRL 0x1CA0
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#define RK3568_SMART0_REGION3_YRGB_MST 0x1CA4
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#define RK3568_SMART0_REGION3_CBR_MST 0x1CA8
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#define RK3568_SMART0_REGION3_VIR 0x1CAC
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#define RK3568_SMART0_REGION3_ACT_INFO 0x1CB0
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#define RK3568_SMART0_REGION3_DSP_INFO 0x1CB4
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#define RK3568_SMART0_REGION3_DSP_ST 0x1CB8
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#define RK3568_SMART0_REGION3_SCL_CTRL 0x1CC0
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#define RK3568_SMART0_REGION3_SCL_FACTOR_YRGB 0x1CC4
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#define RK3568_SMART0_REGION3_SCL_FACTOR_CBR 0x1CC8
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#define RK3568_SMART0_REGION3_SCL_OFFSET 0x1CCC
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#define RK3568_SMART1_CTRL0 0x1E00
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#define RK3568_SMART1_CTRL1 0x1E04
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#define RK3568_SMART1_REGION0_CTRL 0x1E10
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#define RK3568_SMART1_REGION0_YRGB_MST 0x1E14
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#define RK3568_SMART1_REGION0_CBR_MST 0x1E18
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#define RK3568_SMART1_REGION0_VIR 0x1E1C
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#define RK3568_SMART1_REGION0_ACT_INFO 0x1E20
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#define RK3568_SMART1_REGION0_DSP_INFO 0x1E24
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#define RK3568_SMART1_REGION0_DSP_ST 0x1E28
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#define RK3568_SMART1_REGION0_SCL_CTRL 0x1E30
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#define RK3568_SMART1_REGION0_SCL_FACTOR_YRGB 0x1E34
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#define RK3568_SMART1_REGION0_SCL_FACTOR_CBR 0x1E38
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#define RK3568_SMART1_REGION0_SCL_OFFSET 0x1E3C
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#define RK3568_SMART1_REGION1_CTRL 0x1E40
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#define RK3568_SMART1_REGION1_YRGB_MST 0x1E44
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#define RK3568_SMART1_REGION1_CBR_MST 0x1E48
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#define RK3568_SMART1_REGION1_VIR 0x1E4C
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#define RK3568_SMART1_REGION1_ACT_INFO 0x1E50
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#define RK3568_SMART1_REGION1_DSP_INFO 0x1E54
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#define RK3568_SMART1_REGION1_DSP_ST 0x1E58
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#define RK3568_SMART1_REGION1_SCL_CTRL 0x1E60
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#define RK3568_SMART1_REGION1_SCL_FACTOR_YRGB 0x1E64
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#define RK3568_SMART1_REGION1_SCL_FACTOR_CBR 0x1E68
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#define RK3568_SMART1_REGION1_SCL_OFFSET 0x1E6C
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#define RK3568_SMART1_REGION2_CTRL 0x1E70
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#define RK3568_SMART1_REGION2_YRGB_MST 0x1E74
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#define RK3568_SMART1_REGION2_CBR_MST 0x1E78
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#define RK3568_SMART1_REGION2_VIR 0x1E7C
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#define RK3568_SMART1_REGION2_ACT_INFO 0x1E80
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#define RK3568_SMART1_REGION2_DSP_INFO 0x1E84
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#define RK3568_SMART1_REGION2_DSP_ST 0x1E88
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#define RK3568_SMART1_REGION2_SCL_CTRL 0x1E90
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#define RK3568_SMART1_REGION2_SCL_FACTOR_YRGB 0x1E94
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#define RK3568_SMART1_REGION2_SCL_FACTOR_CBR 0x1E98
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#define RK3568_SMART1_REGION2_SCL_OFFSET 0x1E9C
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#define RK3568_SMART1_REGION3_CTRL 0x1EA0
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#define RK3568_SMART1_REGION3_YRGB_MST 0x1EA4
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#define RK3568_SMART1_REGION3_CBR_MST 0x1EA8
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#define RK3568_SMART1_REGION3_VIR 0x1EAC
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#define RK3568_SMART1_REGION3_ACT_INFO 0x1EB0
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#define RK3568_SMART1_REGION3_DSP_INFO 0x1EB4
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#define RK3568_SMART1_REGION3_DSP_ST 0x1EB8
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#define RK3568_SMART1_REGION3_SCL_CTRL 0x1EC0
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#define RK3568_SMART1_REGION3_SCL_FACTOR_YRGB 0x1EC4
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#define RK3568_SMART1_REGION3_SCL_FACTOR_CBR 0x1EC8
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#define RK3568_SMART1_REGION3_SCL_OFFSET 0x1ECC
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#define RK3568_MAX_REG 0x1ED0
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#define RK3588_VOP2_REG_BASE 0xFDD90000
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#define RK3568_SYS_CTRL_LINE_FLAG0 0x70
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#define LINE_FLAG_NUM_MASK 0x1FFF
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#define RK3568_DSP_LINE_FLAG_NUM0_SHIFT 0
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#define RK3568_DSP_LINE_FLAG_NUM1_SHIFT 16
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#define RK3588_VOP_GRF_BASE 0xFD5A4000
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#define RK3588_GRF_VOP_CON2 0x0008
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#define RK3588_GRF_EDP0_ENABLE_SHIFT 0
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#define RK3588_GRF_HDMITX0_ENABLE_SHIFT 1
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#define RK3588_GRF_EDP1_ENABLE_SHIFT 3
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#define RK3588_GRF_HDMITX1_ENABLE_SHIFT 4
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#define RK3588_VO0_GRF_BASE 0xFD5A6000
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#define RK3588_VO1_GRF_BASE 0xFD5A8000
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#define RK3588_PMU_BISR_CON3 0x20C
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#define RK3588_PD_CLUSTER0_REPAIR_EN_SHIFT 9
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#define RK3588_PD_CLUSTER1_REPAIR_EN_SHIFT 10
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#define RK3588_PD_CLUSTER2_REPAIR_EN_SHIFT 11
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#define RK3588_PD_CLUSTER3_REPAIR_EN_SHIFT 12
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#define RK3588_PD_ESMART_REPAIR_EN_SHIFT 15
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#define RK3588_PMU_BISR_STATUS5 0x294
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#define RK3588_PD_CLUSTER0_PWR_STAT_SHIFI 9
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#define RK3588_PD_CLUSTER1_PWR_STAT_SHIFI 10
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#define RK3588_PD_CLUSTER2_PWR_STAT_SHIFI 11
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#define RK3588_PD_CLUSTER3_PWR_STAT_SHIFI 12
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#define RK3588_PD_ESMART_PWR_STAT_SHIFI 15
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#endif
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