/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
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*/
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#ifndef __RK_SPI_H
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#define __RK_SPI_H
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#define HAL_SPI_MASTER_MAX_SCLK_OUT 50000000 /**< Max io clock in master mode */
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#define HAL_SPI_SLAVE_MAX_SCLK_OUT 20000000 /**< Max io in clock in slave mode */
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#define CR0_DATA_FRAME_SIZE_4BIT (0x00 << SPI_CTRLR0_DFS_SHIFT)
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#define CR0_DATA_FRAME_SIZE_8BIT (0x01 << SPI_CTRLR0_DFS_SHIFT)
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#define CR0_DATA_FRAME_SIZE_16BIT (0x02 << SPI_CTRLR0_DFS_SHIFT)
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/* serial clock toggles in middle of first data bit */
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#define CR0_PHASE_1EDGE (0x00 << SPI_CTRLR0_SCPH_SHIFT)
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/* serial clock toggles at start of first data bit */
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#define CR0_PHASE_2EDGE (0x01 << SPI_CTRLR0_SCPH_SHIFT)
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#define CR0_POLARITY_LOW (0x00 << SPI_CTRLR0_SCPOL_SHIFT)
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#define CR0_POLARITY_HIGH (0x01 << SPI_CTRLR0_SCPOL_SHIFT)
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/*
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* The period between ss_n active and
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* sclk_out active is half sclk_out cycles
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*/
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#define CR0_SSD_HALF (0x00 << SPI_CTRLR0_SSD_SHIFT)
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/*
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* The period between ss_n active and
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* sclk_out active is one sclk_out cycle
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*/
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#define CR0_SSD_ONE (0x01 << SPI_CTRLR0_SSD_SHIFT)
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#define CR0_EM_LITTLE (0x0 << SPI_CTRLR0_EM_SHIFT)
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#define CR0_EM_BIG (0x1 << SPI_CTRLR0_EM_SHIFT)
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#define CR0_FIRSTBIT_MSB (0x0 << SPI_CTRLR0_FBM_SHIFT)
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#define CR0_FIRSTBIT_LSB (0x1 << SPI_CTRLR0_FBM_SHIFT)
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#define CR0_BHT_16BIT (0x0 << SPI_CTRLR0_BHT_SHIFT)
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#define CR0_BHT_8BIT (0x1 << SPI_CTRLR0_BHT_SHIFT)
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#define CR0_XFM_TR (0x00 << SPI_CTRLR0_XFM_SHIFT)
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#define CR0_XFM_TO (0x01 << SPI_CTRLR0_XFM_SHIFT)
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#define CR0_XFM_RO (0x02 << SPI_CTRLR0_XFM_SHIFT)
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#define CR0_OPM_MASTER (0x00 << SPI_CTRLR0_OPM_SHIFT)
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#define CR0_OPM_SLAVE (0x01 << SPI_CTRLR0_OPM_SHIFT)
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#define CR0_CSM(nCycles) (((nCycles) << SPI_CTRLR0_CSM_SHIFT) & SPI_CTRLR0_CSM_MASK)
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#define CR0_CSM_0CYCLE CR0_CSM(0)
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#define CR0_CSM_1CYCLE CR0_CSM(1)
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#define CR0_CSM_2CYCLES CR0_CSM(2)
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#define CR0_CSM_3CYCLES CR0_CSM(3)
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/***************************** Structure Definition **************************/
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/** @brief SPI Type definition */
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typedef enum {
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SSI_MOTO_SPI = 0,
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SSI_TI_SSP,
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SSI_NS_MICROWIRE
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} eSPI_SSIType;
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/** @brief SPI Transfer type definition */
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typedef enum {
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SPI_POLL = 0,
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SPI_IT,
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SPI_DMA
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} eSPI_TransferType;
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/** @brief SPI Configuration Structure definition */
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struct SPI_CONFIG {
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UINT32 opMode; /**< Specifies the SPI operating mode, master or slave. */
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UINT32 xfmMode; /**< Specifies the SPI bidirectional mode state, tx only, rx only or trx mode. */
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UINT32 nBytes; /**< Specifies the SPI data size. */
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UINT32 clkPolarity; /**< Specifies the serial clock steady state. */
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UINT32 clkPhase; /**< Specifies the clock active edge for the bit capture. */
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UINT32 firstBit; /**< Specifies whether data transfers start from MSB or LSB bit. */
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UINT32 endianMode; /**< Specifies whether data transfers start from little or big endian. */
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UINT32 apbTransform; /**< Specifies apb transform type. */
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UINT32 ssd; /**< Specifies period between ss_n active and sclk_out. */
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UINT32 speed; /**< Specifies the Baud Rate prescaler value which will be
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used to configure the transmit and receive SCK clock. */
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UINT32 ssiType; /**< Specifies if the TI mode is enabled or not.*/
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UINT32 csm; /**< Specifies Motorola SPI Master SS_N high cycles for each frame data is transfer. */
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};
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/* We have 2 DMA channels per SPI, one for RX and one for TX */
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struct HAL_SPI_DMA_INFO {
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UINT8 channel;
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UINT8 direction;
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UINT32 addr;
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};
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struct HAL_SPI_DEV {
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const UINT32 base;
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const UINT32 clkId;
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const UINT32 clkGateID;
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const UINT32 pclkGateID;
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const UINT8 irqNum;
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const UINT8 isSlave;
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const struct HAL_SPI_DMA_INFO txDma;
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const struct HAL_SPI_DMA_INFO rxDma;
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};
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/** @brief SPI handle Structure definition */
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struct SPI_HANDLE {
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struct SPI_REG *pReg; /**< Specifies SPI registers base address. */
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UINT32 maxFreq; /**< Specifies SPI clock frequency. */
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struct SPI_CONFIG config; /**< Specifies SPI communication parameters. */
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const UINT8 *pTxBuffer; /**< Specifies pointer to SPI Tx transfer Buffer. */
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const UINT8 *pTxBufferEnd; /**< Specifies pointer to SPI Tx End transfer Buffer. */
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UINT8 *pRxBuffer; /**< Specifies pointer to SPI Rx transfer Buffer. */
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UINT8 *pRxBufferEnd; /**< Specifies pointer to SPI Rx End transfer Buffer. */
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UINT32 len; /**< Specifies the transfer length . */
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eSPI_TransferType type; /**< Specifies the transfer type: POLL/IT/DMA. */
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UINT32 dmaBurstSize; /**< Specifies Dma Burst size */
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};
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RETURN_STATUS SPI_Init(struct SPI_HANDLE *pSPI, UINT32 base);
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RETURN_STATUS SPI_DeInit(struct SPI_HANDLE *pSPI);
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RETURN_STATUS SPI_FlushFifo(struct SPI_HANDLE *pSPI);
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RETURN_STATUS SPI_SetCS(struct SPI_HANDLE *pSPI, UINT8 select, UINT8 enable);
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RETURN_STATUS SPI_PioTransfer(struct SPI_HANDLE *pSPI);
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RETURN_STATUS SPI_Stop(struct SPI_HANDLE *pSPI);
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RETURN_STATUS SPI_Configure(struct SPI_HANDLE *pSPI, const UINT8 *pTxData,
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UINT8 *pRxData, UINT32 Size);
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UINT32 SPI_CalculateTimeout(struct SPI_HANDLE *pSPI);
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#endif
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