/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
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*/
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#ifndef _HAL_FSPI_H_
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#define _HAL_FSPI_H_
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#define HAL_FSPI_QUAD_ENABLE
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#define HAL_FSPI_SPEED_THRESHOLD 100000000
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/***************************** Structure Definition **************************/
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/** FSPI_CTRL register datalines, addrlines and cmdlines value */
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#define FSPI_LINES_X1 (0)
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#define FSPI_LINES_X2 (1)
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#define FSPI_LINES_X4 (2)
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/** FSPI_CTRL bit union */
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typedef union {
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UINT32 d32;
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struct {
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unsigned mode : 1; /**< spi mode select */
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unsigned sps : 1; /**< shift in phase at: posedge 1: negedge */
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unsigned reserved3_2 : 2;
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unsigned scic : 4; /**< sclk_idle_level_cycles */
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unsigned cmdlines : 2; /**< cmd bits number */
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unsigned addrlines : 2; /**< address bits number */
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unsigned datalines : 2; /**< data bits number */
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unsigned reserved14_15 : 2;
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unsigned addrbits : 5;
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unsigned reserved31_21 : 11;
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} b;
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} FSPICTRL_DATA;
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/** FSPI_CMD register rw value without shift */
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#define FSPI_READ (0)
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#define FSPI_WRITE (1)
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/** FSPI_CMD regitser addrbits value without shift */
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#define FSPI_ADDR_0BITS (0)
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#define FSPI_ADDR_24BITS (1)
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#define FSPI_ADDR_32BITS (2)
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#define FSPI_ADDR_XBITS (3)
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/** FSPI_CMD bit union */
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typedef union {
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UINT32 d32;
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struct {
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unsigned cmd : 8; /**< command that will send to Serial Flash */
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unsigned dummybits : 4; /**< dummy bits number */
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unsigned rw : 1; /**< 0:read, 1: write */
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unsigned readmode : 1; /**< continuous read mode */
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unsigned addrbits : 2; /**< address bits number */
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unsigned datasize : 14; /**< transferred bytes number */
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unsigned cs : 2; /**< chip select */
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} b;
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} FSPICMD_DATA;
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typedef enum {
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DEV_UNKNON = 0,
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DEV_NOR,
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DEV_PSRAM,
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} eFSPI_devType;
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struct HAL_FSPI_XMMC_DEV {
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eFSPI_devType type;
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UINT32 ctrl;
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UINT32 readCmd;
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UINT32 writeCmd;
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};
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/** XIP may be not accessble, so place it in sram or psram */
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struct HAL_FSPI_HOST {
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struct FSPI_REG *instance;
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UINT8 cs; /**< Should be defined by user in each operation */
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UINT8 mode; /**< Should be defined by user, referring to hal_spi_mem.h */
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UINT8 cell; /**< Record DLL cell for PM resume, Set depend on corresponding device */
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};
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#define HAL_FSPI_MAX_DELAY_LINE_CELLS (0xFFU)
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RETURN_STATUS HAL_FSPI_Init(struct HAL_FSPI_HOST *host);
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RETURN_STATUS HAL_FSPI_DeInit(struct HAL_FSPI_HOST *host);
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RETURN_STATUS HAL_FSPI_XferStart(struct HAL_FSPI_HOST *host, struct HAL_SPI_MEM_OP *op);
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RETURN_STATUS HAL_FSPI_XferData(struct HAL_FSPI_HOST *host, UINT32 len, void *data, UINT32 dir);
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RETURN_STATUS HAL_FSPI_XferData_DMA(struct HAL_FSPI_HOST *host, UINT32 len, void *data, UINT32 dir);
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RETURN_STATUS HAL_FSPI_XferDone(struct HAL_FSPI_HOST *host);
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RETURN_STATUS HAL_FSPI_SpiXfer(struct HAL_FSPI_HOST *host, struct HAL_SPI_MEM_OP *op);
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RETURN_STATUS HAL_FSPI_IRQHelper(struct HAL_FSPI_HOST *host);
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RETURN_STATUS HAL_FSPI_MaskDMAInterrupt(struct HAL_FSPI_HOST *host);
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RETURN_STATUS HAL_FSPI_UnmaskDMAInterrupt(struct HAL_FSPI_HOST *host);
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RETURN_STATUS HAL_FSPI_XmmcSetting(struct HAL_FSPI_HOST *host, struct HAL_SPI_MEM_OP *op);
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RETURN_STATUS HAL_FSPI_XmmcRequest(struct HAL_FSPI_HOST *host, UINT8 on);
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RETURN_STATUS HAL_FSPI_SetDelayLines(struct HAL_FSPI_HOST *host, UINT8 cells);
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RETURN_STATUS HAL_FSPI_DLLDisable(struct HAL_FSPI_HOST *host);
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UINT32 HAL_FSPI_GetXMMCStatus(struct HAL_FSPI_HOST *host);
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UINT32 HAL_FSPI_GetMaxIoSize(struct HAL_FSPI_HOST *host);
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#endif
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