/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
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*/
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/** @addtogroup RK_HAL_Driver
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* @{
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*/
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/** @addtogroup CRU
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* @{
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*/
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#ifndef _HAL_CRU_H_
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#define _HAL_CRU_H_
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#include "HalDef.h"
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/*************************** MACRO Definition ****************************/
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/** @defgroup CRU_Exported_Definition_Group1 Basic Definition
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* @{
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*/
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#define MHZ 1000000
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#define KHZ 1000
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#ifndef PLL_INPUT_OSC_RATE
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#define PLL_INPUT_OSC_RATE (24 * MHZ)
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#endif
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#define CLK_RESET_GET_REG_OFFSET(x) ((uint32_t)((x) / 16))
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#define CLK_RESET_GET_BITS_SHIFT(x) ((uint32_t)((x) % 16))
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#define CLK_GATE_GET_REG_OFFSET(x) ((uint32_t)((x) / 16))
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#define CLK_GATE_GET_BITS_SHIFT(x) ((uint32_t)((x) % 16))
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#define CLK_GET_MUX(x) ((x) & 0x0F0F00FFU)
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#define CLK_GET_DIV(x) ((((x) & 0xFF00U) >> 8) | (((x) & 0xF0F00000U) >> 4))
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#define WIDTH_TO_MASK(width) ((1 << (width)) - 1)
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#define CLK_MUX_REG_OFFSET_SHIFT 0U
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#define CLK_MUX_REG_OFFSET_MASK 0x0000FFFFU
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#define CLK_MUX_SHIFT_SHIFT 16U
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#define CLK_MUX_SHIFT_MASK 0x00FF0000U
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#define CLK_MUX_WIDTH_SHIFT 24U
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#define CLK_MUX_WIDTH_MASK 0xFF000000U
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#define CLK_MUX_GET_REG_OFFSET(x) \
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(((uint32_t)(x) & CLK_MUX_REG_OFFSET_MASK) >> CLK_MUX_REG_OFFSET_SHIFT)
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#define CLK_MUX_GET_BITS_SHIFT(x) \
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(((uint32_t)(x) & CLK_MUX_SHIFT_MASK) >> CLK_MUX_SHIFT_SHIFT)
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#define CLK_MUX_GET_MASK(x) \
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WIDTH_TO_MASK((((uint32_t)(x) & CLK_MUX_WIDTH_MASK) >> CLK_MUX_WIDTH_SHIFT)) \
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<< CLK_MUX_GET_BITS_SHIFT(x)
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#define CLK_DIV_REG_OFFSET_SHIFT 0U
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#define CLK_DIV_REG_OFFSET_MASK 0x0000FFFFU
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#define CLK_DIV_SHIFT_SHIFT 16U
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#define CLK_DIV_SHIFT_MASK 0x00FF0000U
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#define CLK_DIV_WIDTH_SHIFT 24U
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#define CLK_DIV_WIDTH_MASK 0xFF000000U
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#define CLK_DIV_GET_REG_OFFSET(x) \
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(((uint32_t)(x) & CLK_DIV_REG_OFFSET_MASK) >> CLK_DIV_REG_OFFSET_SHIFT)
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#define CLK_DIV_GET_BITS_SHIFT(x) \
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(((uint32_t)(x) & CLK_DIV_SHIFT_MASK) >> CLK_DIV_SHIFT_SHIFT)
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#define CLK_DIV_GET_MASK(x) \
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WIDTH_TO_MASK((((uint32_t)(x) & CLK_DIV_WIDTH_MASK) >> CLK_DIV_WIDTH_SHIFT)) \
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<< CLK_DIV_GET_BITS_SHIFT(x)
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#define RK_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, \
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_frac) \
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{ \
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.rate = _rate##U, .fbDiv = _fbdiv, .postDiv1 = _postdiv1, \
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.refDiv = _refdiv, .postDiv2 = _postdiv2, .dsmpd = _dsmpd, \
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.frac = _frac, \
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}
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#define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \
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{ \
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.rate = _rate##U, .p = _p, .m = _m, \
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.s = _s, .k = _k, \
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}
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struct PLL_CONFIG {
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uint32_t rate;
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uint32_t fbDiv;
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uint32_t postDiv1;
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uint32_t refDiv;
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uint32_t postDiv2;
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uint32_t dsmpd;
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uint32_t frac;
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uint32_t m;
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uint32_t p;
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uint32_t s;
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uint32_t k;
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};
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struct PLL_SETUP {
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__IO uint32_t *conOffset0;
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__IO uint32_t *conOffset1;
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__IO uint32_t *conOffset2;
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__IO uint32_t *conOffset3;
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__IO uint32_t *conOffset6;
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__IO uint32_t *modeOffset;
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__I uint32_t *stat0;
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uint32_t modeShift;
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uint32_t lockShift;
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uint32_t modeMask;
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const struct PLL_CONFIG *rateTable;
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};
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typedef enum {
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GLB_SRST_FST = 0xfdb9,
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GLB_SRST_SND = 0xeca8,
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} eCRU_GlbSrstType;
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typedef enum {
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GLB_RST_FST_WDT0 = 0U,
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GLB_RST_SND_WDT0,
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GLB_RST_FST_WDT1,
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GLB_RST_SND_WDT1,
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GLB_RST_FST_WDT2,
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GLB_RST_SND_WDT2,
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} eCRU_WdtRstType;
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/***************************** Structure Definition **************************/
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/** @} */
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/***************************** Function Declare ******************************/
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/** @defgroup CRU_Public_Function_Declare Public Function Declare
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* @{
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*/
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uint32_t HAL_CRU_GetPllFreq(struct PLL_SETUP *pSetup);
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HAL_Status HAL_CRU_SetPllFreq(struct PLL_SETUP *pSetup, uint32_t rate);
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HAL_Status HAL_CRU_SetPllPowerUp(struct PLL_SETUP *pSetup);
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HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup);
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uint32_t HAL_CRU_GetPllV1Freq(struct PLL_SETUP *pSetup);
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HAL_Status HAL_CRU_SetPllV1Freq(struct PLL_SETUP *pSetup, uint32_t rate);
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HAL_Check HAL_CRU_ClkIsEnabled(uint32_t clk);
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HAL_Status HAL_CRU_ClkEnable(uint32_t clk);
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HAL_Status HAL_CRU_ClkDisable(uint32_t clk);
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HAL_Check HAL_CRU_ClkIsReset(uint32_t clk);
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HAL_Status HAL_CRU_ClkResetAssert(uint32_t clk);
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HAL_Status HAL_CRU_ClkResetDeassert(uint32_t clk);
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HAL_Status HAL_CRU_ClkSetDiv(uint32_t divName, uint32_t divValue);
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uint32_t HAL_CRU_ClkGetDiv(uint32_t divName);
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HAL_Status HAL_CRU_ClkSetMux(uint32_t muxName, uint32_t muxValue);
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uint32_t HAL_CRU_ClkGetMux(uint32_t muxName);
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HAL_Status HAL_CRU_FracdivGetConfig(uint32_t rateOut, uint32_t rate,
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uint32_t *numerator,
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uint32_t *denominator);
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uint32_t HAL_CRU_ClkGetFreq(eCLOCK_Name clockName);
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HAL_Status HAL_CRU_ClkSetFreq(eCLOCK_Name clockName, uint32_t rate);
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HAL_Status HAL_CRU_VopDclkEnable(uint32_t gateId);
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HAL_Status HAL_CRU_VopDclkDisable(uint32_t gateId);
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HAL_Status HAL_CRU_ClkNp5BestDiv(eCLOCK_Name clockName, uint32_t rate, uint32_t pRate, uint32_t *bestdiv);
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HAL_Status HAL_CRU_SetGlbSrst(eCRU_GlbSrstType type);
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HAL_Status HAL_CRU_WdtGlbRstEnable(eCRU_WdtRstType wdtType);
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HAL_Status HAL_CRU_PllCompensation(eCLOCK_Name clockName, int ppm);
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#ifdef HAL_CRU_AS_FEATURE_ENABLED
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/**
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* @brief it is for AS init.
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*/
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void HAL_CRU_AsInit(void);
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/**
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* @brief it is for AS enable.
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* @param ch: channel
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* @param en: 1 is enable, 0 is disable.
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*/
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void HAL_CRU_AsEnable(uint8_t ch, uint8_t en);
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#endif
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/** @} */
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#endif
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/** @} */
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/** @} */
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