/** @file
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*
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* Copyright (c) 2017, Andrei Warkentin <andrey.warkentin@gmail.com>
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* Copyright (c) Microsoft Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include "SdhciHostDxe.h"
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#include <Library/PcdLib.h>
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#include <Library/RockchipPlatfromLib.h>
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#include <Library/CacheMaintenanceLib.h>
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#include <Library/TimerLib.h>
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#include <string.h>
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#define CONFIG_MMC_SDHCI_SDMA
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#define word32 *(volatile unsigned int *)(long)
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//#define SDHCI_MAX_RETRY_COUNT (1000 * 20)
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// MMC/SD/SDIO1 register definitions.
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#define MMCHS1_OFFSET 0x00300000
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#define MMCHS2_OFFSET 0x00340000
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#define MMCHS1_BASE (BCM2836_SOC_REGISTERS + MMCHS1_OFFSET)
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#define MMCHS2_BASE (BCM2836_SOC_REGISTERS + MMCHS2_OFFSET)
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#define MMCHS1_LENGTH 0x00000100
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#define MMCHS2_LENGTH 0x00000100
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#define MMCHS_DMA_ADDRESS (mMmcHsBase + 0x0)
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#define MMCHS_BLK_SIZE (mMmcHsBase + 0x4)
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#define MMCHS_BLK_COUNT (mMmcHsBase + 0x6)
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#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
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/*
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* Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
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*/
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#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
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#define SDHCI_DEFAULT_BOUNDARY_ARG (7)
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#define MMCHS_TRANS_MODE (mMmcHsBase + 0xC)
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#define SDHCI_TRNS_DMA BIT0
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#define SDHCI_TRNS_BLK_CNT_EN BIT1
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#define SDHCI_TRNS_ACMD12 BIT2
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#define SDHCI_TRNS_READ BIT4
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#define SDHCI_TRNS_MULTI BIT5
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#define BLEN_512BYTES (0x200UL << 0)
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#define MMCHS_ARG (mMmcHsBase + 0x8)
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#define MMCHS_CMD (mMmcHsBase + 0xC)
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#define MMCHS_CMD16 (mMmcHsBase + 0xE)
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#define BCE_ENABLE BIT1
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#define DDIR_READ BIT4
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#define DDIR_WRITE (0x0UL << 4)
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#define MSBS_SGLEBLK (0x0UL << 5)
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#define MSBS_MULTBLK BIT5
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#define RSP_TYPE_MASK (0x3UL << 16)
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#define RSP_TYPE_136BITS BIT16
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#define RSP_TYPE_48BITS (0x2UL << 16)
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#define RSP_TYPE_48BUSY (0x3UL << 16)
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#define CCCE_ENABLE BIT19
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#define CICE_ENABLE BIT20
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#define DP_ENABLE BIT21
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#define CMD_TYPE_NORMAL 0
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#define CMD_TYPE_ABORT 3
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#define TYPE(CMD_TYPE) (((CMD_TYPE) & 0x3) << 22)
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#define _INDX(CMD_INDX) ((CMD_INDX & 0x3F) << 24)
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#define MMC_CMD_NUM(CMD) (((CMD) >> 24) & 0x3F)
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#define INDX(CMD_INDX) (TYPE(CMD_TYPE_NORMAL) | _INDX(CMD_INDX))
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#define INDX_ABORT(CMD_INDX) (TYPE(CMD_TYPE_ABORT) | _INDX(CMD_INDX))
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#define MMCHS_RSP10 (mMmcHsBase + 0x10)
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#define MMCHS_RSP32 (mMmcHsBase + 0x14)
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#define MMCHS_RSP54 (mMmcHsBase + 0x18)
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#define MMCHS_RSP76 (mMmcHsBase + 0x1C)
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#define MMCHS_DATA (mMmcHsBase + 0x20)
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#define MMCHS_PRES_STATE (mMmcHsBase + 0x24)
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#define CMDI_MASK BIT0
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#define CMDI_ALLOWED (0x0UL << 0)
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#define CMDI_NOT_ALLOWED BIT0
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#define DATI_MASK BIT1
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#define DATI_ALLOWED (0x0UL << 1)
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#define DATI_NOT_ALLOWED BIT1
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#define WRITE_PROTECT_OFF BIT19
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#define SDHCI_CMD_INHIBIT BIT0
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#define SDHCI_DATA_INHIBIT BIT1
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#define SDHCI_DOING_WRITE BIT8
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#define SDHCI_DOING_READ BIT9)
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#define SDHCI_SPACE_AVAILABLE BIT10
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#define SDHCI_DATA_AVAILABLE BIT11
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#define SDHCI_CARD_PRESENT BIT16
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#define SDHCI_CARD_STATE_STABLE BIT17
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#define SDHCI_CARD_DETECT_PIN_LEVEL BIT18
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#define SDHCI_WRITE_PROTECT BIT19
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#define SDHCI_DATA_0_LVL BIT20
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#define MMCHS_HCTL (mMmcHsBase + 0x28)
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#define DTW_1_BIT (0x0UL << 1)
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#define DTW_4_BIT BIT1
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#define HIGH_SPEED_EN BIT2
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#define DTW_8_BIT BIT5
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#define SDBP_MASK BIT8
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#define SDBP_OFF (0x0UL << 8)
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#define SDBP_ON BIT8
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#define SDVS_MASK (0x7UL << 9)
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#define SDVS_1_8_V (0x5UL << 9)
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#define SDVS_3_0_V (0x6UL << 9)
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#define SDVS_3_3_V (0x7UL << 9)
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#define IWE BIT24
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#define SDHCI_CTRL_LED BIT0
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#define SDHCI_CTRL_4BITBUS BIT1
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#define SDHCI_CTRL_HISPD BIT2
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#define SDHCI_CTRL_DMA_MASK 0x18
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#define SDHCI_CTRL_SDMA 0x00
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#define MMCHS_SYSCTL (mMmcHsBase + 0x2C)
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#define ICE BIT0
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#define ICS_MASK BIT1
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#define ICS BIT1
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#define CEN BIT2
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#define CLKD_MASK (0x3FFUL << 6)
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#define CLKD_80KHZ (0x258UL) //(96*1000/80)/2
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#define CLKD_400KHZ (0xF0UL)
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#define CLKD_12500KHZ (0x200UL)
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#define DTO_MASK (0xFUL << 16)
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#define DTO_VAL (0xEUL << 16)
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#define SRA BIT24
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#define SRC_MASK BIT25
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#define SRC BIT25
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#define SRD BIT26
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#define MMCHS_RESET (mMmcHsBase + 0x2F)
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#define RST_ALL 0x01
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#define RST_CMD 0x02
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#define RST_DATA 0x04
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#define MMCHS_INT_STAT (mMmcHsBase + 0x30)
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#define CC BIT0
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#define TC BIT1
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#define BWR BIT4
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#define BRR BIT5
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#define CARD_INS BIT6
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#define ERRI BIT15
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#define CTO BIT16
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#define DTO BIT20
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#define DCRC BIT21
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#define DEB BIT22
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#define SDHCI_INT_RESPONSE BIT0
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#define SDHCI_INT_DATA_END BIT1
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#define SDHCI_INT_DMA_END BIT3
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#define SDHCI_INT_SPACE_AVAIL BIT4
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#define SDHCI_INT_DATA_AVAIL BIT5
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#define SDHCI_INT_CARD_INSERT BIT6
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#define SDHCI_INT_CARD_REMOVE BIT7
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#define SDHCI_INT_CARD_INT BIT8
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#define SDHCI_INT_ERROR BIT15
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#define SDHCI_INT_TIMEOUT BIT16
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#define SDHCI_INT_CRC BIT17
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#define SDHCI_INT_END_BIT BIT18
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#define SDHCI_INT_INDEX BIT19
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#define SDHCI_INT_DATA_TIMEOUT BIT20
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#define SDHCI_INT_DATA_CRC BIT21
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#define SDHCI_INT_DATA_END_BIT BIT22
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#define SDHCI_INT_BUS_POWER BIT23
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#define SDHCI_INT_ACMD12ERR BIT24
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#define SDHCI_INT_ADMA_ERROR BIT25
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#define MMCHS_IE (mMmcHsBase + 0x34)
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#define CC_EN BIT0
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#define TC_EN BIT1
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#define BWR_EN BIT4
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#define BRR_EN BIT5
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#define CTO_EN BIT16
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#define CCRC_EN BIT17
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#define CEB_EN BIT18
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#define CIE_EN BIT19
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#define DTO_EN BIT20
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#define DCRC_EN BIT21
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#define DEB_EN BIT22
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#define CERR_EN BIT28
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#define BADA_EN BIT29
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#define ALL_EN 0x27f003b //0xFFFFFFFF
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#define ALL_MASK 0xFFFFFFFF
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#define MMCHS_ISE (mMmcHsBase + 0x38)
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#define CC_SIGEN BIT0
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#define TC_SIGEN BIT1
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#define BWR_SIGEN BIT4
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#define BRR_SIGEN BIT5
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#define CTO_SIGEN BIT16
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#define CCRC_SIGEN BIT17
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#define CEB_SIGEN BIT18
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#define CIE_SIGEN BIT19
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#define DTO_SIGEN BIT20
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#define DCRC_SIGEN BIT21
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#define DEB_SIGEN BIT22
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#define CERR_SIGEN BIT28
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#define BADA_SIGEN BIT29
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#define MMCHS_AC12 (mMmcHsBase + 0x3C)
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#define MMCHS_HCTL2 (mMmcHsBase + 0x3E)
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#define SDHCI_CTRL_UHS_MASK 0x0007
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#define SDHCI_CTRL_UHS_SDR12 0x0000
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#define SDHCI_CTRL_UHS_SDR25 0x0001
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#define SDHCI_CTRL_UHS_SDR50 0x0002
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#define SDHCI_CTRL_UHS_SDR104 0x0003
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#define SDHCI_CTRL_UHS_DDR50 0x0004
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#define SDHCI_CTRL_EMMC_SDR50 0x0001
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#define SDHCI_CTRL_EMMC_HS200 0x0003
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#define SDHCI_CTRL_EMMC_HS400 0x0007
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#define SDHCI_CTRL_VDD_180 0x0008
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#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
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#define SDHCI_CTRL_DRV_TYPE_B 0x0000
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#define SDHCI_CTRL_DRV_TYPE_A 0x0010
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#define SDHCI_CTRL_DRV_TYPE_C 0x0020
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#define SDHCI_CTRL_DRV_TYPE_D 0x0030
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#define SDHCI_CTRL_EXEC_TUNING 0x0040
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#define SDHCI_CTRL_TUNED_CLK 0x0080
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#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
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#define MMCHS_CAPA (mMmcHsBase + 0x40)
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#define VS30 BIT25
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#define VS18 BIT26
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#define MMCHS_CUR_CAPA (mMmcHsBase + 0x48)
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#define MMCHS_REV (mMmcHsBase + 0xFC)
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#define BLOCK_COUNT_SHIFT 16
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#define RCA_SHIFT 16
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#define CMD_R1 (RSP_TYPE_48BITS | CCCE_ENABLE | CICE_ENABLE)
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#define CMD_R1B (RSP_TYPE_48BUSY | CCCE_ENABLE | CICE_ENABLE)
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#define CMD_R2 (RSP_TYPE_136BITS | CCCE_ENABLE)
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#define CMD_R3 (RSP_TYPE_48BITS)
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#define CMD_R6 (RSP_TYPE_48BITS | CCCE_ENABLE | CICE_ENABLE)
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#define CMD_R7 (RSP_TYPE_48BITS | CCCE_ENABLE | CICE_ENABLE)
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#define CMD_R1_ADTC (CMD_R1 | DP_ENABLE)
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#define CMD_R1_ADTC_READ (CMD_R1_ADTC | DDIR_READ)
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#define CMD_R1_ADTC_WRITE (CMD_R1_ADTC | DDIR_WRITE)
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#define CMD0 (INDX(0)) // Go idle
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#define CMD1 (INDX(1) | CMD_R3) // MMC: Send Op Cond
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#define CMD2 (INDX(2) | CMD_R2) // Send CID
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#define CMD3 (INDX(3) | CMD_R6) // Set Relative Addr
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#define CMD4 (INDX(4)) // Set DSR
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#define CMD5 (INDX(5) | CMD_R1B) // SDIO: Sleep/Awake
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//#define CMD6 (INDX(6) | CMD_R1_ADTC_READ) // Switch
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#define CMD6 (INDX(6) | CMD_R1B) // Switch
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#define CMD7 (INDX(7) | CMD_R1) // Select/Deselect
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#define CMD8_SD (INDX(8) | CMD_R7) // Send If Cond
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#define CMD8_SD_ARG (0x0UL << 12 | BIT8 | 0xCEUL << 0)
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#define CMD8_MMC (INDX(8) | CMD_R1_ADTC_READ) // Send Ext Csd
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#define CMD8_MMC_ARG (0)
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#define CMD9 (INDX(9) | CMD_R2) // Send CSD
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#define CMD10 (INDX(10) | CMD_R2) // Send CID
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#define CMD11 (INDX(11) | CMD_R1) // Voltage Switch
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#define CMD12 (INDX_ABORT(12) | CMD_R1B) // Stop Transmission
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#define CMD13 (INDX(13) | CMD_R1) // Send Status
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#define CMD15 (INDX(15)) // Go inactive state
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#define CMD16 (INDX(16) | CMD_R1) // Set Blocklen
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#define CMD17 (INDX(17) | CMD_R1_ADTC_READ) // Read Single Block
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#define CMD18 (INDX(18) | CMD_R1_ADTC_READ | MSBS_MULTBLK) // Read Multiple Blocks
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#define CMD19 (INDX(19) | CMD_R1_ADTC_READ) // SD: Send Tuning Block (64 bytes)
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#define CMD20 (INDX(20) | CMD_R1B) // SD: Speed Class Control
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#define CMD23 (INDX(23) | CMD_R1) // Set Block Count for CMD18 and CMD25
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#define CMD24 (INDX(24) | CMD_R1_ADTC_WRITE) // Write Block
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#define CMD25 (INDX(25) | CMD_R1_ADTC_WRITE | MSBS_MULTBLK) // Write Multiple Blocks
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#define CMD55 (INDX(55) | CMD_R1) // App Cmd
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#define ACMD6 (INDX(6) | CMD_R1) // Set Bus Width
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#define ACMD22 (INDX(22) | CMD_R1_ADTC_READ) // SEND_NUM_WR_BLOCKS
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#define ACMD41 (INDX(41) | CMD_R3) // Send Op Cond
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#define ACMD51 (INDX(51) | CMD_R1_ADTC_READ) // Send SCR
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#define MMC_ACMD22 (MMC_INDX(22) | MMC_CMD_WAIT_RESPONSE)
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// User-friendly command names
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#define CMD_IO_SEND_OP_COND CMD5
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#define CMD_SEND_CSD CMD9 // CSD: Card-Specific Data
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#define CMD_STOP_TRANSMISSION CMD12
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#define CMD_SEND_STATUS CMD13
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#define CMD_READ_SINGLE_BLOCK CMD17
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#define CMD_READ_MULTIPLE_BLOCK CMD18
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#define CMD_SET_BLOCK_COUNT CMD23
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#define CMD_WRITE_SINGLE_BLOCK CMD24
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#define CMD_WRITE_MULTIPLE_BLOCK CMD25
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#define DEBUG_MMCHOST_SD DEBUG_INFO
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#define MMC_DATA_READ 1
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#define MMC_DATA_WRITE 2
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typedef struct {
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UINT8 *buffer;
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UINT32 flags;
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UINT32 blocks;
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UINT32 blocksize;
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} SDHCI_DATA;
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//STATIC BOOLEAN mCardIsPresent = FALSE;
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//STATIC CARD_DETECT_STATE mCardDetectState = CardDetectRequired;
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UINT32 LastExecutedCommand = (UINT32) -1;
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STATIC UINTN mMmcHsBase;
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STATIC UINT32 mMmcDataCommand;
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STATIC UINT32 mMmcDataArgument;
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STATIC SDHCI_DATA gSdhciData;
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STATIC
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UINT32
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EFIAPI
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SdMmioWrite32 (
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IN UINTN Address,
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IN UINT32 Value
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)
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{
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UINT32 ret;
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ret = (UINT32)MmioWrite32 (Address, Value);
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// There is a bug about clock domain crossing on writes, delay to avoid it
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//gBS->Stall (STALL_AFTER_REG_WRITE_US);
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return ret;
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}
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STATIC
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UINT32
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EFIAPI
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SdMmioOr32 (
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IN UINTN Address,
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IN UINT32 OrData
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)
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{
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return SdMmioWrite32 (Address, MmioRead32 (Address) | OrData);
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}
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STATIC
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UINT32
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EFIAPI
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SdMmioAnd32 (
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IN UINTN Address,
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IN UINT32 AndData
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)
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{
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return SdMmioWrite32 (Address, MmioRead32 (Address) & AndData);
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}
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STATIC
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UINT32
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EFIAPI
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SdMmioAndThenOr32 (
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IN UINTN Address,
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IN UINT32 AndData,
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IN UINT32 OrData
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)
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{
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return SdMmioWrite32 (Address, (MmioRead32 (Address) & AndData) | OrData);
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}
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void IomemShow(const char *label, unsigned long base, unsigned int start, unsigned int end)
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{
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unsigned int val, offset = start, nr = 0;
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if (label)
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DEBUG ((DEBUG_ERROR, "%a:\n", label));
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DEBUG ((DEBUG_ERROR, "%08lx: ", base + offset));
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for (offset = start; offset <= end; offset += 0x04) {
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if (nr >= 4) {
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DEBUG ((DEBUG_ERROR, "\n%08lx: ", base + offset));
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nr = 0;
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}
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val = MmioRead32(base + offset);
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DEBUG ((DEBUG_ERROR, "%08lx ", val));
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nr++;
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}
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DEBUG ((DEBUG_ERROR, "\n"));
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}
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/**
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These SD commands are optional, according to the SD Spec
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**/
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BOOLEAN
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IgnoreCommand (
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UINT32 Command
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)
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{
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switch (Command) {
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case MMC_CMD20:
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return TRUE;
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default:
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return FALSE;
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}
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}
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/**
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Translates a generic SD command into the format used by the Arasan SD Host Controller
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**/
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UINT32
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TranslateCommand (
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UINT32 Command,
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UINT32 Argument
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)
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{
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UINT32 Translation = 0xffffffff;
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if (LastExecutedCommand == CMD55) {
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switch (Command) {
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case MMC_CMD6:
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Translation = ACMD6;
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DEBUG ((DEBUG_MMCHOST_SD, "ACMD6\n"));
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break;
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case MMC_ACMD22:
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Translation = ACMD22;
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DEBUG ((DEBUG_MMCHOST_SD, "ACMD22\n"));
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break;
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case MMC_ACMD41:
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Translation = ACMD41;
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DEBUG ((DEBUG_MMCHOST_SD, "ACMD41\n"));
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break;
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case MMC_ACMD51:
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Translation = ACMD51;
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DEBUG ((DEBUG_MMCHOST_SD, "ACMD51\n"));
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break;
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default:
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DEBUG ((DEBUG_ERROR, "MMCHost: TranslateCommand(): Unrecognized App command: %d\n", Command));
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}
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} else {
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switch (Command) {
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case MMC_CMD0:
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Translation = CMD0;
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break;
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case MMC_CMD1:
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Translation = CMD1;
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break;
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case MMC_CMD2:
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Translation = CMD2;
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break;
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case MMC_CMD3:
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Translation = CMD3;
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break;
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case MMC_CMD5:
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Translation = CMD5;
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break;
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case MMC_CMD6:
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Translation = CMD6;
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break;
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case MMC_CMD7:
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Translation = CMD7;
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break;
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case MMC_CMD8: {
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if (Argument == CMD8_SD_ARG) {
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Translation = CMD8_SD;
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DEBUG ((DEBUG_MMCHOST_SD, "Sending SD CMD8 variant\n"));
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} else {
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ASSERT (Argument == CMD8_MMC_ARG);
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Translation = CMD8_MMC;
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DEBUG ((DEBUG_MMCHOST_SD, "Sending MMC CMD8 variant\n"));
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}
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break;
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}
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case MMC_CMD9:
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Translation = CMD9;
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break;
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case MMC_CMD11:
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Translation = CMD11;
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break;
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case MMC_CMD12:
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Translation = CMD12;
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break;
|
case MMC_CMD13:
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Translation = CMD13;
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break;
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case MMC_CMD16:
|
Translation = CMD16;
|
break;
|
case MMC_CMD17:
|
Translation = CMD17;
|
break;
|
case MMC_CMD18:
|
Translation = CMD18;
|
break;
|
case MMC_CMD23:
|
Translation = CMD23;
|
break;
|
case MMC_CMD24:
|
Translation = CMD24;
|
break;
|
case MMC_CMD25:
|
Translation = CMD25;
|
break;
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case MMC_CMD55:
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Translation = CMD55;
|
break;
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default:
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DEBUG ((DEBUG_ERROR, "MMCHost: TranslateCommand(): Unrecognized Command: %d\n", Command));
|
}
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}
|
|
return Translation;
|
}
|
|
/**
|
Repeatedly polls a register until its value becomes correct, or until MAX_RETRY_COUNT polls is reached
|
**/
|
EFI_STATUS
|
PollRegisterWithMask (
|
IN UINTN Register,
|
IN UINTN Mask,
|
IN UINTN ExpectedValue
|
)
|
{
|
UINTN RetryCount = 0;
|
|
while (RetryCount < MAX_RETRY_COUNT) {
|
if ((MmioRead32 (Register) & Mask) != ExpectedValue) {
|
RetryCount++;
|
MicroSecondDelay(2);
|
} else {
|
break;
|
}
|
}
|
|
if (RetryCount == MAX_RETRY_COUNT) {
|
return EFI_TIMEOUT;
|
}
|
|
return EFI_SUCCESS;
|
}
|
|
/**
|
Calculate the clock divisor
|
**/
|
EFI_STATUS
|
CalculateClockFrequencyDivisor (
|
IN UINTN TargetFrequency,
|
OUT UINT32 *DivisorValue,
|
OUT UINTN *ActualFrequency
|
)
|
{
|
EFI_STATUS Status;
|
UINT32 Divisor;
|
UINTN BaseFrequency = 0;
|
|
Status = SdhciGetClockRate(TargetFrequency, &BaseFrequency);
|
|
if (EFI_ERROR (Status)) {
|
DEBUG ((DEBUG_ERROR, "Couldn't get RPI_MBOX_CLOCK_RATE_EMMC\n"));
|
return Status;
|
}
|
|
ASSERT (BaseFrequency != 0);
|
Divisor = BaseFrequency / TargetFrequency;
|
|
// Arasan controller is based on 3.0 spec so the div is multiple of 2
|
// Actual Frequency = BaseFequency/(Div*2)
|
Divisor /= 2;
|
|
if ((TargetFrequency < BaseFrequency) &&
|
(TargetFrequency * 2 * Divisor != BaseFrequency)) {
|
Divisor += 1;
|
}
|
|
if (Divisor > MAX_DIVISOR_VALUE) {
|
Divisor = MAX_DIVISOR_VALUE;
|
}
|
|
DEBUG ((DEBUG_MMCHOST_SD, "MMCHost: BaseFrequency 0x%x Divisor 0x%x\n", BaseFrequency, Divisor));
|
|
*DivisorValue = (Divisor & 0xFF) << 8;
|
Divisor >>= 8;
|
*DivisorValue |= (Divisor & 0x03) << 6;
|
|
if (ActualFrequency) {
|
if (Divisor == 0) {
|
*ActualFrequency = BaseFrequency;
|
} else {
|
*ActualFrequency = BaseFrequency / Divisor;
|
*ActualFrequency >>= 1;
|
}
|
DEBUG ((DEBUG_MMCHOST_SD, "MMCHost: *ActualFrequency 0x%x\n", *ActualFrequency));
|
}
|
|
DEBUG ((DEBUG_MMCHOST_SD, "MMCHost: *DivisorValue 0x%x\n", *DivisorValue));
|
|
return EFI_SUCCESS;
|
}
|
|
STATIC
|
EFI_STATUS
|
SdhciSoftReset (
|
IN UINT32 Mask
|
)
|
{
|
DEBUG ((DEBUG_INFO, "SoftReset with mask 0x%x\n", Mask));
|
|
SdMmioOr32 (MMCHS_SYSCTL, Mask);
|
if (PollRegisterWithMask (MMCHS_SYSCTL, Mask, 0) == EFI_TIMEOUT) {
|
DEBUG ((DEBUG_ERROR, "Failed to SoftReset with mask 0x%x\n", Mask));
|
return EFI_TIMEOUT;
|
}
|
|
return EFI_SUCCESS;
|
}
|
|
STATIC void
|
SdhciTransferPio(
|
IN EFI_MMC_HOST_PROTOCOL *This,
|
IN SDHCI_DATA *data
|
)
|
{
|
UINT32 *buf = (UINT32 *)data->buffer;
|
UINT32 len = data->blocksize>>2;
|
|
if (data->flags == MMC_DATA_READ) {
|
while(len--)
|
*buf++ = MmioRead32 (MMCHS_DATA);
|
}
|
else {
|
while(len--)
|
MmioWrite32 (MMCHS_DATA, *buf++);
|
}
|
}
|
|
STATIC EFI_STATUS
|
SdhciTransferData(
|
IN EFI_MMC_HOST_PROTOCOL *This,
|
IN SDHCI_DATA *data,
|
IN UINTN StartAddr
|
)
|
{
|
unsigned int stat, rdy, mask, timeout, block = 0;
|
BOOLEAN transfer_done = FALSE;
|
#ifdef CONFIG_MMC_SDHCI_SDMA
|
unsigned char ctrl;
|
ctrl = MmioRead8(MMCHS_HCTL);
|
ctrl &= ~SDHCI_CTRL_DMA_MASK;
|
MmioWrite8(MMCHS_HCTL, ctrl);
|
#endif
|
|
timeout = 1000000;
|
rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
|
mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
|
do {
|
stat = MmioRead32(MMCHS_INT_STAT);
|
if (stat & SDHCI_INT_ERROR) {
|
//UINT32 i, *Buffer;
|
DEBUG ((DEBUG_ERROR, "+++++%a Error detected in status(0x%X)!\n", __FUNCTION__, stat));
|
#if 0
|
IomemShow("emmc regs", (unsigned long)mMmcHsBase, 0, 0x3E);
|
IomemShow("PHY regs", (unsigned long)(mMmcHsBase+0x800), 0, 0x13);
|
Buffer = (UINT32*)data->buffer;
|
for (i = 0; i < 128*data->blocks; i++) {
|
if (0xCCCCCCCC == Buffer[i]) {
|
break;
|
}
|
}
|
|
DEBUG ((DEBUG_ERROR, "Buffer[%u]:0x%x, 0x%x\n", i-2, Buffer[i-2], Buffer[i-1]));
|
DEBUG ((DEBUG_ERROR, "blocks:%u Trans size:%u, blks:%u\n", data->blocks, i*4, i/128));
|
IomemShow("last buf", (unsigned long)&Buffer[i], 0, 0x1FF);
|
#endif
|
return EFI_DEVICE_ERROR;
|
}
|
if (!transfer_done && (stat & rdy)) {
|
if (!(MmioRead32(MMCHS_PRES_STATE) & mask))
|
continue;
|
MmioWrite32(MMCHS_INT_STAT, rdy);
|
SdhciTransferPio(This, data);
|
data->buffer += data->blocksize;
|
if (++block >= data->blocks) {
|
/* Keep looping until the SDHCI_INT_DATA_END is
|
* cleared, even if we finished sending all the
|
* blocks.
|
*/
|
transfer_done = TRUE;
|
continue;
|
}
|
}
|
#ifdef CONFIG_MMC_SDHCI_SDMA
|
if (!transfer_done && (stat & SDHCI_INT_DMA_END)) {
|
MmioWrite32(MMCHS_INT_STAT, SDHCI_INT_DMA_END);
|
StartAddr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
|
StartAddr += SDHCI_DEFAULT_BOUNDARY_SIZE;
|
MmioWrite32 (MMCHS_DMA_ADDRESS, (UINT32)StartAddr);
|
}
|
#endif
|
|
if (timeout-- > 0)
|
MicroSecondDelay(5);
|
else {
|
DEBUG ((DEBUG_ERROR, "%a Transfer data timeout\n", __FUNCTION__));
|
return EFI_TIMEOUT;
|
}
|
} while (!(stat & SDHCI_INT_DATA_END));
|
|
return EFI_SUCCESS;
|
}
|
|
EFI_STATUS
|
SdhciSendCommand (
|
IN EFI_MMC_HOST_PROTOCOL *This,
|
IN MMC_CMD MmcCmd,
|
IN UINT32 Argument,
|
IN UINT32 CmdSendOKMask
|
)
|
{
|
UINTN MmcStatus;
|
UINTN RetryCount = 0;
|
EFI_STATUS Status = EFI_SUCCESS;
|
|
DEBUG ((DEBUG_MMCHOST_SD, "DATA_CMD REG:0x%x 0x%x 0x%x\n", MmcCmd, Argument, LastExecutedCommand));
|
DEBUG ((DEBUG_MMCHOST_SD, "BLK SIZE:0x%x 0x%x\n", MmioRead16(MMCHS_BLK_SIZE), MmioRead16(MMCHS_BLK_COUNT)));
|
DEBUG ((DEBUG_MMCHOST_SD, "PSTATE:0x%x 0x%x\n", MmioRead32(MMCHS_PRES_STATE), MmioRead32(MMCHS_INT_STAT)));
|
//IomemShow("SDHCI", mMmcHsBase, 0, 0xFF);
|
|
MmioWrite16 (MMCHS_TRANS_MODE, (MmcCmd&0xffff));
|
// Set command argument register
|
MmioWrite32 (MMCHS_ARG, Argument);
|
|
//DEBUG ((DEBUG_ERROR, "MmcCmd:0x%x\n", (MmcCmd>>16)));
|
// Send the command
|
MmioWrite16 (MMCHS_CMD16, (MmcCmd>>16));
|
|
// Check for the command status.
|
while (RetryCount < MAX_RETRY_COUNT) {
|
MmcStatus = MmioRead32(MMCHS_INT_STAT);
|
|
// Read status of command response
|
if ((MmcStatus & ERRI) != 0) {
|
// CMD5 (CMD_IO_SEND_OP_COND) is only valid for SDIO
|
// cards and thus expected to fail.
|
|
DEBUG ((DEBUG_ERROR, "%a(%u): MMC_CMD%u completion TIMEOUT PresState 0x%x MmcStatus 0x%x,0x%x\n",
|
__FUNCTION__, __LINE__, MMC_CMD_NUM (MmcCmd),
|
MmioRead32 (MMCHS_PRES_STATE), MmcStatus, CmdSendOKMask));
|
|
SdhciSoftReset(SRC);
|
|
Status = EFI_DEVICE_ERROR;
|
goto Exit;
|
}
|
|
// Check if command is completed.
|
if ((MmcStatus & CmdSendOKMask) == CmdSendOKMask) {
|
SdMmioWrite32 (MMCHS_INT_STAT, CmdSendOKMask);
|
break;
|
}
|
|
RetryCount++;
|
MicroSecondDelay(1);
|
}
|
|
if (RetryCount == MAX_RETRY_COUNT) {
|
DEBUG ((DEBUG_ERROR, "%a(%u): MMC_CMD%u completion TIMEOUT PresState 0x%x MmcStatus 0x%x,0x%x\n",
|
__FUNCTION__, __LINE__, MMC_CMD_NUM (MmcCmd),
|
MmioRead32 (MMCHS_PRES_STATE), MmcStatus, CmdSendOKMask));
|
Status = EFI_TIMEOUT;
|
goto Exit;
|
}
|
|
Exit:
|
if (EFI_ERROR (Status)) {
|
LastExecutedCommand = (UINT32) -1;
|
} else {
|
LastExecutedCommand = MmcCmd;
|
}
|
return Status;
|
}
|
|
EFI_STATUS
|
MMCSetClock (
|
IN UINTN ClockFrequency
|
)
|
{
|
EFI_STATUS Status;
|
UINT32 Divisor;
|
|
// First turn off the clock
|
SdMmioAnd32 (MMCHS_SYSCTL, ~CEN);
|
|
Status = CalculateClockFrequencyDivisor (ClockFrequency, &Divisor, NULL);
|
if (EFI_ERROR (Status)) {
|
DEBUG ((DEBUG_ERROR, "MMCHost: MmcStandByState(): Fail to initialize SD clock to %u Hz\n",
|
ClockFrequency));
|
return Status;
|
}
|
|
// Setup new divisor
|
SdMmioAndThenOr32 (MMCHS_SYSCTL, (UINT32) ~CLKD_MASK, Divisor);
|
|
// Wait for the clock to stabilise
|
while ((MmioRead32 (MMCHS_SYSCTL) & ICS_MASK) != ICS);
|
|
// Set Data Timeout Counter value, set clock frequency, enable internal clock
|
SdMmioOr32 (MMCHS_SYSCTL, CEN);
|
|
return EFI_SUCCESS;
|
}
|
|
BOOLEAN
|
MMCIsReadOnly (
|
IN EFI_MMC_HOST_PROTOCOL *This
|
)
|
{
|
BOOLEAN IsReadOnly = !((MmioRead32 (MMCHS_PRES_STATE) & WRITE_PROTECT_OFF) == WRITE_PROTECT_OFF);
|
DEBUG ((DEBUG_MMCHOST_SD, "MMCHost: MMCIsReadOnly(): %d\n", IsReadOnly));
|
return IsReadOnly;
|
}
|
|
EFI_STATUS
|
MMCBuildDevicePath (
|
IN EFI_MMC_HOST_PROTOCOL *This,
|
IN EFI_DEVICE_PATH_PROTOCOL **DevicePath
|
)
|
{
|
EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode;
|
EFI_GUID DevicePathGuid = EFI_CALLER_ID_GUID;
|
|
DEBUG ((DEBUG_MMCHOST_SD, "MMCHost: MMCBuildDevicePath()\n"));
|
|
NewDevicePathNode = CreateDeviceNode (HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH));
|
CopyGuid (&((VENDOR_DEVICE_PATH*) NewDevicePathNode)->Guid, &DevicePathGuid);
|
*DevicePath = NewDevicePathNode;
|
|
return EFI_SUCCESS;
|
}
|
|
EFI_STATUS
|
MMCSendCommand (
|
IN EFI_MMC_HOST_PROTOCOL *This,
|
IN MMC_CMD MmcCmd,
|
IN UINT32 Argument
|
)
|
{
|
UINTN MmcStatus;
|
UINTN RetryCount = 0;
|
UINTN CmdSendOKMask;
|
EFI_STATUS Status = EFI_SUCCESS;
|
BOOLEAN IsAppCmd = (LastExecutedCommand == CMD55);
|
BOOLEAN IsDATCmd = FALSE;
|
//BOOLEAN IsADTCCmd = FALSE;
|
SDHCI_DATA *data = &gSdhciData;
|
|
DEBUG ((DEBUG_MMCHOST_SD, "MMCHost: MMCSendCommand(MmcCmd: %08x, Argument: %08x)\n", MmcCmd, Argument));
|
|
if (IgnoreCommand (MmcCmd)) {
|
return EFI_SUCCESS;
|
}
|
|
MmcCmd = TranslateCommand (MmcCmd, Argument);
|
if (MmcCmd == 0xffffffff) {
|
return EFI_UNSUPPORTED;
|
}
|
|
if ((MmcCmd & CMD_R1_ADTC) == CMD_R1_ADTC) {
|
IsDATCmd = TRUE;
|
}
|
#if 0
|
if (((MmcCmd & CMD_R1B) == CMD_R1B &&
|
/*
|
* Abort commands don't get inhibited by DAT.
|
*/
|
(MmcCmd & TYPE (CMD_TYPE_ABORT)) != TYPE (CMD_TYPE_ABORT)) ||
|
IsADTCCmd ||
|
/*
|
* We want to detect BRR/BWR change.
|
*/
|
MmcCmd == CMD_SEND_STATUS) {
|
IsDATCmd = TRUE;
|
}
|
#endif
|
|
CmdSendOKMask = CMDI_MASK;
|
if (IsDATCmd) {
|
CmdSendOKMask |= DATI_MASK;
|
}
|
|
if (PollRegisterWithMask (MMCHS_PRES_STATE,
|
CmdSendOKMask, 0) == EFI_TIMEOUT) {
|
DEBUG ((DEBUG_ERROR, "%a(%u): not ready for MMC_CMD%u PresState 0x%x MmcStatus 0x%x\n",
|
__FUNCTION__, __LINE__, MMC_CMD_NUM (MmcCmd),
|
MmioRead32 (MMCHS_PRES_STATE), MmioRead32 (MMCHS_INT_STAT)));
|
Status = EFI_TIMEOUT;
|
goto Exit;
|
}
|
|
if (IsAppCmd && MmcCmd == ACMD22) {
|
SdMmioWrite32 (MMCHS_BLK_SIZE, 4);
|
data->blocksize = 4;
|
} else if (IsAppCmd && MmcCmd == ACMD51) {
|
SdMmioWrite32 (MMCHS_BLK_SIZE, 8);
|
data->blocksize = 8;
|
} else if (!IsAppCmd && MmcCmd == CMD6) {
|
SdMmioWrite32 (MMCHS_BLK_SIZE, 64);
|
data->blocksize = 64;
|
} else if (IsDATCmd) {
|
SdMmioWrite32 (MMCHS_BLK_SIZE, BLEN_512BYTES);
|
data->blocksize = 512;
|
}
|
|
// Set Data timeout counter value to max value.
|
SdMmioAndThenOr32 (MMCHS_SYSCTL, (UINT32) ~DTO_MASK, DTO_VAL);
|
|
// Clear Interrupt Status Register, but not the Card Inserted bit
|
// to avoid messing with card detection logic.
|
SdMmioWrite32 (MMCHS_INT_STAT, ALL_MASK);
|
|
//DEBUG ((DEBUG_ERROR, "MMC_CMD%u REG:0x%x 0x%x\n", MMC_CMD_NUM(MmcCmd), MmcCmd, Argument));
|
if (IsDATCmd) {
|
//DEBUG ((DEBUG_ERROR, "MMC_CMD%u Data Cmd\n", MMC_CMD_NUM(MmcCmd)));
|
mMmcDataCommand = MmcCmd;
|
mMmcDataArgument = Argument;
|
LastExecutedCommand = MmcCmd;
|
return EFI_SUCCESS;
|
}
|
// Set command argument register
|
SdMmioWrite32 (MMCHS_ARG, Argument);
|
|
// Send the command
|
SdMmioWrite32 (MMCHS_CMD, MmcCmd);
|
//DEBUG ((DEBUG_ERROR, "MmcCmd:0x%x, 0x%x\n", (MmcCmd>>16), Argument));
|
|
// Check for the command status.
|
while (RetryCount < MAX_RETRY_COUNT) {
|
MmcStatus = MmioRead32 (MMCHS_INT_STAT);
|
|
// Read status of command response
|
if ((MmcStatus & ERRI) != 0) {
|
//
|
// CMD5 (CMD_IO_SEND_OP_COND) is only valid for SDIO
|
// cards and thus expected to fail.
|
//
|
if (MmcCmd != CMD_IO_SEND_OP_COND) {
|
DEBUG ((DEBUG_ERROR, "%a(%u): MMC_CMD%u ERRI MmcStatus 0x%x,0x%x\n",
|
__FUNCTION__, __LINE__, MMC_CMD_NUM (MmcCmd), MmcStatus, CmdSendOKMask));
|
DEBUG ((DEBUG_ERROR, "MMC_CMD REG:0x%x 0x%x\n", MmioRead32(MMCHS_CMD), MmioRead32(MMCHS_ARG)));
|
}
|
|
SdhciSoftReset(SRC);
|
|
Status = EFI_DEVICE_ERROR;
|
goto Exit;
|
}
|
|
// Check if command is completed.
|
if ((MmcStatus & CmdSendOKMask) == CmdSendOKMask) {
|
SdMmioWrite32 (MMCHS_INT_STAT, CmdSendOKMask);
|
break;
|
}
|
|
RetryCount++;
|
MicroSecondDelay(1);
|
}
|
|
MicroSecondDelay(1);
|
|
if (RetryCount == MAX_RETRY_COUNT) {
|
DEBUG ((DEBUG_ERROR, "%a(%u): MMC_CMD%u completion TIMEOUT PresState 0x%x MmcStatus 0x%x,0x%x\n",
|
__FUNCTION__, __LINE__, MMC_CMD_NUM (MmcCmd),
|
MmioRead32 (MMCHS_PRES_STATE), MmcStatus, CmdSendOKMask));
|
Status = EFI_TIMEOUT;
|
goto Exit;
|
}
|
|
Exit:
|
SdhciSoftReset(SRC | SRD);
|
if (EFI_ERROR (Status)) {
|
LastExecutedCommand = (UINT32) -1;
|
} else {
|
LastExecutedCommand = MmcCmd;
|
}
|
return Status;
|
}
|
|
EFI_STATUS
|
MMCNotifyState (
|
IN EFI_MMC_HOST_PROTOCOL *This,
|
IN MMC_STATE State
|
)
|
{
|
EFI_STATUS Status;
|
UINTN ClockFrequency;
|
UINT32 Divisor;
|
|
DEBUG ((DEBUG_MMCHOST_SD, "MMCHost: MMCNotifyState(State: %d)\n", State));
|
|
switch (State) {
|
case MmcHwInitializationState:
|
{
|
DEBUG ((DEBUG_MMCHOST_SD, "MMCHost: current divisor %x\n", MmioRead32(MMCHS_SYSCTL)));
|
DEBUG ((DEBUG_MMCHOST_SD, "MMCHost Release: %a, %a\n", __DATE__, __TIME__));
|
Status = SdhciSoftReset(SRA);
|
if (EFI_ERROR (Status)) {
|
return Status;
|
}
|
|
DEBUG ((DEBUG_MMCHOST_SD, "MMCHost: CAP %X CAPH %X\n", MmioRead32(MMCHS_CAPA),MmioRead32(MMCHS_CUR_CAPA)));
|
|
// Lets switch to card detect test mode.
|
//SdMmioOr32 (MMCHS_HCTL, BIT7|BIT6);
|
|
// set card voltage
|
SdMmioAnd32 (MMCHS_HCTL, ~SDBP_ON);
|
SdMmioAndThenOr32 (MMCHS_HCTL, (UINT32) ~SDBP_MASK, SDVS_1_8_V);
|
SdMmioOr32 (MMCHS_HCTL, SDBP_ON);
|
|
DEBUG ((DEBUG_MMCHOST_SD, "MMCHost: AC12 %X HCTL %X\n", MmioRead32(MMCHS_AC12),MmioRead32(MMCHS_HCTL)));
|
|
// First turn off the clock
|
SdMmioAnd32 (MMCHS_SYSCTL, ~CEN);
|
|
// Attempt to set the clock to 400Khz which is the expected initialization speed
|
Status = CalculateClockFrequencyDivisor (400000, &Divisor, NULL);
|
if (EFI_ERROR (Status)) {
|
DEBUG ((DEBUG_ERROR, "MMCHost: MMCNotifyState(): Fail to initialize SD clock\n"));
|
return Status;
|
}
|
|
// Set Data Timeout Counter value, set clock frequency, enable internal clock
|
SdMmioOr32 (MMCHS_SYSCTL, DTO_VAL | Divisor | CEN | ICS | ICE);
|
SdMmioOr32 (MMCHS_HCTL, SDBP_ON);
|
// wait for ICS
|
while ((MmioRead32 (MMCHS_SYSCTL) & ICS_MASK) != ICS);
|
|
DEBUG ((DEBUG_MMCHOST_SD, "MMCHost: AC12 %X HCTL %X\n", MmioRead32(MMCHS_AC12),MmioRead32(MMCHS_HCTL)));
|
|
// Enable interrupts
|
SdMmioWrite32 (MMCHS_IE, ALL_EN);
|
}
|
break;
|
case MmcIdleState:
|
break;
|
case MmcReadyState:
|
break;
|
case MmcIdentificationState:
|
break;
|
case MmcStandByState:
|
ClockFrequency = 25000000;
|
Status = MMCSetClock(ClockFrequency);
|
if (EFI_ERROR (Status)) {
|
DEBUG ((DEBUG_ERROR, "MMCHost: MmcStandByState(): Fail to initialize SD clock to %u Hz\n",
|
ClockFrequency));
|
return Status;
|
}
|
break;
|
case MmcTransferState:
|
break;
|
case MmcSendingDataState:
|
break;
|
case MmcReceiveDataState:
|
break;
|
case MmcProgrammingState:
|
break;
|
case MmcDisconnectState:
|
case MmcInvalidState:
|
default:
|
DEBUG ((DEBUG_ERROR, "MMCHost: MMCNotifyState(): Invalid State: %d\n", State));
|
ASSERT (0);
|
}
|
|
return EFI_SUCCESS;
|
}
|
|
BOOLEAN
|
MMCIsCardPresent (
|
IN EFI_MMC_HOST_PROTOCOL *This
|
)
|
{
|
return TRUE;
|
}
|
|
EFI_STATUS
|
MMCReceiveResponse (
|
IN EFI_MMC_HOST_PROTOCOL *This,
|
IN MMC_RESPONSE_TYPE Type,
|
IN UINT32* Buffer
|
)
|
{
|
ASSERT (Buffer != NULL);
|
|
if (Type == MMC_RESPONSE_TYPE_R2) {
|
|
// 16-byte response
|
Buffer[0] = MmioRead32 (MMCHS_RSP10);
|
Buffer[1] = MmioRead32 (MMCHS_RSP32);
|
Buffer[2] = MmioRead32 (MMCHS_RSP54);
|
Buffer[3] = MmioRead32 (MMCHS_RSP76);
|
|
Buffer[3] <<= 8;
|
Buffer[3] |= (Buffer[2] >> 24) & 0xFF;
|
Buffer[2] <<= 8;
|
Buffer[2] |= (Buffer[1] >> 24) & 0xFF;
|
Buffer[1] <<= 8;
|
Buffer[1] |= (Buffer[0] >> 24) & 0xFF;
|
Buffer[0] <<= 8;
|
|
DEBUG ((DEBUG_MMCHOST_SD,
|
"MMCHost: MMCReceiveResponse(Type: %x), Buffer[0-3]: %08x, %08x, %08x, %08x\n",
|
Type, Buffer[0], Buffer[1], Buffer[2], Buffer[3]));
|
} else {
|
// 4-byte response
|
Buffer[0] = MmioRead32 (MMCHS_RSP10);
|
DEBUG ((DEBUG_MMCHOST_SD, "MMCHost: MMCReceiveResponse(Type: %08x), Buffer[0]: %08x\n", Type, Buffer[0]));
|
}
|
|
gBS->Stall (STALL_AFTER_REC_RESP_US);
|
if (LastExecutedCommand == CMD_STOP_TRANSMISSION) {
|
DEBUG ((DEBUG_MMCHOST_SD, "MMCHost: soft-resetting after CMD12\n"));
|
return SdhciSoftReset(SRC | SRD);
|
}
|
return EFI_SUCCESS;
|
}
|
|
EFI_STATUS
|
MMCReadBlockData (
|
IN EFI_MMC_HOST_PROTOCOL *This,
|
IN EFI_LBA Lba,
|
IN UINTN Length,
|
IN UINT32* Buffer
|
)
|
{
|
|
UINT16 Mode;
|
EFI_STATUS Status = EFI_SUCCESS;
|
SDHCI_DATA *data = &gSdhciData;
|
UINT32 cmd = 0;
|
UINTN StartAddr = (UINTN)Buffer;
|
|
DEBUG ((DEBUG_MMCHOST_SD, "%a(%u): LBA: 0x%x, Length: 0x%x, Buffer: 0x%x)\n",
|
__FUNCTION__, __LINE__, Lba, Length, Buffer));
|
|
if (Buffer == NULL) {
|
DEBUG ((DEBUG_ERROR, "%a(%u): NULL Buffer\n", __FUNCTION__, __LINE__));
|
return EFI_INVALID_PARAMETER;
|
}
|
|
if ((StartAddr & 0x7) != 0x0) {
|
DEBUG ((DEBUG_ERROR, "%a(%u): Buffer need 8 Byte align\n", __FUNCTION__, __LINE__));
|
return EFI_INVALID_PARAMETER;
|
}
|
|
if (Length % sizeof (UINT32) != 0) {
|
DEBUG ((DEBUG_ERROR, "%a(%u): bad Length %u\n", __FUNCTION__, __LINE__, Length));
|
return EFI_INVALID_PARAMETER;
|
}
|
|
if (data->blocksize == 0 || data->blocksize > 512)
|
{
|
DEBUG ((DEBUG_ERROR, "%a(%u): blocksize %u\n", __FUNCTION__, __LINE__, data->blocksize));
|
return EFI_INVALID_PARAMETER;
|
}
|
|
data->flags = MMC_DATA_READ;
|
data->blocks = (UINT32)((Length) / data->blocksize);
|
data->buffer = (UINT8 *)Buffer;
|
//memset(Buffer, 0xCC, Length);
|
|
MmioWrite16 (MMCHS_BLK_SIZE, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, data->blocksize));
|
MmioWrite16 (MMCHS_BLK_COUNT, (UINT16)data->blocks);
|
|
Mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_READ;
|
if (data->blocks > 1)
|
Mode |= (SDHCI_TRNS_MULTI /*| SDHCI_TRNS_ACMD12*/);
|
|
#ifdef CONFIG_MMC_SDHCI_SDMA
|
MmioWrite32 (MMCHS_DMA_ADDRESS, (UINT32)StartAddr);
|
Mode |= SDHCI_TRNS_DMA;
|
InvalidateDataCacheRange (Buffer, Length);
|
#endif
|
//MmioWrite16 (MMCHS_TRANS_MODE, Mode);
|
cmd = (mMmcDataCommand & 0xFFFF0000) | Mode;
|
Status = SdhciSendCommand(This, cmd, mMmcDataArgument, CMDI_MASK /*| DATI_MASK*/);
|
if (EFI_ERROR (Status)) {
|
DEBUG ((DEBUG_ERROR, "%a(%u): bad cmd %x\n", __FUNCTION__, __LINE__, mMmcDataCommand));
|
goto Exit;
|
}
|
|
Status = SdhciTransferData(This, data, StartAddr);
|
if (EFI_ERROR (Status)) {
|
DEBUG ((DEBUG_ERROR, "%a(%u): SdhciTransferData fail!\n", __FUNCTION__, __LINE__));
|
goto Exit;
|
}
|
|
MicroSecondDelay(1);
|
Exit:
|
//stat = MmioRead32(MMCHS_INT_STAT);
|
MmioWrite32 (MMCHS_INT_STAT, ALL_MASK);
|
SdhciSoftReset(SRC | SRD);
|
return Status;
|
}
|
|
EFI_STATUS
|
MMCWriteBlockData (
|
IN EFI_MMC_HOST_PROTOCOL *This,
|
IN EFI_LBA Lba,
|
IN UINTN Length,
|
IN UINT32* Buffer
|
)
|
{
|
UINT16 Mode;
|
EFI_STATUS Status = EFI_SUCCESS;
|
SDHCI_DATA *data = &gSdhciData;
|
UINT32 cmd = 0;
|
UINTN StartAddr = (UINTN)Buffer;
|
|
DEBUG ((DEBUG_MMCHOST_SD, "%a(%u): LBA: 0x%x, Length: 0x%x, Buffer: 0x%x)\n",
|
__FUNCTION__, __LINE__, Lba, Length, Buffer));
|
|
if (Buffer == NULL) {
|
DEBUG ((DEBUG_ERROR, "%a(%u): NULL Buffer\n", __FUNCTION__, __LINE__));
|
return EFI_INVALID_PARAMETER;
|
}
|
|
if ((StartAddr & 0x7) != 0x0) {
|
DEBUG ((DEBUG_ERROR, "%a(%u): Buffer need 8 Byte align\n", __FUNCTION__, __LINE__));
|
return EFI_INVALID_PARAMETER;
|
}
|
|
if (Length % sizeof (UINT32) != 0) {
|
DEBUG ((DEBUG_ERROR, "%a(%u): bad Length %u\n", __FUNCTION__, __LINE__, Length));
|
return EFI_INVALID_PARAMETER;
|
}
|
|
data->flags = MMC_DATA_WRITE;
|
data->blocks = (UINT32)((Length + data->blocksize - 1) / data->blocksize);
|
data->buffer = (UINT8 *)Buffer;
|
MmioWrite16 (MMCHS_BLK_SIZE, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, data->blocksize));
|
MmioWrite16 (MMCHS_BLK_COUNT, (UINT16)data->blocks);
|
|
Mode = SDHCI_TRNS_BLK_CNT_EN;
|
if (data->blocks > 1)
|
Mode |= SDHCI_TRNS_MULTI;
|
|
#ifdef CONFIG_MMC_SDHCI_SDMA
|
MmioWrite32 (MMCHS_DMA_ADDRESS, (UINT32)StartAddr);
|
Mode |= SDHCI_TRNS_DMA;
|
WriteBackDataCacheRange (Buffer, Length);
|
#endif
|
|
cmd = (mMmcDataCommand & 0xFFFF0000) | Mode;
|
Status = SdhciSendCommand(This, cmd, mMmcDataArgument, CMDI_MASK /*| DATI_MASK*/);
|
if (EFI_ERROR (Status)) {
|
DEBUG ((DEBUG_ERROR, "%a(%u): bad cmd %x\n", __FUNCTION__, __LINE__, mMmcDataCommand));
|
goto Exit;
|
}
|
|
Status = SdhciTransferData(This, data, StartAddr);
|
if (EFI_ERROR (Status)) {
|
DEBUG ((DEBUG_ERROR, "%a(%u): SdhciTransferData fail!\n", __FUNCTION__, __LINE__));
|
goto Exit;
|
}
|
|
MicroSecondDelay(1);
|
Exit:
|
//stat = MmioRead32(MMCHS_INT_STAT);
|
MmioWrite32 (MMCHS_INT_STAT, ALL_MASK);
|
SdhciSoftReset(SRC | SRD);
|
return Status;
|
}
|
|
EFI_STATUS
|
MMCSetIos (
|
IN EFI_MMC_HOST_PROTOCOL *This,
|
IN UINT32 BusClockFreq,
|
IN UINT32 BusWidth,
|
IN UINT32 TimingMode
|
)
|
{
|
EFI_STATUS Status = EFI_SUCCESS;
|
UINT32 Ctrl, Ctrl2;
|
|
if (BusClockFreq > 200*1000*1000) {
|
return EFI_UNSUPPORTED;
|
}
|
|
Ctrl = MmioRead8(MMCHS_HCTL);
|
if (TimingMode != EMMCBACKWARD) {
|
Ctrl2 = MmioRead16(MMCHS_HCTL2);
|
/* Select Bus Speed Mode for host */
|
Ctrl2 &= ~SDHCI_CTRL_UHS_MASK;
|
|
switch (TimingMode) {
|
case EMMCHS52DDR1V2:
|
case EMMCHS52DDR1V8:
|
case EMMCHS52:
|
//Ctrl |= HIGH_SPEED_EN;
|
Ctrl &= ~HIGH_SPEED_EN;
|
Ctrl2 |= (SDHCI_CTRL_VDD_180 | SDHCI_CTRL_DRV_TYPE_A | SDHCI_CTRL_EMMC_SDR50);
|
break;
|
case EMMCBACKWARD:
|
case EMMCHS26:
|
Ctrl &= ~HIGH_SPEED_EN;
|
break;
|
case EMMCHS400DDR1V8:
|
case EMMCHS400DDR1V2:
|
Ctrl |= HIGH_SPEED_EN;
|
Ctrl2 |= (SDHCI_CTRL_VDD_180 | SDHCI_CTRL_DRV_TYPE_A | SDHCI_CTRL_EMMC_HS400);
|
break;
|
|
default:
|
return EFI_UNSUPPORTED;
|
}
|
MmioWrite16(MMCHS_HCTL2, Ctrl2);
|
}
|
|
switch (BusWidth) {
|
case 1:
|
Ctrl &= ~DTW_4_BIT;
|
break;
|
case 4:
|
Ctrl |= DTW_4_BIT;;
|
break;
|
case 8:
|
Ctrl &= ~DTW_4_BIT;
|
Ctrl |= DTW_8_BIT;
|
break;
|
default:
|
return EFI_UNSUPPORTED;
|
}
|
|
MmioWrite8(MMCHS_HCTL, Ctrl);
|
if (BusClockFreq) {
|
Status = MMCSetClock (BusClockFreq);
|
}
|
return Status;
|
}
|
|
BOOLEAN
|
MMCIsMultiBlock (
|
IN EFI_MMC_HOST_PROTOCOL *This
|
)
|
{
|
return TRUE;
|
}
|
|
EFI_MMC_HOST_PROTOCOL gSdhciHost =
|
{
|
MMC_HOST_PROTOCOL_REVISION,
|
MMCIsCardPresent,
|
MMCIsReadOnly,
|
MMCBuildDevicePath,
|
MMCNotifyState,
|
MMCSendCommand,
|
MMCReceiveResponse,
|
MMCReadBlockData,
|
MMCWriteBlockData,
|
MMCSetIos,
|
MMCIsMultiBlock
|
};
|
|
EFI_STATUS
|
MMCInitialize (
|
IN EFI_HANDLE ImageHandle,
|
IN EFI_SYSTEM_TABLE *SystemTable
|
)
|
{
|
EFI_STATUS Status;
|
EFI_HANDLE Handle = NULL;
|
|
DEBUG ((DEBUG_MMCHOST_SD, "RkSdhciHost: MMCInitialize()\n"));
|
|
mMmcHsBase = PcdGet32 (PcdSdhciDxeBaseAddress);
|
SdhciEmmcDxeIoMux();
|
|
#if 0
|
word32(mMmcHsBase + 0x800) = (0x1 << 1);
|
MicroSecondDelay(10);
|
word32(mMmcHsBase + 0x800) = 0;
|
|
word32(0xFD7C0000 + 0x0A7C) = ((0x1FUL << 4) << 16) | (0x1F << 4);
|
MicroSecondDelay(10);
|
word32(0xFD7C0000 + 0x0A7C) = ((0x1FUL << 4) << 16) | (0 << 4);
|
|
word32(0xFD5FD000 + 0x40) = 0xFFFF6666;
|
word32(0xFD5FD000 + 0x58) = 0xFFFF6666;
|
word32(0xFD5FD000 + 0x5C) = 0xFFFF6666;
|
#endif
|
|
Status = gBS->InstallMultipleProtocolInterfaces (
|
&Handle,
|
&gEmbeddedMmcHostProtocolGuid,
|
&gSdhciHost,
|
NULL
|
);
|
ASSERT_EFI_ERROR (Status);
|
|
return Status;
|
}
|
