/** @file
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Copyright 2017, 2020 NXP
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef USB_HCD_H_
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#define USB_HCD_H_
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#include <Base.h>
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/* Global constants */
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#define DWC3_GSNPSID_MASK 0xffff0000
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#define DWC3_SYNOPSYS_ID 0x55330000
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#define DWC3_RELEASE_MASK 0xffff
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#define DWC3_REG_OFFSET 0xC100
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#define DWC3_RELEASE_190a 0x190a
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/* Global Configuration Register */
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#define DWC3_GCTL_U2RSTECN BIT16
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#define DWC3_GCTL_PRTCAPDIR(N) ((N) << 12)
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#define DWC3_GCTL_PRTCAP_HOST 1
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#define DWC3_GCTL_PRTCAP_OTG 3
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#define DWC3_GCTL_CORESOFTRESET BIT11
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#define DWC3_GCTL_SCALEDOWN(N) ((N) << 4)
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#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
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#define DWC3_GCTL_DISSCRAMBLE BIT3
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#define DWC3_GCTL_DSBLCLKGTNG BIT0
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/* Global HWPARAMS1 Register */
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#define DWC3_GHWPARAMS1_EN_PWROPT(N) (((N) & (3 << 24)) >> 24)
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#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
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/* Global USB2 PHY Configuration Register */
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#define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT31
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/* Global USB3 PIPE Control Register */
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#define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT31
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/* Global Frame Length Adjustment Register */
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#define GFLADJ_30MHZ_REG_SEL BIT7
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#define GFLADJ_30MHZ(N) ((N) & 0x3f)
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#define GFLADJ_30MHZ_DEFAULT 0x20
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/* Default to the FSL XHCI defines */
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#define USB3_ENABLE_BEAT_BURST 0xF
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#define USB3_ENABLE_BEAT_BURST_MASK 0xFF
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#define USB3_SET_BEAT_BURST_LIMIT 0xF00
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typedef struct {
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UINT32 GEvntAdrLo;
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UINT32 GEvntAdrHi;
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UINT32 GEvntSiz;
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UINT32 GEvntCount;
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} G_EVENT_BUFFER;
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typedef struct {
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UINT32 DDepCmdPar2;
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UINT32 DDepCmdPar1;
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UINT32 DDepCmdPar0;
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UINT32 DDepCmd;
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} D_PHYSICAL_EP;
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typedef struct {
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UINT32 GSBusCfg0;
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UINT32 GSBusCfg1;
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UINT32 GTxThrCfg;
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UINT32 GRxThrCfg;
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UINT32 GCtl;
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UINT32 Res1;
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UINT32 GSts;
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UINT32 Res2;
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UINT32 GSnpsId;
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UINT32 GGpio;
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UINT32 GUid;
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UINT32 GUctl;
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UINT64 GBusErrAddr;
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UINT64 GPrtbImap;
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UINT32 GHwParams0;
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UINT32 GHwParams1;
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UINT32 GHwParams2;
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UINT32 GHwParams3;
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UINT32 GHwParams4;
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UINT32 GHwParams5;
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UINT32 GHwParams6;
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UINT32 GHwParams7;
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UINT32 GDbgFifoSpace;
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UINT32 GDbgLtssm;
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UINT32 GDbgLnmcc;
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UINT32 GDbgBmu;
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UINT32 GDbgLspMux;
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UINT32 GDbgLsp;
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UINT32 GDbgEpInfo0;
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UINT32 GDbgEpInfo1;
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UINT64 GPrtbImapHs;
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UINT64 GPrtbImapFs;
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UINT32 Res3[28];
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UINT32 GUsb2PhyCfg[16];
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UINT32 GUsb2I2cCtl[16];
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UINT32 GUsb2PhyAcc[16];
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UINT32 GUsb3PipeCtl[16];
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UINT32 GTxFifoSiz[32];
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UINT32 GRxFifoSiz[32];
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G_EVENT_BUFFER GEvntBuf[32];
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UINT32 GHwParams8;
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UINT32 Res4[11];
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UINT32 GFLAdj;
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UINT32 Res5[51];
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UINT32 DCfg;
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UINT32 DCtl;
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UINT32 DEvten;
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UINT32 DSts;
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UINT32 DGCmdPar;
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UINT32 DGCmd;
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UINT32 Res6[2];
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UINT32 DAlepena;
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UINT32 Res7[55];
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D_PHYSICAL_EP DPhyEpCmd[32];
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UINT32 Res8[128];
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UINT32 OCfg;
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UINT32 OCtl;
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UINT32 OEvt;
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UINT32 OEvtEn;
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UINT32 OSts;
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UINT32 Res9[3];
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UINT32 AdpCfg;
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UINT32 AdpCtl;
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UINT32 AdpEvt;
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UINT32 AdpEvten;
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UINT32 BcCfg;
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UINT32 Res10;
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UINT32 BcEvt;
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UINT32 BcEvten;
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} DWC3;
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#endif
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