/** @file
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Copyright 2018-2020 NXP
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef CHASSIS_H__
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#define CHASSIS_H__
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#include <Uefi.h>
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#define NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS 0x1E00000
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#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFE)
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#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
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#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
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/**
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The Device Configuration Unit provides general purpose configuration and
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status for the device. These registers only support 32-bit accesses.
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**/
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#pragma pack(1)
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typedef struct {
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UINT8 Reserved0[0x70 - 0x0];
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UINT32 DeviceDisableRegister1; // Device Disable Register 1
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UINT32 DeviceDisableRegister2; // Device Disable Register 2
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UINT32 DeviceDisableRegister3; // Device Disable Register 3
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UINT32 DeviceDisableRegister4; // Device Disable Register 4
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UINT32 DeviceDisableRegister5; // Device Disable Register 5
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UINT32 DeviceDisableRegister6; // Device Disable Register 6
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UINT32 DeviceDisableRegister7; // Device Disable Register 7
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UINT8 Reserved1[0xa4 - 0x8c];
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UINT32 Svr; // System Version Register
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UINT8 Reserved2[0x100 - 0xa8];
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UINT32 RcwSr[32]; // Reset Control Word Status Register
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} NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG;
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#pragma pack()
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#endif // CHASSIS_H__
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