/** @file
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Secondary System Description Table Fields (SSDT)
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Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
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Copyright (c) 2019, Marvell International Ltd. and its affiliates.<BR>
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Copyright (C) 2021, Semihalf.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "Cn913xCEx7Eval/Pcie.h"
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#include "IcuInterrupts.h"
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DefinitionBlock ("Cn9132CEx7EvalSsdt.aml", "SSDT", 2, "MRVL", "CN913X", 3)
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{
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Scope (_SB)
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{
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Device (AHC1)
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{
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Name (_HID, "LNRO001E") // _HID: Hardware ID
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Name (_UID, 0x01) // _UID: Unique ID
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Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
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Method (_STA) // _STA: Device status
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{
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Return (0xF)
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}
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Name (_CLS, Package (0x03) // _CLS: Class Code
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{
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0x01,
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0x06,
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0x01
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})
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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Memory32Fixed (ReadWrite,
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0xF6540000, // Address Base (MMIO)
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0x00030000, // Address Length
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)
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Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
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{
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CP_GIC_SPI_CP2_SATA_H0
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}
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})
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}
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Device (XHC3)
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{
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Name (_HID, "PNP0D10") // _HID: Hardware ID
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Name (_UID, 0x03) // _UID: Unique ID
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Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
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Method (_STA) // _STA: Device status
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{
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Return (0xF)
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}
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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Memory32Fixed (ReadWrite,
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0xF6500000, // Address Base (MMIO)
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0x00004000, // Address Length
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)
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Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
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{
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CP_GIC_SPI_CP2_USB_H0
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}
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})
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}
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Device (XHC4)
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{
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Name (_HID, "PNP0D10") // _HID: Hardware ID
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Name (_UID, 0x04) // _UID: Unique ID
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Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
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Method (_STA) // _STA: Device status
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{
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Return (0xF)
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}
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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Memory32Fixed (ReadWrite,
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0xF6510000, // Address Base (MMIO)
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0x00004000, // Address Length
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)
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Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
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{
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CP_GIC_SPI_CP2_USB_H1
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}
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})
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}
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Device (XSM2)
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{
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Name (_HID, "MRVL0101") // _HID: Hardware ID
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Name (_UID, 0x01) // _UID: Unique ID
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Method (_STA) // _STA: Device status
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{
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Return (0xF)
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}
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Name (_CRS, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite,
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0xf412a600, // Address Base
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0x00000010, // Address Length
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)
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})
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Device (PHY0)
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{
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Name (_ADR, 0x0)
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Name (_DSD, Package () {
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ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
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Package () {
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Package () { "compatible", "ethernet-phy-ieee802.3-c45" },
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}
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})
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}
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}
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Device (PP22)
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{
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Name (_HID, "MRVL0110") // _HID: Hardware ID
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Name (_CCA, 0x01) // Cache-coherent controller
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Name (_UID, 0x02) // _UID: Unique ID
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Method (_STA) // _STA: Device status
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{
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Return (0xF)
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}
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Name (_CRS, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, 0xf6000000 , 0x100000)
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Memory32Fixed (ReadWrite, 0xf6129000 , 0xb000)
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Memory32Fixed (ReadWrite, 0xf6220000 , 0x800)
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})
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Name (_DSD, Package () {
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ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
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Package () {
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Package () { "clock-frequency", 333333333 },
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}
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})
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Device (ETH0)
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{
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Name (_ADR, 0x0)
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Name (_CRS, ResourceTemplate ()
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{
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Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
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{
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CP_GIC_SPI_PP2_CP2_PORT0
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}
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})
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Name (_DSD, Package () {
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ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
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Package () {
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Package () { "port-id", 0 },
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Package () { "gop-port-id", 0 },
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Package () { "phy-mode", "5gbase-r"},
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Package () { "phy-handle", \_SB.XSM2.PHY0},
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}
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})
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}
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}
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Device (RNG2)
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{
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Name (_HID, "PRP0001") // _HID: Hardware ID
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Name (_UID, 0x02) // _UID: Unique ID
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Method (_STA) // _STA: Device status
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{
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Return (0xF)
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}
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Name (_CRS, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, 0xF6760000, 0x7D)
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Interrupt (ResourceConsumer, Level, ActiveHigh, Shared)
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{
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CP_GIC_SPI_CP2_EIP_RNG0
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}
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})
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Name (_DSD, Package () {
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ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
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Package () {
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Package () { "compatible", "inside-secure,safexcel-eip76" },
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}
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})
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}
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Device (PCI4)
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{
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Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
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Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
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Name (_SEG, 0x04) // _SEG: PCI Segment
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Name (_BBN, 0x00) // _BBN: BIOS Bus Number
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Name (_UID, 0x04) // _UID: Unique ID
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Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
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Method (_STA) // _STA: Device status
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{
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Return (0xF)
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}
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Name (_PRT, Package () // _PRT: PCI Routing Table
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{
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Package () { 0xFFFF, 0x0, 0x0, 0x40 },
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Package () { 0xFFFF, 0x1, 0x0, 0x40 },
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Package () { 0xFFFF, 0x2, 0x0, 0x40 },
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Package () { 0xFFFF, 0x3, 0x0, 0x40 }
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})
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Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
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{
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Name (RBUF, ResourceTemplate ()
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{
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WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
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0x0000, // Granularity
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CP2_PCI0_BUS_MIN, // Range Minimum
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CP2_PCI0_BUS_MAX, // Range Maximum
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0x0000, // Translation Offset
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CP2_PCI0_BUS_COUNT // Length
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)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
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0x00000000, // Granularity
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CP2_PCI0_MMIO32_BASE, // Range Minimum
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CP2_PCI0_MMIO32_MAX, // Range Maximum
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0x00000000, // Translation Offset
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CP2_PCI0_MMIO32_SIZE // Length
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)
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QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
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0x0000000000000000, // Granularity
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CP2_PCI0_MMIO64_BASE, // Range Minimum
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CP2_PCI0_MMIO64_MAX, // Range Maximum
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0x00000000, // Translation Offset
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CP2_PCI0_MMIO64_SIZE // Length
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)
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DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x00000000, // Granularity
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CP2_PCI0_IO_BASE, // Range Minimum
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0x0000FFFF, // Range Maximum
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CP2_PCI0_IO_TRANSLATION, // Translation Address
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CP2_PCI0_IO_SIZE, // Length
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,
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,
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,
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TypeTranslation
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)
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})
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Return (RBUF) /* \_SB_.PCI4._CRS.RBUF */
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} // Method(_CRS)
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Device (RES0)
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{
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Name (_HID, "PNP0C02")
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Name (_CRS, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite,
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CP2_PCI0_ECAM_BASE, // Range Minimum
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CP2_PCI0_ECAM_SIZE // Length
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)
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})
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}
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Name (SUPP, 0x00)
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Name (CTRL, 0x00)
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Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
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{
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CreateDWordField (Arg3, 0x00, CDW1)
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If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
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{
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CreateDWordField (Arg3, 0x04, CDW2)
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CreateDWordField (Arg3, 0x08, CDW3)
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Store (CDW2, SUPP) /* \_SB_.PCI4.SUPP */
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Store (CDW3, CTRL) /* \_SB_.PCI4.CTRL */
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If (LNotEqual (And (SUPP, 0x16), 0x16))
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{
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And (CTRL, 0x1E, CTRL) /* \_SB_.PCI4.CTRL */
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}
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And (CTRL, 0x1D, CTRL) /* \_SB_.PCI4.CTRL */
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If (LNotEqual (Arg1, One))
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{
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Or (CDW1, 0x08, CDW1) /* \_SB_.PCI4._OSC.CDW1 */
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}
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If (LNotEqual (CDW3, CTRL))
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{
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Or (CDW1, 0x10, CDW1) /* \_SB_.PCI4._OSC.CDW1 */
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}
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Store (CTRL, CDW3) /* \_SB_.PCI4._OSC.CDW3 */
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Return (Arg3)
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}
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Else
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{
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Or (CDW1, 0x04, CDW1) /* \_SB_.PCI4._OSC.CDW1 */
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Return (Arg3)
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}
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} // Method(_OSC)
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}
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Device (PCI5)
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{
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Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
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Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
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Name (_SEG, 0x05) // _SEG: PCI Segment
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Name (_BBN, 0x00) // _BBN: BIOS Bus Number
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Name (_UID, 0x05) // _UID: Unique ID
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Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
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Method (_STA) // _STA: Device status
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{
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Return (0xF)
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}
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Name (_PRT, Package () // _PRT: PCI Routing Table
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{
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Package () { 0xFFFF, 0x0, 0x0, 0x40 },
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Package () { 0xFFFF, 0x1, 0x0, 0x40 },
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Package () { 0xFFFF, 0x2, 0x0, 0x40 },
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Package () { 0xFFFF, 0x3, 0x0, 0x40 }
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})
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Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
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{
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Name (RBUF, ResourceTemplate ()
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{
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WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
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0x0000, // Granularity
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CP2_PCI1_BUS_MIN, // Range Minimum
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CP2_PCI1_BUS_MAX, // Range Maximum
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0x0000, // Translation Offset
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CP2_PCI1_BUS_COUNT // Length
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)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
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0x00000000, // Granularity
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CP2_PCI1_MMIO32_BASE, // Range Minimum
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CP2_PCI1_MMIO32_MAX, // Range Maximum
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0x00000000, // Translation Offset
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CP2_PCI1_MMIO32_SIZE // Length
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)
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QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
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0x0000000000000000, // Granularity
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CP2_PCI1_MMIO64_BASE, // Range Minimum
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CP2_PCI1_MMIO64_MAX, // Range Maximum
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0x00000000, // Translation Offset
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CP2_PCI1_MMIO64_SIZE // Length
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)
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DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x00000000, // Granularity
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CP2_PCI1_IO_BASE, // Range Minimum
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0x0000FFFF, // Range Maximum
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CP2_PCI1_IO_TRANSLATION, // Translation Address
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CP2_PCI1_IO_SIZE, // Length
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,
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,
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,
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TypeTranslation
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)
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})
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Return (RBUF) /* \_SB_.PCI5._CRS.RBUF */
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} // Method(_CRS)
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Device (RES0)
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{
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Name (_HID, "PNP0C02")
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Name (_CRS, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite,
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CP2_PCI1_ECAM_BASE, // Range Minimum
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CP2_PCI1_ECAM_SIZE // Length
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)
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})
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}
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Name (SUPP, 0x00)
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Name (CTRL, 0x00)
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Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
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{
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CreateDWordField (Arg3, 0x00, CDW1)
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If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
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{
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CreateDWordField (Arg3, 0x04, CDW2)
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CreateDWordField (Arg3, 0x08, CDW3)
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Store (CDW2, SUPP) /* \_SB_.PCI5.SUPP */
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Store (CDW3, CTRL) /* \_SB_.PCI5.CTRL */
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If (LNotEqual (And (SUPP, 0x16), 0x16))
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{
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And (CTRL, 0x1E, CTRL) /* \_SB_.PCI5.CTRL */
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}
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And (CTRL, 0x1D, CTRL) /* \_SB_.PCI5.CTRL */
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If (LNotEqual (Arg1, One))
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{
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Or (CDW1, 0x08, CDW1) /* \_SB_.PCI5._OSC.CDW1 */
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}
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If (LNotEqual (CDW3, CTRL))
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{
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Or (CDW1, 0x10, CDW1) /* \_SB_.PCI5._OSC.CDW1 */
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}
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Store (CTRL, CDW3) /* \_SB_.PCI5._OSC.CDW3 */
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Return (Arg3)
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}
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Else
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{
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Or (CDW1, 0x04, CDW1) /* \_SB_.PCI5._OSC.CDW1 */
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Return (Arg3)
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}
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} // Method(_OSC)
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}
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Device (PCI6)
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{
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Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
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Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
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Name (_SEG, 0x06) // _SEG: PCI Segment
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Name (_BBN, 0x00) // _BBN: BIOS Bus Number
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Name (_UID, 0x06) // _UID: Unique ID
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Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
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Method (_STA) // _STA: Device status
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{
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Return (0xF)
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}
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Name (_PRT, Package () // _PRT: PCI Routing Table
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{
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Package () { 0xFFFF, 0x0, 0x0, 0x40 },
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Package () { 0xFFFF, 0x1, 0x0, 0x40 },
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Package () { 0xFFFF, 0x2, 0x0, 0x40 },
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Package () { 0xFFFF, 0x3, 0x0, 0x40 }
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})
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Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
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{
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Name (RBUF, ResourceTemplate ()
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{
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WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
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0x0000, // Granularity
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CP2_PCI2_BUS_MIN, // Range Minimum
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CP2_PCI2_BUS_MAX, // Range Maximum
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0x0000, // Translation Offset
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CP2_PCI2_BUS_COUNT // Length
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)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
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0x00000000, // Granularity
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CP2_PCI2_MMIO32_BASE, // Range Minimum
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CP2_PCI2_MMIO32_MAX, // Range Maximum
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0x00000000, // Translation Offset
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CP2_PCI2_MMIO32_SIZE // Length
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)
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QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
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0x0000000000000000, // Granularity
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CP2_PCI2_MMIO64_BASE, // Range Minimum
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CP2_PCI2_MMIO64_MAX, // Range Maximum
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0x00000000, // Translation Offset
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CP2_PCI2_MMIO64_SIZE // Length
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)
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DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x00000000, // Granularity
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CP2_PCI2_IO_BASE, // Range Minimum
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0x0000FFFF, // Range Maximum
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CP2_PCI2_IO_TRANSLATION, // Translation Address
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CP2_PCI2_IO_SIZE, // Length
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,
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,
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,
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TypeTranslation
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)
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})
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Return (RBUF) /* \_SB_.PCI6._CRS.RBUF */
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} // Method(_CRS)
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Device (RES0)
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{
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Name (_HID, "PNP0C02")
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Name (_CRS, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite,
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CP2_PCI2_ECAM_BASE, // Range Minimum
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CP2_PCI2_ECAM_SIZE // Length
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)
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})
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}
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Name (SUPP, 0x00)
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Name (CTRL, 0x00)
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Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
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{
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CreateDWordField (Arg3, 0x00, CDW1)
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If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
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{
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CreateDWordField (Arg3, 0x04, CDW2)
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CreateDWordField (Arg3, 0x08, CDW3)
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Store (CDW2, SUPP) /* \_SB_.PCI6.SUPP */
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Store (CDW3, CTRL) /* \_SB_.PCI6.CTRL */
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If (LNotEqual (And (SUPP, 0x16), 0x16))
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{
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And (CTRL, 0x1E, CTRL) /* \_SB_.PCI6.CTRL */
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}
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And (CTRL, 0x1D, CTRL) /* \_SB_.PCI6.CTRL */
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If (LNotEqual (Arg1, One))
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{
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Or (CDW1, 0x08, CDW1) /* \_SB_.PCI6._OSC.CDW1 */
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}
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If (LNotEqual (CDW3, CTRL))
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{
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Or (CDW1, 0x10, CDW1) /* \_SB_.PCI6._OSC.CDW1 */
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}
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Store (CTRL, CDW3) /* \_SB_.PCI6._OSC.CDW3 */
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Return (Arg3)
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}
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Else
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{
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Or (CDW1, 0x04, CDW1) /* \_SB_.PCI6._OSC.CDW1 */
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Return (Arg3)
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}
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} // Method(_OSC)
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}
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}
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}
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