/**
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*
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* Copyright (C) 2018, Marvell International Ltd. and its affiliates.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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* Glossary - abbreviations used in Marvell SampleAtReset library implementation:
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* ICU - Interrupt Consolidation Unit
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* AP - Application Processor hardware block (Armada 7k8k incorporates AP806)
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* CP - South Bridge hardware blocks (Armada 7k8k incorporates CP110)
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*
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**/
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#include "IcuLib.h"
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STATIC EFI_EVENT mEfiExitBootServicesEvent;
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STATIC CONST ICU_IRQ IrqMapNonSecure[] = {
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{27, 0, IcuIrqTypeLevel}, /* SD/MMC */
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{39, 1, IcuIrqTypeLevel}, /* PPv2 Irq */
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{40, 2, IcuIrqTypeLevel}, /* PPv2 Irq */
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{41, 3, IcuIrqTypeLevel}, /* PPv2 Irq */
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{43, 4, IcuIrqTypeLevel}, /* PPv2 Irq */
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{44, 5, IcuIrqTypeLevel}, /* PPv2 Irq */
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{45, 6, IcuIrqTypeLevel}, /* PPv2 Irq */
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{47, 7, IcuIrqTypeLevel}, /* PPv2 Irq */
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{48, 8, IcuIrqTypeLevel}, /* PPv2 Irq */
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{49, 9, IcuIrqTypeLevel}, /* PPv2 Irq */
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{51, 10, IcuIrqTypeLevel}, /* PPv2 Irq */
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{52, 11, IcuIrqTypeLevel}, /* PPv2 Irq */
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{53, 12, IcuIrqTypeLevel}, /* PPv2 Irq */
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{55, 13, IcuIrqTypeLevel}, /* PPv2 Irq */
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{56, 14, IcuIrqTypeLevel}, /* PPv2 Irq */
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{57, 15, IcuIrqTypeLevel}, /* PPv2 Irq */
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{88, 16, IcuIrqTypeLevel}, /* EIP-197 ring-0 */
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{105, 17, IcuIrqTypeLevel}, /* USB3 Host-1 Irq */
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{106, 18, IcuIrqTypeLevel}, /* USB3 Host-0 Irq */
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{107, 19, IcuIrqTypeLevel}, /* SATA Host-1 Irq */
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{109, 19, IcuIrqTypeLevel}, /* SATA Host-0 Irq */
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{122, 20, IcuIrqTypeLevel}, /* UART 0 Irq */
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{123, 21, IcuIrqTypeLevel}, /* UART 1 Irq */
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{124, 22, IcuIrqTypeLevel}, /* UART 2 Irq */
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{125, 23, IcuIrqTypeLevel}, /* UART 3 Irq */
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{127, 24, IcuIrqTypeLevel}, /* GOP-3 Irq */
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{128, 25, IcuIrqTypeLevel}, /* GOP-2 Irq */
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{129, 26, IcuIrqTypeLevel}, /* GOP-0 Irq */
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};
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/*
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* SEI - System Error Interrupts
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* Note: SPI ID 0-20 are reserved for North-Bridge
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*/
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STATIC ICU_IRQ IrqMapSei[] = {
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{11, 21, IcuIrqTypeLevel}, /* SEI error CP-2-CP */
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{15, 22, IcuIrqTypeLevel}, /* PIDI-64 SOC */
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{16, 23, IcuIrqTypeLevel}, /* D2D error Irq */
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{17, 24, IcuIrqTypeLevel}, /* D2D Irq */
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{18, 25, IcuIrqTypeLevel}, /* NAND error */
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{19, 26, IcuIrqTypeLevel}, /* PCIx4 error */
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{20, 27, IcuIrqTypeLevel}, /* PCIx1_0 error */
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{21, 28, IcuIrqTypeLevel}, /* PCIx1_1 error */
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{25, 29, IcuIrqTypeLevel}, /* SDIO reg error */
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{75, 30, IcuIrqTypeLevel}, /* IOB error */
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{94, 31, IcuIrqTypeLevel}, /* EIP150 error */
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{97, 32, IcuIrqTypeLevel}, /* XOR-1 system error */
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{99, 33, IcuIrqTypeLevel}, /* XOR-0 system error */
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{108, 34, IcuIrqTypeLevel}, /* SATA-1 error */
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{110, 35, IcuIrqTypeLevel}, /* SATA-0 error */
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{114, 36, IcuIrqTypeLevel}, /* TDM-MC error */
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{116, 37, IcuIrqTypeLevel}, /* DFX server Irq */
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{117, 38, IcuIrqTypeLevel}, /* Device bus error */
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{147, 39, IcuIrqTypeLevel}, /* Audio error */
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{171, 40, IcuIrqTypeLevel}, /* PIDI Sync error */
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};
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/* REI - RAM Error Interrupts */
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STATIC CONST ICU_IRQ IrqMapRei[] = {
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{12, 0, IcuIrqTypeLevel}, /* REI error CP-2-CP */
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{26, 1, IcuIrqTypeLevel}, /* SDIO memory error */
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{87, 2, IcuIrqTypeLevel}, /* EIP-197 ECC error */
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{93, 3, IcuIrqTypeEdge}, /* EIP-150 RAM error */
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{96, 4, IcuIrqTypeLevel}, /* XOR-1 memory Irq */
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{98, 5, IcuIrqTypeLevel}, /* XOR-0 memory Irq */
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{100, 6, IcuIrqTypeEdge}, /* USB3 device tx parity */
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{101, 7, IcuIrqTypeEdge}, /* USB3 device rq parity */
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{103, 8, IcuIrqTypeEdge}, /* USB3H-1 RAM error */
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{104, 9, IcuIrqTypeEdge}, /* USB3H-0 RAM error */
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};
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STATIC CONST ICU_CONFIG IcuInitialConfig = {
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.NonSecure = { IrqMapNonSecure, ARRAY_SIZE (IrqMapNonSecure) },
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.Sei = { IrqMapSei, ARRAY_SIZE (IrqMapSei) },
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.Rei = { IrqMapRei, ARRAY_SIZE (IrqMapRei) },
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};
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STATIC
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VOID
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IcuClearIrq (
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IN UINTN IcuBase,
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IN UINTN Nr
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)
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{
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MmioWrite32 (IcuBase + ICU_INT_CFG (Nr), 0);
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}
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STATIC
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VOID
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IcuSetIrq (
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IN UINTN IcuBase,
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IN CONST ICU_IRQ *Irq,
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IN UINTN SpiBase,
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IN ICU_GROUP Group
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)
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{
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UINT32 IcuInt;
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IcuInt = (Irq->SpiId + SpiBase) | (1 << ICU_INT_ENABLE_OFFSET);
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IcuInt |= Irq->IrqType << ICU_IS_EDGE_OFFSET;
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IcuInt |= Group << ICU_GROUP_OFFSET;
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MmioWrite32 (IcuBase + ICU_INT_CFG (Irq->IcuId), IcuInt);
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}
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STATIC
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VOID
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IcuConfigure (
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IN UINTN CpIndex,
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IN MV_SOC_ICU_DESC *IcuDesc,
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IN CONST ICU_CONFIG *Config
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)
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{
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UINTN IcuBase, Index, SpiOffset, SpiBase;
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CONST ICU_IRQ *Irq;
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ICU_MSI *Msi;
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/* Get ICU registers base address */
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IcuBase = ICU_REG_BASE (CpIndex);
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/* Get the base of the GIC SPI ID in the MSI message */
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SpiBase = IcuDesc->IcuSpiBase;
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/* Get multiple CP110 instances SPI ID shift */
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SpiOffset = ICU_SPI_OFFSET (CpIndex);
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/* Get MSI addresses per interrupt group */
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Msi = IcuDesc->IcuMsi;
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/* Set the address for SET_SPI and CLR_SPI registers in AP */
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for (Index = 0; Index < IcuGroupMax; Index++, Msi++) {
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MmioWrite32 (IcuBase + ICU_SET_SPI_AL (Msi->Group),
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Msi->SetSpiAddr & 0xFFFFFFFF);
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MmioWrite32 (IcuBase + ICU_SET_SPI_AH (Msi->Group), Msi->SetSpiAddr >> 32);
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MmioWrite32 (IcuBase + ICU_CLR_SPI_AL (Msi->Group),
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Msi->ClrSpiAddr & 0xFFFFFFFF);
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MmioWrite32 (IcuBase + ICU_CLR_SPI_AH (Msi->Group), Msi->ClrSpiAddr >> 32);
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}
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/* Mask all ICU interrupts */
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for (Index = 0; Index < MAX_ICU_IRQS; Index++) {
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IcuClearIrq (IcuBase, Index);
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}
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/* Configure the ICU interrupt lines */
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Irq = Config->NonSecure.Map;
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for (Index = 0; Index < Config->NonSecure.Size; Index++, Irq++) {
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IcuSetIrq (IcuBase, Irq, SpiBase + SpiOffset, IcuGroupNsr);
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}
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Irq = Config->Sei.Map;
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for (Index = 0; Index < Config->Sei.Size; Index++, Irq++) {
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IcuSetIrq (IcuBase, Irq, SpiBase, IcuGroupSei);
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}
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Irq = Config->Rei.Map;
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for (Index = 0; Index < Config->Rei.Size; Index++, Irq++) {
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IcuSetIrq (IcuBase, Irq, SpiBase, IcuGroupRei);
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}
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}
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STATIC
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VOID
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IcuClearGicSpi (
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IN UINTN CpIndex,
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IN MV_SOC_ICU_DESC *IcuDesc
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)
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{
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CONST ICU_CONFIG *Config;
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UINTN Index, SpiOffset, SpiBase;
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CONST ICU_IRQ *Irq;
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ICU_MSI *Msi;
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Config = &IcuInitialConfig;
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/* Get the base of the GIC SPI ID in the MSI message */
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SpiBase = IcuDesc->IcuSpiBase;
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/* Get multiple CP110 instances SPI ID shift */
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SpiOffset = ICU_SPI_OFFSET (CpIndex);
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/* Get MSI addresses per interrupt group */
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Msi = IcuDesc->IcuMsi;
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/* Clear ICU-generated GIC SPI interrupts */
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Irq = Config->NonSecure.Map;
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for (Index = 0; Index < Config->NonSecure.Size; Index++, Irq++) {
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MmioWrite32 (Msi->ClrSpiAddr, Irq->SpiId + SpiBase + SpiOffset);
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}
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}
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VOID
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EFIAPI
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IcuCleanUp (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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MV_SOC_ICU_DESC *IcuDesc;
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UINTN CpCount, CpIndex;
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IcuDesc = Context;
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CpCount = FixedPcdGet8 (PcdMaxCpCount);
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for (CpIndex = 0; CpIndex < CpCount; CpIndex++) {
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IcuClearGicSpi (CpIndex, IcuDesc);
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}
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}
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EFI_STATUS
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EFIAPI
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ArmadaIcuInitialize (
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)
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{
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MV_SOC_ICU_DESC *IcuDesc;
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UINTN CpCount, CpIndex;
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EFI_STATUS Status;
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CpCount = FixedPcdGet8 (PcdMaxCpCount);
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ASSERT (CpCount <= ICU_MAX_SUPPORTED_UNITS);
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/* Obtain SoC description of the ICU */
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Status = ArmadaSoCDescIcuGet (&IcuDesc);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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/* Configure default ICU to GIC interrupt mapping for each CP110 */
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for (CpIndex = 0; CpIndex < CpCount; CpIndex++) {
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IcuConfigure (CpIndex, IcuDesc, &IcuInitialConfig);
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}
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/*
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* In order to be immune to the OS capability of clearing ICU-generated
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* GIC interrupts, register ExitBootServices event, that will
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* make sure they remain disabled during OS boot.
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*/
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Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES,
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TPL_NOTIFY,
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IcuCleanUp,
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IcuDesc,
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&mEfiExitBootServicesEvent);
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return Status;
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}
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