/** @file
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This driver is used to manage SD/MMC PCI host controllers which are compliance
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with SD Host Controller Simplified Specification version 3.00.
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It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
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Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2018, Marvell International, Ltd. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "XenonSdMmcOverride.h"
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/**
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Read/Write specified SD/MMC host controller mmio register.
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@param[in] PciIo The PCI IO protocol instance.
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@param[in] BarIndex The BAR index of the standard PCI Configuration
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header to use as the base address for the memory
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operation to perform.
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@param[in] Offset The offset within the selected BAR to start the
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memory operation.
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@param[in] Read A boolean to indicate it's read or write operation.
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@param[in] Count The width of the mmio register in bytes.
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Must be 1, 2 , 4 or 8 bytes.
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@param[in, out] Data For read operations, the destination buffer to store
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the results. For write operations, the source buffer
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to write data from. The caller is responsible for
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having ownership of the data buffer and ensuring its
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size not less than Count bytes.
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@retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
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@retval EFI_SUCCESS The read/write operation succeeds.
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@retval Others The read/write operation fails.
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**/
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EFI_STATUS
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EFIAPI
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XenonHcRwMmio (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT8 BarIndex,
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IN UINT32 Offset,
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IN BOOLEAN Read,
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IN UINT8 Count,
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IN OUT VOID *Data
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)
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{
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EFI_STATUS Status;
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if ((PciIo == NULL) || (Data == NULL)) {
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return EFI_INVALID_PARAMETER;
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}
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if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) {
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return EFI_INVALID_PARAMETER;
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}
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if (Read) {
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Status = PciIo->Mem.Read (
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PciIo,
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EfiPciIoWidthUint8,
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BarIndex,
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(UINT64) Offset,
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Count,
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Data
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);
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} else {
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Status = PciIo->Mem.Write (
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PciIo,
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EfiPciIoWidthUint8,
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BarIndex,
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(UINT64) Offset,
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Count,
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Data
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);
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}
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return Status;
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}
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/**
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Do OR operation with the value of the specified SD/MMC host controller mmio register.
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@param[in] PciIo The PCI IO protocol instance.
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@param[in] BarIndex The BAR index of the standard PCI Configuration
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header to use as the base address for the memory
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operation to perform.
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@param[in] Offset The offset within the selected BAR to start the
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memory operation.
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@param[in] Count The width of the mmio register in bytes.
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Must be 1, 2 , 4 or 8 bytes.
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@param[in] OrData The pointer to the data used to do OR operation.
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The caller is responsible for having ownership of
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the data buffer and ensuring its size not less than
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Count bytes.
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@retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
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@retval EFI_SUCCESS The OR operation succeeds.
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@retval Others The OR operation fails.
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**/
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EFI_STATUS
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EFIAPI
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XenonHcOrMmio (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT8 BarIndex,
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IN UINT32 Offset,
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IN UINT8 Count,
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IN VOID *OrData
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)
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{
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EFI_STATUS Status;
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UINT64 Data;
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UINT64 Or;
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Status = XenonHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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if (Count == 1) {
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Or = *(UINT8*) OrData;
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} else if (Count == 2) {
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Or = *(UINT16*) OrData;
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} else if (Count == 4) {
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Or = *(UINT32*) OrData;
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} else if (Count == 8) {
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Or = *(UINT64*) OrData;
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} else {
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return EFI_INVALID_PARAMETER;
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}
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Data |= Or;
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Status = XenonHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
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return Status;
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}
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/**
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Do AND operation with the value of the specified SD/MMC host controller mmio register.
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@param[in] PciIo The PCI IO protocol instance.
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@param[in] BarIndex The BAR index of the standard PCI Configuration
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header to use as the base address for the memory
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operation to perform.
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@param[in] Offset The offset within the selected BAR to start the
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memory operation.
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@param[in] Count The width of the mmio register in bytes.
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Must be 1, 2 , 4 or 8 bytes.
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@param[in] AndData The pointer to the data used to do AND operation.
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The caller is responsible for having ownership of
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the data buffer and ensuring its size not less than
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Count bytes.
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@retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
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@retval EFI_SUCCESS The AND operation succeeds.
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@retval Others The AND operation fails.
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**/
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EFI_STATUS
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EFIAPI
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XenonHcAndMmio (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT8 BarIndex,
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IN UINT32 Offset,
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IN UINT8 Count,
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IN VOID *AndData
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)
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{
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EFI_STATUS Status;
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UINT64 Data;
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UINT64 And;
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Status = XenonHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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if (Count == 1) {
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And = *(UINT8*) AndData;
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} else if (Count == 2) {
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And = *(UINT16*) AndData;
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} else if (Count == 4) {
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And = *(UINT32*) AndData;
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} else if (Count == 8) {
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And = *(UINT64*) AndData;
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} else {
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return EFI_INVALID_PARAMETER;
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}
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Data &= And;
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Status = XenonHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
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return Status;
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}
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/**
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Wait for the value of the specified MMIO register set to the test value.
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@param[in] PciIo The PCI IO protocol instance.
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@param[in] BarIndex The BAR index of the standard PCI Configuration
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header to use as the base address for the memory
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operation to perform.
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@param[in] Offset The offset within the selected BAR to start the
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memory operation.
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@param[in] Count The width of the mmio register in bytes.
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Must be 1, 2, 4 or 8 bytes.
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@param[in] MaskValue The mask value of memory.
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@param[in] TestValue The test value of memory.
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@retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
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@retval EFI_SUCCESS The MMIO register has expected value.
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@retval Others The MMIO operation fails.
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**/
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EFI_STATUS
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EFIAPI
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XenonHcCheckMmioSet (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT8 BarIndex,
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IN UINT32 Offset,
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IN UINT8 Count,
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IN UINT64 MaskValue,
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IN UINT64 TestValue
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)
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{
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EFI_STATUS Status;
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UINT64 Value;
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//
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// Access PCI MMIO space to see if the value is the tested one.
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//
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Value = 0;
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Status = XenonHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Value);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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Value &= MaskValue;
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if (Value == TestValue) {
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return EFI_SUCCESS;
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}
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return EFI_NOT_READY;
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}
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/**
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Wait for the value of the specified MMIO register set to the test value.
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@param[in] PciIo The PCI IO protocol instance.
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@param[in] BarIndex The BAR index of the standard PCI Configuration
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header to use as the base address for the memory
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operation to perform.
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@param[in] Offset The offset within the selected BAR to start the
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memory operation.
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@param[in] Count The width of the mmio register in bytes.
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Must be 1, 2, 4 or 8 bytes.
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@param[in] MaskValue The mask value of memory.
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@param[in] TestValue The test value of memory.
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@param[in] Timeout The time out value for wait memory set, uses 1
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microsecond as a unit.
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@retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
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range.
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@retval EFI_SUCCESS The MMIO register has expected value.
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@retval Others The MMIO operation fails.
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**/
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EFI_STATUS
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EFIAPI
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XenonHcWaitMmioSet (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT8 BarIndex,
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IN UINT32 Offset,
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IN UINT8 Count,
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IN UINT64 MaskValue,
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IN UINT64 TestValue,
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IN UINT64 Timeout
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)
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{
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EFI_STATUS Status;
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BOOLEAN InfiniteWait;
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if (Timeout == 0) {
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InfiniteWait = TRUE;
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} else {
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InfiniteWait = FALSE;
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}
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while (InfiniteWait || (Timeout > 0)) {
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Status = XenonHcCheckMmioSet (
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PciIo,
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BarIndex,
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Offset,
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Count,
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MaskValue,
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TestValue
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);
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if (Status != EFI_NOT_READY) {
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return Status;
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}
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//
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// Stall for 1 microsecond.
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//
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gBS->Stall (1);
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Timeout--;
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}
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return EFI_TIMEOUT;
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}
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