/********************************************************************************
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Copyright (C) 2016 Marvell International Ltd.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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*******************************************************************************/
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#ifndef __PP2_DXE_H__
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#define __PP2_DXE_H__
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#include <Protocol/AdapterInformation.h>
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#include <Protocol/Cpu.h>
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#include <Protocol/DevicePath.h>
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#include <Protocol/DriverBinding.h>
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#include <Protocol/Ip4.h>
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#include <Protocol/Ip6.h>
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#include <Protocol/MvPhy.h>
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#include <Protocol/SimpleNetwork.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/DmaLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/NetLib.h>
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#include <Library/PcdLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/UefiLib.h>
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#include "Mvpp2LibHw.h"
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#define MVPP2_MAX_PORT 3
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#define PP2DXE_SIGNATURE SIGNATURE_32('P', 'P', '2', 'D')
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#define INSTANCE_FROM_AIP(a) CR((a), PP2DXE_CONTEXT, Aip, PP2DXE_SIGNATURE)
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#define INSTANCE_FROM_SNP(a) CR((a), PP2DXE_CONTEXT, Snp, PP2DXE_SIGNATURE)
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/* OS API */
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#define Mvpp2Alloc(v) AllocateZeroPool(v)
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#define Mvpp2Free(p) FreePool(p)
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#define Mvpp2Memset(a, v, s) SetMem((a), (s), (v))
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#define Mvpp2Mdelay(t) gBS->Stall((t) * 1000)
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#define Mvpp2Fls(v) 1
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#define Mvpp2IsBroadcastEtherAddr(da) 1
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#define Mvpp2IsMulticastEtherAddr(da) 1
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#define Mvpp2Prefetch(v) do {} while(0);
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#define Mvpp2Printf(...) do {} while(0);
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#define Mvpp2SwapVariables(a,b) do { typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
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#define Mvpp2SwapBytes16(x) SwapBytes16((x))
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#define Mvpp2Iphdr EFI_IP4_HEADER
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#define Mvpp2Ipv6hdr EFI_IP6_HEADER
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#define MVPP2_ALIGN(x, m) ALIGN_VALUE((x), (m))
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#define MVPP2_ENOMEM -1
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#define MVPP2_EINVAL -2
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#define MVPP2_ERANGE -3
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#define MVPP2_USEC_PER_SEC 1000000L
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#define DmaAddrT UINTN
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#define PhysAddrT UINTN
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#define Upper32Bits(n) ((UINT32)(((n) >> 16) >> 16))
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#define Lower32Bits(n) ((UINT32)(n))
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#define ARCH_DMA_MINALIGN 64
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/* Port speeds */
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#define MV_PORT_SPEED_10 SPEED_10
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#define MV_PORT_SPEED_100 SPEED_100
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#define MV_PORT_SPEED_1000 SPEED_1000
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#define MV_PORT_SPEED_2500 SPEED_2500
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#define MV_PORT_SPEED_10000 SPEED_10000
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/* L2 and L3 protocol macros */
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#define MV_IPPR_TCP 0
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#define MV_IPPR_UDP 1
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#define MV_IPPR_IPIP 2
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#define MV_IPPR_ICMPV6 3
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#define MV_IPPR_IGMP 4
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#define MV_ETH_P_IP 5
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#define MV_ETH_P_IPV6 6
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#define MV_ETH_P_PPP_SES 7
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#define MV_ETH_P_ARP 8
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#define MV_ETH_P_8021Q 9
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#define MV_ETH_P_8021AD 10
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#define MV_ETH_P_EDSA 11
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#define MV_PPP_IP 12
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#define MV_PPP_IPV6 13
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#define MV_ETH_ALEN NET_ETHER_ADDR_LEN
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/* PHY modes */
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#define MV_MODE_SGMII PHY_CONNECTION_SGMII
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#define MV_MODE_RGMII PHY_CONNECTION_RGMII
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#define MV_MODE_XAUI PHY_CONNECTION_XAUI
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#define MV_MODE_RXAUI PHY_CONNECTION_RXAUI
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#define MV_MODE_SFI PHY_CONNECTION_SFI
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#define MV_MODE_QSGMII 100
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#define PP2DXE_MAX_PHY 2
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/* Gop */
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/* Sets the field located at the specified in data */
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#define U32_SET_FIELD(data, mask, val) ((data) = (((data) & ~(mask)) | (val)))
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#define MV_RGMII_TX_FIFO_MIN_TH 0x41
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#define MV_SGMII_TX_FIFO_MIN_TH 0x5
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#define MV_SGMII2_5_TX_FIFO_MIN_TH 0xB
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/* BM constants */
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#define MVPP2_BM_POOLS_NUM 8
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#define MVPP2_BM_LONG_BUF_NUM 1024
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#define MVPP2_BM_SHORT_BUF_NUM 2048
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#define MVPP2_BM_POOL_SIZE_MAX (SIZE_16KB - MVPP2_BM_POOL_PTR_ALIGN/4)
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#define MVPP2_BM_POOL_PTR_ALIGN 128
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#define MVPP2_BM_SWF_LONG_POOL(Port) ((Port > 2) ? 2 : Port)
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#define MVPP2_BM_SWF_SHORT_POOL 3
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#define MVPP2_BM_POOL 0
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#define MVPP2_BM_SIZE 64
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/*
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* BM short pool packet Size
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* These value assure that for SWF the total number
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* of bytes allocated for each buffer will be 512
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*/
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#define MVPP2_BM_SHORT_PKT_SIZE 512
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/*
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* Page table entries are set to 1MB, or multiples of 1MB
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* (not < 1MB). driver uses less bd's so use 1MB bdspace.
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*/
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#define BD_SPACE (1 << 20)
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/* Buffer has to be aligned to 1M */
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#define MVPP2_BUFFER_ALIGN_SIZE (1 << 20)
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/* RX constants */
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#define RX_BUFFER_SIZE (ALIGN_VALUE(MTU + WRAP, ARCH_DMA_MINALIGN))
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#define MVPP2_RXQ_OFFSET 0
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#define BUFF_HDR_OFFS 32
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#define BM_ALIGN 32
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#define ETH_HLEN 14
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/* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
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#define WRAP (2 + ETH_HLEN + 4 + 32)
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#define MTU 1500
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/*
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* Maximum retries of checking, wheter HW really sent the packet
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* after it was done is software.
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*/
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#define MVPP2_TX_SEND_MAX_POLLING_COUNT 10000
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/* Structures */
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typedef struct {
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/* Physical number of this Tx queue */
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UINT8 Id;
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/* Logical number of this Tx queue */
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UINT8 LogId;
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/* Number of Tx DMA descriptors in the descriptor ring */
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INT32 Size;
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/* Number of currently used Tx DMA descriptor in the descriptor ring */
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INT32 count;
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UINT32 DonePktsCoal;
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/* Virtual address of thex Tx DMA descriptors array */
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MVPP2_TX_DESC *Descs;
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/* DMA address of the Tx DMA descriptors array */
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DmaAddrT DescsPhys;
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/* Index of the last Tx DMA descriptor */
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INT32 LastDesc;
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/* Index of the next Tx DMA descriptor to process */
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INT32 NextDescToProc;
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} MVPP2_TX_QUEUE;
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typedef struct {
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/* RX queue number, in the range 0-31 for physical RXQs */
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UINT8 Id;
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/* Num of rx descriptors in the rx descriptor ring */
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INT32 Size;
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UINT32 PktsCoal;
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UINT32 TimeCoal;
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/* Virtual address of the RX DMA descriptors array */
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MVPP2_RX_DESC *Descs;
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/* DMA address of the RX DMA descriptors array */
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DmaAddrT DescsPhys;
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/* Index of the last RX DMA descriptor */
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INT32 LastDesc;
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/* Index of the next RX DMA descriptor to process */
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INT32 NextDescToProc;
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/* ID of Port to which physical RXQ is mapped */
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INT32 Port;
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/* Port's logic RXQ number to which physical RXQ is mapped */
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INT32 LogicRxq;
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} MVPP2_RX_QUEUE;
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enum Mvpp2BmType {
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MVPP2_BM_FREE,
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MVPP2_BM_SWF_LONG,
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MVPP2_BM_SWF_SHORT
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};
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typedef struct {
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/* Pool number in the range 0-7 */
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INT32 Id;
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enum Mvpp2BmType type;
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/* Buffer Pointers Pool External (BPPE) Size */
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INT32 Size;
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/* Number of buffers for this pool */
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INT32 BufNum;
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/* Pool buffer Size */
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INT32 BufSize;
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/* Packet Size */
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INT32 PktSize;
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/* BPPE virtual base address */
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UINT32 *VirtAddr;
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/* BPPE physical base address */
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DmaAddrT PhysAddr;
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/* Ports using BM pool */
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UINT32 PortMap;
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} MVPP2_BMS_POOL;
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typedef struct Pp2DxePort PP2DXE_PORT;
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/* Structure for preallocation for buffer */
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typedef struct {
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MVPP2_TX_DESC *TxDescs[MVPP2_MAX_PORT];
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MVPP2_TX_DESC *AggrTxDescs;
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MVPP2_RX_DESC *RxDescs[MVPP2_MAX_PORT];
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DmaAddrT RxBuffers[MVPP2_MAX_PORT];
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} BUFFER_LOCATION;
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/* Shared Packet Processor resources */
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typedef struct {
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/* Shared registers' base addresses */
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UINT64 Base;
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UINT64 MpcsBase;
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UINT64 Rfu1Base;
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UINT64 SmiBase;
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UINT64 XpcsBase;
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/* Preallocated buffers */
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BUFFER_LOCATION BufferLocation;
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/* List of pointers to Port structures */
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PP2DXE_PORT **PortList;
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/* Aggregated TXQs */
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MVPP2_TX_QUEUE *AggrTxqs;
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/* BM pools */
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MVPP2_BMS_POOL *BmPools[MVPP2_MAX_PORT];
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BOOLEAN BmEnabled;
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/* PRS shadow table */
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MVPP2_PRS_SHADOW *PrsShadow;
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/* PRS auxiliary table for double vlan entries control */
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BOOLEAN *PrsDoubleVlans;
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/* Tclk value */
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UINT32 Tclk;
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} MVPP2_SHARED;
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/* Individual Port structure */
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struct Pp2DxePort {
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UINT8 Id;
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UINT8 GopIndex;
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INT32 Irq;
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MVPP2_SHARED *Priv;
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/* Per-Port registers' base address */
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UINT64 GmacBase;
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UINT64 XlgBase;
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MVPP2_RX_QUEUE *Rxqs;
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MVPP2_TX_QUEUE *Txqs;
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INT32 PktSize;
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UINT32 PendingCauseRx;
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/* Flags */
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UINTN Flags;
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UINT16 TxRingSize;
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UINT16 RxRingSize;
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INT32 PhyInterface;
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UINT32 PhyIndex;
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BOOLEAN Link;
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BOOLEAN Duplex;
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BOOLEAN AlwaysUp;
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PHY_SPEED Speed;
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MVPP2_BMS_POOL *PoolLong;
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MVPP2_BMS_POOL *PoolShort;
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UINT8 TxpNum;
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/* Index of first Port's physical RXQ */
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UINT8 FirstRxq;
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};
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typedef struct {
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MAC_ADDR_DEVICE_PATH Pp2Mac;
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EFI_DEVICE_PATH_PROTOCOL End;
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} PP2_DEVICE_PATH;
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#define QUEUE_DEPTH 64
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typedef struct {
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UINT32 Signature;
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INTN Instance;
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EFI_HANDLE Controller;
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EFI_LOCK Lock;
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EFI_SIMPLE_NETWORK_PROTOCOL Snp;
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MARVELL_PHY_PROTOCOL *Phy;
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PHY_DEVICE *PhyDev;
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PP2DXE_PORT Port;
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BOOLEAN Initialized;
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BOOLEAN LateInitialized;
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VOID *CompletionQueue[QUEUE_DEPTH];
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UINTN CompletionQueueHead;
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UINTN CompletionQueueTail;
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EFI_EVENT EfiExitBootServicesEvent;
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PP2_DEVICE_PATH *DevicePath;
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EFI_ADAPTER_INFORMATION_PROTOCOL Aip;
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} PP2DXE_CONTEXT;
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/* Inline helpers */
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STATIC
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inline
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VOID
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Mvpp2Write (
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IN MVPP2_SHARED *Priv,
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IN UINT32 Offset,
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IN UINT32 data
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)
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{
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ASSERT (Priv->Base != 0);
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MmioWrite32 (Priv->Base + Offset, data);
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}
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STATIC
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inline
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UINT32
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Mvpp2Read (
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IN MVPP2_SHARED *Priv,
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IN UINT32 Offset
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)
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{
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ASSERT (Priv->Base != 0);
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return MmioRead32 (Priv->Base + Offset);
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}
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STATIC
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inline
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UINT32
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Mvpp2Rfu1Read (
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IN MVPP2_SHARED *Priv,
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UINT32 Offset
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)
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{
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ASSERT (Priv->Rfu1Base != 0);
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return MmioRead32 (Priv->Rfu1Base + Offset);
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}
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STATIC
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inline
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UINT32
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Mvpp2Rfu1Write (
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IN MVPP2_SHARED *Priv,
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IN UINT32 Offset,
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IN UINT32 Data
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)
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{
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ASSERT (Priv->Rfu1Base != 0);
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return MmioWrite32 (Priv->Rfu1Base + Offset, Data);
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}
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STATIC
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inline
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UINT32
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Mvpp2SmiRead (
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IN MVPP2_SHARED *Priv,
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IN UINT32 Offset
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)
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{
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ASSERT (Priv->SmiBase != 0);
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return MmioRead32 (Priv->SmiBase + Offset);
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}
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STATIC
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inline
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UINT32
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Mvpp2SmiWrite (
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IN MVPP2_SHARED *Priv,
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IN UINT32 Offset,
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IN UINT32 Data
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)
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{
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ASSERT (Priv->SmiBase != 0);
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return MmioWrite32 (Priv->SmiBase + Offset, Data);
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}
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STATIC
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inline
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VOID
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Mvpp2GmacWrite (
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IN PP2DXE_PORT *Port,
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IN UINT32 Offset,
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IN UINT32 Data
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)
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{
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ASSERT (Port->Priv->Base != 0);
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MmioWrite32 (Port->Priv->Base + Offset, Data);
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}
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STATIC
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inline
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UINT32
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Mvpp2GmacRead (
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IN PP2DXE_PORT *Port,
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IN UINT32 Offset
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)
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{
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ASSERT (Port->Priv->Base != 0);
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return MmioRead32 (Port->Priv->Base + Offset);
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}
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STATIC
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inline
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VOID
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MvGop110GmacWrite (
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IN PP2DXE_PORT *Port,
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IN UINT32 Offset,
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IN UINT32 Data
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)
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{
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ASSERT (Port->GmacBase != 0);
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MmioWrite32 (Port->GmacBase + Offset, Data);
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}
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STATIC
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inline
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UINT32
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MvGop110GmacRead (
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IN PP2DXE_PORT *Port,
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IN UINT32 Offset
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)
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{
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ASSERT (Port->GmacBase != 0);
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return MmioRead32 (Port->GmacBase + Offset);
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}
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STATIC
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inline
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VOID
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Mvpp2XlgWrite (
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IN PP2DXE_PORT *Port,
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IN UINT32 Offset,
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IN UINT32 Data
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)
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{
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ASSERT (Port->XlgBase != 0);
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MmioWrite32 (Port->XlgBase + Offset, Data);
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}
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STATIC
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inline
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UINT32
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Mvpp2XlgRead (
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IN PP2DXE_PORT *Port,
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IN UINT32 Offset
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)
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{
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ASSERT (Port->XlgBase != 0);
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return MmioRead32 (Port->XlgBase + Offset);
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}
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/* SNP callbacks */
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EFI_STATUS
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EFIAPI
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Pp2SnpStart (
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IN EFI_SIMPLE_NETWORK_PROTOCOL *This
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);
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EFI_STATUS
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EFIAPI
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Pp2SnpStop (
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IN EFI_SIMPLE_NETWORK_PROTOCOL *This
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);
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EFI_STATUS
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EFIAPI
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Pp2DxeSnpInitialize (
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IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
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IN UINTN ExtraRxBufferSize OPTIONAL,
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IN UINTN ExtraTxBufferSize OPTIONAL
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);
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EFI_STATUS
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EFIAPI
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Pp2SnpReset (
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IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
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IN BOOLEAN ExtendedVerification
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);
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EFI_STATUS
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EFIAPI
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Pp2SnpShutdown (
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IN EFI_SIMPLE_NETWORK_PROTOCOL *This
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);
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EFI_STATUS
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EFIAPI
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Pp2SnpReceiveFilters (
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IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
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IN UINT32 Enable,
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IN UINT32 Disable,
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IN BOOLEAN ResetMCastFilter,
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IN UINTN MCastFilterCnt OPTIONAL,
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IN EFI_MAC_ADDRESS *MCastFilter OPTIONAL
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);
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EFI_STATUS
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EFIAPI
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Pp2SnpStationAddress (
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IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
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IN BOOLEAN Reset,
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IN EFI_MAC_ADDRESS *NewMac
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);
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EFI_STATUS
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EFIAPI
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Pp2SnpNetStat (
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IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
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IN BOOLEAN Reset,
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IN OUT UINTN *StatisticsSize OPTIONAL,
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OUT EFI_NETWORK_STATISTICS *StatisticsTable OPTIONAL
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);
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EFI_STATUS
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EFIAPI
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Pp2SnpIpToMac (
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IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
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IN BOOLEAN IPv6,
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IN EFI_IP_ADDRESS *IP,
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OUT EFI_MAC_ADDRESS *MAC
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);
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EFI_STATUS
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EFIAPI
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Pp2SnpGetStatus (
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IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
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OUT UINT32 *InterruptStatus OPTIONAL,
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OUT VOID **TxBuf OPTIONAL
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);
|
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EFI_STATUS
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EFIAPI
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Pp2SnpTransmit (
|
IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
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IN UINTN HeaderSize,
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IN UINTN BufferSize,
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IN VOID *Buffer,
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IN EFI_MAC_ADDRESS *SrcAddr OPTIONAL,
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IN EFI_MAC_ADDRESS *DestAddr OPTIONAL,
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IN UINT16 *EtherTypePtr OPTIONAL
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);
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EFI_STATUS
|
EFIAPI
|
Pp2SnpReceive (
|
IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
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OUT UINTN *HeaderSize OPTIONAL,
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IN OUT UINTN *BufferSize,
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OUT VOID *Buffer,
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OUT EFI_MAC_ADDRESS *SrcAddr OPTIONAL,
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OUT EFI_MAC_ADDRESS *DstAddr OPTIONAL,
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OUT UINT16 *EtherType OPTIONAL
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);
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#endif
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