/********************************************************************************
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Copyright (C) 2016 Marvell International Ltd.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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*******************************************************************************/
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#ifndef __MVPP2_LIB_H__
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#define __MVPP2_LIB_H__
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#include "Mvpp2LibHw.h"
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#include "Pp2Dxe.h"
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/* number of RXQs used by single Port */
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STATIC INT32 RxqNumber = 1;
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/* number of TXQs used by single Port */
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STATIC INT32 TxqNumber = 1;
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VOID
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Mvpp2PrsMacPromiscSet (
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IN MVPP2_SHARED *Priv,
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IN INT32 PortId,
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IN BOOLEAN Add
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);
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VOID
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Mvpp2PrsMacMultiSet (
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IN MVPP2_SHARED *Priv,
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IN INT32 PortId,
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IN INT32 Index,
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IN BOOLEAN Add
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);
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INT32
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Mvpp2PrsDefaultInit (
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IN MVPP2_SHARED *Priv
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);
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INT32
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Mvpp2PrsMacDaAccept (
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IN MVPP2_SHARED *Priv,
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IN INT32 PortId,
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IN const UINT8 *Da,
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IN BOOLEAN Add
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);
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VOID
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Mvpp2PrsMcastDelAll (
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IN MVPP2_SHARED *Priv,
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IN INT32 PortId
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);
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INT32
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Mvpp2PrsTagModeSet (
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IN MVPP2_SHARED *Priv,
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IN INT32 PortId,
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IN INT32 type
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);
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INT32
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Mvpp2PrsDefFlow (
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IN PP2DXE_PORT *Port
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);
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VOID
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Mvpp2ClsInit (
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IN MVPP2_SHARED *Priv
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);
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VOID
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Mvpp2ClsPortConfig (
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IN PP2DXE_PORT *Port
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);
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VOID
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Mvpp2ClsOversizeRxqSet (
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IN PP2DXE_PORT *Port
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);
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VOID
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Mvpp2BmPoolHwCreate (
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IN MVPP2_SHARED *Priv,
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IN MVPP2_BMS_POOL *BmPool,
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IN INT32 Size
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);
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VOID
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Mvpp2BmPoolBufsizeSet (
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IN MVPP2_SHARED *Priv,
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IN MVPP2_BMS_POOL *BmPool,
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IN INT32 BufSize
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);
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VOID
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Mvpp2BmStop (
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IN MVPP2_SHARED *Priv,
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IN INT32 Pool
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);
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VOID
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Mvpp2BmIrqClear (
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IN MVPP2_SHARED *Priv,
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IN INT32 Pool
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);
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VOID
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Mvpp2RxqLongPoolSet (
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IN PP2DXE_PORT *Port,
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IN INT32 Lrxq,
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IN INT32 LongPool
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);
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VOID
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Mvpp2RxqShortPoolSet (
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IN PP2DXE_PORT *Port,
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IN INT32 Lrxq,
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IN INT32 ShortPool
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);
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VOID
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Mvpp2BmPoolMcPut (
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IN PP2DXE_PORT *Port,
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IN INT32 Pool,
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IN UINT32 BufPhysAddr,
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IN UINT32 BufVirtAddr,
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IN INT32 McId
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);
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VOID
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Mvpp2PoolRefill (
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IN PP2DXE_PORT *Port,
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IN UINT32 Bm,
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IN UINT32 PhysAddr,
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IN UINT32 Cookie
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);
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INTN
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Mvpp2BmPoolCtrl (
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IN MVPP2_SHARED *Priv,
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IN INTN Pool,
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IN enum Mvpp2Command cmd
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);
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VOID
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Mvpp2InterruptsMask (
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IN VOID *arg
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);
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VOID
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Mvpp2InterruptsUnmask (
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IN VOID *arg
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);
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VOID
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Mvpp2PortEnable (
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IN PP2DXE_PORT *Port
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);
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VOID
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Mvpp2PortDisable (
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IN PP2DXE_PORT *Port
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);
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VOID
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Mvpp2DefaultsSet (
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IN PP2DXE_PORT *Port
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);
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VOID
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Mvpp2IngressEnable (
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IN PP2DXE_PORT *Port
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);
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VOID
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Mvpp2IngressDisable (
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IN PP2DXE_PORT *Port
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);
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VOID
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Mvpp2EgressEnable (
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IN PP2DXE_PORT *Port
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);
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VOID
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Mvpp2EgressDisable (
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IN PP2DXE_PORT *Port
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);
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UINT32
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Mvpp2BmCookieBuild (
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IN MVPP2_RX_DESC *RxDesc,
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IN INT32 Cpu
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);
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INT32
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Mvpp2TxqDrainSet (
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IN PP2DXE_PORT *Port,
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IN INT32 Txq,
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IN BOOLEAN En
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);
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INT32
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Mvpp2TxqPendDescNumGet (
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IN PP2DXE_PORT *Port,
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IN MVPP2_TX_QUEUE *Txq
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);
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UINT32
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Mvpp2AggrTxqPendDescNumGet (
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IN MVPP2_SHARED *Priv,
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IN INT32 Cpu
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);
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MVPP2_TX_DESC *
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Mvpp2TxqNextDescGet (
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MVPP2_TX_QUEUE *Txq
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);
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VOID
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Mvpp2AggrTxqPendDescAdd (
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IN PP2DXE_PORT *Port,
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IN INT32 Pending
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);
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INT32
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Mvpp2AggrDescNumCheck (
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IN MVPP2_SHARED *Priv,
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IN MVPP2_TX_QUEUE *AggrTxq,
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IN INT32 Num,
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IN INT32 Cpu
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);
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INT32
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Mvpp2TxqAllocReservedDesc (
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IN MVPP2_SHARED *Priv,
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IN MVPP2_TX_QUEUE *Txq,
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IN INT32 Num
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);
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VOID
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Mvpp2TxqDescPut (
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IN MVPP2_TX_QUEUE *Txq
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);
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UINT32
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Mvpp2TxqDescCsum (
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IN INT32 L3Offs,
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IN INT32 L3Proto,
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IN INT32 IpHdrLen,
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IN INT32 L4Proto
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);
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VOID
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Mvpp2TxqSentCounterClear (
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IN OUT VOID *arg
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);
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VOID
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Mvpp2GmacMaxRxSizeSet (
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IN PP2DXE_PORT *Port
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);
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VOID
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Mvpp2TxpMaxTxSizeSet (
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IN PP2DXE_PORT *Port
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);
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VOID
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Mvpp2RxPktsCoalSet (
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IN PP2DXE_PORT *Port,
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IN OUT MVPP2_RX_QUEUE *Rxq,
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IN UINT32 Pkts
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);
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VOID
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Mvpp2RxTimeCoalSet (
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IN PP2DXE_PORT *Port,
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IN OUT MVPP2_RX_QUEUE *Rxq,
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IN UINT32 Usec
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);
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VOID
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Mvpp2AggrTxqHwInit (
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IN OUT MVPP2_TX_QUEUE *AggrTxq,
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IN INT32 DescNum,
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IN INT32 Cpu,
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IN MVPP2_SHARED *Priv
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);
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VOID
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Mvpp2RxqHwInit (
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IN PP2DXE_PORT *Port,
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IN OUT MVPP2_RX_QUEUE *Rxq
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);
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VOID
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Mvpp2RxqDropPkts (
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IN PP2DXE_PORT *Port,
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IN OUT MVPP2_RX_QUEUE *Rxq,
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IN INT32 Cpu
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);
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VOID
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Mvpp2TxqHwInit (
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IN PP2DXE_PORT *Port,
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IN OUT MVPP2_TX_QUEUE *Txq
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);
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VOID
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Mvpp2TxqHwDeinit (
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IN PP2DXE_PORT *Port,
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IN OUT MVPP2_TX_QUEUE *Txq
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);
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VOID
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Mvpp2PortPowerUp (
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IN PP2DXE_PORT *Port
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);
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VOID
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Mvpp2RxFifoInit (
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IN MVPP2_SHARED *Priv
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);
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VOID
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Mvpp2RxqHwDeinit (
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IN PP2DXE_PORT *Port,
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IN OUT MVPP2_RX_QUEUE *Rxq
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);
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INT32
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MvGop110NetcInit (
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IN PP2DXE_PORT *Port,
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IN UINT32 NetCompConfig,
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IN enum MvNetcPhase phase
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);
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UINT32
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MvpPp2xGop110NetcCfgCreate (
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IN PP2DXE_PORT *Port
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);
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INT32
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MvGop110PortInit (
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IN PP2DXE_PORT *Port
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);
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INT32
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MvGop110GmacReset (
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IN PP2DXE_PORT *Port,
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IN enum MvReset ResetCmd
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);
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INT32
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MvGop110GpcsModeCfg (
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IN PP2DXE_PORT *Port,
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BOOLEAN En
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);
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INT32
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MvGop110BypassClkCfg (
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IN PP2DXE_PORT *Port,
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IN BOOLEAN En
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);
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INT32
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MvGop110GpcsReset (
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IN PP2DXE_PORT *Port,
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IN enum MvReset ResetCmd
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);
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VOID
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MvGop110Xlg2GigMacCfg (
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IN PP2DXE_PORT *Port
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);
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INT32
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MvGop110GmacModeCfg (
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IN PP2DXE_PORT *Port
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);
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VOID
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MvGop110GmacRgmiiCfg (
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IN PP2DXE_PORT *Port
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);
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VOID
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MvGop110GmacSgmii25Cfg (
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IN PP2DXE_PORT *Port
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);
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VOID
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MvGop110GmacSgmiiCfg (
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IN PP2DXE_PORT *Port
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);
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VOID
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MvGop110GmacQsgmiiCfg (
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IN PP2DXE_PORT *Port
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);
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INT32
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Mvpp2SmiPhyAddrCfg (
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IN PP2DXE_PORT *Port,
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IN INT32 PortId,
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IN INT32 Addr
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);
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EFI_STATUS
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MvGopXpcsModeCfg (
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IN PP2DXE_PORT *Port,
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IN INT32 NumOfLanes
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);
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VOID
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MvGopMpcsModeCfg (
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IN PP2DXE_PORT *Port
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);
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VOID
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MvGopXlgMacModeCfg (
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IN PP2DXE_PORT *Port
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);
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VOID
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MvGopXpcsUnreset (
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IN PP2DXE_PORT *Port
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);
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VOID
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MvGopXlgMacUnreset (
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IN PP2DXE_PORT *Port
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);
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BOOLEAN
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MvGop110PortIsLinkUp (
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IN PP2DXE_PORT *Port
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);
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BOOLEAN
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MvGop110GmacLinkStatusGet (
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IN PP2DXE_PORT *Port
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);
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VOID
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MvGop110PortDisable (
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IN PP2DXE_PORT *Port
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);
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VOID
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MvGop110PortEnable (
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IN PP2DXE_PORT *Port
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);
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VOID
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MvGop110GmacPortEnable (
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IN PP2DXE_PORT *Port
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);
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VOID
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MvGop110GmacPortDisable (
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IN PP2DXE_PORT *Port
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);
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VOID
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MvGop110GmacPortLinkEventMask (
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IN PP2DXE_PORT *Port
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);
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INT32
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MvGop110PortEventsMask (
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IN PP2DXE_PORT *Port
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);
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VOID
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MvGop110XlgPortLinkEventMask (
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IN PP2DXE_PORT *Port
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);
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VOID
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MvGop110GmacForceLinkUp (
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IN PP2DXE_PORT *Port
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);
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INT32
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MvGop110FlCfg (
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IN PP2DXE_PORT *Port
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);
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INT32
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MvGop110SpeedDuplexSet (
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IN PP2DXE_PORT *Port,
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IN INT32 Speed,
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IN enum MvPortDuplex Duplex
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);
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INT32
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MvGop110GmacSpeedDuplexSet (
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IN PP2DXE_PORT *Port,
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IN INT32 Speed,
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IN enum MvPortDuplex Duplex
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);
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VOID
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Mvpp2AxiConfig (
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IN MVPP2_SHARED *Priv
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);
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VOID
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Mvpp2TxpClean (
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IN PP2DXE_PORT *Port,
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IN INT32 Txp,
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IN MVPP2_TX_QUEUE *Txq
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);
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VOID
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Mvpp2CleanupTxqs (
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IN PP2DXE_PORT *Port
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);
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VOID
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Mvpp2CleanupRxqs (
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IN PP2DXE_PORT *Port
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);
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/* Get number of physical egress Port */
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STATIC
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inline
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INT32
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Mvpp2EgressPort (
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IN PP2DXE_PORT *Port
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)
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{
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return MVPP2_MAX_TCONT + Port->Id;
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}
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/* Get number of physical TXQ */
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STATIC
|
inline
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INT32
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Mvpp2TxqPhys (
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IN INT32 PortId,
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IN INT32 Txq
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)
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{
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return (MVPP2_MAX_TCONT + PortId) * MVPP2_MAX_TXQ + Txq;
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}
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/* Set Pool number in a BM Cookie */
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STATIC
|
inline
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UINT32
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Mvpp2BmCookiePoolSet (
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IN UINT32 Cookie,
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IN INT32 Pool
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)
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{
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UINT32 Bm;
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Bm = Cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
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Bm |= ((Pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
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return Bm;
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}
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/* Get Pool number from a BM Cookie */
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STATIC
|
inline
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INT32
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Mvpp2BmCookiePoolGet (
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IN UINT32 Cookie
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)
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{
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return (Cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
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}
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/* Release buffer to BM */
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STATIC
|
inline
|
VOID
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Mvpp2BmPoolPut (
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IN MVPP2_SHARED *Priv,
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IN INT32 Pool,
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IN UINT64 BufPhysAddr,
|
IN UINT64 BufVirtAddr
|
)
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{
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UINT32 Val = 0;
|
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Val = (Upper32Bits(BufVirtAddr) & MVPP22_ADDR_HIGH_MASK) << MVPP22_BM_VIRT_HIGH_RLS_OFFST;
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Val |= (Upper32Bits(BufPhysAddr) & MVPP22_ADDR_HIGH_MASK) << MVPP22_BM_PHY_HIGH_RLS_OFFSET;
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Mvpp2Write(Priv, MVPP22_BM_PHY_VIRT_HIGH_RLS_REG, Val);
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Mvpp2Write(Priv, MVPP2_BM_VIRT_RLS_REG, (UINT32)BufVirtAddr);
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Mvpp2Write(Priv, MVPP2_BM_PHY_RLS_REG(Pool), (UINT32)BufPhysAddr);
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}
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STATIC
|
inline
|
VOID
|
Mvpp2InterruptsEnable (
|
IN PP2DXE_PORT *Port,
|
IN INT32 CpuMask
|
)
|
{
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Mvpp2Write(Port->Priv, MVPP2_ISR_ENABLE_REG(Port->Id), MVPP2_ISR_ENABLE_INTERRUPT(CpuMask));
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}
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STATIC
|
inline
|
VOID
|
Mvpp2InterruptsDisable (
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IN PP2DXE_PORT *Port,
|
IN INT32 CpuMask
|
)
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{
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Mvpp2Write(Port->Priv, MVPP2_ISR_ENABLE_REG(Port->Id), MVPP2_ISR_DISABLE_INTERRUPT(CpuMask));
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}
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/* Get number of Rx descriptors occupied by received packets */
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STATIC
|
inline
|
INT32
|
Mvpp2RxqReceived (
|
IN PP2DXE_PORT *Port,
|
IN INT32 RxqId
|
)
|
{
|
UINT32 Val = Mvpp2Read(Port->Priv, MVPP2_RXQ_STATUS_REG(RxqId));
|
|
return Val & MVPP2_RXQ_OCCUPIED_MASK;
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}
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/*
|
* Update Rx Queue status with the number of occupied and available
|
* Rx descriptor slots.
|
*/
|
STATIC
|
inline
|
VOID
|
Mvpp2RxqStatusUpdate (
|
IN PP2DXE_PORT *Port,
|
IN INT32 RxqId,
|
IN INT32 UsedCount,
|
IN INT32 FreeCount
|
)
|
{
|
/*
|
* Decrement the number of used descriptors and increment count
|
* increment the number of free descriptors.
|
*/
|
UINT32 Val = UsedCount | (FreeCount << MVPP2_RXQ_NUM_NEW_OFFSET);
|
|
Mvpp2Write(Port->Priv, MVPP2_RXQ_STATUS_UPDATE_REG(RxqId), Val);
|
}
|
|
/* Get pointer to next RX descriptor to be processed by SW */
|
STATIC
|
inline
|
MVPP2_RX_DESC *
|
Mvpp2RxqNextDescGet (
|
IN MVPP2_RX_QUEUE *Rxq
|
)
|
{
|
INT32 RxDesc = Rxq->NextDescToProc;
|
|
Rxq->NextDescToProc = MVPP2_QUEUE_NEXT_DESC(Rxq, RxDesc);
|
Mvpp2Prefetch(Rxq->Descs + Rxq->NextDescToProc);
|
return Rxq->Descs + RxDesc;
|
}
|
|
/*
|
* Get number of sent descriptors and decrement counter.
|
* The number of sent descriptors is returned.
|
* Per-CPU access
|
*/
|
STATIC
|
inline
|
INT32
|
Mvpp2TxqSentDescProc (
|
IN PP2DXE_PORT *Port,
|
IN MVPP2_TX_QUEUE *Txq
|
)
|
{
|
UINT32 Val;
|
|
/* Reading status reg resets transmitted descriptor counter */
|
#ifdef MVPP2V1
|
Val = Mvpp2Read(Port->Priv, MVPP2_TXQ_SENT_REG(Txq->Id));
|
#else
|
Val = Mvpp2Read(Port->Priv, MVPP22_TXQ_SENT_REG(Txq->Id));
|
#endif
|
|
return (Val & MVPP2_TRANSMITTED_COUNT_MASK) >> MVPP2_TRANSMITTED_COUNT_OFFSET;
|
}
|
|
STATIC
|
inline
|
MVPP2_RX_QUEUE *
|
Mvpp2GetRxQueue (
|
IN PP2DXE_PORT *Port,
|
IN UINT32 Cause
|
)
|
{
|
INT32 Queue = Mvpp2Fls(Cause) - 1;
|
|
return &Port->Rxqs[Queue];
|
}
|
|
STATIC
|
inline
|
MVPP2_TX_QUEUE *
|
Mvpp2GetTxQueue (
|
IN PP2DXE_PORT *Port,
|
IN UINT32 Cause
|
)
|
{
|
INT32 Queue = Mvpp2Fls(Cause) - 1;
|
|
return &Port->Txqs[Queue];
|
}
|
|
STATIC
|
inline
|
void
|
Mvpp2x2TxdescPhysAddrSet (
|
IN DmaAddrT PhysAddr,
|
IN MVPP2_TX_DESC *TxDesc
|
)
|
{
|
UINT64 *BufPhysAddrP = &TxDesc->BufPhysAddrHwCmd2;
|
|
*BufPhysAddrP &= ~(MVPP22_ADDR_MASK);
|
*BufPhysAddrP |= PhysAddr & MVPP22_ADDR_MASK;
|
}
|
#endif /* __MVPP2_LIB_H__ */
|
