/********************************************************************************
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Copyright (C) 2016 Marvell International Ltd.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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*******************************************************************************/
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#include <Protocol/DriverBinding.h>
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#include <Protocol/Mdio.h>
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#include <Protocol/MvPhy.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/UefiLib.h>
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#include "MvPhyDxe.h"
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#define TIMEOUT 500
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STATIC MARVELL_MDIO_PROTOCOL *Mdio;
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//
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// Table with available Mdio controllers
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//
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STATIC UINT8 * CONST MdioDeviceTable = PcdGetPtr (PcdMdioControllersEnabled);
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//
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// Table with PHY to Mdio controller mappings
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//
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STATIC UINT8 * CONST Phy2MdioController = PcdGetPtr (PcdPhy2MdioController);
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//
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// Table with PHYs' SMI addresses
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//
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STATIC UINT8 * CONST PhySmiAddresses = PcdGetPtr (PcdPhySmiAddresses);
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STATIC MV_PHY_DEVICE MvPhyDevices[] = {
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{ MV_PHY_DEVICE_1512, MvPhyInit1512 },
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{ MV_PHY_DEVICE_1112, MvPhyInit1112 },
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{ 0, NULL }
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};
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EFI_STATUS
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MvPhyStatus (
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IN CONST MARVELL_PHY_PROTOCOL *This,
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IN PHY_DEVICE *PhyDev
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);
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EFI_STATUS
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MvPhyReset (
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IN PHY_DEVICE *PhyDev
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)
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{
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UINT32 Reg = 0;
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INTN timeout = TIMEOUT;
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Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMCR, &Reg);
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Reg |= BMCR_RESET;
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Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMCR, Reg);
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while ((Reg & BMCR_RESET) && timeout--) {
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Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMCR, &Reg);
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gBS->Stall(1000);
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}
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if (Reg & BMCR_RESET) {
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DEBUG((DEBUG_ERROR, "PHY reset timed out\n"));
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return EFI_TIMEOUT;
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}
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return EFI_SUCCESS;
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}
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/* Marvell 88E1111S */
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EFI_STATUS
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MvPhyM88e1111sConfig (
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IN PHY_DEVICE *PhyDev
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)
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{
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UINT32 Reg;
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if ((PhyDev->Connection == PHY_CONNECTION_RGMII) ||
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(PhyDev->Connection == PHY_CONNECTION_RGMII_ID) ||
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(PhyDev->Connection == PHY_CONNECTION_RGMII_RXID) ||
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(PhyDev->Connection == PHY_CONNECTION_RGMII_TXID)) {
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Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_CR, &Reg);
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if ((PhyDev->Connection == PHY_CONNECTION_RGMII) ||
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(PhyDev->Connection == PHY_CONNECTION_RGMII_ID)) {
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Reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
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} else if (PhyDev->Connection == PHY_CONNECTION_RGMII_RXID) {
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Reg &= ~MIIM_88E1111_TX_DELAY;
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Reg |= MIIM_88E1111_RX_DELAY;
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} else if (PhyDev->Connection == PHY_CONNECTION_RGMII_TXID) {
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Reg &= ~MIIM_88E1111_RX_DELAY;
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Reg |= MIIM_88E1111_TX_DELAY;
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}
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Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_CR, Reg);
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Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_SR, &Reg);
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Reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
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if (Reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES)
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Reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII;
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else
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Reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII;
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Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_SR, Reg);
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}
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if (PhyDev->Connection == PHY_CONNECTION_SGMII) {
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Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_SR, &Reg);
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Reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
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Reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
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Reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
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Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_SR, Reg);
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}
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if (PhyDev->Connection == PHY_CONNECTION_RTBI) {
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Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_CR, &Reg);
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Reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
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Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_CR, Reg);
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Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_SR, &Reg);
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Reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
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MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
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Reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
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Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_SR, Reg);
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/* Soft reset */
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MvPhyReset (PhyDev);
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Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_SR, &Reg);
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Reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
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MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
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Reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI |
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MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
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Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_SR, Reg);
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}
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Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMCR, &Reg);
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Reg |= (BMCR_ANENABLE | BMCR_ANRESTART);
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Reg &= ~BMCR_ISOLATE;
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Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMCR, Reg);
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/* Soft reset */
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MvPhyReset (PhyDev);
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return EFI_SUCCESS;
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}
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EFI_STATUS
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MvPhyParseStatus (
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IN PHY_DEVICE *PhyDev
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)
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{
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UINT32 Data;
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UINT32 Speed;
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Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1xxx_PHY_STATUS, &Data);
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if ((Data & MIIM_88E1xxx_PHYSTAT_LINK) &&
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!(Data & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
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INTN i = 0;
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DEBUG((DEBUG_ERROR,"MvPhyDxe: Waiting for PHY realtime link"));
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while (!(Data & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
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if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
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DEBUG((DEBUG_ERROR," TIMEOUT !\n"));
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PhyDev->LinkUp = FALSE;
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break;
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}
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if ((i++ % 1000) == 0)
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DEBUG((DEBUG_ERROR, "."));
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gBS->Stall(1000);
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Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1xxx_PHY_STATUS, &Data);
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}
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DEBUG((DEBUG_ERROR," done\n"));
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gBS->Stall(500000);
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} else {
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if (Data & MIIM_88E1xxx_PHYSTAT_LINK) {
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DEBUG((DEBUG_ERROR, "MvPhyDxe: link up, "));
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PhyDev->LinkUp = TRUE;
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} else {
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DEBUG((DEBUG_ERROR, "MvPhyDxe: link down, "));
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PhyDev->LinkUp = FALSE;
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}
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}
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if (Data & MIIM_88E1xxx_PHYSTAT_DUPLEX) {
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DEBUG((DEBUG_ERROR, "full duplex, "));
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PhyDev->FullDuplex = TRUE;
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} else {
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DEBUG((DEBUG_ERROR, "half duplex, "));
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PhyDev->FullDuplex = FALSE;
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}
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Speed = Data & MIIM_88E1xxx_PHYSTAT_SPEED;
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switch (Speed) {
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case MIIM_88E1xxx_PHYSTAT_GBIT:
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DEBUG((DEBUG_ERROR, "speed 1000\n"));
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PhyDev->Speed = SPEED_1000;
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break;
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case MIIM_88E1xxx_PHYSTAT_100:
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DEBUG((DEBUG_ERROR, "speed 100\n"));
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PhyDev->Speed = SPEED_100;
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break;
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default:
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DEBUG((DEBUG_ERROR, "speed 10\n"));
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PhyDev->Speed = SPEED_10;
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break;
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}
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return EFI_SUCCESS;
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}
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/**
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Configure PHY device autonegotiation.
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@param[in out] *PhyDevice A pointer to configured PHY device structure.
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**/
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STATIC
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EFI_STATUS
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MvPhyConfigureAutonegotiation (
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IN OUT PHY_DEVICE *PhyDevice
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)
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{
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UINT32 Data;
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INTN Index;
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/* Read BMSR register in order to check autoneg capabilities and status. */
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Mdio->Read (Mdio, PhyDevice->Addr, PhyDevice->MdioIndex, MII_BMSR, &Data);
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if ((Data & BMSR_ANEGCAPABLE) && !(Data & BMSR_ANEGCOMPLETE)) {
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DEBUG ((DEBUG_INFO,
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"%a: Waiting for PHY auto negotiation...",
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__FUNCTION__));
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/* Wait for autonegotiation to complete and read media status */
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for (Index = 0; !(Data & BMSR_ANEGCOMPLETE); Index++) {
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if (Index > PHY_AUTONEGOTIATE_TIMEOUT) {
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DEBUG ((DEBUG_ERROR, "%a: Timeout\n", __FUNCTION__));
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PhyDevice->LinkUp = FALSE;
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return EFI_TIMEOUT;
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}
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gBS->Stall (1000); /* 1 ms */
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Mdio->Read (Mdio, PhyDevice->Addr, PhyDevice->MdioIndex, MII_BMSR, &Data);
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}
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PhyDevice->LinkUp = TRUE;
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DEBUG ((DEBUG_INFO, "%a: link up\n", __FUNCTION__));
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} else {
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Mdio->Read (Mdio, PhyDevice->Addr, PhyDevice->MdioIndex, MII_BMSR, &Data);
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if (Data & BMSR_LSTATUS) {
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PhyDevice->LinkUp = TRUE;
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DEBUG ((DEBUG_INFO, "%a: link up\n", __FUNCTION__));
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} else {
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PhyDevice->LinkUp = FALSE;
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DEBUG ((DEBUG_INFO, "%a: link down\n", __FUNCTION__));
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}
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}
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return EFI_SUCCESS;
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}
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STATIC
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VOID
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MvPhy1512WriteBits (
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IN PHY_DEVICE *PhyDev,
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IN UINT8 RegNum,
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IN UINT16 Offset,
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IN UINT16 Len,
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IN UINT16 Data)
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{
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UINT32 Reg, Mask;
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if ((Len + Offset) >= 16)
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Mask = 0 - (1 << Offset);
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else
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Mask = (1 << (Len + Offset)) - (1 << Offset);
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Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, RegNum, &Reg);
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Reg &= ~Mask;
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Reg |= Data << Offset;
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Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, RegNum, Reg);
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}
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STATIC
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EFI_STATUS
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MvPhyInit1512 (
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IN CONST MARVELL_PHY_PROTOCOL *Snp,
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IN OUT PHY_DEVICE *PhyDev
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)
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{
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EFI_STATUS Status;
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if (PhyDev->Connection == PHY_CONNECTION_SGMII) {
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/* Select page 0xff and update configuration registers according to
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* Marvell Release Notes - Alaska 88E1510/88E1518/88E1512 Rev A0,
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* Errata Section 3.1 - needed in SGMII mode.
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*/
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Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 22, 0x00ff);
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Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 17, 0x214B);
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Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 16, 0x2144);
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Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 17, 0x0C28);
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Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 16, 0x2146);
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Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 17, 0xB233);
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Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 16, 0x214D);
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Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 17, 0xCC0C);
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Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 16, 0x2159);
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/* Reset page selection and select page 0x12 */
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Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 22, 0x0000);
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Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 22, 0x0012);
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/* Write HWCFG_MODE = SGMII to Copper */
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MvPhy1512WriteBits(PhyDev, 20, 0, 3, 1);
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/* Phy reset - necessary after changing mode */
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MvPhy1512WriteBits(PhyDev, 20, 15, 1, 1);
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/* Reset page selection */
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Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 22, 0x0000);
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gBS->Stall(100);
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}
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MvPhyM88e1111sConfig (PhyDev);
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/* autonegotiation on startup is not always required */
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if (!PcdGetBool (PcdPhyStartupAutoneg))
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return EFI_SUCCESS;
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Status = MvPhyConfigureAutonegotiation (PhyDev);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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MvPhyParseStatus (PhyDev);
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return EFI_SUCCESS;
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}
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/**
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Initialize Marvell 88E1112 PHY.
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@param[in] MvPhyProtocol Marvell PHY protocol instance.
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@param[in out] *PhyDevice PHY device structure.
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**/
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STATIC
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EFI_STATUS
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MvPhyInit1112 (
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IN CONST MARVELL_PHY_PROTOCOL *MvPhyProtocol,
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IN OUT PHY_DEVICE *PhyDevice
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)
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{
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EFI_STATUS Status;
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MvPhyM88e1111sConfig (PhyDevice);
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if (PcdGetBool (PcdPhyStartupAutoneg)) {
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Status = MvPhyConfigureAutonegotiation (PhyDevice);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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MvPhyParseStatus (PhyDevice);
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}
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return EFI_SUCCESS;
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}
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EFI_STATUS
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MvPhyInit (
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IN CONST MARVELL_PHY_PROTOCOL *Snp,
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IN UINT32 PhyIndex,
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IN PHY_CONNECTION PhyConnection,
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IN OUT PHY_DEVICE **OutPhyDev
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)
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{
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EFI_STATUS Status;
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PHY_DEVICE *PhyDev;
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UINT8 *DeviceIds;
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UINT8 MdioIndex;
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UINT8 PhyId;
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Status = gBS->LocateProtocol (
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&gMarvellMdioProtocolGuid,
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NULL,
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(VOID **) &Mdio
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);
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if (EFI_ERROR(Status))
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return Status;
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MdioIndex = Phy2MdioController[PhyIndex];
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/* Verify correctness of PHY <-> MDIO assignment */
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if ((MdioDeviceTable[MdioIndex] == 0) ||
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(MdioIndex >= Mdio->ControllerCount)) {
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DEBUG ((DEBUG_ERROR, "MvPhyDxe: Incorrect Mdio controller assignment for PHY#%d", PhyIndex));
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return EFI_INVALID_PARAMETER;
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}
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DeviceIds = PcdGetPtr (PcdPhyDeviceIds);
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PhyId = DeviceIds[PhyIndex];
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if (PhyId >= MV_PHY_DEVICE_ID_MAX) {
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DEBUG ((DEBUG_ERROR,
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"%a, Incorrect PHY ID (0x%x) for PHY#%d\n",
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__FUNCTION__,
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PhyId,
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PhyIndex));
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return EFI_INVALID_PARAMETER;
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}
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/* perform setup common for all PHYs */
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PhyDev = AllocateZeroPool (sizeof (PHY_DEVICE));
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PhyDev->Addr = PhySmiAddresses[PhyIndex];
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PhyDev->Connection = PhyConnection;
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PhyDev->MdioIndex = MdioIndex;
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DEBUG ((DEBUG_INFO,
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"MvPhyDxe: MdioIndex is %d, PhyAddr is %d, connection %d\n",
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PhyDev->MdioIndex,
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PhyDev->Addr,
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PhyConnection));
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*OutPhyDev = PhyDev;
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return MvPhyDevices[PhyId].DevInit (Snp, PhyDev);
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}
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|
EFI_STATUS
|
MvPhyStatus (
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IN CONST MARVELL_PHY_PROTOCOL *This,
|
IN PHY_DEVICE *PhyDev
|
)
|
{
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UINT32 Data;
|
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Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMSR, &Data);
|
Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMSR, &Data);
|
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if ((Data & BMSR_LSTATUS) == 0) {
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PhyDev->LinkUp = FALSE;
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} else {
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PhyDev->LinkUp = TRUE;
|
}
|
|
return EFI_SUCCESS;
|
}
|
|
EFI_STATUS
|
EFIAPI
|
MvPhyDxeInitialise (
|
IN EFI_HANDLE ImageHandle,
|
IN EFI_SYSTEM_TABLE *SystemTable
|
)
|
{
|
MARVELL_PHY_PROTOCOL *Phy;
|
EFI_STATUS Status;
|
EFI_HANDLE Handle = NULL;
|
|
Phy = AllocateZeroPool (sizeof (MARVELL_PHY_PROTOCOL));
|
Phy->Status = MvPhyStatus;
|
Phy->Init = MvPhyInit;
|
|
Status = gBS->InstallMultipleProtocolInterfaces (
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&Handle,
|
&gMarvellPhyProtocolGuid, Phy,
|
NULL
|
);
|
|
if (EFI_ERROR(Status)) {
|
DEBUG((DEBUG_ERROR, "Failed to install interfaces\n"));
|
return Status;
|
}
|
DEBUG((DEBUG_ERROR, "Succesfully installed protocol interfaces\n"));
|
|
return EFI_SUCCESS;
|
}
|
