UEFI Porting Guide
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==================
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This document provides instructions for adding support for new Marvell Armada
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board. For the sake of simplicity new Marvell board will be called "new_board".
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1. Create configuration files for new target
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1.1 Create FDF file for new board
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- Copy and rename edk2-platforms/Platform/Marvell/Armada/Armada70x0.fdf to
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edk2-platforms/Platform/Marvell/Armada/new_board.fdf
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- Change the first no-comment line:
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[FD.Armada70x0_EFI] to [FD.{new_board}_EFI]
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1.2 Create DSC file for new board
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- Add new_board.dsc file to edk2-platforms/Platform/Marvell/Armada directory
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- Insert following [Defines] section to new_board.dsc:
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[Defines]
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PLATFORM_NAME = {new_board}
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PLATFORM_GUID = {newly_generated_GUID}
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PLATFORM_VERSION = 0.1
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DSC_SPECIFICATION = 0x00010019
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OUTPUT_DIRECTORY = {output_directory}
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SUPPORTED_ARCHITECTURES = AARCH64
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BUILD_TARGETS = DEBUG|RELEASE
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SKUID_IDENTIFIER = DEFAULT
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FLASH_DEFINITION = {path_to_fdf_file}
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- Add "!include Armada.dsc.inc" entry to new_board.dsc
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2. Driver support
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- According to content of files from
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edk2-platforms/Silicon/Marvell/Documentation/PortingGuide.txt
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insert PCD entries into new_board.dsc for every needed interface (as listed below).
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3. Compilation
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- Refer to edk2-platforms/Platform/Marvell/Readme.md. Remember to change
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{platform} to new_board in order to point build system to newly created DSC file.
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4. Output file
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- Output files (and among others FD file, which may be used by ATF) are
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generated under directory pointed by "OUTPUT_DIRECTORY" entry (see point 1.2).
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5. ACPI support (optional)
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- The tables can be enabled as in A70x0Db example:
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<path to edk2-platforms>/Platforms/Marvell/Armada/AcpiTables/Armada70x0Db/
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- Enable compilation of the tables in the board's .dsc file. Add it to the
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output flash image contents via .fdf.inc file - path to it defined as
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BOARD_DXE_FV_COMPONENTS. Example:
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Armada70x0Db.dsc:
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BOARD_DXE_FV_COMPONENTS = Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc
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[Components.AARCH64]
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Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/AcpiTables.inf
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Armada70x0Db.fdf.inc:
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!if $(ARCH) == AARCH64
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# ACPI support
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INF RuleOverride = ACPITABLE Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/AcpiTables.inf
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!endif
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COMPHY configuration
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====================
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In order to configure ComPhy library, following PCDs are available:
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- gMarvellTokenSpaceGuid.PcdComPhyDevices
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This array indicates, which ones of the ComPhy chips defined in
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MVHW_COMPHY_DESC template will be configured.
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Every ComPhy PCD has <Num> part where <Num> stands for chip ID (order is not
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important, but configuration will be set for first PcdComPhyChipCount chips).
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Every chip has 3 ComPhy PCDs and three of them comprise per-board lanes
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settings for this chip. Their format is array of up to 10 values reflecting
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defined numbers for SPEED/TYPE/INVERT, whose description can be found in:
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OpenPlatformPkg/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h
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- gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes
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(Array of types - currently supported are:
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CP_UNCONNECTED 0x0
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CP_PCIE0 0x1
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CP_PCIE1 0x2
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CP_PCIE2 0x3
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CP_PCIE3 0x4
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CP_SATA0 0x5
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CP_SATA1 0x6
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CP_SATA2 0x7
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CP_SATA3 0x8
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CP_SGMII0 0x9
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CP_SGMII1 0xA
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CP_SGMII2 0xB
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CP_SGMII3 0xC
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CP_QSGMII 0xD
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CP_USB3_HOST0 0xE
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CP_USB3_HOST1 0xF
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CP_USB3_DEVICE 0x10
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CP_XAUI0 0x11
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CP_XAUI1 0x12
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CP_XAUI2 0x13
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CP_XAUI3 0x14
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CP_RXAUI0 0x15
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CP_RXAUI1 0x16
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CP_SFI 0x17 )
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- gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds
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(Array of speeds - currently supported are:
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CP_1_25G 0x1
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CP_1_5G 0x2
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CP_2_5G 0x3
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CP_3G 0x4
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CP_3_125G 0x5
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CP_5G 0x6
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CP_5_15625G 0x7
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CP_6G 0x8
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CP_6_25G 0x9
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CP_10_3125G 0xA )
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- gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags
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(Array of lane inversion types - currently supported are:
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CP_NO_INVERT 0x0
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CP_TXD_INVERT 0x1
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CP_RXD_INVERT 0x2
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CP_ALL_INVERT 0x3 )
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Example
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-------
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#ComPhy
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gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
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gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_SGMII1), $(CP_USB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) }
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gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) }
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PHY Driver configuration
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========================
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MvPhyDxe provides basic initialization and status routines for Marvell PHYs.
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Currently only 1512 and 1112 series PHYs are supported. Following PCDs are required:
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- gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg
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(boolean - if true, driver waits for autonegotiation on startup)
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- gMarvellTokenSpaceGuid.PcdPhyDeviceIds
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(list of values corresponding to MV_PHY_DEVICE_ID enum)
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- gMarvellTokenSpaceGuid.PcdPhySmiAddresses
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(addresses of PHY devices)
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- gMarvellTokenSpaceGuid.PcdPhy2MdioController
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(Array specifying, which Mdio controller the PHY is attached to)
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MV_PHY_DEVICE_ID:
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typedef enum {
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0 MV_PHY_DEVICE_1512,
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1 MV_PHY_DEVICE_1112,
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} MV_PHY_DEVICE_ID;
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It should be extended when adding support for other PHY models.
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Disable autonegotiation:
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gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
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assuming, that PHY models are 1512 and 1112 for two consecutive ports:
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gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x1 }
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MDIO configuration
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==================
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MDIO driver provides access to network PHYs' registers via EFI_MDIO_READ and
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EFI_MDIO_WRITE functions (EFI_MDIO_PROTOCOL). Following PCD is required:
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- gMarvellTokenSpaceGuid.PcdMdioControllers
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(Array with used controllers
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Set to 0x1 for enabled, 0x0 for disabled)
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I2C configuration
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=================
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In order to enable driver on a new platform, following steps need to be taken:
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- add following line to .dsc file:
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edk2-platforms/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
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- add following line to .fdf file:
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INF edk2-platforms/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
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- add PCDs with relevant values to .dsc file:
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- gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57 }
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(addresses of I2C slave devices on bus)
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- gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 }
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(buses to which accoring slaves are attached)
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- gMarvellTokenSpaceGuid.PcdI2cBusCount|2
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(number of SoC's I2C buses)
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- gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x1, 0x1 }
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(array with used controllers)
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- gMarvellTokenSpaceGuid.PcdI2cClockFrequency|200000000
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(I2C host controller clock frequency)
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- gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000
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(baud rate used in I2C transmission)
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PciEmulation configuration
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==========================
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Installation of various NonDiscoverable devices via PciEmulation driver is performed
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via set of PCDs. Following are available:
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- gMarvellTokenSpaceGuid.PcdPciEXhci
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(Indicates, which Xhci devices are used)
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- gMarvellTokenSpaceGuid.PcdPciEAhci
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(Indicates, which Ahci devices are used)
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- gMarvellTokenSpaceGuid.PcdPciESdhci
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(Indicates, which Sdhci devices are used)
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All above PCD's correspond to hardware description in a dedicated structure:
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STATIC PCI_E_PLATFORM_DESC A70x0PlatDescTemplate
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in Platform/Marvell/PciEmulation/PciEmulation.c file. It comprises device
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count, base addresses, register region size and DMA-coherency type.
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Example
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-------
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Assuming we want to enable second XHCI port and one SDHCI port on Armada
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70x0 board, following needs to be declared:
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gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 0x1 }
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gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 }
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SATA configuration
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==================
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There is one additional PCD for AHCI:
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- gMarvellTokenSpaceGuid.PcdSataBaseAddress
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(Base address of SATA controller register space - used in SATA ComPhy init
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sequence)
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Pp2Dxe configuration
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====================
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Pp2Dxe is driver supporting PP2 NIC on Marvell platforms. Following PCDs
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are required to operate:
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- gMarvellTokenSpaceGuid.PcdPp2Controllers
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(Array with used controllers
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Set to 0x1 for enabled, 0x0 for disabled)
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- gMarvellTokenSpaceGuid.PcdPp2Port2Controller
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(Array specifying, to which controller the port belongs to)
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- gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes
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(Indicates speed of the network interface:
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PHY_RGMII 0x0
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PHY_RGMII_ID 0x1
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PHY_RGMII_TXID 0x2
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PHY_RGMII_RXID 0x3
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PHY_SGMII 0x4
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PHY_RTBI 0x5
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PHY_XAUI 0x6
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PHY_RXAUI 0x7
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PHY_SFI 0x8 )
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- gMarvellTokenSpaceGuid.PcdPp2PhyIndexes
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(Array specifying, to which PHY from
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gMarvellTokenSpaceGuid.PcdPhyDeviceIds is used. If none,
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e.g. in 10G SFI in-band link detection, 0xFF value must
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be specified)
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- gMarvellTokenSpaceGuid.PcdPp2PortIds
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(Identificators of PP2 ports)
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- gMarvellTokenSpaceGuid.PcdPp2GopIndexes
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(Indexes used in GOP operation)
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- gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp
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(Set to 0x1 for always-up interface, 0x0 otherwise)
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- gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed
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(Indicates speed of the network interface:
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PHY_SPEED_10 0x1
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PHY_SPEED_100 0x2
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PHY_SPEED_1000 0x3
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PHY_SPEED_2500 0x4
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PHY_SPEED_10000 0x5 )
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UTMI PHY configuration
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======================
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In order to configure UTMI, following PCDs are available:
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- gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled
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(Array with used controllers
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Set to 0x1 for enabled, 0x0 for disabled)
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- gMarvellTokenSpaceGuid.PcdUtmiPortType
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(Indicates type of the connected USB port:
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UTMI_USB_HOST0 0x0
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UTMI_USB_HOST1 0x1
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UTMI_USB_DEVICE0 0x2 )
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Example
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-------
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# UtmiPhy
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gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }
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gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
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SPI driver configuration
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========================
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Following PCDs are available for configuration of spi driver:
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- gMarvellTokenSpaceGuid.PcdSpiClockFrequency
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(Frequency (in Hz) of SPI clock)
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- gMarvellTokenSpaceGuid.PcdSpiMaxFrequency
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(Max SCLK line frequency (in Hz) (max transfer frequency) )
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SpiFlash configuration
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======================
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Folowing PCDs for spi flash driver configuration must be set properly:
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- gMarvellTokenSpaceGuid.PcdSpiFlashMode
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(Default SCLK mode (see SPI_MODE enum in file
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edk2-platforms/Platform/Marvell/Drivers/Spi/MvSpi.h))
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- gMarvellTokenSpaceGuid.PcdSpiFlashCs
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(Chip select used for communication with the Flash)
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MPP configuration
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=================
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Multi-Purpose Ports (MPP) are configurable through platform PCDs.
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In order to set desired pin multiplexing, .dsc file needs to be modified.
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(edk2-platforms/Platform/Marvell/Armada/{platform_name}.dsc - please refer to
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Documentation/Build.txt for currently supported {platftorm_name} )
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Following PCDs are available:
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- gMarvellTokenSpaceGuid.PcdMppChipCount
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(Indicates how many different chips are placed on board. So far up to 4 chips
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are supported)
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Every MPP PCD has <Num> part where
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<Num> stands for chip ID (order is not important, but configuration will be
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set for first PcdMppChipCount chips).
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Below is example for the first chip (Chip0).
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- gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag
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(Indicates that register order is reversed. (Needs to be used only for AP806-Z1) )
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- gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress
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(This is base address for MPP configuration register)
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- gMarvellTokenSpaceGuid.PcdChip0MppPinCount
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(Defines how many MPP pins are available)
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- gMarvellTokenSpaceGuid.PcdChip0MppSel0
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- gMarvellTokenSpaceGuid.PcdChip0MppSel1
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- gMarvellTokenSpaceGuid.PcdChip0MppSel2
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(This registers defines functions of 10 pins in ascending order)
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Examples
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--------
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# APN806-A0 MPP SET
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gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
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gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
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gMarvellTokenSpaceGuid.PcdChip0MppRegCount|3
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gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x0 }
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gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
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Set pin 6 and 7 to 0xa function:
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gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xa, 0x0, 0x0 }
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Ramdisk configuration
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=====================
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There is one PCD available for Ramdisk configuration
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- gMarvellTokenSpaceGuid.PcdRamDiskSize
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(Defines size of Ramdisk)
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