/** @file
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PCI Host Bridge Library instance for Marvell 70x0/80x0
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Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
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Copyright (c) 2019 Marvell International Ltd. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PiDxe.h>
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#include <IndustryStandard/Pci22.h>
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#include <Library/ArmLib.h>
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/MvGpioLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Protocol/BoardDesc.h>
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#include "PciHostBridgeLibConstructor.h"
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/**
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This function configures PCIE controllers IATU windows.
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@param [in] PcieDbiAddress PCIE controller base address.
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@param [in] Index IATU window index.
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@param [in] CpuBase Address from the CPU perspective.
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@param [in] PciBase Target PCIE address.
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@param [in] Size IATU window size.
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@param [in] Type IATU window type.
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@param [in] EnableFlags Extra configuration flags.
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@retval none
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**/
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STATIC
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VOID
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ConfigureWindow (
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IN EFI_PHYSICAL_ADDRESS PcieDbiAddress,
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IN UINTN Index,
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IN UINT64 CpuBase,
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IN UINT64 PciBase,
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IN UINT64 Size,
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IN UINTN Type,
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IN UINTN EnableFlags
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)
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{
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ArmDataMemoryBarrier ();
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MmioWrite32 (PcieDbiAddress + IATU_VIEWPORT_OFF,
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IATU_VIEWPORT_OUTBOUND | IATU_VIEWPORT_REGION_INDEX (Index));
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ArmDataMemoryBarrier ();
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MmioWrite32 (PcieDbiAddress + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,
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(UINT32)(CpuBase & MAX_UINT32));
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MmioWrite32 (PcieDbiAddress + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,
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(UINT32)(CpuBase >> 32));
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MmioWrite32 (PcieDbiAddress + IATU_LIMIT_ADDR_OFF_OUTBOUND_0,
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(UINT32)(CpuBase + Size - 1));
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MmioWrite32 (PcieDbiAddress + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,
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(UINT32)(PciBase & MAX_UINT32));
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MmioWrite32 (PcieDbiAddress + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,
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(UINT32)(PciBase >> 32));
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MmioWrite32 (PcieDbiAddress + IATU_REGION_CTRL_1_OFF_OUTBOUND_0,
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Type);
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MmioWrite32 (PcieDbiAddress + IATU_REGION_CTRL_2_OFF_OUTBOUND_0,
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IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN | EnableFlags);
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}
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/**
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Perform PCIE slot reset using external GPIO pin.
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@param [in] PcieDbiAddress PCIE controller base address.
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@retval none
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**/
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STATIC
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VOID
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WaitForLink (
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IN EFI_PHYSICAL_ADDRESS PcieDbiAddress
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)
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{
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UINT32 Mask;
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UINT32 Status;
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UINT32 Timeout;
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if (!(MmioRead32 (PcieDbiAddress + PCIE_PM_STATUS) & PCIE_PM_LTSSM_STAT_MASK)) {
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DEBUG ((DEBUG_INIT, "%a: no PCIE device detected\n", __FUNCTION__));
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return;
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}
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/* Wait for the link to establish itself. */
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DEBUG ((DEBUG_INIT, "%a: waiting for PCIE link\n", __FUNCTION__));
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Mask = PCIE_GLOBAL_STATUS_RDLH_LINK_UP | PCIE_GLOBAL_STATUS_PHY_LINK_UP;
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Timeout = PCIE_LINK_UP_TIMEOUT_US / 10;
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do {
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Status = MmioRead32 (PcieDbiAddress + PCIE_GLOBAL_STATUS_REG);
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if ((Status & Mask) == Mask) {
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DEBUG ((DEBUG_ERROR, "pcie@0x%x link UP\n", PcieDbiAddress));
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break;
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}
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/* Wait 10us between each link status check. */
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gBS->Stall (10);
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} while (Timeout--);
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}
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/**
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Perform PCIE slot reset using external GPIO pin.
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@param [in] *PcieResetGpio GPIO pin description.
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@retval EFI_SUCEESS PCIE slot reset succeeded.
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@retval Other Return error status.
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**/
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STATIC
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EFI_STATUS
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ResetPcieSlot (
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IN MV_GPIO_PIN CONST *PcieResetGpio
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)
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{
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EMBEDDED_GPIO_MODE Mode;
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EMBEDDED_GPIO_PIN GpioPin;
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EMBEDDED_GPIO *GpioProtocol;
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EFI_STATUS Status;
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/* Get GPIO protocol. */
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Status = MvGpioGetProtocol (PcieResetGpio->ControllerType, &GpioProtocol);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "%a: Unable to find GPIO protocol\n", __FUNCTION__));
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return Status;
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}
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GpioPin = GPIO (PcieResetGpio->ControllerId, PcieResetGpio->PinNumber),
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/* Activate reset. */
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Mode = PcieResetGpio->ActiveHigh ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0;
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Status = GpioProtocol->Set (GpioProtocol, GpioPin, Mode);
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/*
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* According to the PCIE specification, the reset signal must be active
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* for minimum 100ms. To be on a safe side, use 150ms delay.
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*/
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MemoryFence ();
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gBS->Stall (150 * 1000);
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/* Dectivate reset. */
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Mode = PcieResetGpio->ActiveHigh ? GPIO_MODE_OUTPUT_0 : GPIO_MODE_OUTPUT_1;
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Status = GpioProtocol->Set (GpioProtocol, GpioPin, Mode);
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/*
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* The controller cannot be configured (e.g. the clocks have to establish)
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* during 20ms period after the reset is deactivated.
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*/
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MemoryFence ();
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gBS->Stall (20 * 1000);
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return EFI_SUCCESS;
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}
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/**
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Obtain resources and perform a low-level PCIE controllers
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configuration.
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@param [in] ImageHandle The image handle.
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@param [in] *SystemTable The system table.
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@retval EFI_SUCEESS PCIE configuration successful.
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@retval Other Return error status.
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**/
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EFI_STATUS
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EFIAPI
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Armada7k8kPciHostBridgeLibConstructor (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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MV_BOARD_PCIE_DESCRIPTION CONST *BoardPcieDescription;
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MARVELL_BOARD_DESC_PROTOCOL *BoardDescriptionProtocol;
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MV_PCIE_CONTROLLER CONST *PcieController;
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EFI_PHYSICAL_ADDRESS PcieDbiAddress;
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EFI_STATUS Status;
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UINTN Index;
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/* Obtain list of available controllers */
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Status = gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid,
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NULL,
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(VOID **)&BoardDescriptionProtocol);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR,
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"%a: Cannot locate BoardDesc protocol\n",
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__FUNCTION__));
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return EFI_DEVICE_ERROR;
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}
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Status = BoardDescriptionProtocol->PcieDescriptionGet (
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BoardDescriptionProtocol,
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&BoardPcieDescription);
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if (Status == EFI_NOT_FOUND) {
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/* No controllers used on the platform, exit silently */
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return EFI_SUCCESS;
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} else if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR,
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"%a: Cannot get Pcie board desc from BoardDesc protocol\n",
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__FUNCTION__));
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return EFI_DEVICE_ERROR;
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}
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for (Index = 0; Index < BoardPcieDescription->PcieControllerCount; Index++) {
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PcieController = &(BoardPcieDescription->PcieControllers[Index]);
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ASSERT (PcieController->PcieBusMin == 0);
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if (PcieController->HaveResetGpio == TRUE) {
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/* Reset PCIE slot */
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Status = ResetPcieSlot (&PcieController->PcieResetGpio);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR,
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"%a: Cannot reset Pcie Slot\n",
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__FUNCTION__));
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return EFI_DEVICE_ERROR;
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}
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}
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/* Low level PCIE controller configuration */
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PcieDbiAddress = PcieController->PcieDbiAddress;
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MmioAndThenOr32 (PcieDbiAddress + PORT_LINK_CTRL_OFF,
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~PORT_LINK_CTRL_OFF_LINK_CAPABLE_MASK,
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PORT_LINK_CTRL_OFF_LINK_CAPABLE_x4);
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MmioAndThenOr32 (PcieDbiAddress + GEN2_CTRL_OFF,
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~GEN2_CTRL_OFF_NUM_OF_LANES_MASK,
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GEN2_CTRL_OFF_NUM_OF_LANES(4) | GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE);
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MmioAndThenOr32 (PcieDbiAddress + PCIE_GLOBAL_CTRL_OFFSET,
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~(PCIE_GLOBAL_CTRL_DEVICE_TYPE_MASK | PCIE_GLOBAL_APP_LTSSM_EN),
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PCIE_GLOBAL_CTRL_DEVICE_TYPE_RC);
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MmioWrite32 (PcieDbiAddress + PCIE_ARCACHE_TRC_REG,
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ARCACHE_DEFAULT_VALUE);
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MmioWrite32 (PcieDbiAddress + PCIE_AWCACHE_TRC_REG,
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AWCACHE_DEFAULT_VALUE);
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MmioAndThenOr32 (PcieDbiAddress + PCIE_ARUSER_REG,
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~AX_USER_DOMAIN_MASK,
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AX_USER_DOMAIN_OUTER_SHAREABLE);
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MmioAndThenOr32 (PcieDbiAddress + PCIE_AWUSER_REG,
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~AX_USER_DOMAIN_MASK,
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AX_USER_DOMAIN_OUTER_SHAREABLE);
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MmioAndThenOr32 (PcieDbiAddress + PCIE_LINK_CTL_2,
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~TARGET_LINK_SPEED_MASK,
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LINK_SPEED_GEN_3);
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MmioAndThenOr32 (PcieDbiAddress + PCIE_LINK_CAPABILITY,
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~TARGET_LINK_SPEED_MASK,
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LINK_SPEED_GEN_3);
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MmioOr32 (PcieDbiAddress + PCIE_GEN3_EQU_CTRL,
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GEN3_EQU_EVAL_2MS_DISABLE);
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MmioOr32 (PcieDbiAddress + PCIE_GLOBAL_CTRL_OFFSET,
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PCIE_GLOBAL_APP_LTSSM_EN);
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/* Region 0: MMIO32 range */
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ConfigureWindow (PcieDbiAddress,
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PcieController->PcieMmio32WinBase - PcieController->PcieMmio32Translation,
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PcieController->PcieMmio32WinBase,
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PcieController->PcieMmio32WinBase,
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PcieController->PcieMmio32WinSize,
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IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM,
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0);
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/* Region 1: Type 0 config space */
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ConfigureWindow (PcieDbiAddress,
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1,
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PcieController->ConfigSpaceAddress,
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0x0,
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SIZE_64KB,
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IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0,
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IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE);
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/* Region 2: Type 1 config space */
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ConfigureWindow (PcieDbiAddress,
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2,
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PcieController->ConfigSpaceAddress + SIZE_64KB,
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0x0,
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PcieController->PcieBusMax * SIZE_1MB,
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IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1,
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IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE);
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/* Region 3: port I/O range */
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ConfigureWindow (PcieDbiAddress,
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3,
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PcieController->PcieIoTranslation,
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PcieController->PcieIoWinBase,
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PcieController->PcieIoWinSize,
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IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO,
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0);
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/* Region 4: MMIO64 range */
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ConfigureWindow (PcieDbiAddress,
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4,
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PcieController->PcieMmio64WinBase,
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PcieController->PcieMmio64WinBase,
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PcieController->PcieMmio64WinSize,
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IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM,
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0);
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MmioOr32 (PcieDbiAddress + PCIE_GLOBAL_INT_MASK1_REG,
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PCIE_INT_A_ASSERT_MASK |
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PCIE_INT_B_ASSERT_MASK |
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PCIE_INT_C_ASSERT_MASK |
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PCIE_INT_D_ASSERT_MASK);
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WaitForLink (PcieDbiAddress);
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/* Enable the RC */
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MmioOr32 (PcieDbiAddress + PCI_COMMAND_OFFSET,
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EFI_PCI_COMMAND_IO_SPACE |
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EFI_PCI_COMMAND_MEMORY_SPACE |
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EFI_PCI_COMMAND_BUS_MASTER);
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}
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return EFI_SUCCESS;
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}
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