/** @file
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PCI Host Bridge Library instance for Marvell Armada 70x0/80x0
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Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
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Copyright (c) 2019 Marvell International Ltd. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PiDxe.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/DevicePathLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PciHostBridgeLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Protocol/BoardDesc.h>
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#include <Protocol/PciHostBridgeResourceAllocation.h>
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#include <Protocol/PciRootBridgeIo.h>
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#pragma pack(1)
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typedef struct {
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ACPI_HID_DEVICE_PATH AcpiDevicePath;
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EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
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} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
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#pragma pack ()
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STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePathTemplate = {
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{
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{
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ACPI_DEVICE_PATH,
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ACPI_DP,
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{
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(UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
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(UINT8)((sizeof (ACPI_HID_DEVICE_PATH)) >> 8)
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}
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},
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EISA_PNP_ID (0x0A08), // PCI Express
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0 // AcpiDevicePath.UID
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},
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{
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END_DEVICE_PATH_TYPE,
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END_ENTIRE_DEVICE_PATH_SUBTYPE,
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{
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END_DEVICE_PATH_LENGTH,
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0
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}
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}
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};
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GLOBAL_REMOVE_IF_UNREFERENCED
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CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
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L"Mem", L"I/O", L"Bus"
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};
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/**
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Return all the root bridge instances in an array.
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@param Count Return the count of root bridge instances.
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@return All the root bridge instances in an array.
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The array should be passed into PciHostBridgeFreeRootBridges()
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when it's not used.
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**/
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PCI_ROOT_BRIDGE *
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EFIAPI
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PciHostBridgeGetRootBridges (
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UINTN *Count
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)
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{
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MV_BOARD_PCIE_DESCRIPTION CONST *BoardPcieDescription;
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MARVELL_BOARD_DESC_PROTOCOL *BoardDescriptionProtocol;
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EFI_PCI_ROOT_BRIDGE_DEVICE_PATH *EfiPciRootBridgeDevicePath;
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MV_PCIE_CONTROLLER CONST *PcieController;
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PCI_ROOT_BRIDGE *PciRootBridges;
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PCI_ROOT_BRIDGE *RootBridge;
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EFI_STATUS Status;
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UINTN Index;
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*Count = 0;
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/* Obtain list of available controllers */
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Status = gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid,
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NULL,
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(VOID **)&BoardDescriptionProtocol);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR,
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"%a: Cannot locate BoardDesc protocol\n",
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__FUNCTION__));
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return NULL;
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}
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Status = BoardDescriptionProtocol->PcieDescriptionGet (
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BoardDescriptionProtocol,
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&BoardPcieDescription);
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if (Status == EFI_NOT_FOUND) {
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/* No controllers used on the platform, exit silently */
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return NULL;
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} else if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR,
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"%a: Cannot get Pcie board desc from BoardDesc protocol\n",
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__FUNCTION__));
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return NULL;
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}
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/* Assign return values */
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PciRootBridges = AllocateZeroPool (BoardPcieDescription->PcieControllerCount *
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sizeof (PCI_ROOT_BRIDGE));
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if (PciRootBridges == NULL) {
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DEBUG ((DEBUG_ERROR, "%a: Fail to allocate resources\n", __FUNCTION__));
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return NULL;
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}
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*Count = BoardPcieDescription->PcieControllerCount;
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RootBridge = PciRootBridges;
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/* Fill information of all root bridge instances */
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for (Index = 0; Index < *Count; Index++, RootBridge++) {
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EfiPciRootBridgeDevicePath = AllocateCopyPool (
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sizeof (EFI_PCI_ROOT_BRIDGE_DEVICE_PATH),
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&mEfiPciRootBridgeDevicePathTemplate
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);
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EfiPciRootBridgeDevicePath->AcpiDevicePath.UID = Index;
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PcieController = &(BoardPcieDescription->PcieControllers[Index]);
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RootBridge->Segment = Index;
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RootBridge->Supports = 0;
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RootBridge->Attributes = RootBridge->Supports;
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RootBridge->DmaAbove4G = FALSE;
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#ifndef MDE_CPU_ARM
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RootBridge->AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |
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EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
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#else
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RootBridge->AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM;
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#endif
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RootBridge->Bus.Base = PcieController->PcieBusMin;
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RootBridge->Bus.Limit = PcieController->PcieBusMax;
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RootBridge->Io.Base = PcieController->PcieIoWinBase;
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RootBridge->Io.Limit = PcieController->PcieIoWinBase +
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PcieController->PcieIoWinSize - 1;
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RootBridge->Io.Translation = MAX_UINT64 -
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PcieController->PcieIoTranslation + 1;
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RootBridge->Mem.Base = PcieController->PcieMmio32WinBase;
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RootBridge->Mem.Limit = PcieController->PcieMmio32WinBase +
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PcieController->PcieMmio32WinSize - 1;
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RootBridge->Mem.Translation = MAX_UINT64 -
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PcieController->PcieMmio32Translation + 1;
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#ifndef MDE_CPU_ARM
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RootBridge->MemAbove4G.Base = PcieController->PcieMmio64WinBase;
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RootBridge->MemAbove4G.Limit = PcieController->PcieMmio64WinBase +
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PcieController->PcieMmio64WinSize - 1;
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RootBridge->MemAbove4G.Translation = MAX_UINT64 -
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PcieController->PcieMmio64Translation + 1;
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#else
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RootBridge->MemAbove4G.Base = MAX_UINT64;
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RootBridge->MemAbove4G.Limit = 0;
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RootBridge->MemAbove4G.Translation = 0;
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#endif
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/* No separate ranges for prefetchable and non-prefetchable BARs */
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RootBridge->PMem.Base = MAX_UINT64;
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RootBridge->PMem.Limit = 0;
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RootBridge->PMemAbove4G.Base = MAX_UINT64;
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RootBridge->PMemAbove4G.Limit = 0;
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RootBridge->NoExtendedConfigSpace = FALSE;
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RootBridge->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)EfiPciRootBridgeDevicePath;
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}
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return PciRootBridges;
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}
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/**
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Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
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@param Bridges The root bridge instances array.
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@param Count The count of the array.
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**/
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VOID
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EFIAPI
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PciHostBridgeFreeRootBridges (
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PCI_ROOT_BRIDGE *Bridges,
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UINTN Count
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)
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{
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FreePool (Bridges);
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}
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/**
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Inform the platform that the resource conflict happens.
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@param HostBridgeHandle Handle of the Host Bridge.
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@param Configuration Pointer to PCI I/O and PCI memory resource
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descriptors. The Configuration contains the resources
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for all the root bridges. The resource for each root
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bridge is terminated with END descriptor and an
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additional END is appended indicating the end of the
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entire resources. The resource descriptor field
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values follow the description in
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EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
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.SubmitResources().
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**/
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VOID
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EFIAPI
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PciHostBridgeResourceConflict (
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EFI_HANDLE HostBridgeHandle,
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VOID *Configuration
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)
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{
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EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
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CHAR16 *MemoryTypeDescription[] = { L"(Prefetchable)", L"" };
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CHAR16 *MemoryType;
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UINTN RootBridgeIndex;
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DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));
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RootBridgeIndex = 0;
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Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration;
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while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
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DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
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for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
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ASSERT (Descriptor->ResType <
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ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr));
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DEBUG ((DEBUG_ERROR,
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" %s: Length/Alignment = 0x%lx / 0x%lx\n",
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mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
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Descriptor->AddrLen, Descriptor->AddrRangeMax));
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if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
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if (Descriptor->SpecificFlag &
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EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) {
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MemoryType = MemoryTypeDescription[0];
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} else {
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MemoryType = MemoryTypeDescription[1];
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}
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DEBUG ((DEBUG_ERROR,
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" Granularity/SpecificFlag = %ld / %02x%s\n",
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Descriptor->AddrSpaceGranularity,
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Descriptor->SpecificFlag,
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MemoryType));
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}
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}
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/* Skip the END descriptor for root bridge */
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ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
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Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
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(EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1);
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}
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}
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