/** @file
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PCH preserved MMIO resource definitions.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_PRESERVED_RESOURCES_H_
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#define _PCH_PRESERVED_RESOURCES_H_
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/**
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PCH preserved MMIO range, 24 MB, from 0xFD000000 to 0xFE7FFFFF
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Detailed recommended static allocation
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+-------------------------------------------------------------------------+
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| Size | Start | End | Usage |
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| 16 MB | 0xFD000000 | 0xFDFFFFFF | SBREG |
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| 64 KB | 0xFE000000 | 0xFE00FFFF | PMC MBAR |
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| 4 KB | 0xFE010000 | 0xFE010FFF | SPI BAR0 |
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| 88 KB | 0xFE020000 | 0xFE035FFF | SerialIo BAR in ACPI mode |
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| 24 KB | 0xFE036000 | 0xFE03BFFF | Unused |
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| 4 KB | 0xFE03C000 | 0xFE03CFFF | Thermal Device in ACPI mode |
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| 524 KB | 0xFE03D000 | 0xFE0BFFFF | Unused |
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| 256 KB | 0xFE0C0000 | 0xFE0FFFFF | TraceHub FW BAR |
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| 1 MB | 0xFE100000 | 0xFE1FFFFF | TraceHub MTB BAR |
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| 2 MB | 0xFE200000 | 0xFE3FFFFF | TraceHub SW BAR |
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| 64 KB | 0xFE400000 | 0xFE40FFFF | CIO2 MMIO BAR in ACPI mode |
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| 2 MB - 64KB | 0xFE410000 | 0xFE5FFFFF | Unused |
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| 2 MB | 0xFE600000 | 0xFE7FFFFF | Temp address |
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+-------------------------------------------------------------------------+
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**/
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#define PCH_PRESERVED_BASE_ADDRESS 0xFD000000 ///< Pch preserved MMIO base address
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#define PCH_PRESERVED_MMIO_SIZE 0x01800000 ///< 24MB
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#define PCH_PCR_BASE_ADDRESS 0xFD000000 ///< SBREG MMIO base address
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#define PCH_PCR_MMIO_SIZE 0x01000000 ///< 16MB
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#define PCH_PWRM_BASE_ADDRESS 0xFE000000 ///< PMC MBAR MMIO base address
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#define PCH_PWRM_MMIO_SIZE 0x00010000 ///< 64KB
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#define PCH_SPI_BASE_ADDRESS 0xFED1C000 + 0x3800 ///< SPI MBAR MMIO base address
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#define PCH_SPI_MMIO_SIZE 0x00001000 ///< 4KB
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#define PCH_SERIAL_IO_BASE_ADDRESS 0xFE020000 ///< SerialIo MMIO base address
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#define PCH_SERIAL_IO_MMIO_SIZE 0x00016000 ///< 88KB
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#define PCH_THERMAL_BASE_ADDRESS 0xFE03C000 ///< Thermal Device in ACPI mode
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#define PCH_THERMAL_MMIO_SIZE 0x00001000 ///< 4KB
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#define PCH_TRACE_HUB_FW_BASE_ADDRESS 0xFE0C0000 ///< TraceHub FW MMIO base address
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#define PCH_TRACE_HUB_FW_MMIO_SIZE 0x00040000 ///< 256KB
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#define PCH_TRACE_HUB_MTB_BASE_ADDRESS 0xFE100000 ///< TraceHub MTB MMIO base address
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#define PCH_TRACE_HUB_MTB_MMIO_SIZE 0x00100000 ///< 1MB
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#define PCH_TRACE_HUB_SW_BASE_ADDRESS 0xFE200000 ///< TraceHub SW MMIO base address
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#define PCH_TRACE_HUB_SW_MMIO_SIZE 0x00200000 ///< 2MB
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#define PCH_CIO2_BASE_ADDRESS 0xFE400000 ///< CIO2 MMIO BAR in ACPI mode
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#define PCH_CIO2_MMIO_SIZE 0x00010000 ///< 64KB
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#define PCH_TEMP_BASE_ADDRESS 0xFE600000 ///< preserved temp address for misc usage
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#define PCH_TEMP_MMIO_SIZE 0x00200000 ///< 2MB
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#define RCRB 0xFED1C000
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#define SPIBAR 0x3800
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#endif // _PCH_PRESERVED_RESOURCES_H_
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