/** @file
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Build time limits of PCH resources.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_LIMITS_H_
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#define _PCH_LIMITS_H_
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//
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// PCIe limits
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//
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#define PCH_MAX_PCIE_ROOT_PORTS PCH_H_PCIE_MAX_ROOT_PORTS
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#define PCH_H_PCIE_MAX_ROOT_PORTS 20
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#define PCH_LP_PCIE_MAX_ROOT_PORTS 12
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#define PCH_MAX_PCIE_CONTROLLERS PCH_H_PCIE_MAX_CONTROLLERS
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#define PCH_PCIE_CONTROLLER_PORTS 4
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#define PCH_H_PCIE_MAX_CONTROLLERS (PCH_H_PCIE_MAX_ROOT_PORTS / PCH_PCIE_CONTROLLER_PORTS)
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#define PCH_LP_PCIE_MAX_CONTROLLERS (PCH_LP_PCIE_MAX_ROOT_PORTS / PCH_PCIE_CONTROLLER_PORTS)
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//
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// PCIe clocks limits
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//
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#define PCH_LP_PCIE_MAX_CLK_REQ 6
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#define PCH_H_PCIE_MAX_CLK_REQ 16
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//
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// RST PCIe Storage Cycle Router limits
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//
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#define PCH_MAX_RST_PCIE_STORAGE_CR 3
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//
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// SATA limits
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//
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#define PCH_MAX_SATA_PORTS PCH_H_AHCI_MAX_PORTS
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#define PCH_H_AHCI_MAX_PORTS 8 ///< Max number of sata ports in SKL PCH H
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#define PCH_LP_AHCI_MAX_PORTS 3 ///< Max number of sata ports in SKL PCH LP
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#define PCH_SATA_MAX_DEVICES_PER_PORT 1 ///< Max support device numner per port, Port Multiplier is not support.
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//
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// USB limits
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//
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#define PCH_MAX_USB2_PORTS PCH_H_XHCI_MAX_USB2_PORTS
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#define PCH_H_XHCI_MAX_USB2_PHYSICAL_PORTS 14 ///< Max Physical Connector XHCI, not counting virtual ports like USB-R.
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#define PCH_LP_XHCI_MAX_USB2_PHYSICAL_PORTS 10 ///< Max Physical Connector XHCI, not counting virtual ports like USB-R.
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#define PCH_H_XHCI_MAX_USB2_PORTS 16 ///< 14 High Speed lanes + Including two ports reserved for USBr
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#define PCH_LP_XHCI_MAX_USB2_PORTS 12 ///< 10 High Speed lanes + Including two ports reserved for USBr
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#define PCH_MAX_USB3_PORTS PCH_H_XHCI_MAX_USB3_PORTS
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#define PCH_H_XHCI_MAX_USB3_PORTS 10 ///< 10 Super Speed lanes
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#define PCH_LP_XHCI_MAX_USB3_PORTS 6 ///< 6 Super Speed lanes
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#define PCH_XHCI_MAX_SSIC_PORT_COUNT 2 ///< 2 SSIC ports in SKL PCH-LP and SKL PCH-H
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//
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// SerialIo limits
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//
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#define PCH_SERIALIO_MAX_CONTROLLERS 11 ///< Number of SerialIo controllers, this includes I2C, SPI and UART
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#define PCH_SERIALIO_MAX_I2C_CONTROLLERS 6 ///< Number of SerialIo I2C controllers
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#define PCH_LP_SERIALIO_MAX_I2C_CONTROLLERS 6 ///< Number of SerialIo I2C controllers for PCH-LP
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#define PCH_H_SERIALIO_MAX_I2C_CONTROLLERS 4 ///< Number of SerialIo I2C controllers for PCH-H
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#define PCH_SERIALIO_MAX_SPI_CONTROLLERS 2 ///< Number of SerialIo SPI controllers
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#define PCH_SERIALIO_MAX_UART_CONTROLLERS 3 ///< Number of SerialIo UART controllers
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//
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// ISH limits
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//
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#define PCH_ISH_MAX_GP_PINS 8
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#define PCH_ISH_MAX_UART_CONTROLLERS 2
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#define PCH_ISH_MAX_I2C_CONTROLLERS 3
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#define PCH_ISH_MAX_SPI_CONTROLLERS 1
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//
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// SCS limits
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//
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#define PCH_SCS_MAX_CONTROLLERS 3 ///< Number of Storage and Communication Subsystem controllers, this includes eMMC, SDIO, SDCARD
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//
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// Flash Protection Range Register
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//
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#define PCH_FLASH_PROTECTED_RANGES 5
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//
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// Number of eSPI slaves
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//
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#define PCH_ESPI_MAX_SLAVE_ID 2
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#endif // _PCH_LIMITS_H_
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