/** @file
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*
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* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
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* Copyright (c) 2015, Linaro Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#ifndef _I2C_HW_H_
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#define _I2C_HW_H_
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#include <Uefi.h>
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#include <Library/IoLib.h>
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// The HNS I2C port 5 is under I2C extender
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#define I2C_EXTENDER_PORT_HNS 5
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#define I2C_READ_TIMEOUT 500
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#define I2C_DRV_ONCE_WRITE_BYTES_NUM 8
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#define I2C_DRV_ONCE_READ_BYTES_NUM 8
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#define I2C_READ_SIGNAL 0x0100
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#define I2C_TXRX_THRESHOLD 0x7
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#define I2C_SS_SCLHCNT 0x493
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#define I2C_SS_SCLLCNT 0x4fe
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#define I2C_CMD_STOP_BIT BIT9
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#define I2C_REG_WRITE(reg,data) \
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MmioWrite32 ((reg), (data))
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#define I2C_REG_READ(reg,result) \
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(result) = MmioRead32 ((reg))
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#define I2C_CON_OFFSET 0x0
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#define I2C_TAR_OFFSET 0x4
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#define I2C_SAR_OFFSET 0x8
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#define I2C_DATA_CMD_OFFSET 0x10
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#define I2C_SS_SCL_HCNT_OFFSET 0x14
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#define I2C_SS_SCL_LCNT_OFFSET 0x18
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#define I2C_FS_SCL_HCNT_OFFSET 0x1c
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#define I2C_FS_SCL_LCNT_OFFSET 0x20
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#define I2C_INTR_STAT_OFFSET 0x2c
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#define I2C_INTR_MASK_OFFSET 0x30
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#define I2C_RAW_INTR_STAT_OFFSET 0x34
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#define I2C_RX_TL_OFFSET 0x38
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#define I2C_TX_TL_OFFSET 0x3c
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#define I2C_CLR_INTR_OFFSET 0x40
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#define I2C_CLR_RX_UNDER_OFFSET 0x44
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#define I2C_CLR_RX_OVER_OFFSET 0x48
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#define I2C_CLR_TX_OVER_OFFSET 0x4c
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#define I2C_CLR_RD_REQ_OFFSET 0x50
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#define I2C_CLR_TX_ABRT_OFFSET 0x54
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#define I2C_CLR_RX_DONE_OFFSET 0x58
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#define I2C_CLR_ACTIVITY_OFFSET 0x5c
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#define I2C_CLR_STOP_DET_OFFSET 0x60
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#define I2C_CLR_START_DET_OFFSET 0x64
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#define I2C_CLR_GEN_CALL_OFFSET 0x68
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#define I2C_ENABLE_OFFSET 0x6c
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#define I2C_STATUS_OFFSET 0x70
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#define I2C_TXFLR_OFFSET 0x74
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#define I2C_RXFLR_OFFSET 0x78
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#define I2C_SDA_HOLD 0x7c
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#define I2C_TX_ABRT_SOURCE_OFFSET 0x80
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#define I2C_SLV_DATA_ONLY_OFFSET 0x84
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#define I2C_DMA_CR_OFFSET 0x88
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#define I2C_DMA_TDLR_OFFSET 0x8c
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#define I2C_DMA_RDLR_OFFSET 0x90
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#define I2C_SDA_SETUP_OFFSET 0x94
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#define I2C_ACK_GENERAL_CALL_OFFSET 0x98
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#define I2C_ENABLE_STATUS_OFFSET 0x9c
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typedef union tagI2c0Con
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{
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struct
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{
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UINT32 master : 1 ;
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UINT32 Speed : 2 ;
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UINT32 slave_10bit : 1 ;
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UINT32 master_10bit : 1 ;
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UINT32 restart_en : 1 ;
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UINT32 slave_disable : 1 ;
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UINT32 Reserved_0 : 25 ;
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} bits;
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UINT32 Val32;
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} I2C0_CON_U;
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typedef union tagI2c0Tar
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{
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struct
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{
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UINT32 ic_tar : 10 ;
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UINT32 gc_or_start : 1 ;
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UINT32 special : 1 ;
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UINT32 ic_10bitaddr_master : 1 ;
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UINT32 Reserved_1 : 19 ;
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} bits;
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UINT32 Val32;
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} I2C0_TAR_U;
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typedef union tagI2c0DataCmd
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{
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struct
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{
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UINT32 dat : 8 ;
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UINT32 cmd : 1 ;
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UINT32 Reserved_5 : 23 ;
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} bits;
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UINT32 Val32;
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} I2C0_DATA_CMD_U;
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typedef union tagI2c0SsSclHcnt
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{
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struct
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{
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UINT32 ic_ss_scl_hcnt : 16 ;
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UINT32 Reserved_7 : 16 ;
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} bits;
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UINT32 Val32;
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} I2C0_SS_SCL_HCNT_U;
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typedef union tagI2c0SsSclLcnt
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{
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struct
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{
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UINT32 ic_ss_scl_lcnt : 16 ;
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UINT32 Reserved_9 : 16 ;
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} bits;
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UINT32 Val32;
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} I2C0_SS_SCL_LCNT_U;
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typedef union tagI2c0FsSclHcnt
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{
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struct
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{
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UINT32 ic_fs_scl_hcnt : 16 ;
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UINT32 Reserved_11 : 16 ;
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} bits;
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UINT32 Val32;
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} I2C0_FS_SCL_HCNT_U;
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typedef union tagI2c0FsSclLcnt
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{
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struct
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{
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UINT32 ic_fs_scl_lcnt : 16 ;
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UINT32 Reserved_13 : 16 ;
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} bits;
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UINT32 Val32;
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} I2C0_FS_SCL_LCNT_U;
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typedef union tagI2c0IntrMask
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{
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struct
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{
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UINT32 m_rx_under : 1 ;
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UINT32 m_rx_over : 1 ;
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UINT32 m_rx_full : 1 ;
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UINT32 m_tx_over : 1 ;
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UINT32 m_tx_empty : 1 ;
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UINT32 m_rd_req : 1 ;
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UINT32 m_tx_abrt : 1 ;
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UINT32 m_rx_done : 1 ;
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UINT32 m_activity : 1 ;
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UINT32 m_stop_det : 1 ;
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UINT32 m_start_det : 1 ;
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UINT32 m_gen_call : 1 ;
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UINT32 Reserved_17 : 20 ;
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} bits;
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UINT32 Val32;
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} I2C0_INTR_MASK_U;
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typedef union tagI2c0RxTl
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{
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struct
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{
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UINT32 rx_tl : 8 ;
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UINT32 Reserved_21 : 24 ;
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} bits;
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UINT32 Val32;
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} I2C0_RX_TL_U;
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typedef union tagI2c0TxTl
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{
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struct
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{
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UINT32 tx_tl : 8 ;
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UINT32 Reserved_23 : 24 ;
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} bits;
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UINT32 Val32;
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} I2C0_TX_TL_U;
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typedef union tagI2c0Enable
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{
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struct
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{
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UINT32 enable : 1 ;
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UINT32 Reserved_47 : 31 ;
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} bits;
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UINT32 Val32;
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} I2C0_ENABLE_U;
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typedef union tagI2c0Status
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{
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struct
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{
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UINT32 activity : 1 ;
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UINT32 tfnf : 1 ;
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UINT32 tfe : 1 ;
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UINT32 rfne : 1 ;
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UINT32 rff : 1 ;
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UINT32 mst_activity : 1 ;
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UINT32 slv_activity : 1 ;
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UINT32 Reserved_49 : 25 ;
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} bits;
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UINT32 Val32;
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} I2C0_STATUS_U;
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typedef union tagI2c0Txflr
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{
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struct
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{
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UINT32 txflr : 4 ;
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UINT32 Reserved_51 : 28 ;
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} bits;
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UINT32 Val32;
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} I2C0_TXFLR_U;
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typedef union tagI2c0Rxflr
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{
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struct
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{
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UINT32 rxflr : 4 ;
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UINT32 Reserved_53 : 28 ;
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} bits;
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UINT32 Val32;
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} I2C0_RXFLR_U;
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typedef union tagI2c0EnableStatus
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{
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struct
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{
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UINT32 ic_en : 1 ;
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UINT32 slv_disable_while_busy: 1 ;
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UINT32 slv_rx_data_lost : 1 ;
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UINT32 Reserved_69 : 29 ;
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} bits;
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UINT32 Val32;
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} I2C0_ENABLE_STATUS_U;
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typedef enum {
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I2CTx,
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I2CRx
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} I2CTransfer;
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#endif
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