/** @file
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*
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* Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved.
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* Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#ifndef _OEM_CONFIG_DATA_H_
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#define _OEM_CONFIG_DATA_H_
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#define PCIE_MAX_TOTAL_PORTS 16
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#define OEM_CONFIG_NAME L"OemConfig"
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#define PLATFORM_SETUP_VARIABLE_FLAG (EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE)
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#pragma pack(1)
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typedef struct {
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/*Memory Config*/
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UINT8 DdrDebugLevel;
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UINT8 DdrFreqLimit;
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UINT8 DdrRefreshSupport;
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UINT8 DdrRefreshRate;
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UINT8 RankMargin;
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UINT8 RankMarginMode;
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UINT32 rmtPatternLength;
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UINT8 perbitmargin;
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UINT8 CaMargin;
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UINT8 CaVrefMarginOption;
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UINT8 NumaEn;
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UINT8 HwMemTest;
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UINT8 DieInterleaving;
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UINT8 ChannelInterleaving;
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UINT8 RankInterleaving;
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UINT8 EccSupport;
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/*iBMC Config*/
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UINT8 BmcWdtEnable;
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UINT8 BmcWdtTimeout;
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UINT8 BmcWdtAction;
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UINT8 OSWdtEnable;
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UINT8 OSWdtTimeout;
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UINT8 OSWdtAction;
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/*PCIe Config*/
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UINT8 PcieSRIOVSupport;
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UINT8 PciePort[PCIE_MAX_TOTAL_PORTS];
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UINT8 PcieLinkSpeedPort[PCIE_MAX_TOTAL_PORTS];
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UINT8 PcieLinkDeEmphasisPort[PCIE_MAX_TOTAL_PORTS];
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UINT8 PcieLinkStatusPort[PCIE_MAX_TOTAL_PORTS];
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UINT8 PcieLinkSpeedRateStatusPort[PCIE_MAX_TOTAL_PORTS];
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UINT8 PcieLinkMaxPort[PCIE_MAX_TOTAL_PORTS];
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UINT8 PcieMaxPayloadSizePort[PCIE_MAX_TOTAL_PORTS];
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UINT8 PcieAspmPort[PCIE_MAX_TOTAL_PORTS];
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/*Misc Config*/
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UINT8 EnableSmmu;
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UINT8 EnableFdtTable;
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UINT8 EnableGOP;
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/*RAS Config*/
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UINT8 EnRasSupport;
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UINT8 EnPoison;
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UINT8 CheckAlgorithm;
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UINT8 PatrolScrub;
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UINT8 PatrolScrubDuration;
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UINT8 DemandScrubMode;
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UINT8 CorrectErrorThreshold;
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UINT8 AdvanceDeviceCorrection;
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UINT8 RankSparing;
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UINT8 FunnelPeriod;
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UINT8 DpcFeature;
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UINT8 EcrcFeature;
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UINT8 CompletionTimeout;
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UINT8 CompletionTimeoutValue;
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UINT8 HotPlug;
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} OEM_CONFIG_DATA;
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#pragma pack()
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#endif
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