/** @file
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*
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* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
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* Copyright (c) 2015, Linaro Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#ifndef _HW_MEM_INIT_LIB_H_
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#define _HW_MEM_INIT_LIB_H_
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#include <PlatformArch.h>
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#define I2C_CHANNEL 2
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#define MAX_I2C_DEV 6
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#define SPD_MODULE_PART 18
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#define SPD_MODULE_PART_DDR4 20
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#define NVRAM_ADDR 0x00D00000
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typedef enum {
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DDR_FREQ_AUTO = 0,
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DDR_FREQ_800,
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DDR_FREQ_1000,
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DDR_FREQ_1066,
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DDR_FREQ_1200,
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DDR_FREQ_1333,
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DDR_FREQ_1400,
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DDR_FREQ_1600,
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DDR_FREQ_1800,
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DDR_FREQ_1866,
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DDR_FREQ_2000,
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DDR_FREQ_2133,
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DDR_FREQ_2200,
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DDR_FREQ_2400,
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DDR_FREQ_2600,
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DDR_FREQ_2666,
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DDR_FREQ_2800,
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DDR_FREQ_2933,
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DDR_FREQ_3000,
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DDR_FREQ_3200,
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DDR_FREQ_MAX
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} DDR_FREQUENCY_INDEX;
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struct baseMargin {
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INT16 n;
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INT16 p;
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};
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struct rankMargin {
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struct baseMargin rank[MAX_CHANNEL][MAX_RANK_CH];
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};
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typedef struct _NVRAM_RANK_DATA {
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UINT16 MR0;
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UINT16 MR1;
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UINT16 MR2;
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UINT16 MR3;
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UINT16 MR4;
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UINT16 MR5;
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UINT16 MR6[9];
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} NVRAM_RANK_DATA;
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typedef struct _NVRAM_DIMM_DATA {
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NVRAM_RANK_DATA Rank[MAX_RANK_DIMM];
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} NVRAM_DIMM_DATA;
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typedef struct _NVRAM_CHANNEL_DATA {
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NVRAM_DIMM_DATA Dimm[MAX_DIMM];
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UINT32 DDRC_CFG_ECC;
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UINT32 DDRC_CFG_WORKMODE;
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UINT32 DDRC_CFG_WORKMODE1;
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UINT32 DDRC_CFG_WORKMODE2;
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UINT32 DDRC_CFG_DDRMODE;
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UINT32 DDRC_CFG_DIMM;
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UINT32 DDRC_CFG_RNKVOL_0;
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UINT32 DDRC_CFG_RNKVOL_1;
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UINT32 DDRC_CFG_RNKVOL_2;
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UINT32 DDRC_CFG_RNKVOL_3;
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UINT32 DDRC_CFG_RNKVOL_4;
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UINT32 DDRC_CFG_RNKVOL_5;
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UINT32 DDRC_CFG_RNKVOL_6;
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UINT32 DDRC_CFG_RNKVOL_7;
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UINT32 DDRC_CFG_RNKVOL_8;
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UINT32 DDRC_CFG_RNKVOL_9;
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UINT32 DDRC_CFG_RNKVOL_10;
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UINT32 DDRC_CFG_RNKVOL_11;
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UINT32 DDRC_CFG_ODT_0;
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UINT32 DDRC_CFG_ODT_1;
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UINT32 DDRC_CFG_ODT_2;
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UINT32 DDRC_CFG_ODT_3;
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UINT32 DDRC_CFG_ODT_4;
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UINT32 DDRC_CFG_ODT_5;
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UINT32 DDRC_CFG_ODT_6;
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UINT32 DDRC_CFG_ODT_7;
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UINT32 DDRC_CFG_ODT_8;
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UINT32 DDRC_CFG_ODT_9;
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UINT32 DDRC_CFG_ODT_10;
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UINT32 DDRC_CFG_ODT_11;
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UINT32 DDRC_CFG_TIMING0;
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UINT32 DDRC_CFG_TIMING1;
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UINT32 DDRC_CFG_TIMING2;
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UINT32 DDRC_CFG_TIMING3;
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UINT32 DDRC_CFG_TIMING4;
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UINT32 DDRC_CFG_TIMING5;
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UINT32 DDRC_CFG_TIMING6;
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UINT32 DDRC_CFG_TIMING7;
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UINT32 DDRC_CFG_DFI_LAT0;
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UINT32 DDRC_CFG_DFI_LAT1;
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UINT32 DDRC_CFG_DDRPHY;
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UINT32 Config[24];
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BOOLEAN Status;
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} NVRAM_CHANNEL_DATA;
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typedef struct _NVRAM_DATA {
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UINT32 NvramCrc;
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NVRAM_CHANNEL_DATA Channel[MAX_SOCKET][MAX_CHANNEL];
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UINT32 DdrFreqIdx;
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} NVRAM_DATA;
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struct DDR_RANK_DATA {
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BOOLEAN Enabled;
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};
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typedef struct _DDR_DIMM_DATA {
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BOOLEAN Enabled;
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UINT8 DramType; //Byte 2
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UINT8 ModuleType; //Byte 3
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UINT8 BankNum; //Byte 4
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UINT8 RowBits; //Byte 5
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UINT8 ColBits; //Byte 5
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UINT8 SpdVdd; //Byte 6
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UINT8 RankNum; //Byte 7
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UINT8 PrimaryBusWidth; //Byte 8
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UINT8 ExtensionBusWidth; //Byte 8
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UINT8 SpdModPart[SPD_MODULE_PART]; // Module Part Number
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UINT8 SpdModPartDDR4[SPD_MODULE_PART_DDR4]; // Module Part Number DDR4
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UINT16 SpdMMfgId; // Module Mfg Id from SPD
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UINT32 SpdSerialNum;
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UINT32 RankSize;
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UINT16 DimmSize;
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UINT16 DimmSpeed;
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UINT16 SpdMMDate;
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struct DDR_RANK_DATA Rank[MAX_RANK_DIMM];
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} DDR_DIMM_DATA;
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typedef struct _DDR_CHANNEL_DATA {
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BOOLEAN Enabled;
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DDR_DIMM_DATA Dimm[MAX_DIMM];
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UINT8 CurrentDimmNum;
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} DDR_CHANNEL_DATA;
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typedef struct _MEMORY_DATA {
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UINT8 RascBypass;
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} MEMORY_DATA;
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typedef struct _NUMAINFO_DATA {
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UINT8 NodeId;
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UINT64 Base;
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UINT64 Length;
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UINT32 ScclInterleaveEn;
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} NUMAINFO_DATA;
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typedef struct _GBL_DATA_INTERFACE {
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DDR_CHANNEL_DATA Channel[MAX_SOCKET][MAX_CHANNEL];
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UINT32 DdrFreqIdx;
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UINT32 Freq;
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UINT32 EccEn;
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UINT32 MemSize;
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BOOLEAN SetupExist;
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NVRAM_DATA NvRamData;
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MEMORY_DATA MemData;
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NUMAINFO_DATA NumaInfo[MAX_SOCKET][MAX_NUM_PER_TYPE];
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} GBL_INTERFACE;
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typedef union {
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struct {
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UINT16 freqIndex:4; //Frequency Index;
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UINT16 slot0:4; //Channel slot0 for DIMM
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UINT16 slot1:4; //Channel slot1 for DIMM
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UINT16 slot2:4; //Channel slot2 for DIMM
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}Bits;
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UINT16 Data;
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}ODT_VALUE_INDEX;
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typedef union {
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struct {
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UINT8 RTTNom:3;
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UINT8 reserved_3:1;
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UINT8 RTTWr:2;
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UINT8 reserved_6:2;
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}Bits;
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UINT8 Data;
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}ODT_RTT_VALUE_DDR3;
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typedef union {
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struct {
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UINT8 RTTNom:3;
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UINT8 RTTPark:3;
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UINT8 RTTWr:2;
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}Bits;
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UINT8 Data;
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}ODT_RTT_VALUE_DDR4;
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typedef union {
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struct {
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UINT16 tarDimm:2; // target DIMM
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UINT16 tarRank:2; // target Rank
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UINT16 slot0:4; // Channel slot0 for DIMM
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UINT16 slot1:4; // Channel slot1 for DIMM
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UINT16 slot2:4; // Channel slot2 for DIMM
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}Bits;
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UINT16 Data;
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}ODT_ACTIVE_INDEX;
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struct ODT_VALUE_STRUCT_DDR3 {
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UINT16 config; // ODT_VALUE_INDEX
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UINT8 dramOdt[MAX_DIMM][MAX_RANK_DIMM]; // ODT_VALUE_RTT_DDR3
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};
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struct ODT_VALUE_STRUCT_DDR4 {
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UINT16 config;
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UINT8 dramOdt[MAX_DIMM][MAX_RANK_DIMM];
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};
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struct ODT_ACTIVE_STRUCT {
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UINT16 config; // ODT config index
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UINT16 actBits[2]; // WR :Bits[3;0] = D0_R[3:0] Bits[7:4] = D1_R[3:0] Bits[11:8] = D2_R[3:0]
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};
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// JEDEC manufacturer IDs from JEP-106
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#define MFGID_AENEON 0x5705
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#define MFGID_QIMONDA 0x5105
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#define MFGID_NEC 0x1000
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#define MFGID_IDT 0xB300
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#define MFGID_TI 0x9700
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#define MFGID_HYNIX 0xAD00
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#define MFGID_MICRON 0x2C00
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#define MFGID_INFINEON 0xC100
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#define MFGID_SAMSUNG 0xCE00
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#define MFGID_TEK 0x3D00
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#define MFGID_KINGSTON 0x9801
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#define MFGID_ELPIDA 0xFE02
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#define MFGID_SMART 0x9401
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#define MFGID_AGILENT 0xC802
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#define MFGID_NANYA 0x0B03
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#define MFGID_INPHI 0xB304
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#define MFGID_MONTAGE 0x3206
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#define MFGID_RAMAXEL 0x4304
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//
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// DDR3 frequencies 800 - 2667
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// DDR4 frequencies 1333 - 3200
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//
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#define DDR_800 0 // tCK(ns)=2.5
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#define DDR_1000 1 // tCK(ns)=2.0
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#define DDR_1066 2 // tCK(ns)=1.875
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#define DDR_1200 3 // tCK(ns)=1.667
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#define DDR_1333 4 // tCK(ns)=1.5
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#define DDR_1400 5 // tCK(ns)=1.429
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#define DDR_1600 6 // tCK(ns)=1.25
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#define DDR_1800 7 // tCK(ns)=1.11
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#define DDR_1866 8 // tCK(ns)=1.07
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#define DDR_2000 9 // tCK(ns)=1.0
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#define DDR_2133 10 // tCK(ns)=0.9375
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#define DDR_2200 11 // tCK(ns)=0.909
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#define DDR_2400 12 // tCK(ns)=0.833
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#define DDR_2600 13 // tCK(ns)=0.769
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#define DDR_2666 14 // tCK(ns)=0.750
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#define DDR_2800 15 // tCK(ns)=0.714
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#define DDR_2933 16 // tCK(ns)=0.682
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#define DDR_3000 17 // tCK(ns)=0.667
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#define DDR_3200 18 // tCK(ns)=0.625
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#define DDR_MAX (DDR_3200)
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#define FREQUENCY_MTB_OFFSET 1000000
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#define FREQUENCY_FTB_OFFSET 1000
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//
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#define DDR_800_TCK_MIN 25000
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#define DDR_1000_TCK_MIN 20000
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#define DDR_1067_TCK_MIN 18750
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#define DDR_1200_TCK_MIN 16670
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#define DDR_1333_TCK_MIN 15000
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#define DDR_1400_TCK_MIN 14290
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#define DDR_1600_TCK_MIN 12500
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#define DDR_1800_TCK_MIN 11100
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#define DDR_1867_TCK_MIN 10710
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#define DDR_2000_TCK_MIN 10000
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#define DDR_2133_TCK_MIN 9380
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#define DDR_2200_TCK_MIN 9090
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#define DDR_2400_TCK_MIN 8330
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#define DDR_2600_TCK_MIN 7690
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#define DDR_2667_TCK_MIN 7500
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#define DDR_2800_TCK_MIN 7140
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#define DDR_2933_TCK_MIN 6820
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#define DDR_3000_TCK_MIN 6670
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#define DDR_3200_TCK_MIN 6250
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//
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// Serial Presence Detect bytes (JEDEC revision 1.0)
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//
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#define SPD_SIZE 0 // Bytes used, Device size, CRC coverage
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#define SPD_REVISION 1 // SPD Encoding Revision
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#define SPD_KEY_BYTE 2 // DRAM Device Type
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#define SPD_TYPE_DDR3 0x0B // DDR3 SDRAM
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#define SPD_TYPE_DDR4 0x0C // DDR4 SDRAM
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#define SPD_KEY_BYTE2 3 // Module Type and Thickness (RDIMM or UDIMM)
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#define SPD_RDIMM 1 // Module type is RDIMM
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#define SPD_UDIMM 2 // Module type is UDIMM
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#define SPD_SODIMM 3 // Module type is SODIMM
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#define SPD_MICRO_DIMM 4 // Module type is Micro-DIMM
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#define SPD_LRDIMM_DDR4 4 // Module type is LRDIMM (DDR4)
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#define SPD_MINI_RDIMM 5 // Module type is Mini-RDIMM
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#define SPD_MINI_UDIMM 6 // Module type is Mini-UDIMM
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#define SPD_MINI_CDIMM 7 // Module type is Mini-CDIMM
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#define SPD_ECC_SO_UDIMM 9 // Module type is 72b-SO-UDIMM
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#define SPD_ECC_SO_RDIMM 8 // Module type is 72b-SO-RDIMM
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#define SPD_ECC_SO_CDIMM 10 // Module type is 72b-SO-CDIMM
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#define SPD_LRDIMM 11 // Module type is LRDIMM
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#define SPD_UDIMM_ECC 18 // Module type is UDIMM-ECC
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#define SPD_SDRAM_BANKS 4 // SDRAM Density and number of internal banks
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#define SPD_1Gb 2 // Total SDRAM Capacity 1 Gigabits
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#define SPD_2Gb 3 // Total SDRAM Capacity 2 Gigabits
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#define SPD_4Gb 4 // Total SDRAM Capacity 4 Gigabits
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#define SPD_8Gb 5 // Total SDRAM Capacity 8 Gigabits
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#define SPD_16Gb 6 // Total SDRAM Capacity 16 Gigabits
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#define SPD_32Gb 7 // Total SDRAM Capacity 32 Gigabits
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#define SPD_SDRAM_ADDR 5 // Number of Row and Column address bits
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#define SPD_ROW_12 0 // 12 row bits
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#define SPD_ROW_13 1 // 13 row bits
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#define SPD_ROW_14 2 // 14 row bits
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#define SPD_ROW_15 3 // 15 row bits
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#define SPD_ROW_16 4 // 16 row bits
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#define SPD_ROW_17 5 // 17 row bits
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#define SPD_ROW_18 6 // 18 row bits
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#define SPD_COL_9 0 // 9 colum bits
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#define SPD_COL_10 1 // 10 colum bits
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#define SPD_COL_11 2 // 11 colum bits
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#define SPD_COL_12 3 // 12 colum bits
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#define SPD_VDD_SUPPORT 6 // Vdd DIMM supports
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#define SPD_VDD_150 0 // Module Supports 1.50V
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#define SPD_VDD_135 BIT1 // Module Supports 1.35V
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#define SPD_VDD_125 BIT2 // Module Supports 1.25V
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#define SPD_MODULE_ORG_DDR3 7 // Number of Ranks and SDRAM device width
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#define SPD_MODULE_ORG_DDR4 12 // DDR4 Module Organization
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#define DEVICE_WIDTH_X4 0 // SDRAM device width = 4 bits
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#define DEVICE_WIDTH_X8 1 // SDRAM device width = 8 bits
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#define DEVICE_WIDTH_X16 2 // SDRAM device width = 16 bits
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#define SPD_NUM_RANKS_1 0
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#define SPD_NUM_RANKS_2 1
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#define SPD_NUM_RANKS_4 3
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#define SPD_NUM_RANKS_8 4
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#define SPD_MEM_BUS_WID 8 // Width of SDRAM memory bus
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#define SPD_FTB 9 // Timebase for fine grain timing calculations
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#define SPD_MTB_DIVEND 10 // Medium Time Base Dividend
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#define SPD_MTB_DIVISOR 11 // Medium Time Base Divisor
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#define SPD_MIN_TCK 12 // Minimum cycle time (at max CL)
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#define SPD_TCKMIN_800 20 // tCK(MTB)=20, tCK(ns)=2.5
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#define SPD_TCKMIN_1067 15 // tCK(MTB)=15, tCK(ns)=1.875
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#define SPD_TCKMIN_1333 12 // tCK(MTB)=12, tCK(ns)=1.5
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#define SPD_TCKMIN_1600 10 // tCK(MTB)=10, tCK(ns)=1.25
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#define SPD_TCKMIN_1867 9 // tCK(MTB)=9, tCK(ns)=1.07
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#define SPD_TCKMIN_2133 8 // tCK(MTB)=8, tCK(ns)=0.9375
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#define SPD_TCKMIN_2400 7 // tCK(MTB)=7, tCK(ns)=.833
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#define SPD_CAS_LT_SUP_LSB 14 // CAS Latencies Supported, Least Significant Byte
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#define SPD_CAS_LT_SUP_MSB 15 // CAS Latencies Supported, Most Significant Byte
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#define SPD_MIN_TAA 16 // Minimum CAS Latency Time (tAAmin)
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#define SPD_MIN_TWR 17 // Minimum Write Recovery Time
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#define SPD_MIN_TRCD 18 // Minimum RAS to CAS delay
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#define SPD_MIN_TRRD 19 // Minimum Row active to row active delay
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#define SPD_MIN_TRP 20 // Minimum Row Precharge time
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#define SPD_EXT_TRC_TRAS 21 // Upper nibbles for min tRAS and tRC
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#define SPD_MIN_TRAS 22 // Minimum Active to Precharge time
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#define SPD_MIN_TRC 23 // Minimum Active to Active/Refresh time
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#define SPD_MIN_TRFC_LSB 24 // Minimum Refresh Recovery time least-significant byte
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#define SPD_MIN_TRFC_MSB 25 // Minimum Refresh Recovery time most-significant byte
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#define SPD_MIN_TWTR 26 // Minimum Internal Write to Read command delay
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#define SPD_MIN_TRTP 27 // Minimum Internal Read to Precharge command delay
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#define SPD_UN_TFAW 28 // Upper Nibble for tFAW
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#define SPD_MIN_TFAW 29 // Minimum Four Activate Window Delay Time (tFAWmin)
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#define SPD_OD_SUP 30 // SDRAM Output Drivers Supported
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#define SPD_RFSH_OPT 31 // SDRAM Refresh Options
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#define ETR BIT0 // Bit location for Extended Temp Range
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#define ETRR BIT1 // Bit location for Extended Temp Refresh Rate
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#define ASR BIT2 // Bit location for Automatic Self Refresh
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#define ODTS BIT3 // Bit location for On-die Thermal Sensor
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#define SPD_DIMM_TS 32 // Module Temperature Sensor
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#define SPD_SDRAM_TYPE 33 // SDRAM device type
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#define SPD_FTB_TCK 34 // Fine Offset for SDRAM tCK
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#define SPD_FTB_TAA 35 // Fine Offset for SDRAM tAA
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#define SPD_FTB_TRCD 36 // Fine Offset for SDRAM tRCD
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#define SPD_FTB_TRP 37 // Fine Offset for SDRAM tRP
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#define SPD_FTB_TRC 38 // Fine Offset for SDRAM tRC
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#define SPD_OPT_FEAT 41 // SDRAM Optional Features
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#define SPD_PTRR BIT7 // Indicates if the DIMM is pTRR compliant
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// UDIMM specific bytes
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// Applicable when Module Type (key byte 3) = 2, 3, 4, 6, or 8
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#define SPD_ADDR_MAP_FECTD 63 // Address Mapping from Edge Connector to DRAM
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// RDIMM specific bytes
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// Applicable when Module Type (key byte 3) = 1, 5, or 9
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#define SPD_RDIMM_ATTR 63 // RDIMM module attributes
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#define SPD_DIMM_HS 64 // Module Heat Spreader Solution
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#define SPD_REG_VEN_LSB 65 // Register Vendor ID LSB
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#define SPD_REG_VEN_MSB 66 // Register Vendor ID MSB
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#define SPD_REG_REV 67 // Register Revision
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#define SPD_CNTL_0 69 // Register Control Word 0 & 1
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#define SPD_CNTL_1 70 // Register Control Word 2 & 3
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#define SPD_CNTL_2 71 // Register Control Word 4 & 5
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#define SPD_CNTL_3 72 // Register Control Word 6 & 7 (reserved)
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#define SPD_CNTL_4 73 // Register Control Word 8 & 9 (reserved)
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#define SPD_CNTL_5 74 // Register Control Word 10 & 11 (reserved)
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#define SPD_CNTL_6 75 // Register Control Word 12 & 13 (reserved)
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#define SPD_CNTL_7 76 // Register Control Word 14 & 15 (reserved)
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// LRDIMM specific bytes
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// Applicable when Module Type (key byte 3) = 0xB
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// Based on DDR3 SPD 1.0 Document Release 2.1 draft, dated May 27, 2011
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#define SPD_LRDIMM_ATTR 63 // LRDIMM module attributes
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#define SPD_LRBUF_REV 64 // LR Buffer Revision
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#define SPD_LRBUF_VEN_LSB 65 // LR Buffer Vendor ID LSB
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#define SPD_LRBUF_VEN_MSB 66 // LR Buffer Vendor ID MSB
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#define SPD_LR_F0_RC2_3 67 // LR Buffer Function 0, Control Word 2 & 3
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#define SPD_LR_F0_RC4_5 68 // LR Buffer Function 0, Control Word 4 & 5
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#define SPD_LR_F1_RC8_11 69 // LR Buffer Function 1, Control Word 8 & 11
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#define SPD_LR_F1_RC12_13 70 // LR Buffer Function 1, Control Word 12 & 13
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#define SPD_LR_F1_RC14_15 71 // LR Buffer Function 1, Control Word 14 & 15
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// Speed bin 0 = 800 & 1066
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#define SPD_LR_SB0_MDQ_DS_ODT 72 // LR Buffer Function 3, Control Word 8 & 9
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#define SPD_LR_SB0_DR01_QODT_ACT 73 // LR Buffer Function 3 & 4, Control Word 10 & 11
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#define SPD_LR_SB0_DR23_QODT_ACT 74 // LR Buffer Function 5 & 6, Control Word 10 & 11
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#define SPD_LR_SB0_DR45_QODT_ACT 75 // LR Buffer Function 7 & 8, Control Word 10 & 11
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#define SPD_LR_SB0_DR67_QODT_ACT 76 // LR Buffer Function 9 & 10, Control Word 10 & 11
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#define SPD_LR_SB0_MR1_2_RTT 77 // LR Buffer SMBus offsets 0xC0 - 0xC7
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// Speed bin 1 = 1333 & 1600
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#define SPD_LR_SB1_MDQ_DS_ODT 78 // LR Buffer Function 3, Control Word 8 & 9
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#define SPD_LR_SB1_DR01_QODT_ACT 79 // LR Buffer Function 3 & 4, Control Word 10 & 11
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#define SPD_LR_SB1_DR23_QODT_ACT 80 // LR Buffer Function 5 & 6, Control Word 10 & 11
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#define SPD_LR_SB1_DR45_QODT_ACT 81 // LR Buffer Function 7 & 8, Control Word 10 & 11
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#define SPD_LR_SB1_DR67_QODT_ACT 82 // LR Buffer Function 9 & 10, Control Word 10 & 11
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#define SPD_LR_SB1_MR1_2_RTT 83 // LR Buffer SMBus offsets 0xC0 - 0xC7
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// Speed bin 2 = 1866 & 2133
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#define SPD_LR_SB2_MDQ_DS_ODT 84 // LR Buffer Function 3, Control Word 8 & 9
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#define SPD_LR_SB2_DR01_QODT_ACT 85 // LR Buffer Function 3 & 4, Control Word 10 & 11
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#define SPD_LR_SB2_DR23_QODT_ACT 86 // LR Buffer Function 5 & 6, Control Word 10 & 11
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#define SPD_LR_SB2_DR45_QODT_ACT 87 // LR Buffer Function 7 & 8, Control Word 10 & 11
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#define SPD_LR_SB2_DR67_QODT_ACT 88 // LR Buffer Function 9 & 10, Control Word 10 & 11
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#define SPD_LR_SB2_MR1_2_RTT 89 // LR Buffer SMBus offsets 0xC0 - 0xC7
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#define SPD_LR_150_MIN_MOD_DELAY 90 // LR DIMM minimum DQ Read propagation delay at 1.5V
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#define SPD_LR_150_MAX_MOD_DELAY 91 // LR DIMM maximum DQ Read propagation delay at 1.5V
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#define SPD_LR_135_MIN_MOD_DELAY 92 // LR DIMM minimum DQ Read propagation delay at 1.35V
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#define SPD_LR_135_MAX_MOD_DELAY 93 // LR DIMM maximum DQ Read propagation delay at 1.35V
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#define SPD_LR_12x_MIN_MOD_DELAY 94 // LR DIMM minimum DQ Read propagation delay at 1.2xV
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#define SPD_LR_12x_MAX_MOD_DELAY 95 // LR DIMM maximum DQ Read propagation delay at 1.2xV
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#define SPD_LR_PERS_BYTE_0 102 // LR DIMM Personality Byte
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#define SPD_LR_PERS_BYTE_1 103 // LR DIMM Personality Byte
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#define SPD_LR_PERS_BYTE_2 104 // LR DIMM Personality Byte
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#define SPD_LR_PERS_BYTE_3 105 // LR DIMM Personality Byte
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#define SPD_LR_PERS_BYTE_4 106 // LR DIMM Personality Byte
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#define SPD_LR_PERS_BYTE_5 107 // LR DIMM Personality Byte
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#define SPD_LR_PERS_BYTE_6 108 // LR DIMM Personality Byte
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#define SPD_LR_PERS_BYTE_7 109 // LR DIMM Personality Byte
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#define SPD_LR_PERS_BYTE_8 110 // LR DIMM Personality Byte
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#define SPD_LR_PERS_BYTE_9 111 // LR DIMM Personality Byte
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#define SPD_LR_PERS_BYTE_10 112 // LR DIMM Personality Byte
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#define SPD_LR_PERS_BYTE_11 113 // LR DIMM Personality Byte
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#define SPD_LR_PERS_BYTE_12 114 // LR DIMM Personality Byte
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#define SPD_LR_PERS_BYTE_13 115 // LR DIMM Personality Byte
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#define SPD_LR_PERS_BYTE_14 116 // LR DIMM Personality Byte
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#define SPD_LR_PERS_BYTES_TOTAL 15 // LR DIMM Total number of Personality Bytes
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// End module specific section
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#define SPD_MMID_LSB 117 // Module Manufacturer ID Code, Least Significant Byte
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#define SPD_MMID_MSB 118 // Module Manufacturer ID Code, Mostst Significant Byte
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#define SPD_MM_LOC 119 // Module Manufacturing Location
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#define SPD_MM_DATE 120 // Module Manufacturing Date 120-121
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#define SPD_MODULE_SN 122 // Module Serial Number 122-125
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#define SPD_CRC_LSB 126 // LSB of 16-bit CRC
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#define SPD_CRC_MSB 127 // MSB of 16-bit CRC
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#define SPD_MODULE_PN 128 // Module Part Number 128-145
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#define SPD_MODULE_RC 146 // Module Revision Code 146-147
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#define SPD_DRAM_MIDC_LSB 148 // DRAM Manufacturer ID Code, Least Significant Byte
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#define SPD_DRAM_MIDC_MSB 149 // DRAM Manufacturer ID Code, Most Significant Byte
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#ifdef MEM_NVDIMM_EN
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#define SPD_NVDIMM_ID_N 174 // If NVDIMM value will be 'N'
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#define SPD_NVDIMM_ID_V 175 // If NVDIMM value will be 'V'
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#endif //MEM_NVDIMM_EN
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#define SPD_BYTE_200 200 // Fixed value 0xBE
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//
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// DDR4 Specific Bytes
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//
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#define SPD_SDRAM_TYPE_DDR4 6 // SDRAM Device Type (DDR4)
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#define SPD_OPT_FEAT_DDR4 7 // SDRAM Optional Features (DDR4)
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#define SPD_MAC_MASK BIT0 | BIT1 | BIT2 // Mask for Maximum Active Count field
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#define SPD_TRR_IMMUNE BIT3 // Indicates this DIMM does not require DRAM Maintenance
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#define SPD_RFSH_OPT_DDR4 8 // SDRAM Refresh Options (DDR4)
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#define SPD_VDD_DDR4 11 // Vdd DIMM supports (DDR4)
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#define SPD_VDD_120 3 // Module operable and endurant 1.20V
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#define SPD_MODULE_ORG_DDR4 12 // Number of Ranks and SDRAM device width (DDR4)
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#define SPD_MEM_BUS_WID_DDR4 13 // Width of SDRAM memory bus
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#define SPD_DIMM_TS_DDR4 14 // Module Thermal Sensor
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#define SPD_TB_DDR4 17 // Timebase [3:2] MTB, [1:0] FTB
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#define SPD_MIN_TCK_DDR4 18 // Minimum cycle time
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#define SPD_TCKMIN_DDR4_1600 10 // tCK(MTB)=10, tCK(ns)=1.25
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#define SPD_TCKMIN_DDR4_1866 9 // tCK(MTB)=9, tCK(ns)=1.071
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#define SPD_TCKMIN_DDR4_2133 8 // tCK(MTB)=8, tCK(ns)=.938
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#define SPD_TCKMIN_DDR4_2400 7 // tCK(MTB)=7, tCK(ns)=.833
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#define SPD_MAX_TCK_DDR4 19 // Maximum cycle time
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#define SPD_CAS_LT_SUP_1_DDR4 20 // CAS Latencies Supported, first byte
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#define SPD_CAS_LT_SUP_2_DDR4 21 // CAS Latencies Supported, second byte
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#define SPD_CAS_LT_SUP_3_DDR4 22 // CAS Latencies Supported, third byte
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#define SPD_CAS_LT_SUP_4_DDR4 23 // CAS Latencies Supported, fourth byte
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#define SPD_MIN_TAA_DDR4 24 // Minimum CAS Latency Time (tAAmin)
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#define SPD_MIN_TRCD_DDR4 25 // Minimum RAS to CAS delay
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#define SPD_MIN_TRP_DDR4 26 // Minimum Row Precharge time
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#define SPD_EXT_TRC_TRAS_DDR4 27 // Upper nibbles for min tRAS and tRC
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#define SPD_MIN_TRAS_DDR4 28 // Minimum Active to Precharge time
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#define SPD_MIN_TRC_DDR4 29 // Minimum Active to Active/Refresh time
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#define SPD_MIN_TRFC1_LSB_DDR4 30 // Minimum Refresh Recovery time least-significant byte
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#define SPD_MIN_TRFC1_MSB_DDR4 31 // Minimum Refresh Recovery time most-significant byte
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#define SPD_MIN_TRFC2_LSB_DDR4 32 // Minimum Refresh Recovery time least-significant byte
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#define SPD_MIN_TRFC2_MSB_DDR4 33 // Minimum Refresh Recovery time most-significant byte
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#define SPD_MIN_TRFC3_LSB_DDR4 34 // Minimum Refresh Recovery time least-significant byte
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#define SPD_MIN_TRFC3_MSB_DDR4 35 // Minimum Refresh Recovery time most-significant byte
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#define SPD_TFAW_UPPER_DDR4 36 // Upper nibble for tFAW
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#define SPD_MIN_TFAW_DDR4 37 // Minimum For Active Window Delay Time (tFAW)
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#define SPD_MIN_TRRDS_DDR4 38 // Minimum Active to Active Delay Time tRRD_S Different Bank Group
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#define SPD_MIN_TRRDL_DDR4 39 // Minimum Active to Active Delay Time tRRD_L Same Bank Group
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#define SPD_MIN_TCCDL_DDR4 40 // Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group
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#define SPD_FTB_TCCDL_DDR4 117 // Fine offset for tCCD_L
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#define SPD_FTB_TRRDL_DDR4 118 // Fine offset for tRRD_L
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#define SPD_FTB_TRRDS_DDR4 119 // Fine offset for tRRD_S
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#define SPD_FTB_TRC_DDR4 120 // Fine offset for TRC
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#define SPD_FTB_TRP_DDR4 121 // Fine offset for TRP
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#define SPD_FTB_TRCD_DDR4 122 // Fine offset for TRCD
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#define SPD_FTB_TAA_DDR4 123 // Fine offset for TAA
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#define SPD_FTB_MAX_TCK_DDR4 124 // Fine offset for max TCK
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#define SPD_FTB_MIN_TCK_DDR4 125 // Fine offset for min TCK
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#define SPD_MIRROR_UNBUFFERED 131 // Unbuffered:Address Mapping from Edge Connector to DRAM
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#define SPD_MIRROR_REGISTERED 136 // Registered:Address Address Mapping from Register to DRAM
|
|
#define SPD_MMID_LSB_DDR4 320 // Module Manufacturer ID Code, Least Significant Byte
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#define SPD_MMID_MSB_DDR4 321 // Module Manufacturer ID Code, Most Significant Byte
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#define SPD_MM_LOC_DDR4 322 // Module Manufacturing Location
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#define SPD_MM_DATE_DDR4 323 // Module Manufacturing Date 323-324
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#define SPD_MODULE_SN_DDR4 325 // Module Serial Number 325-328
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#define SPD_MODULE_PN_DDR4 329 // Module Part Number 329-348
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#define SPD_MODULE_RC_DDR4 349 // Module Revision Code
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#define SPD_DRAM_MIDC_LSB_DDR4 350 // DRAM Manufacturer ID Code, Least Significant Byte
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#define SPD_DRAM_MIDC_MSB_DDR4 351 // DRAM Manufacturer ID Code, Most Significant Byte
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#define SPD_DRAM_REV_DDR4 352 // DRAM Revision ID
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#define SPD_CRC_LSB_DDR4 382 // LSB of 16-bit CRC
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#define SPD_CRC_MSB_DDR4 383 // MSB of 16-bit CRC
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// Begin DDR4 module specific section
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#define SPD_MODULE_NH_DDR4 128 // Module Nominal Height
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#define SPD_MODULE_MT_DDR4 129 // Module Maximum Thickness
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#define SPD_REF_RAW_CARD_DDR4 130 // Reference Raw Card Used
|
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// UDIMM specific bytes
|
// Applicable when Module Type (key byte 3) = 2
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#define SPD_ADDR_MAP_FECTD_DDR4 131 // Address Mapping from Edge Connector to DRAM
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|
// RDIMM specific bytes
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// Applicable when Module Type (key byte 3) = 1
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#define SPD_RDIMM_ATTR_DDR4 131 // RDIMM module attributes
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#define SPD_DIMM_HS_DDR4 132 // Module Heat Spreader Solution
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#define SPD_REG_VEN_LSB_DDR4 133 // Register Vendor ID LSB
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#define SPD_REG_VEN_MSB_DDR4 134 // Register Vendor ID MSB
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#define SPD_REG_REV_DDR4 135 // Register Revision
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#define SPD_ADD_MAPPING_DDR4 136 // Address mapping from Reg to DRAM
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#define SPD_REG_OD_CTL_DDR4 137 // Register Output Drive Strength for Control
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#define SPD_REG_OD_CK_DDR4 138 // Register Output Drive Strength for Clock
|
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// LRDIMM specific bytes
|
// Applicable when Module Type (key byte 3) = 0x4
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#define SPD_LRDIMM_ATTR_DDR4 131 // LRDIMM module attributes
|
#define SPD_LRBUF_HS_DDR4 132 // LR Buffer Heat Spreader Solution
|
#define SPD_LRBUF_VEN_LSB_DDR4 133 // LR Buffer Vendor ID LSB
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#define SPD_LRBUF_VEN_MSB_DDR4 134 // LR Buffer Vendor ID MSB
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#define SPD_LRBUF_REV_DDR4 135 // LR Buffer Register Revision
|
#define SPD_LRBUF_DB_REV_DDR4 139 // LR Buffer Data Buffer Revision
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#define SPD_LRBUF_DRAM_VREFDQ_R0_DDR4 140 // LR Buffer DRAM VrefDQ for Package Rank 0
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#define SPD_LRBUF_DRAM_VREFDQ_R1_DDR4 141 // LR Buffer DRAM VrefDQ for Package Rank 1
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#define SPD_LRBUF_DRAM_VREFDQ_R2_DDR4 142 // LR Buffer DRAM VrefDQ for Package Rank 2
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#define SPD_LRBUF_DRAM_VREFDQ_R3_DDR4 143 // LR Buffer DRAM VrefDQ for Package Rank 3
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#define SPD_LRBUF_DB_VREFDQ_DDR4 144 // LR Data Buffer VrefDQ for DRAM Interface
|
#define SPD_LRBUF_DB_DS_RTT_LE1866_DDR4 145 // LR Data Buffer MDQ Drive Strength and RTT for data rate <= 1866
|
#define SPD_LRBUF_DB_DS_RTT_GT1866_LE2400_DDR4 146 // LR Data Buffer MDQ Drive Strength and RTT for data rate > 1866 and <= 2400
|
#define SPD_LRBUF_DB_DS_RTT_GT2400_LE3200_DDR4 147 // LR Data Buffer MDQ Drive Strength and RTT for data rate > 2400 and <= 3200
|
#define SPD_LRBUF_DRAM_DS_DDR4 148 // LR Buffer DRAM Drive Strength (for data rates <= 1866, 1866 < data rate <= 2400, and 2400 < data rate <= 3200)
|
#define SPD_LRBUF_DRAM_ODT_WR_NOM_LE1866_DDR4 149 // LR Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 1866
|
#define SPD_LRBUF_DRAM_ODT_WR_NOM_GT1866_LE2400_DDR4 150 // LR Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate > 1866 and <= 2400
|
#define SPD_LRBUF_DRAM_ODT_WR_NOM_GT2400_LE3200_DDR4 151 // LR Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate > 2400 and <= 3200
|
#define SPD_LRBUF_DRAM_ODT_PARK_LE1866_DDR4 152 // LR Buffer DRAM ODT (RTT_PARK) for data rate <= 1866
|
#define SPD_LRBUF_DRAM_ODT_PARK_GT1866_LE2400_DDR4 153 // LR Buffer DRAM ODT (RTT_PARK) for data rate > 1866 and <= 2400
|
#define SPD_LRBUF_DRAM_ODT_PARK_GT2400_LE3200_DDR4 154 // LR Buffer DRAM ODT (RTT_PARK) for data rate > 2400 and <= 3200
|
|
//
|
// End DDR4 Specific Bytes
|
//
|
#define BANK0 0
|
#define BANK1 BIT0
|
#define BANK2 BIT1
|
#define BANK3 BIT0 + BIT1
|
#define BANK4 BIT2
|
#define BANK5 BIT2 + BIT0
|
#define BANK6 BIT2 + BIT1
|
#define BANK7 BIT2 + BIT1 + BIT0
|
|
#define RDIMM_RC00 0x00
|
#define RDIMM_RC01 0x01
|
#define RDIMM_RC02 0x02
|
#define RDIMM_RC03 0x03
|
#define RDIMM_RC04 0x04
|
#define RDIMM_RC05 0x05
|
#define RDIMM_RC08 0x08
|
#define RDIMM_RC09 0x09
|
#define RDIMM_RC0A 0x0A
|
#define RDIMM_RC0B 0x0B
|
#define RDIMM_RC0C 0x0C
|
#define RDIMM_RC0D 0x0D
|
#define RDIMM_RC0E 0x0E
|
#define RDIMM_RC0F 0x0F
|
#define RDIMM_RC1x 0x10
|
#define RDIMM_RC2x 0x20
|
#define RDIMM_RC3x 0x30
|
#define RDIMM_RC4x 0x40
|
#define RDIMM_RC5x 0x50
|
#define RDIMM_RC6x 0x60
|
#define RDIMM_RC7x 0x70
|
#define RDIMM_RC8x 0x80
|
#define RDIMM_RC9x 0x90
|
#define RDIMM_RCAx 0xA0
|
|
#define LRDIMM_BC00 0x00
|
#define LRDIMM_BC01 0x01
|
#define LRDIMM_BC02 0x02
|
#define LRDIMM_BC03 0x03
|
#define LRDIMM_BC04 0x04
|
#define LRDIMM_BC05 0x05
|
#define LRDIMM_BC06 0x06
|
#define LRDIMM_BC07 0x07
|
#define LRDIMM_BC08 0x08
|
#define LRDIMM_BC09 0x09
|
#define LRDIMM_BC0A 0x0A
|
#define LRDIMM_BC0B 0x0B
|
#define LRDIMM_BC0C 0x0C
|
#define LRDIMM_BC0E 0x0E
|
|
#define LRDIMM_BC0x 0x00
|
#define LRDIMM_BC1x 0x10
|
#define LRDIMM_BC2x 0x20
|
#define LRDIMM_BC3x 0x30
|
#define LRDIMM_BC4x 0x40
|
#define LRDIMM_BC5x 0x50
|
#define LRDIMM_BC6x 0x60
|
#define LRDIMM_BC7x 0x70
|
#define LRDIMM_BC8x 0x80
|
#define LRDIMM_BC9x 0x90
|
#define LRDIMM_BCAx 0xA0
|
#define LRDIMM_BCBx 0xB0
|
#define LRDIMM_BCCx 0xC0
|
#define LRDIMM_BCDx 0xD0
|
#define LRDIMM_BCEx 0xE0
|
#define LRDIMM_BCFx 0xF0
|
#define LRDIMM_F0 0x0
|
#define LRDIMM_F1 0x1
|
#define LRDIMM_F5 0x5
|
#define LRDIMM_F6 0x6
|
#define LRDIMM_F7 0x7
|
#define LRDIMM_F8 0x8
|
#define LRDIMM_F9 0x9
|
|
#endif /* _HW_MEM_INIT_LIB_H_ */
|
