/** @file
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*
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* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
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* Copyright (c) 2018, Linaro Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#ifndef _EINJ_H_
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#define _EINJ_H_
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#include "Apei.h"
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#define EINJ_ACTION_NO 10
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#define EINJ_BEGIN_OPERATION_VALUE 0xFFFF
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#define EINJ_END_OPERATION_VALUE 0
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#define EINJ_WRITE_MASK 0xFFFFFFFF
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#define EINJ_READ_VALUE 0xFFFF
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#define EINJ_READ_MASK 0xFFFFFFFF
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#define EINJ_TRIGGER_ERROR_ACTION_NO 1
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#define EFI_ACPI_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08
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#define EFI_ACPI_EINJ_GET_EXCUTE_OPERATION_TIMINGS 0x09
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extern EFI_ACPI_TABLE_PROTOCOL *mAcpiTableProtocol;
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extern EFI_ACPI_SDT_PROTOCOL *mAcpiSdtProtocol;
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extern APEI_TRUSTED_FIRMWARE_STRUCTURE *mApeiTrustedfirmwareData;
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//
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// Error Type Definition
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//
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#define EINJ_PROCESSOR_CORRECTABLE BIT0
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#define EINJ_PROCESSOR_UNCORRECTABLE_NONFATAL BIT1
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#define EINJ_PROCESSOR_UNCORRECTABLE_FATAL BIT2
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#define EINJ_MEMORY_CORRECTABLE BIT3
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#define EINJ_MEMORY_UNCORRECTABLE_NONFATAL BIT4
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#define EINJ_MEMORY_UNCORRECTABLE_FATAL BIT5
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#define EINJ_PCIE_CORRECTABLE BIT6
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#define EINJ_PCIE_UNCORRECTABLE_NONFATAL BIT7
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#define EINJ_PCIE_UNCORRECTABLE_FATAL BIT8
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#define EINJ_PLATFORM_CORRECTABLE BIT9
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#define EINJ_PLATFORM_UNCORRECTABLE_NONFATAL BIT10
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#define EINJ_PLATFORM_UNCORRECTABLE_FATAL BIT11
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#define EINJ_VENDOR_DEFINED_ERROR_TYPE BIT31
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#define EINJ_PROCESSOR_APIC_VALID BIT0
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#define EINJ_MEMORY_ADDRESS_VALID BIT1
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#define EINJ_PCIE_SBDF_VALID BIT2
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///
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/// EINJ Table
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///
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typedef struct {
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EFI_ACPI_6_0_ERROR_INJECTION_TABLE_HEADER EinjTableHeader;
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EFI_ACPI_6_0_EINJ_INJECTION_INSTRUCTION_ENTRY EinjInstructionEntry[EINJ_ACTION_NO];
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} EINJ_TABLE;
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typedef struct {
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EFI_ACPI_6_0_EINJ_TRIGGER_ACTION_TABLE TriggerErrorHeader;
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EFI_ACPI_6_0_EINJ_INJECTION_INSTRUCTION_ENTRY ErrorInstructionEntry[EINJ_TRIGGER_ERROR_ACTION_NO];
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} EINJ_TRIGGER_ERROR_ACTION;
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typedef struct {
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UINT32 Reserved: 8;
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UINT32 Function: 3;
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UINT32 Device: 5;
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UINT32 PrimaryOrDeviceBus: 8;
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UINT32 Segment: 8;
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} EINJ_PCIE_SBDF;
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typedef struct {
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UINT32 ErrorType;
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UINT32 VendorErrorTypeOffset;
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UINT32 Flags;
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UINT32 ApicId;
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UINT64 MemAddress;
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UINT64 MemAddressRange;
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EINJ_PCIE_SBDF PcieSBDF;
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} EINJ_SET_ERROR_TYPE_WITH_ADDRESS;
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typedef struct {
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UINT32 Length;
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UINT32 SBDF;
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UINT16 VendorId;
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UINT16 DeviceId;
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UINT8 RevId;
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UINT8 Reserved[3];
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} EINJ_VENDOR_ERROR_TYPE;
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typedef struct {
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UINT64 OperationBegin;
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UINT64 ErrorType;
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UINT64 ErrorCapabilities;
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UINT64 BusyStatus;
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UINT64 CommandStatus;
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UINT64 Timing;
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EINJ_TRIGGER_ERROR_ACTION *TriggerErrorActionTablePtr;
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EINJ_SET_ERROR_TYPE_WITH_ADDRESS ErrorTypeWithAddress;
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EINJ_VENDOR_ERROR_TYPE VendorErrorTypeExtension;
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EINJ_TRIGGER_ERROR_ACTION TriggerErrorActionTable;
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} EINJ_DATA_STRUCTURE;
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// V2
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typedef struct _EINJ_CONTEXT {
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EINJ_TABLE *EINJ;
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EINJ_DATA_STRUCTURE *EinjData;
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EFI_ACPI_6_0_EINJ_INJECTION_INSTRUCTION_ENTRY *GetErrorTypeEntry;
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EFI_ACPI_6_0_EINJ_INJECTION_INSTRUCTION_ENTRY *ExecuteOperationEntry;
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} EINJ_CONTEXT;
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EFI_STATUS
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InitEinjTable(VOID);
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// Version2
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EFI_STATUS
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EinjConfigErrorInjectCapability(
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EINJ_CONTEXT *Context,
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UINT32 BitsSupportedErrorType
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);
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EFI_STATUS
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EinjHeaderCreator(
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EINJ_CONTEXT *Context
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);
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/***OEM***/
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EFI_STATUS
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OemInitEinjTable(VOID);
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EFI_STATUS
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OemEinjConfigExecuteOperationEntry(
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EINJ_CONTEXT *Context
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);
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VOID
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EinjSetAcpiTable(
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EINJ_CONTEXT *Context
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);
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#endif // _EINJ_H_
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