/** @file
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*
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* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
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* Copyright (c) 2018, Linaro Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#ifndef _PLATFORM_ARCH_H_
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#define _PLATFORM_ARCH_H_
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#define MAX_SOCKET 2
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#define MAX_DIE 4
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#define MAX_DDRC 2
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#define MAX_NODE (MAX_SOCKET * MAX_DIE)
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#define MAX_CHANNEL 4
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#define MAX_DIMM 3
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#define MAX_RANK_CH 12
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#define MAX_RANK_DIMM 4
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#define MAX_DIMM_SIZE 32 // In GB
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// Max NUMA node number for each node type
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#define MAX_NUM_PER_TYPE 8
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#define RASC_BASE (0x5000)
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/* configuration register for Rank statistical information */
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#define RASC_CFG_INFOIDX_REG (RASC_BASE + 0x5C)
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/* configuration register for Sparing level */
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#define RASC_CFG_SPLVL_REG (RASC_BASE + 0xB8)
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// for acpi
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#define NODE_IN_SOCKET 2
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#define CORE_NUM_PER_SOCKET 32
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#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT 10
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#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT 8
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#define S1_BASE 0x40000000000
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//
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// ACPI table information used to initialize tables.
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//
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#define EFI_ACPI_ARM_OEM_ID 'H','I','S','I',' ',' ' // OEMID 6 bytes long
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#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64 ('H','I','P','0','7',' ',' ',' ') // OEM table id 8 bytes long
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#define EFI_ACPI_ARM_OEM_REVISION 0x00000000
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#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32 ('I','N','T','L')
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#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
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// A macro to initialise the common header part of EFI ACPI tables as defined by
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// EFI_ACPI_DESCRIPTION_HEADER structure.
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#define ARM_ACPI_HEADER(Signature, Type, Revision) { \
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Signature, /* UINT32 Signature */ \
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sizeof (Type), /* UINT32 Length */ \
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Revision, /* UINT8 Revision */ \
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0, /* UINT8 Checksum */ \
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{ EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \
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EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \
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EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \
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EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \
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EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \
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}
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#endif
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