/** @file
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*
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* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
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* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
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* Copyright (c) 2016, Linaro Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
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*
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**/
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//#include "ArmPlatform.h"
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/*
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See ACPI 6.1 Spec, 6.2.11, PCI Firmware Spec 3.0, 4.5
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*/
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#define PCI_OSC_SUPPORT() \
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Name(SUPP, Zero) /* PCI _OSC Support Field value */ \
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Name(CTRL, Zero) /* PCI _OSC Control Field value */ \
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Method(_OSC,4) { \
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If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \
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/* Create DWord-adressable fields from the Capabilities Buffer */ \
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CreateDWordField(Arg3,0,CDW1) \
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CreateDWordField(Arg3,4,CDW2) \
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CreateDWordField(Arg3,8,CDW3) \
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/* Save Capabilities DWord2 & 3 */ \
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Store(CDW2,SUPP) \
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Store(CDW3,CTRL) \
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/* Only allow native hot plug control if OS supports: */ \
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/* ASPM */ \
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/* Clock PM */ \
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/* MSI/MSI-X */ \
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If(LNotEqual(And(SUPP, 0x16), 0x16)) { \
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And(CTRL,0x1E,CTRL) \
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}\
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\
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/* Do not allow native PME, AER */ \
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/* Never allow SHPC (no SHPC controller in this system)*/ \
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And(CTRL,0x10,CTRL) \
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If(LNotEqual(Arg1,One)) { /* Unknown revision */ \
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Or(CDW1,0x08,CDW1) \
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} \
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\
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If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \
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Or(CDW1,0x10,CDW1) \
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} \
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\
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/* Update DWORD3 in the buffer */ \
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Store(CTRL,CDW3) \
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Return(Arg3) \
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} Else { \
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Or(CDW1,4,CDW1) /* Unrecognized UUID */ \
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Return(Arg3) \
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} \
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} // End _OSC
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Scope(_SB)
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{
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// PCIe Root bus
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Device (PCI0)
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{
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Name (_HID, "PNP0A08") // PCI Express Root Bridge
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Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
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Name(_SEG, 0) // Segment of this Root complex
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Name(_BBN, 0) // Base Bus Number
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Name(_CCA, 1)
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Method (_CRS, 0, Serialized) { // Root complex resources
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Name (RBUF, ResourceTemplate () {
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WordBusNumber ( // Bus numbers assigned to this root
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ResourceProducer, MinFixed, MaxFixed, PosDecode,
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0, // AddressGranularity
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0x0, // AddressMinimum - Minimum Bus Number
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0x1f, // AddressMaximum - Maximum Bus Number
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0, // AddressTranslation - Set to 0
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0x20 // RangeLength - Number of Busses
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)
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QWordMemory ( // 64-bit BAR Windows
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ResourceProducer,
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PosDecode,
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MinFixed,
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MaxFixed,
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Cacheable,
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ReadWrite,
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0x0, // Granularity
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0xb2000000, // Min Base Address pci address
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0xb7feffff, // Max Base Address
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0x0, // Translate
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0x5ff0000 // Length
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)
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QWordIO (
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ResourceProducer,
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MinFixed,
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MaxFixed,
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PosDecode,
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EntireRange,
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0x0, // Granularity
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0x0, // Min Base Address
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0xffff, // Max Base Address
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0xb7ff0000, // Translate
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0x10000 // Length
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)
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}) // Name(RBUF)
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Return (RBUF)
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} // Method(_CRS)
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PCI_OSC_SUPPORT()
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Device (RES0)
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{
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Name (_HID, "HISI0081") // HiSi PCIe RC config base address
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Name (_CRS, ResourceTemplate (){
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Memory32Fixed (ReadWrite, 0xa0090000 , 0x10000)
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})
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}
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} // Device(PCI0)
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Device (RES0)
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{
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Name (_HID, "HISI0081") // HiSi PCIe RC config base address
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Name (_CID, "PNP0C02") // Motherboard reserved resource
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Name (_UID, 0x0) // Unique ID
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Name (_CRS, ResourceTemplate (){
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Memory32Fixed (ReadWrite, 0xa0090000 , 0x10000)
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})
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}
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// PCIe Root bus
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Device (PCI1)
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{
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Name (_HID, "PNP0A08") // PCI Express Root Bridge
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Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
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Name(_SEG, 1) // Segment of this Root complex
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Name(_BBN, 0xe0) // Base Bus Number
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Name(_CCA, 1)
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Method (_CRS, 0, Serialized) { // Root complex resources
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Name (RBUF, ResourceTemplate () {
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WordBusNumber ( // Bus numbers assigned to this root
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ResourceProducer, MinFixed, MaxFixed, PosDecode,
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0, // AddressGranularity
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0xe0, // AddressMinimum - Minimum Bus Number
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0xff, // AddressMaximum - Maximum Bus Number
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0, // AddressTranslation - Set to 0
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0x20 // RangeLength - Number of Busses
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)
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QWordMemory ( // 64-bit BAR Windows
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ResourceProducer,
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PosDecode,
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MinFixed,
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MaxFixed,
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Cacheable,
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ReadWrite,
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0x0, // Granularity
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0xb8000000, // Min Base Address pci address
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0xbdfeffff, // Max Base Address
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0x0, // Translate
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0x5ff0000 // Length
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)
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QWordIO (
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ResourceProducer,
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MinFixed,
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MaxFixed,
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PosDecode,
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EntireRange,
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0x0, // Granularity
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0x0, // Min Base Address
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0xffff, // Max Base Address
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0xbdff0000, // Translate
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0x10000 // Length
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)
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}) // Name(RBUF)
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Return (RBUF)
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} // Method(_CRS)
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PCI_OSC_SUPPORT()
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Device (RES1)
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{
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Name (_HID, "HISI0081") // HiSi PCIe RC config base address
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Name (_CID, "PNP0C02") // Motherboard reserved resource
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Name (_UID, 0x1) // Unique ID
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Name (_CRS, ResourceTemplate (){
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Memory32Fixed (ReadWrite, 0xa0200000 , 0x10000)
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})
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}
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} // Device(PCI1)
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Device (RES1)
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{
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Name (_HID, "HISI0081") // HiSi PCIe RC config base address
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Name (_CRS, ResourceTemplate (){
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Memory32Fixed (ReadWrite, 0xa0200000 , 0x10000)
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})
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}
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// PCIe Root bus
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Device (PCI2)
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{
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Name (_HID, "PNP0A08") // PCI Express Root Bridge
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Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
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Name(_SEG, 2) // Segment of this Root complex
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Name(_BBN, 0x80) // Base Bus Number
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Name(_CCA, 1)
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Method (_CRS, 0, Serialized) { // Root complex resources
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Name (RBUF, ResourceTemplate () {
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WordBusNumber ( // Bus numbers assigned to this root
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ResourceProducer, MinFixed, MaxFixed, PosDecode,
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0, // AddressGranularity
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0x80, // AddressMinimum - Minimum Bus Number
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0x9f, // AddressMaximum - Maximum Bus Number
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0, // AddressTranslation - Set to 0
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0x20 // RangeLength - Number of Busses
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)
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QWordMemory ( // 64-bit BAR Windows
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ResourceProducer,
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PosDecode,
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MinFixed,
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MaxFixed,
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Cacheable,
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ReadWrite,
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0x0, // Granularity
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0xaa000000, // Min Base Address
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0xaffeffff, // Max Base Address
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0x0, // Translate
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0x5ff0000 // Length
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)
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QWordIO (
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ResourceProducer,
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MinFixed,
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MaxFixed,
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PosDecode,
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EntireRange,
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0x0, // Granularity
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0x0, // Min Base Address
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0xffff, // Max Base Address
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0xafff0000, // Translate
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0x10000 // Length
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)
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}) // Name(RBUF)
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Return (RBUF)
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} // Method(_CRS)
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PCI_OSC_SUPPORT()
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Device (RES2)
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{
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Name (_HID, "HISI0081") // HiSi PCIe RC config base address
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Name (_CRS, ResourceTemplate (){
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Memory32Fixed (ReadWrite, 0xa00a0000, 0x10000)
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})
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}
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} // Device(PCI2)
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Device (RES2)
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{
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Name (_HID, "HISI0081") // HiSi PCIe RC config base address
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Name (_CID, "PNP0C02") // Motherboard reserved resource
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Name (_UID, 0x2) // Unique ID
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Name (_CRS, ResourceTemplate (){
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Memory32Fixed (ReadWrite, 0xa00a0000, 0x10000)
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})
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}
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Device (RESP) //reserve for ecam resource
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{
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Name (_HID, "PNP0C02")
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Name (_CRS, ResourceTemplate (){
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Memory32Fixed (ReadWrite, 0xb0000000, 0x2000000) //ECAM space for PCI0 [bus 00-1f]
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Memory32Fixed (ReadWrite, 0xbe000000, 0x2000000) //ECAM space for PCI1 [bus e0-ff]
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Memory32Fixed (ReadWrite, 0xa8000000, 0x2000000) //ECAM space for PCI2 [bus 80-9f]
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})
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}
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}
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