/** @file
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*
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* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
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* Copyright (c) 2016, Linaro Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#ifndef __PCIE_KERNEL_API_H__
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#define __PCIE_KERNEL_API_H__
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#define PCIE_MAX_OUTBOUND (6)
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#define PCIE_MAX_INBOUND (4)
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#define PCIE3_MAX_OUTBOUND (16)
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#define PCIE3_MAX_INBOUND (16)
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#define PCIE_LINK_LOOP_CNT (0x1000)
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#define PCIE_IATU_ADDR_MASK (0xFFFFF000)
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#define PCIE_1M_ALIGN_SHIRFT (20)
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#define PCIE_BDF_MASK (0xF0000FFF)
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#define PCIE_BUS_SHIRFT (20)
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#define PCIE_DEV_SHIRFT (15)
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#define PCIE_FUNC_SHIRFT (12)
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#define PCIE_DBI_CS2_ENABLE (0x1)
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#define PCIE_DBI_CS2_DISABLE (0x0)
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#define PCIE_DMA_CHANLE_READ (0x1)
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#define PCIE_DMA_CHANLE_WRITE (0x0)
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#define PCIE_ERR_IATU_TABLE_NULL EFIERR (1)
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#define PCIE_ERR_LINK_OVER_TIME EFIERR (2)
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#define PCIE_ERR_UNIMPLEMENT_PCIE_TYPE EFIERR (3)
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#define PCIE_ERR_ALREADY_INIT EFIERR (4)
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#define PCIE_ERR_PARAM_INVALID EFIERR (5)
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#define PCIE_ERR_MEM_OPT_OVER EFIERR (6)
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#define PCIE_ERR_NOT_INIT EFIERR (7)
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#define PCIE_ERR_CFG_OPT_OVER EFIERR (8)
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#define PCIE_ERR_DMA_READ_CHANLE_BUSY EFIERR (9)
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#define PCIE_ERR_DMA_WRITE_CHANLE_BUSY EFIERR (10)
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#define PCIE_ERR_DMAR_NO_RESORCE EFIERR (11)
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#define PCIE_ERR_DMAW_NO_RESORCE EFIERR (12)
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#define PCIE_ERR_DMA_OVER_MAX_RESORCE EFIERR (13)
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#define PCIE_ERR_NO_IATU_WINDOW EFIERR (14)
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#define PCIE_ERR_DMA_TRANSPORT_OVER_TIME EFIERR (15)
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#define PCIE_ERR_DMA_MEM_ALLOC_ERROR EFIERR (16)
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#define PCIE_ERR_DMA_ABORT EFIERR (17)
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#define PCIE_ERR_UNSUPPORT_BAR_TYPE EFIERR (18)
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typedef enum {
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PCIE_ROOT_COMPLEX,
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PCIE_END_POINT,
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PCIE_NTB_TO_NTB,
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PCIE_NTB_TO_RP,
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} PCIE_PORT_TYPE;
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typedef enum {
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PCIE_GEN1_0 = 1, //PCIE 1.0
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PCIE_GEN2_0 = 2, //PCIE 2.0
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PCIE_GEN3_0 = 4 //PCIE 3.0
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} PCIE_PORT_GEN;
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typedef enum {
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PCIE_WITDH_X1 = 0x1,
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PCIE_WITDH_X2 = 0x3,
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PCIE_WITDH_X4 = 0x7,
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PCIE_WITDH_X8 = 0xf,
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PCIE_WITDH_INVALID
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} PCIE_PORT_WIDTH;
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typedef struct {
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PCIE_PORT_TYPE PortType;
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PCIE_PORT_WIDTH PortWidth;
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PCIE_PORT_GEN PortGen;
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UINT8 PcieLinkUp;
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} PCIE_PORT_INFO;
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typedef struct tagPciecfg_params
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{
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UINT32 preemphasis;
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UINT32 deemphasis;
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UINT32 swing;
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UINT32 balance;
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}pcie_cfg_params_s;
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typedef enum {
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PCIE_CORRECTABLE_ERROR = 0,
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PCIE_NON_FATAL_ERROR,
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PCIE_FATAL_ERROR,
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PCIE_UNSUPPORTED_REQUEST_ERROR,
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PCIE_ALL_ERROR
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} PCIE_ERROR_TYPE;
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typedef union tagPcieDeviceStatus
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{
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struct
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{
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UINT16 correctable_error : 1;
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UINT16 non_fatal_error : 1;
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UINT16 fatal_error : 1;
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UINT16 unsupported_error : 1;
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UINT16 aux_power : 1;
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UINT16 transaction_pending : 1;
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UINT16 reserved_6_15 : 10;
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}Bits;
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UINT16 Value;
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}pcie_device_status_u;
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typedef union tagPcieUcAerStatus
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{
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struct
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{
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UINT32 undefined : 1 ; /* [0] undefined */
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UINT32 reserved_1_3 : 3 ; /* reserved */
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UINT32 data_link_proto_error : 1 ; /* Data Link Protocol Error Status */
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UINT32 reserved_5_11 : 7 ; /* reserved */
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UINT32 poisoned_tlp_status : 1 ; /* Poisoned TLP Status */
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UINT32 flow_control_proto_error : 1 ; /* Flow Control Protocol Error Status */
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UINT32 completion_time_out : 1 ; /* Completion Timeout Status */
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UINT32 compler_abort_status : 1 ; /* Completer Abort Status */
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UINT32 unexpect_completion_status : 1 ; /* Unexpected Completion Status */
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UINT32 receiver_overflow_status : 1 ; /*Receiver Overflow Status */
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UINT32 malformed_tlp_status : 1 ; /* Malformed TLP Status*/
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UINT32 ecrc_error_status : 1 ; /* ECRC Error Status */
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UINT32 unsupport_request_error_status : 1 ; /* Unsupported Request Error Status */
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UINT32 reserved_21 : 1 ; /* reserved */
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UINT32 uncorrectable_interal_error : 1 ; /* Uncorrectable Internal Error Status */
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UINT32 reserved_23 : 1 ; /* reserved*/
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UINT32 atomicop_egress_blocked_status : 1 ; /* AtomicOp Egress Blocked Status */
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UINT32 tlp_prefix_blocked_error_status : 1 ; /* TLP Prefix Blocked Error Status */
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UINT32 reserved_26_31 : 1 ; /* reserved */
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}Bits;
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UINT32 Value;
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}pcie_uc_aer_status_u;
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typedef union tagPcieCoAerStatus
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{
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struct
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{
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UINT32 receiver_error_status : 1 ; /* Receiver Error Status */
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UINT32 reserved_1_5 : 5 ; /* Reserved */
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UINT32 bad_tlp_status : 1 ; /* Bad TLP Status */
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UINT32 bad_dllp_status : 1 ; /* Bad DLLP Status */
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UINT32 reply_num_rollover_status : 1 ; /* REPLAY_NUM Rollover Status*/
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UINT32 reserved_9_11 : 3 ; /* Reserved */
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UINT32 reply_timer_timeout : 1 ; /* Replay Timer Timeout Status */
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UINT32 advisory_nonfatal_error : 1 ; /* Advisory Non-Fatal Error Status*/
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UINT32 corrected_internal_error : 1 ; /*Corrected Internal Error Status*/
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UINT32 reserved_15_31 : 1 ; /* Reserved */
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}Bits;
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UINT32 Value;
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}pcie_co_aer_status_u;
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typedef struct tagPcieAerStatus
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{
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pcie_uc_aer_status_u uc_aer_status;
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pcie_co_aer_status_u co_aer_status;
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}pcie_aer_status_s;
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typedef struct tagPcieLoopTestResult
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{
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UINT32 tx_pkts_cnt;
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UINT32 rx_pkts_cnt;
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UINT32 error_pkts_cnt;
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UINT32 droped_pkts_cnt;
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UINT32 push_cnt;
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pcie_device_status_u device_status;
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pcie_aer_status_s pcie_aer_status;
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} pcie_loop_test_result_s;
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typedef struct tagPcieDmaChannelAttrs {
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UINT32 dma_chan_en;
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UINT32 dma_mode;
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UINT32 channel_status;
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}pcie_dma_channel_attrs_s;
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typedef enum tagPcieDmaChannelStatus
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{
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PCIE_DMA_CS_RESERVED = 0,
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PCIE_DMA_CS_RUNNING = 1,
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PCIE_DMA_CS_HALTED = 2,
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PCIE_DMA_CS_STOPPED = 3
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}pcie_dma_channel_status_e;
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typedef enum tagPcieDmaIntType{
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PCIE_DMA_INT_TYPE_DONE=0,
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PCIE_DMA_INT_TYPE_ABORT,
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PCIE_DMA_INT_ALL,
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PCIE_DMA_INT_NONE
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}pcie_dma_int_type_e;
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typedef enum tagPcieMulWinSize
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{
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WIN_SIZE_4K = 0xc,
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WIN_SIZE_8K,
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WIN_SIZE_16K,
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WIN_SIZE_32K,
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WIN_SIZE_64K,
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WIN_SIZE_128K,
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WIN_SIZE_256K,
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WIN_SIZE_512K,
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WIN_SIZE_1M,
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WIN_SIZE_2M,
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WIN_SIZE_4M,
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WIN_SIZE_8M,
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WIN_SIZE_16M,
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WIN_SIZE_32M,
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WIN_SIZE_64M,
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WIN_SIZE_128M,
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WIN_SIZE_256M,
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WIN_SIZE_512M,
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WIN_SIZE_1G,
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WIN_SIZE_2G,
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WIN_SIZE_4G,
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WIN_SIZE_8G,
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WIN_SIZE_16G,
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WIN_SIZE_32G,
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WIN_SIZE_64G,
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WIN_SIZE_128G,
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WIN_SIZE_256G,
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WIN_SIZE_512G = 0x27,
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}pcie_mul_win_size_e;
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typedef struct tagPcieMultiCastCfg
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{
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UINT64 multicast_base_addr;
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pcie_mul_win_size_e base_addr_size;
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UINT64 base_translate_addr;
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}pcie_multicast_cfg_s;
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typedef enum tagPcieMode
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{
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PCIE_EP_DEVICE = 0x0,
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LEGACY_PCIE_EP_DEVICE = 0x1,
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RP_OF_PCIE_RC = 0x4,
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PCIE_INVALID = 0x100
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}pcie_mode_e;
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typedef struct{
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UINT32 PortIndex;
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PCIE_PORT_INFO PortInfo;
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UINT64 iep_bar01; /*iep bar 01*/
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UINT64 iep_bar23;
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UINT64 iep_bar45;
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UINT64 iep_bar01_xlat;
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UINT64 iep_bar23_xlat;
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UINT64 iep_bar45_xlat;
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UINT64 iep_bar_lmt23;
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UINT64 iep_bar_lmt45; /*bar limit*/
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UINT64 eep_bar01;
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UINT64 eep_bar23;
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UINT64 eep_bar45;
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UINT64 eep_bar23_xlat;
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UINT64 eep_bar45_xlat;
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UINT64 eep_bar_lmt23; /*bar limit*/
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UINT64 eep_bar_lmt45; /*bar limit*/
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} PCIE_NTB_CFG;
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extern int pcie_mode_get(UINT32 Port, PCIE_PORT_INFO *port_info);
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extern int pcie_port_ctrl(UINT32 Port, UINT32 port_ctrl);
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extern int pcie_link_speed_set(UINT32 Port, PCIE_PORT_GEN speed);
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extern int pcie_port_cfg_set(UINT32 Port, pcie_cfg_params_s *cfg_params);
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extern int pcie_port_cfg_get(UINT32 Port, pcie_cfg_params_s *cfg_params);
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extern int pcie_dma_chan_ctl(UINT32 Port,UINT32 channel,UINT32 control);
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extern int pcie_dma_chan_attribu_set(UINT32 Port,UINT32 channel, pcie_dma_channel_attrs_s *dma_attribute);
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extern int pcie_dma_cur_status_get(UINT32 Port, UINT32 channel, pcie_dma_channel_status_e *dma_channel_status);
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extern int pcie_dma_int_enable(UINT32 Port, UINT32 channel, pcie_dma_int_type_e int_type);
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extern int pcie_dma_int_mask(UINT32 Port, UINT32 channel, pcie_dma_int_type_e int_type);
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extern int pcie_dma_tranfer_stop(UINT32 Port, UINT32 channel);
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extern int pcie_dma_int_status_get(UINT32 Port, UINT32 channel, int *dma_int_status);
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extern int pcie_dma_int_clear(UINT32 Port, UINT32 channel, pcie_dma_int_type_e dma_int_type);
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extern int pcie_dma_read(UINT32 Port,void *source, void *dest,UINT32 transfer_size, UINT32 burst_size);
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extern int pcie_dma_write(UINT32 Port,void *source, void *dest,UINT32 transfer_size, UINT32 burst_size);
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extern int pcie_multicast_cfg_set(UINT32 Port,pcie_multicast_cfg_s *multicast_cfg,UINT32 win_num);
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extern int pcie_setup_ntb(UINT32 Port, PCIE_NTB_CFG *ntb_cfg);
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extern int pcie_ntb_doorbell_send(UINT32 Port,UINT32 doorbell);
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extern int pcie_loop_test_start(UINT32 Port, UINT32 loop_type);
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extern int pcie_loop_test_stop(UINT32 Port, UINT32 loop_type);
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extern int pcie_loop_test_get(UINT32 Port, UINT32 loop_type, pcie_loop_test_result_s *test_result);
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extern int pcie_port_reset(UINT32 Port);
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extern int pcie_port_error_report_enable(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, PCIE_ERROR_TYPE pcie_error);
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extern int pcie_port_error_report_disable(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, PCIE_ERROR_TYPE pcie_error);
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extern int pcie_device_error_status_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,UINT32 clear, \
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pcie_device_status_u *pcie_stat);
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extern int pcie_port_aer_cap_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,UINT32 *aer_cap);
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extern int pcie_port_aer_status_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,pcie_uc_aer_status_u *pcie_aer_status);
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extern int pcie_port_aer_status_clr(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func);
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extern int pcie_port_aer_report_enable(UINT32 Port, PCIE_ERROR_TYPE pcie_aer_type);
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extern int pcie_port_aer_report_disable(UINT32 Port, PCIE_ERROR_TYPE pcie_aer_type);
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extern int pcie_cfg_read(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, UINT32 reg_offset, UINT32 * value, UINT32 length);
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extern int pcie_cfg_write(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, UINT32 reg_offset, UINT8 * data, UINT32 length);
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extern int pcie_mem_read(UINT32 Port,void * local_addr, void *pcie_mem_addr,UINT32 length);
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extern int pcie_mem_write(UINT32 Port,void *local_addr , void *pcie_mem_addr,UINT32 length);
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#endif
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